00001 /* 00002 * Copyright 2003, 2004, 2005, 2006 PathScale, Inc. All Rights Reserved. 00003 */ 00004 00005 /* ppc.h -- Header file for PowerPC opcode table 00006 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004 00007 Free Software Foundation, Inc. 00008 Written by Ian Lance Taylor, Cygnus Support 00009 00010 This file is part of GDB, GAS, and the GNU binutils. 00011 00012 GDB, GAS, and the GNU binutils are free software; you can redistribute 00013 them and/or modify them under the terms of the GNU General Public 00014 License as published by the Free Software Foundation; either version 00015 1, or (at your option) any later version. 00016 00017 GDB, GAS, and the GNU binutils are distributed in the hope that they 00018 will be useful, but WITHOUT ANY WARRANTY; without even the implied 00019 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 00020 the GNU General Public License for more details. 00021 00022 You should have received a copy of the GNU General Public License 00023 along with this file; see the file COPYING. If not, write to the Free 00024 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 00025 00026 #ifndef PPC_H 00027 #define PPC_H 00028 00029 /* The opcode table is an array of struct powerpc_opcode. */ 00030 00031 struct powerpc_opcode 00032 { 00033 /* The opcode name. */ 00034 const char *name; 00035 00036 /* The opcode itself. Those bits which will be filled in with 00037 operands are zeroes. */ 00038 unsigned long opcode; 00039 00040 /* The opcode mask. This is used by the disassembler. This is a 00041 mask containing ones indicating those bits which must match the 00042 opcode field, and zeroes indicating those bits which need not 00043 match (and are presumably filled in by operands). */ 00044 unsigned long mask; 00045 00046 /* One bit flags for the opcode. These are used to indicate which 00047 specific processors support the instructions. The defined values 00048 are listed below. */ 00049 unsigned long flags; 00050 00051 /* An array of operand codes. Each code is an index into the 00052 operand table. They appear in the order which the operands must 00053 appear in assembly code, and are terminated by a zero. */ 00054 unsigned char operands[8]; 00055 }; 00056 00057 /* The table itself is sorted by major opcode number, and is otherwise 00058 in the order in which the disassembler should consider 00059 instructions. */ 00060 extern const struct powerpc_opcode powerpc_opcodes[]; 00061 extern const int powerpc_num_opcodes; 00062 00063 /* Values defined for the flags field of a struct powerpc_opcode. */ 00064 00065 /* Opcode is defined for the PowerPC architecture. */ 00066 #define PPC_OPCODE_PPC 1 00067 00068 /* Opcode is defined for the POWER (RS/6000) architecture. */ 00069 #define PPC_OPCODE_POWER 2 00070 00071 /* Opcode is defined for the POWER2 (Rios 2) architecture. */ 00072 #define PPC_OPCODE_POWER2 4 00073 00074 /* Opcode is only defined on 32 bit architectures. */ 00075 #define PPC_OPCODE_32 8 00076 00077 /* Opcode is only defined on 64 bit architectures. */ 00078 #define PPC_OPCODE_64 0x10 00079 00080 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 00081 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 00082 but it also supports many additional POWER instructions. */ 00083 #define PPC_OPCODE_601 0x20 00084 00085 /* Opcode is supported in both the Power and PowerPC architectures 00086 (ie, compiler's -mcpu=common or assembler's -mcom). */ 00087 #define PPC_OPCODE_COMMON 0x40 00088 00089 /* Opcode is supported for any Power or PowerPC platform (this is 00090 for the assembler's -many option, and it eliminates duplicates). */ 00091 #define PPC_OPCODE_ANY 0x80 00092 00093 /* Opcode is supported as part of the 64-bit bridge. */ 00094 #define PPC_OPCODE_64_BRIDGE 0x100 00095 00096 /* Opcode is supported by Altivec Vector Unit */ 00097 #define PPC_OPCODE_ALTIVEC 0x200 00098 00099 /* Opcode is supported by PowerPC 403 processor. */ 00100 #define PPC_OPCODE_403 0x400 00101 00102 /* Opcode is supported by PowerPC BookE processor. */ 00103 #define PPC_OPCODE_BOOKE 0x800 00104 00105 /* Opcode is only supported by 64-bit PowerPC BookE processor. */ 00106 #define PPC_OPCODE_BOOKE64 0x1000 00107 00108 /* Opcode is supported by PowerPC 440 processor. */ 00109 #define PPC_OPCODE_440 0x2000 00110 00111 /* Opcode is only supported by Power4 architecture. */ 00112 #define PPC_OPCODE_POWER4 0x4000 00113 00114 /* Opcode isn't supported by Power4 architecture. */ 00115 #define PPC_OPCODE_NOPOWER4 0x8000 00116 00117 /* Opcode is only supported by POWERPC Classic architecture. */ 00118 #define PPC_OPCODE_CLASSIC 0x10000 00119 00120 /* Opcode is only supported by e500x2 Core. */ 00121 #define PPC_OPCODE_SPE 0x20000 00122 00123 /* Opcode is supported by e500x2 Integer select APU. */ 00124 #define PPC_OPCODE_ISEL 0x40000 00125 00126 /* Opcode is an e500 SPE floating point instruction. */ 00127 #define PPC_OPCODE_EFS 0x80000 00128 00129 /* Opcode is supported by branch locking APU. */ 00130 #define PPC_OPCODE_BRLOCK 0x100000 00131 00132 /* Opcode is supported by performance monitor APU. */ 00133 #define PPC_OPCODE_PMR 0x200000 00134 00135 /* Opcode is supported by cache locking APU. */ 00136 #define PPC_OPCODE_CACHELCK 0x400000 00137 00138 /* Opcode is supported by machine check APU. */ 00139 #define PPC_OPCODE_RFMCI 0x800000 00140 00141 /* A macro to extract the major opcode from an instruction. */ 00142 #define PPC_OP(i) (((i) >> 26) & 0x3f) 00143 00144 /* The operands table is an array of struct powerpc_operand. */ 00145 00146 struct powerpc_operand 00147 { 00148 /* The number of bits in the operand. */ 00149 int bits; 00150 00151 /* How far the operand is left shifted in the instruction. */ 00152 int shift; 00153 00154 /* Insertion function. This is used by the assembler. To insert an 00155 operand value into an instruction, check this field. 00156 00157 If it is NULL, execute 00158 i |= (op & ((1 << o->bits) - 1)) << o->shift; 00159 (i is the instruction which we are filling in, o is a pointer to 00160 this structure, and op is the opcode value; this assumes twos 00161 complement arithmetic). 00162 00163 If this field is not NULL, then simply call it with the 00164 instruction and the operand value. It will return the new value 00165 of the instruction. If the ERRMSG argument is not NULL, then if 00166 the operand value is illegal, *ERRMSG will be set to a warning 00167 string (the operand will be inserted in any case). If the 00168 operand value is legal, *ERRMSG will be unchanged (most operands 00169 can accept any value). */ 00170 unsigned long (*insert) 00171 (unsigned long instruction, long op, int dialect, const char **errmsg); 00172 00173 /* Extraction function. This is used by the disassembler. To 00174 extract this operand type from an instruction, check this field. 00175 00176 If it is NULL, compute 00177 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 00178 if ((o->flags & PPC_OPERAND_SIGNED) != 0 00179 && (op & (1 << (o->bits - 1))) != 0) 00180 op -= 1 << o->bits; 00181 (i is the instruction, o is a pointer to this structure, and op 00182 is the result; this assumes twos complement arithmetic). 00183 00184 If this field is not NULL, then simply call it with the 00185 instruction value. It will return the value of the operand. If 00186 the INVALID argument is not NULL, *INVALID will be set to 00187 non-zero if this operand type can not actually be extracted from 00188 this operand (i.e., the instruction does not match). If the 00189 operand is valid, *INVALID will not be changed. */ 00190 long (*extract) (unsigned long instruction, int dialect, int *invalid); 00191 00192 /* One bit syntax flags. */ 00193 unsigned long flags; 00194 }; 00195 00196 /* Elements in the table are retrieved by indexing with values from 00197 the operands field of the powerpc_opcodes table. */ 00198 00199 extern const struct powerpc_operand powerpc_operands[]; 00200 00201 /* Values defined for the flags field of a struct powerpc_operand. */ 00202 00203 /* This operand takes signed values. */ 00204 #define PPC_OPERAND_SIGNED (01) 00205 00206 /* This operand takes signed values, but also accepts a full positive 00207 range of values when running in 32 bit mode. That is, if bits is 00208 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 00209 this flag is ignored. */ 00210 #define PPC_OPERAND_SIGNOPT (02) 00211 00212 /* This operand does not actually exist in the assembler input. This 00213 is used to support extended mnemonics such as mr, for which two 00214 operands fields are identical. The assembler should call the 00215 insert function with any op value. The disassembler should call 00216 the extract function, ignore the return value, and check the value 00217 placed in the valid argument. */ 00218 #define PPC_OPERAND_FAKE (04) 00219 00220 /* The next operand should be wrapped in parentheses rather than 00221 separated from this one by a comma. This is used for the load and 00222 store instructions which want their operands to look like 00223 reg,displacement(reg) 00224 */ 00225 #define PPC_OPERAND_PARENS (010) 00226 00227 /* This operand may use the symbolic names for the CR fields, which 00228 are 00229 lt 0 gt 1 eq 2 so 3 un 3 00230 cr0 0 cr1 1 cr2 2 cr3 3 00231 cr4 4 cr5 5 cr6 6 cr7 7 00232 These may be combined arithmetically, as in cr2*4+gt. These are 00233 only supported on the PowerPC, not the POWER. */ 00234 #define PPC_OPERAND_CR (020) 00235 00236 /* This operand names a register. The disassembler uses this to print 00237 register names with a leading 'r'. */ 00238 #define PPC_OPERAND_GPR (040) 00239 00240 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 00241 #define PPC_OPERAND_GPR_0 (0100) 00242 00243 /* This operand names a floating point register. The disassembler 00244 prints these with a leading 'f'. */ 00245 #define PPC_OPERAND_FPR (0200) 00246 00247 /* This operand is a relative branch displacement. The disassembler 00248 prints these symbolically if possible. */ 00249 #define PPC_OPERAND_RELATIVE (0400) 00250 00251 /* This operand is an absolute branch address. The disassembler 00252 prints these symbolically if possible. */ 00253 #define PPC_OPERAND_ABSOLUTE (01000) 00254 00255 /* This operand is optional, and is zero if omitted. This is used for 00256 example, in the optional BF field in the comparison instructions. The 00257 assembler must count the number of operands remaining on the line, 00258 and the number of operands remaining for the opcode, and decide 00259 whether this operand is present or not. The disassembler should 00260 print this operand out only if it is not zero. */ 00261 #define PPC_OPERAND_OPTIONAL (02000) 00262 00263 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 00264 is omitted, then for the next operand use this operand value plus 00265 1, ignoring the next operand field for the opcode. This wretched 00266 hack is needed because the Power rotate instructions can take 00267 either 4 or 5 operands. The disassembler should print this operand 00268 out regardless of the PPC_OPERAND_OPTIONAL field. */ 00269 #define PPC_OPERAND_NEXT (04000) 00270 00271 /* This operand should be regarded as a negative number for the 00272 purposes of overflow checking (i.e., the normal most negative 00273 number is disallowed and one more than the normal most positive 00274 number is allowed). This flag will only be set for a signed 00275 operand. */ 00276 #define PPC_OPERAND_NEGATIVE (010000) 00277 00278 /* This operand names a vector unit register. The disassembler 00279 prints these with a leading 'v'. */ 00280 #define PPC_OPERAND_VR (020000) 00281 00282 /* This operand is for the DS field in a DS form instruction. */ 00283 #define PPC_OPERAND_DS (040000) 00284 00285 /* This operand is for the DQ field in a DQ form instruction. */ 00286 #define PPC_OPERAND_DQ (0100000) 00287 00288 /* The POWER and PowerPC assemblers use a few macros. We keep them 00289 with the operands table for simplicity. The macro table is an 00290 array of struct powerpc_macro. */ 00291 00292 struct powerpc_macro 00293 { 00294 /* The macro name. */ 00295 const char *name; 00296 00297 /* The number of operands the macro takes. */ 00298 unsigned int operands; 00299 00300 /* One bit flags for the opcode. These are used to indicate which 00301 specific processors support the instructions. The values are the 00302 same as those for the struct powerpc_opcode flags field. */ 00303 unsigned long flags; 00304 00305 /* A format string to turn the macro into a normal instruction. 00306 Each %N in the string is replaced with operand number N (zero 00307 based). */ 00308 const char *format; 00309 }; 00310 00311 extern const struct powerpc_macro powerpc_macros[]; 00312 extern const int powerpc_num_macros; 00313 00314 #endif /* PPC_H */
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