00001 /* Opcode table for the ARC. 00002 Copyright 1994, 1995, 1997, 2001, 2002, 2003 00003 Free Software Foundation, Inc. 00004 Contributed by Doug Evans (dje@cygnus.com). 00005 00006 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 00007 the GNU Binutils. 00008 00009 GAS/GDB is free software; you can redistribute it and/or modify 00010 it under the terms of the GNU General Public License as published by 00011 the Free Software Foundation; either version 2, or (at your option) 00012 any later version. 00013 00014 GAS/GDB is distributed in the hope that it will be useful, 00015 but WITHOUT ANY WARRANTY; without even the implied warranty of 00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00017 GNU General Public License for more details. 00018 00019 You should have received a copy of the GNU General Public License 00020 along with GAS or GDB; see the file COPYING. If not, write to 00021 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, 00022 MA 02111-1307, USA. */ 00023 00024 00025 /* List of the various cpu types. 00026 The tables currently use bit masks to say whether the instruction or 00027 whatever is supported by a particular cpu. This lets us have one entry 00028 apply to several cpus. 00029 00030 The `base' cpu must be 0. The cpu type is treated independently of 00031 endianness. The complete `mach' number includes endianness. 00032 These values are internal to opcodes/bfd/binutils/gas. */ 00033 #define ARC_MACH_5 0 00034 #define ARC_MACH_6 1 00035 #define ARC_MACH_7 2 00036 #define ARC_MACH_8 4 00037 00038 /* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ 00039 #define ARC_MACH_BIG 16 00040 00041 /* Mask of number of bits necessary to record cpu type. */ 00042 #define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) 00043 00044 /* Mask of number of bits necessary to record cpu type + endianness. */ 00045 #define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) 00046 00047 /* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ 00048 00049 typedef unsigned int arc_insn; 00050 00051 struct arc_opcode { 00052 char *syntax; /* syntax of insn */ 00053 unsigned long mask, value; /* recognize insn if (op&mask) == value */ 00054 int flags; /* various flag bits */ 00055 00056 /* Values for `flags'. */ 00057 00058 /* Return CPU number, given flag bits. */ 00059 #define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 00060 00061 /* Return MACH number, given flag bits. */ 00062 #define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) 00063 00064 /* First opcode flag bit available after machine mask. */ 00065 #define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) 00066 00067 /* This insn is a conditional branch. */ 00068 #define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) 00069 #define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) 00070 #define SYNTAX_LENGTH (SYNTAX_3OP ) 00071 #define SYNTAX_2OP (SYNTAX_3OP << 1) 00072 #define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) 00073 #define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) 00074 #define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) 00075 00076 #define I(x) (((x) & 31) << 27) 00077 #define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) 00078 #define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) 00079 #define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) 00080 #define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ 00081 00082 /* These values are used to optimize assembly and disassembly. Each insn 00083 is on a list of related insns (same first letter for assembly, same 00084 insn code for disassembly). */ 00085 00086 struct arc_opcode *next_asm; /* Next instr to try during assembly. */ 00087 struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ 00088 00089 /* Macros to create the hash values for the lists. */ 00090 #define ARC_HASH_OPCODE(string) \ 00091 ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) 00092 #define ARC_HASH_ICODE(insn) \ 00093 ((unsigned int) (insn) >> 27) 00094 00095 /* Macros to access `next_asm', `next_dis' so users needn't care about the 00096 underlying mechanism. */ 00097 #define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) 00098 #define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) 00099 }; 00100 00101 /* this is an "insert at front" linked list per Metaware spec 00102 that new definitions override older ones. */ 00103 extern struct arc_opcode *arc_ext_opcodes; 00104 00105 struct arc_operand_value { 00106 char *name; /* eg: "eq" */ 00107 short value; /* eg: 1 */ 00108 unsigned char type; /* index into `arc_operands' */ 00109 unsigned char flags; /* various flag bits */ 00110 00111 /* Values for `flags'. */ 00112 00113 /* Return CPU number, given flag bits. */ 00114 #define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 00115 /* Return MACH number, given flag bits. */ 00116 #define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) 00117 }; 00118 00119 struct arc_ext_operand_value { 00120 struct arc_ext_operand_value *next; 00121 struct arc_operand_value operand; 00122 }; 00123 00124 extern struct arc_ext_operand_value *arc_ext_operands; 00125 00126 struct arc_operand { 00127 /* One of the insn format chars. */ 00128 unsigned char fmt; 00129 00130 /* The number of bits in the operand (may be unused for a modifier). */ 00131 unsigned char bits; 00132 00133 /* How far the operand is left shifted in the instruction, or 00134 the modifier's flag bit (may be unused for a modifier. */ 00135 unsigned char shift; 00136 00137 /* Various flag bits. */ 00138 int flags; 00139 00140 /* Values for `flags'. */ 00141 00142 /* This operand is a suffix to the opcode. */ 00143 #define ARC_OPERAND_SUFFIX 1 00144 00145 /* This operand is a relative branch displacement. The disassembler 00146 prints these symbolically if possible. */ 00147 #define ARC_OPERAND_RELATIVE_BRANCH 2 00148 00149 /* This operand is an absolute branch address. The disassembler 00150 prints these symbolically if possible. */ 00151 #define ARC_OPERAND_ABSOLUTE_BRANCH 4 00152 00153 /* This operand is an address. The disassembler 00154 prints these symbolically if possible. */ 00155 #define ARC_OPERAND_ADDRESS 8 00156 00157 /* This operand is a long immediate value. */ 00158 #define ARC_OPERAND_LIMM 0x10 00159 00160 /* This operand takes signed values. */ 00161 #define ARC_OPERAND_SIGNED 0x20 00162 00163 /* This operand takes signed values, but also accepts a full positive 00164 range of values. That is, if bits is 16, it takes any value from 00165 -0x8000 to 0xffff. */ 00166 #define ARC_OPERAND_SIGNOPT 0x40 00167 00168 /* This operand should be regarded as a negative number for the 00169 purposes of overflow checking (i.e., the normal most negative 00170 number is disallowed and one more than the normal most positive 00171 number is allowed). This flag will only be set for a signed 00172 operand. */ 00173 #define ARC_OPERAND_NEGATIVE 0x80 00174 00175 /* This operand doesn't really exist. The program uses these operands 00176 in special ways. */ 00177 #define ARC_OPERAND_FAKE 0x100 00178 00179 /* separate flags operand for j and jl instructions */ 00180 #define ARC_OPERAND_JUMPFLAGS 0x200 00181 00182 /* allow warnings and errors to be issued after call to insert_xxxxxx */ 00183 #define ARC_OPERAND_WARN 0x400 00184 #define ARC_OPERAND_ERROR 0x800 00185 00186 /* this is a load operand */ 00187 #define ARC_OPERAND_LOAD 0x8000 00188 00189 /* this is a store operand */ 00190 #define ARC_OPERAND_STORE 0x10000 00191 00192 /* Modifier values. */ 00193 /* A dot is required before a suffix. Eg: .le */ 00194 #define ARC_MOD_DOT 0x1000 00195 00196 /* A normal register is allowed (not used, but here for completeness). */ 00197 #define ARC_MOD_REG 0x2000 00198 00199 /* An auxiliary register name is expected. */ 00200 #define ARC_MOD_AUXREG 0x4000 00201 00202 /* Sum of all ARC_MOD_XXX bits. */ 00203 #define ARC_MOD_BITS 0x7000 00204 00205 /* Non-zero if the operand type is really a modifier. */ 00206 #define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) 00207 00208 /* enforce read/write only register restrictions */ 00209 #define ARC_REGISTER_READONLY 0x01 00210 #define ARC_REGISTER_WRITEONLY 0x02 00211 #define ARC_REGISTER_NOSHORT_CUT 0x04 00212 00213 /* Insertion function. This is used by the assembler. To insert an 00214 operand value into an instruction, check this field. 00215 00216 If it is NULL, execute 00217 i |= (p & ((1 << o->bits) - 1)) << o->shift; 00218 (I is the instruction which we are filling in, O is a pointer to 00219 this structure, and OP is the opcode value; this assumes twos 00220 complement arithmetic). 00221 00222 If this field is not NULL, then simply call it with the 00223 instruction and the operand value. It will return the new value 00224 of the instruction. If the ERRMSG argument is not NULL, then if 00225 the operand value is illegal, *ERRMSG will be set to a warning 00226 string (the operand will be inserted in any case). If the 00227 operand value is legal, *ERRMSG will be unchanged. 00228 00229 REG is non-NULL when inserting a register value. */ 00230 00231 arc_insn (*insert) 00232 (arc_insn insn, const struct arc_operand *operand, int mods, 00233 const struct arc_operand_value *reg, long value, const char **errmsg); 00234 00235 /* Extraction function. This is used by the disassembler. To 00236 extract this operand type from an instruction, check this field. 00237 00238 If it is NULL, compute 00239 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 00240 if ((o->flags & ARC_OPERAND_SIGNED) != 0 00241 && (op & (1 << (o->bits - 1))) != 0) 00242 op -= 1 << o->bits; 00243 (I is the instruction, O is a pointer to this structure, and OP 00244 is the result; this assumes twos complement arithmetic). 00245 00246 If this field is not NULL, then simply call it with the 00247 instruction value. It will return the value of the operand. If 00248 the INVALID argument is not NULL, *INVALID will be set to 00249 non-zero if this operand type can not actually be extracted from 00250 this operand (i.e., the instruction does not match). If the 00251 operand is valid, *INVALID will not be changed. 00252 00253 INSN is a pointer to an array of two `arc_insn's. The first element is 00254 the insn, the second is the limm if present. 00255 00256 Operands that have a printable form like registers and suffixes have 00257 their struct arc_operand_value pointer stored in OPVAL. */ 00258 00259 long (*extract) 00260 (arc_insn *insn, const struct arc_operand *operand, int mods, 00261 const struct arc_operand_value **opval, int *invalid); 00262 }; 00263 00264 /* Bits that say what version of cpu we have. These should be passed to 00265 arc_init_opcode_tables. At present, all there is is the cpu type. */ 00266 00267 /* CPU number, given value passed to `arc_init_opcode_tables'. */ 00268 #define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) 00269 /* MACH number, given value passed to `arc_init_opcode_tables'. */ 00270 #define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) 00271 00272 /* Special register values: */ 00273 #define ARC_REG_SHIMM_UPDATE 61 00274 #define ARC_REG_SHIMM 63 00275 #define ARC_REG_LIMM 62 00276 00277 /* Non-zero if REG is a constant marker. */ 00278 #define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) 00279 00280 /* Positions and masks of various fields: */ 00281 #define ARC_SHIFT_REGA 21 00282 #define ARC_SHIFT_REGB 15 00283 #define ARC_SHIFT_REGC 9 00284 #define ARC_MASK_REG 63 00285 00286 /* Delay slot types. */ 00287 #define ARC_DELAY_NONE 0 /* no delay slot */ 00288 #define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ 00289 #define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ 00290 00291 /* Non-zero if X will fit in a signed 9 bit field. */ 00292 #define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) 00293 00294 extern const struct arc_operand arc_operands[]; 00295 extern const int arc_operand_count; 00296 extern struct arc_opcode arc_opcodes[]; 00297 extern const int arc_opcodes_count; 00298 extern const struct arc_operand_value arc_suffixes[]; 00299 extern const int arc_suffixes_count; 00300 extern const struct arc_operand_value arc_reg_names[]; 00301 extern const int arc_reg_names_count; 00302 extern unsigned char arc_operand_map[]; 00303 00304 /* Utility fns in arc-opc.c. */ 00305 int arc_get_opcode_mach (int, int); 00306 00307 /* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ 00308 void arc_opcode_init_tables (int); 00309 void arc_opcode_init_insert (void); 00310 void arc_opcode_init_extract (void); 00311 const struct arc_opcode *arc_opcode_lookup_asm (const char *); 00312 const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); 00313 int arc_opcode_limm_p (long *); 00314 const struct arc_operand_value *arc_opcode_lookup_suffix 00315 (const struct arc_operand *type, int value); 00316 int arc_opcode_supported (const struct arc_opcode *); 00317 int arc_opval_supported (const struct arc_operand_value *); 00318 int arc_limm_fixup_adjust (arc_insn); 00319 int arc_insn_is_j (arc_insn); 00320 int arc_insn_not_jl (arc_insn); 00321 int arc_operand_type (int); 00322 struct arc_operand_value *get_ext_suffix (char *); 00323 int arc_get_noshortcut_flag (void);
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