osprey-gcc-4.2.0/gcc/config/rs6000/rs6000.h File Reference

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Data Types
type	rs6000_cpu_select
type	rs6000_args
Defines
#define	OBJECT_XCOFF   1
#define	OBJECT_ELF   2
#define	OBJECT_PEF   3
#define	OBJECT_MACHO   4
#define	TARGET_ELF   (TARGET_OBJECT_FORMAT == OBJECT_ELF)
#define	TARGET_XCOFF   (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
#define	TARGET_MACOS   (TARGET_OBJECT_FORMAT == OBJECT_PEF)
#define	TARGET_MACHO   (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
#define	TARGET_AIX   0
#define	DOT_SYMBOLS   1
#define	TARGET_CPU_DEFAULT   ((char *)0)
#define	PPC405_ERRATUM77   0
#define	ASM_CPU_SPEC   "%{!mcpu*: \ %{mpower: %{!mpower2: -mpwr}} \ %{mpower2: -mpwrx} \ %{mpowerpc64*: -mppc64} \ %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ %{mno-power: %{!mpowerpc*: -mcom}} \ %{!mno-power: %{!mpower*: %(asm_default)}}} \%{mcpu=common: -mcom} \%{mcpu=power: -mpwr} \%{mcpu=power2: -mpwrx} \%{mcpu=power3: -mppc64} \%{mcpu=power4: -mpower4} \%{mcpu=power5: -mpower4} \%{mcpu=power5+: -mpower4} \%{mcpu=power6: -mpower4 -maltivec} \%{mcpu=powerpc: -mppc} \%{mcpu=rios: -mpwr} \%{mcpu=rios1: -mpwr} \%{mcpu=rios2: -mpwrx} \%{mcpu=rsc: -mpwr} \%{mcpu=rsc1: -mpwr} \%{mcpu=rs64a: -mppc64} \%{mcpu=401: -mppc} \%{mcpu=403: -m403} \%{mcpu=405: -m405} \%{mcpu=405fp: -m405} \%{mcpu=440: -m440} \%{mcpu=440fp: -m440} \%{mcpu=505: -mppc} \%{mcpu=601: -m601} \%{mcpu=602: -mppc} \%{mcpu=603: -mppc} \%{mcpu=603e: -mppc} \%{mcpu=ec603e: -mppc} \%{mcpu=604: -mppc} \%{mcpu=604e: -mppc} \%{mcpu=620: -mppc64} \%{mcpu=630: -mppc64} \%{mcpu=740: -mppc} \%{mcpu=750: -mppc} \%{mcpu=G3: -mppc} \%{mcpu=7400: -mppc -maltivec} \%{mcpu=7450: -mppc -maltivec} \%{mcpu=G4: -mppc -maltivec} \%{mcpu=801: -mppc} \%{mcpu=821: -mppc} \%{mcpu=823: -mppc} \%{mcpu=860: -mppc} \%{mcpu=970: -mpower4 -maltivec} \%{mcpu=G5: -mpower4 -maltivec} \%{mcpu=8540: -me500} \%{maltivec: -maltivec} \-many"
#define	CPP_DEFAULT_SPEC   ""
#define	ASM_DEFAULT_SPEC   ""
#define	SUBTARGET_EXTRA_SPECS
#define	EXTRA_SPECS
#define	TARGET_MFCRF   0
#define	TARGET_POPCNTB   0
#define	TARGET_FPRND   0
#define	TARGET_SECURE_PLT   0
#define	TARGET_32BIT   (! TARGET_64BIT)
#define	HAVE_AS_TLS   0
#define	RS6000_SYMBOL_REF_TLS_P(RTX)   (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
#define	TARGET_DEFAULT   (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
#define	rs6000_cpu_attr   ((enum attr_cpu)rs6000_cpu)
#define	PROCESSOR_COMMON   PROCESSOR_PPC601
#define	PROCESSOR_POWER   PROCESSOR_RIOS1
#define	PROCESSOR_POWERPC   PROCESSOR_PPC604
#define	PROCESSOR_POWERPC64   PROCESSOR_RS64A
#define	PROCESSOR_DEFAULT   PROCESSOR_RIOS1
#define	PROCESSOR_DEFAULT64   PROCESSOR_RS64A
#define	ASSEMBLER_DIALECT   (TARGET_NEW_MNEMONICS ? 1 : 0)
#define	OPTION_DEFAULT_SPECS
#define	TARGET_DEBUG_STACK   rs6000_debug_stack
#define	TARGET_DEBUG_ARG   rs6000_debug_arg
#define	MASK_ALIGN_POWER   0x00000000
#define	MASK_ALIGN_NATURAL   0x00000001
#define	TARGET_ALIGN_NATURAL   (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
#define	TARGET_LONG_DOUBLE_128   (rs6000_long_double_type_size == 128)
#define	TARGET_IEEEQUAD   rs6000_ieeequad
#define	TARGET_ALTIVEC_ABI   rs6000_altivec_abi
#define	TARGET_SPE_ABI   0
#define	TARGET_SPE   0
#define	TARGET_E500   0
#define	TARGET_ISEL   0
#define	TARGET_FPRS   1
#define	TARGET_E500_SINGLE   0
#define	TARGET_E500_DOUBLE   0
#define	TARGET_NO_LWSYNC   TARGET_E500
#define	OVERRIDE_OPTIONS   rs6000_override_options (TARGET_CPU_DEFAULT)
#define	OPTIMIZATION_OPTIONS(LEVEL, SIZE)   optimization_options(LEVEL,SIZE)
#define	CAN_DEBUG_WITHOUT_FP
#define	REGISTER_TARGET_PRAGMAS()
#define	TARGET_CPU_CPP_BUILTINS()   rs6000_cpu_cpp_builtins (pfile)
#define	RS6000_CPU_CPP_ENDIAN_BUILTINS()
#define	PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)
#define	BITS_BIG_ENDIAN   1
#define	BYTES_BIG_ENDIAN   1
#define	WORDS_BIG_ENDIAN   1
#define	MAX_BITS_PER_WORD   64
#define	UNITS_PER_WORD   (! TARGET_POWERPC64 ? 4 : 8)
#define	MIN_UNITS_PER_WORD   4
#define	UNITS_PER_FP_WORD   8
#define	UNITS_PER_ALTIVEC_WORD   16
#define	UNITS_PER_SPE_WORD   8
#define	PTRDIFF_TYPE   "int"
#define	SIZE_TYPE   "long unsigned int"
#define	WCHAR_TYPE   "short unsigned int"
#define	WCHAR_TYPE_SIZE   16
#define	SHORT_TYPE_SIZE   16
#define	INT_TYPE_SIZE   32
#define	LONG_TYPE_SIZE   (TARGET_32BIT ? 32 : 64)
#define	LONG_LONG_TYPE_SIZE   64
#define	FLOAT_TYPE_SIZE   32
#define	DOUBLE_TYPE_SIZE   64
#define	LONG_DOUBLE_TYPE_SIZE   rs6000_long_double_type_size
#define	LIBGCC2_LONG_DOUBLE_TYPE_SIZE   64
#define	WIDEST_HARDWARE_FP_SIZE   64
#define	POINTER_SIZE   (TARGET_32BIT ? 32 : 64)
#define	PARM_BOUNDARY   (TARGET_32BIT ? 32 : 64)
#define	STACK_BOUNDARY   ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
#define	FUNCTION_BOUNDARY   32
#define	BIGGEST_ALIGNMENT   128
#define	LOCAL_ALIGNMENT(TYPE, ALIGN)
#define	EMPTY_FIELD_BOUNDARY   32
#define	STRUCTURE_SIZE_BOUNDARY   8
#define	MEMBER_TYPE_FORCES_BLK(FIELD, MODE)
#define	PCC_BITFIELD_TYPE_MATTERS   1
#define	CONSTANT_ALIGNMENT(EXP, ALIGN)
#define	DATA_ALIGNMENT(TYPE, ALIGN)
#define	STRICT_ALIGNMENT   0
#define	SLOW_UNALIGNED_ACCESS(MODE, ALIGN)
#define	FIRST_PSEUDO_REGISTER   114
#define	PRE_GCC3_DWARF_FRAME_REGISTERS   77
#define	DWARF_FRAME_REGISTERS   ((FIRST_PSEUDO_REGISTER - 1) + 32)
#define	DWARF_REG_TO_UNWIND_COLUMN(r)   ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
#define	DBX_REGISTER_NUMBER(REGNO)   rs6000_dbx_register_number (REGNO)
#define	DWARF_FRAME_REGNUM(REGNO)   (REGNO)
#define	DWARF2_FRAME_REG_OUT(REGNO, FOR_EH)
#define	FIXED_REGISTERS
#define	CALL_USED_REGISTERS
#define	CALL_REALLY_USED_REGISTERS
#define	MQ_REGNO   64
#define	CR0_REGNO   68
#define	CR1_REGNO   69
#define	CR2_REGNO   70
#define	CR3_REGNO   71
#define	CR4_REGNO   72
#define	MAX_CR_REGNO   75
#define	XER_REGNO   76
#define	FIRST_ALTIVEC_REGNO   77
#define	LAST_ALTIVEC_REGNO   108
#define	TOTAL_ALTIVEC_REGS   (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
#define	VRSAVE_REGNO   109
#define	VSCR_REGNO   110
#define	SPE_ACC_REGNO   111
#define	SPEFSCR_REGNO   112
#define	FIRST_SAVED_ALTIVEC_REGNO   (FIRST_ALTIVEC_REGNO+20)
#define	FIRST_SAVED_FP_REGNO   (14+32)
#define	FIRST_SAVED_GP_REGNO   13
#define	MAYBE_R2_AVAILABLE   2,
#define	MAYBE_R2_FIXED
#define	REG_ALLOC_ORDER
#define	FP_REGNO_P(N)   ((N) >= 32 && (N) <= 63)
#define	CR_REGNO_P(N)   ((N) >= 68 && (N) <= 75)
#define	CR_REGNO_NOT_CR0_P(N)   ((N) >= 69 && (N) <= 75)
#define	INT_REGNO_P(N)   ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
#define	SPE_SIMD_REGNO_P(N)   ((N) <= 31)
#define	XER_REGNO_P(N)   ((N) == XER_REGNO)
#define	ALTIVEC_REGNO_P(N)   ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
#define	HARD_REGNO_NREGS(REGNO, MODE)   rs6000_hard_regno_nregs ((REGNO), (MODE))
#define	HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE)
#define	ALTIVEC_VECTOR_MODE(MODE)
#define	SPE_VECTOR_MODE(MODE)
#define	UNITS_PER_SIMD_WORD
#define	HARD_REGNO_MODE_OK(REGNO, MODE)   rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
#define	MODES_TIEABLE_P(MODE1, MODE2)
#define	HARD_REGNO_RENAME_OK(SRC, DST)   (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
#define	REGISTER_MOVE_COST   rs6000_register_move_cost
#define	MEMORY_MOVE_COST   rs6000_memory_move_cost
#define	BRANCH_COST   3
#define	LOGICAL_OP_NON_SHORT_CIRCUIT   0
#define	FIXED_SCRATCH   (TARGET_SPE ? 14 : 11)
#define	CONDITIONAL_REGISTER_USAGE   rs6000_conditional_register_usage ()
#define	STACK_POINTER_REGNUM   1
#define	HARD_FRAME_POINTER_REGNUM   31
#define	FRAME_POINTER_REGNUM   113
#define	FRAME_POINTER_REQUIRED   0
#define	ARG_POINTER_REGNUM   67
#define	STATIC_CHAIN_REGNUM   11
#define	LINK_REGISTER_REGNUM   65
#define	COUNT_REGISTER_REGNUM   66
#define	N_REG_CLASSES   (int) LIM_REG_CLASSES
#define	REG_CLASS_NAMES
#define	REG_CLASS_CONTENTS
#define	REGNO_REG_CLASS(REGNO)
#define	INDEX_REG_CLASS   GENERAL_REGS
#define	BASE_REG_CLASS   BASE_REGS
#define	PREFERRED_RELOAD_CLASS(X, CLASS)
#define	SECONDARY_RELOAD_CLASS(CLASS, MODE, IN)   rs6000_secondary_reload_class (CLASS, MODE, IN)
#define	SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)
#define	CLASS_MAX_NREGS(CLASS, MODE)
#define	CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)
#define	STACK_GROWS_DOWNWARD
#define	DWARF_CIE_DATA_ALIGNMENT   (-((int) (TARGET_32BIT ? 4 : 8)))
#define	FRAME_GROWS_DOWNWARD   (flag_stack_protect != 0)
#define	RS6000_REG_SAVE
#define	RS6000_SAVE_AREA
#define	RS6000_SAVE_TOC
#define	RS6000_ALIGN(n, a)   (((n) + (a) - 1) & ~((a) - 1))
#define	STARTING_FRAME_OFFSET
#define	STACK_DYNAMIC_OFFSET(FUNDECL)
#define	FIRST_PARM_OFFSET(FNDECL)   RS6000_SAVE_AREA
#define	ARG_POINTER_CFA_OFFSET(FNDECL)   0
#define	REG_PARM_STACK_SPACE(FNDECL)   RS6000_REG_SAVE
#define	OUTGOING_REG_PARM_STACK_SPACE
#define	STACK_POINTER_OFFSET   RS6000_SAVE_AREA
#define	ACCUMULATE_OUTGOING_ARGS   1
#define	RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE)   0
#define	FUNCTION_VALUE(VALTYPE, FUNC)   rs6000_function_value ((VALTYPE), (FUNC))
#define	LIBCALL_VALUE(MODE)   rs6000_libcall_value ((MODE))
#define	DRAFT_V4_STRUCT_RET   0
#define	DEFAULT_PCC_STRUCT_RETURN   0
#define	STACK_SAVEAREA_MODE(LEVEL)
#define	GP_ARG_MIN_REG   3
#define	GP_ARG_MAX_REG   10
#define	GP_ARG_NUM_REG   (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
#define	FP_ARG_MIN_REG   33
#define	FP_ARG_AIX_MAX_REG   45
#define	FP_ARG_V4_MAX_REG   40
#define	FP_ARG_MAX_REG
#define	FP_ARG_NUM_REG   (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
#define	ALTIVEC_ARG_MIN_REG   (FIRST_ALTIVEC_REGNO + 2)
#define	ALTIVEC_ARG_MAX_REG   (ALTIVEC_ARG_MIN_REG + 11)
#define	ALTIVEC_ARG_NUM_REG   (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
#define	GP_ARG_RETURN   GP_ARG_MIN_REG
#define	FP_ARG_RETURN   FP_ARG_MIN_REG
#define	ALTIVEC_ARG_RETURN   (FIRST_ALTIVEC_REGNO + 2)
#define	CALL_NORMAL   0x00000000
#define	CALL_V4_CLEAR_FP_ARGS   0x00000002
#define	CALL_V4_SET_FP_ARGS   0x00000004
#define	CALL_LONG   0x00000008
#define	CALL_LIBCALL   0x00000010
#define	WORLD_SAVE_P(INFO)   0
#define	FUNCTION_VALUE_REGNO_P(N)
#define	FUNCTION_ARG_REGNO_P(N)
#define	INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS)   init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
#define	INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME)   init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
#define	INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME)   init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
#define	FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)   function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
#define	FUNCTION_ARG(CUM, MODE, TYPE, NAMED)   function_arg (&CUM, MODE, TYPE, NAMED)
#define	FUNCTION_ARG_PADDING(MODE, TYPE)   function_arg_padding (MODE, TYPE)
#define	FUNCTION_ARG_BOUNDARY(MODE, TYPE)   function_arg_boundary (MODE, TYPE)
#define	EXPAND_BUILTIN_VA_START(valist, nextarg)   rs6000_va_start (valist, nextarg)
#define	PAD_VARARGS_DOWN   (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
#define	FUNCTION_PROFILER(FILE, LABELNO)   output_function_profiler ((FILE), (LABELNO));
#define	EXIT_IGNORE_STACK   1
#define	EPILOGUE_USES(REGNO)
#define	TRAMPOLINE_SIZE   rs6000_trampoline_size ()
#define	INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT)   rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
#define	RETURN_ADDRESS_OFFSET
#define	RETURN_ADDR_RTX(COUNT, FRAME)   (rs6000_return_addr (COUNT, FRAME))
#define	ELIMINABLE_REGS
#define	CAN_ELIMINATE(FROM, TO)
#define	INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)   ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
#define	HAVE_PRE_DECREMENT   1
#define	HAVE_PRE_INCREMENT   1
#define	REGNO_OK_FOR_INDEX_P(REGNO)
#define	REGNO_OK_FOR_BASE_P(REGNO)
#define	MAX_REGS_PER_ADDRESS   2
#define	CONSTANT_ADDRESS_P(X)
#define	LEGITIMATE_CONSTANT_P(X)
#define	EASY_VECTOR_15(n)   ((n) >= -16 && (n) <= 15)
#define	EASY_VECTOR_15_ADD_SELF(n)
#define	REG_OK_STRICT_FLAG   0
#define	INT_REG_OK_FOR_INDEX_P(X, STRICT)
#define	INT_REG_OK_FOR_BASE_P(X, STRICT)
#define	REG_OK_FOR_INDEX_P(X)   INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
#define	REG_OK_FOR_BASE_P(X)   INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
#define	GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)
#define	LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
#define	LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
#define	GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
#define	RS6000_PIC_OFFSET_TABLE_REGNUM   30
#define	PIC_OFFSET_TABLE_REGNUM   (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
#define	TOC_REGISTER   (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
#define	CASE_VECTOR_MODE   SImode
#define	CASE_VECTOR_PC_RELATIVE   1
#define	DEFAULT_SIGNED_CHAR   0
#define	MAX_FIXED_MODE_SIZE   GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
#define	MOVE_MAX   (! TARGET_POWERPC64 ? 4 : 8)
#define	MAX_MOVE_MAX   8
#define	SLOW_BYTE_ACCESS   1
#define	WORD_REGISTER_OPERATIONS
#define	LOAD_EXTEND_OP(MODE)   ZERO_EXTEND
#define	SHORT_IMMEDIATES_SIGN_EXTEND
#define	TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)   1
#define	CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)   ((VALUE) = ((MODE) == SImode ? 32 : 64))
#define	CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)   ((VALUE) = -1)
#define	Pmode   (TARGET_32BIT ? SImode : DImode)
#define	STACK_SIZE_MODE   (TARGET_32BIT ? SImode : DImode)
#define	FUNCTION_MODE   SImode
#define	NO_FUNCTION_CSE
#define	SHIFT_COUNT_TRUNCATED   (TARGET_POWER ? 1 : 0)
#define	SELECT_CC_MODE(OP, X, Y)
#define	REVERSIBLE_CC_MODE(MODE)   1
#define	REVERSE_CONDITION(CODE, MODE)   rs6000_reverse_condition (MODE, CODE)
#define	ASM_COMMENT_START   " #"
#define	ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN)
#define	RS6000_WEAK   0
#define	ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET)
#define	TARGET_ASM_FILE_START   rs6000_file_start
#define	ASM_APP_ON   ""
#define	ASM_APP_OFF   ""
#define	REGISTER_NAMES
#define	ADDITIONAL_REGISTER_NAMES
#define	RS6000_CALL_GLUE   "cror 31,31,31"
#define	ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)
#define	ASM_OUTPUT_ALIGN(FILE, LOG)
#define	INCOMING_RETURN_ADDR_RTX   gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
#define	DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
#define	EH_RETURN_DATA_REGNO(N)   ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
#define	EH_RETURN_STACKADJ_RTX   gen_rtx_REG (Pmode, 10)
#define	PRINT_OPERAND(FILE, X, CODE)   print_operand (FILE, X, CODE)
#define	PRINT_OPERAND_PUNCT_VALID_P(CODE)   ((CODE) == '.' || (CODE) == '&')
#define	PRINT_OPERAND_ADDRESS(FILE, ADDR)   print_operand_address (FILE, ADDR)
#define	opaque_V2SI_type_node   (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
#define	opaque_V2SF_type_node   (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
#define	opaque_p_V2SI_type_node   (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
#define	opaque_V4SI_type_node   (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
#define	V16QI_type_node   (rs6000_builtin_types[RS6000_BTI_V16QI])
#define	V2SI_type_node   (rs6000_builtin_types[RS6000_BTI_V2SI])
#define	V2SF_type_node   (rs6000_builtin_types[RS6000_BTI_V2SF])
#define	V4HI_type_node   (rs6000_builtin_types[RS6000_BTI_V4HI])
#define	V4SI_type_node   (rs6000_builtin_types[RS6000_BTI_V4SI])
#define	V4SF_type_node   (rs6000_builtin_types[RS6000_BTI_V4SF])
#define	V8HI_type_node   (rs6000_builtin_types[RS6000_BTI_V8HI])
#define	unsigned_V16QI_type_node   (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
#define	unsigned_V8HI_type_node   (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
#define	unsigned_V4SI_type_node   (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
#define	bool_char_type_node   (rs6000_builtin_types[RS6000_BTI_bool_char])
#define	bool_short_type_node   (rs6000_builtin_types[RS6000_BTI_bool_short])
#define	bool_int_type_node   (rs6000_builtin_types[RS6000_BTI_bool_int])
#define	pixel_type_node   (rs6000_builtin_types[RS6000_BTI_pixel])
#define	bool_V16QI_type_node   (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
#define	bool_V8HI_type_node   (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
#define	bool_V4SI_type_node   (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
#define	pixel_V8HI_type_node   (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
#define	long_integer_type_internal_node   (rs6000_builtin_types[RS6000_BTI_long])
#define	long_unsigned_type_internal_node   (rs6000_builtin_types[RS6000_BTI_unsigned_long])
#define	intQI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_INTQI])
#define	uintQI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_UINTQI])
#define	intHI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_INTHI])
#define	uintHI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_UINTHI])
#define	intSI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_INTSI])
#define	uintSI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_UINTSI])
#define	float_type_internal_node   (rs6000_builtin_types[RS6000_BTI_float])
#define	void_type_internal_node   (rs6000_builtin_types[RS6000_BTI_void])
Typedefs
typedef struct rs6000_args	CUMULATIVE_ARGS
Enumerations
enum	processor_type {   PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6, PROCESSOR_I386,   PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, PROCESSOR_K6,   PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_max, PROCESSOR_M88100,   PROCESSOR_M88110, PROCESSOR_M88000, PROCESSOR_700, PROCESSOR_7100,   PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_8000, PROCESSOR_RIOS1,   PROCESSOR_RIOS2, PROCESSOR_RS64A, PROCESSOR_MPCCORE, PROCESSOR_PPC403,   PROCESSOR_PPC405, PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604,   PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750,   PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_SH1, PROCESSOR_SH2,   PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4, PROCESSOR_SH5,   PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900, PROCESSOR_R6000,   PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120,   PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,   PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000, PROCESSOR_R4KC,   PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000, PROCESSOR_SB1,   PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8, PROCESSOR_SUPERSPARC,   PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, PROCESSOR_HYPERSPARC,   PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701, PROCESSOR_V9,   PROCESSOR_ULTRASPARC, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,   PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,   PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,   PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,   PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,   PROCESSOR_SB1, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,   PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,   PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,   PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,   PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,   PROCESSOR_SB1, PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6,   PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO,   PROCESSOR_K6, PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_max,   PROCESSOR_M88100, PROCESSOR_M88110, PROCESSOR_M88000, PROCESSOR_700,   PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_8000,   PROCESSOR_RIOS1, PROCESSOR_RIOS2, PROCESSOR_RS64A, PROCESSOR_MPCCORE,   PROCESSOR_PPC403, PROCESSOR_PPC405, PROCESSOR_PPC601, PROCESSOR_PPC603,   PROCESSOR_PPC604, PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630,   PROCESSOR_PPC750, PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_SH1,   PROCESSOR_SH2, PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4,   PROCESSOR_SH5, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,   PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,   PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,   PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,   PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,   PROCESSOR_SB1, PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8,   PROCESSOR_SUPERSPARC, PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934,   PROCESSOR_HYPERSPARC, PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701,   PROCESSOR_V9, PROCESSOR_ULTRASPARC, PROCESSOR_DEFAULT, PROCESSOR_R3000,   PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100,   PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600,   PROCESSOR_R4650, PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500,   PROCESSOR_R8000, PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC,   PROCESSOR_SR71000, PROCESSOR_SB1, PROCESSOR_DEFAULT, PROCESSOR_R3000,   PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100,   PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600,   PROCESSOR_R4650, PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500,   PROCESSOR_R8000, PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC,   PROCESSOR_SR71000, PROCESSOR_SB1, PROCESSOR_EV4, PROCESSOR_EV5,   PROCESSOR_EV6, PROCESSOR_MAX, ARM_CORE, PROCESSOR_I386,   PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, PROCESSOR_K6,   PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_K8, PROCESSOR_NOCONA,   PROCESSOR_max, PROCESSOR_ITANIUM, PROCESSOR_ITANIUM2, PROCESSOR_max,   PROCESSOR_DEFAULT, PROCESSOR_IQ2000, PROCESSOR_IQ10, PROCESSOR_DEFAULT,   PROCESSOR_4KC, PROCESSOR_5KC, PROCESSOR_20KC, PROCESSOR_M4K,   PROCESSOR_R3000, PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000,   PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4130,   PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,   PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R7000, PROCESSOR_R8000,   PROCESSOR_R9000, PROCESSOR_SB1, PROCESSOR_SR71000, PROCESSOR_700,   PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_7300,   PROCESSOR_8000, PROCESSOR_RIOS1, PROCESSOR_RIOS2, PROCESSOR_RS64A,   PROCESSOR_MPCCORE, PROCESSOR_PPC403, PROCESSOR_PPC405, PROCESSOR_PPC440,   PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604, PROCESSOR_PPC604e,   PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750, PROCESSOR_PPC7400,   PROCESSOR_PPC7450, PROCESSOR_PPC8540, PROCESSOR_POWER4, PROCESSOR_POWER5,   PROCESSOR_9672_G5, PROCESSOR_9672_G6, PROCESSOR_2064_Z900, PROCESSOR_2084_Z990,   PROCESSOR_max, PROCESSOR_SH1, PROCESSOR_SH2, PROCESSOR_SH2E,   PROCESSOR_SH2A, PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4,   PROCESSOR_SH4A, PROCESSOR_SH5, PROCESSOR_V7, PROCESSOR_CYPRESS,   PROCESSOR_V8, PROCESSOR_SUPERSPARC, PROCESSOR_SPARCLITE, PROCESSOR_F930,   PROCESSOR_F934, PROCESSOR_HYPERSPARC, PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET,   PROCESSOR_TSC701, PROCESSOR_V9, PROCESSOR_ULTRASPARC, PROCESSOR_ULTRASPARC3,   PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6, PROCESSOR_MAX,   ARM_CORE, PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM,   PROCESSOR_PENTIUMPRO, PROCESSOR_K6, PROCESSOR_ATHLON, PROCESSOR_PENTIUM4,   PROCESSOR_K8, PROCESSOR_NOCONA, PROCESSOR_GENERIC32, PROCESSOR_GENERIC64,   PROCESSOR_AMDFAM10, PROCESSOR_max, PROCESSOR_ITANIUM, PROCESSOR_ITANIUM2,   PROCESSOR_max, PROCESSOR_DEFAULT, PROCESSOR_IQ2000, PROCESSOR_IQ10,   PROCESSOR_R3000, PROCESSOR_4KC, PROCESSOR_4KP, PROCESSOR_5KC,   PROCESSOR_5KF, PROCESSOR_20KC, PROCESSOR_24K, PROCESSOR_24KX,   PROCESSOR_M4K, PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000,   PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4130,   PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,   PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R7000, PROCESSOR_R8000,   PROCESSOR_R9000, PROCESSOR_SB1, PROCESSOR_SB1A, PROCESSOR_SR71000,   PROCESSOR_MAX, PROCESSOR_MN10300, PROCESSOR_AM33, PROCESSOR_AM33_2,   PROCESSOR_MS1_64_001, PROCESSOR_MS1_16_002, PROCESSOR_MS1_16_003, PROCESSOR_MS2,   PROCESSOR_700, PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200,   PROCESSOR_7300, PROCESSOR_8000, PROCESSOR_RIOS1, PROCESSOR_RIOS2,   PROCESSOR_RS64A, PROCESSOR_MPCCORE, PROCESSOR_PPC403, PROCESSOR_PPC405,   PROCESSOR_PPC440, PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604,   PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750,   PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_PPC8540, PROCESSOR_POWER4,   PROCESSOR_POWER5, PROCESSOR_9672_G5, PROCESSOR_9672_G6, PROCESSOR_2064_Z900,   PROCESSOR_2084_Z990, PROCESSOR_2094_Z9_109, PROCESSOR_max, PROCESSOR_SH1,   PROCESSOR_SH2, PROCESSOR_SH2E, PROCESSOR_SH2A, PROCESSOR_SH3,   PROCESSOR_SH3E, PROCESSOR_SH4, PROCESSOR_SH4A, PROCESSOR_SH5,   PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8, PROCESSOR_SUPERSPARC,   PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, PROCESSOR_HYPERSPARC,   PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701, PROCESSOR_V9,   PROCESSOR_ULTRASPARC, PROCESSOR_ULTRASPARC3, PROCESSOR_NIAGARA }
enum	rs6000_dependence_cost {   max_dep_latency = 1000, no_dep_costly, all_deps_costly, true_store_to_load_dep_costly,   store_to_load_dep_costly, max_dep_latency = 1000, no_dep_costly, all_deps_costly,   true_store_to_load_dep_costly, store_to_load_dep_costly }
enum	rs6000_nop_insertion {   sched_finish_regroup_exact = 1000, sched_finish_pad_groups, sched_finish_none, sched_finish_regroup_exact = 1000,   sched_finish_pad_groups, sched_finish_none }
enum	group_termination { current_group, previous_group, current_group, previous_group }
enum	reg_class {   NO_REGS, R2, R0_1, INDEX_REGS,   BASE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS,   CR_REGS, Q_REGS, SPECIAL_REGS, ACCUM0_REGS,   ACCUM_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R24_REG, R25_REG, R27_REG,   GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, LPCOUNT_REG, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, FPU_REGS, LO_REGS,   STACK_REG, BASE_REGS, HI_REGS, CC_REG,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REG, POINTER_X_REGS, POINTER_Y_REGS, POINTER_Z_REGS,   STACK_REG, BASE_POINTER_REGS, POINTER_REGS, ADDW_REGS,   SIMPLE_LD_REGS, LD_REGS, NO_LD_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0R1_REGS,   R2R3_REGS, EXT_LOW_REGS, EXT_REGS, ADDR_REGS,   INDEX_REGS, BK_REG, SP_REG, RC_REG,   COUNTER_REGS, INT_REGS, GENERAL_REGS, DP_REG,   ST_REG, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, S_REGS, INDEX_REGS, SP_REGS,   A_REGS, SI_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   REPEAT_REGS, CR_REGS, ACCUM_REGS, OTHER_FLAG_REGS,   F0_REGS, F1_REGS, BR_FLAG_REGS, FLAG_REGS,   EVEN_REGS, GPR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, A0H_REG, A0L_REG, A0_REG,   A1H_REG, ACCUM_HIGH_REGS, A1L_REG, ACCUM_LOW_REGS,   A1_REG, ACCUM_REGS, X_REG, X_OR_ACCUM_LOW_REGS,   X_OR_ACCUM_REGS, YH_REG, YH_OR_ACCUM_HIGH_REGS, X_OR_YH_REGS,   YL_REG, YL_OR_ACCUM_LOW_REGS, X_OR_YL_REGS, X_OR_Y_REGS,   Y_REG, ACCUM_OR_Y_REGS, PH_REG, X_OR_PH_REGS,   PL_REG, PL_OR_ACCUM_LOW_REGS, X_OR_PL_REGS, YL_OR_PL_OR_ACCUM_LOW_REGS,   P_REG, ACCUM_OR_P_REGS, YL_OR_P_REGS, ACCUM_LOW_OR_YL_OR_P_REGS,   Y_OR_P_REGS, ACCUM_Y_OR_P_REGS, NO_FRAME_Y_ADDR_REGS, Y_ADDR_REGS,   ACCUM_LOW_OR_Y_ADDR_REGS, ACCUM_OR_Y_ADDR_REGS, X_OR_Y_ADDR_REGS, Y_OR_Y_ADDR_REGS,   P_OR_Y_ADDR_REGS, NON_HIGH_YBASE_ELIGIBLE_REGS, YBASE_ELIGIBLE_REGS, J_REG,   J_OR_DAU_16_BIT_REGS, BMU_REGS, NOHIGH_NON_ADDR_REGS, NON_ADDR_REGS,   SLOW_MEM_LOAD_REGS, NOHIGH_NON_YBASE_REGS, NO_ACCUM_NON_YBASE_REGS, NON_YBASE_REGS,   YBASE_VIRT_REGS, ACCUM_LOW_OR_YBASE_REGS, ACCUM_OR_YBASE_REGS, X_OR_YBASE_REGS,   Y_OR_YBASE_REGS, ACCUM_LOW_YL_PL_OR_YBASE_REGS, P_OR_YBASE_REGS, ACCUM_Y_P_OR_YBASE_REGS,   Y_ADDR_OR_YBASE_REGS, YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS, YBASE_OR_YBASE_ELIGIBLE_REGS, NO_HIGH_ALL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG,   MULTIPLY_64_REG, LOW_REGS, HIGH_REGS, REAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,   MAC_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ADDR_REGS, DATA_REGS, FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, AREG, DREG,   CREG, BREG, SIREG, DIREG,   AD_REGS, Q_REGS, NON_Q_REGS, INDEX_REGS,   LEGACY_REGS, GENERAL_REGS, FP_TOP_REG, FP_SECOND_REG,   FLOAT_REGS, SSE_REGS, MMX_REGS, FP_TOP_SSE_REGS,   FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS, INT_SSE_REGS,   FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,   FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS,   ADDL_REGS, GR_REGS, FR_REGS, GR_AND_BR_REGS,   GR_AND_FR_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, D_REGS, X_REGS,   Y_REGS, SP_REGS, DA_REGS, DB_REGS,   Z_REGS, D8_REGS, Q_REGS, D_OR_X_REGS,   D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS, A_REGS,   X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS, A_OR_D_REGS,   A_OR_SP_REGS, H_REGS, S_REGS, D_OR_S_REGS,   X_OR_S_REGS, Y_OR_S_REGS, SP_OR_S_REGS, D_OR_X_OR_S_REGS,   D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS, A_OR_S_REGS, D_OR_A_OR_S_REGS,   TMP_REGS, D_OR_A_OR_TMP_REGS, G_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, DATA_REGS, ADDR_REGS,   FP_REGS, GENERAL_REGS, DATA_OR_FP_REGS, ADDR_OR_FP_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, AP_REG,   XRF_REGS, GENERAL_REGS, AGRF_REGS, XGRF_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, ONLYR1_REGS,   LRW_REGS, GENERAL_REGS, C_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, REMAINDER_REG,   HIMULT_REG, SYSTEM_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, DATA_REGS, ADDRESS_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,   ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,   EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS,   SP_OR_ADDRESS_OR_EXTENDED_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0,   FLOAT_REGS, FP_REGS, GEN_AND_FP_REGS, FRAME_POINTER_REG,   STACK_POINTER_REG, GEN_AND_MEM_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS,   FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,   FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, MUL_REGS,   GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, OUT_REGS,   STD_REGS, ARG_REGS, SRC_REGS, DST_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0_REGS,   R15_REGS, BASE_REGS, GENERAL_REGS, FP_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, BASE_REGS,   GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS, VRSAVE_REGS,   NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,   LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,   CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, ADDR_REGS, GENERAL_REGS,   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REGS, PR_REGS,   T_REGS, MAC_REGS, FPUL_REGS, SIBCALL_REGS,   GENERAL_REGS, FP0_REGS, FP_REGS, DF_REGS,   FPSCR_REGS, GENERAL_FP_REGS, TARGET_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, M16_NA_REGS, M16_REGS,   T_REG, M16_T_REGS, GR_REGS, FP_REGS,   HI_REG, LO_REG, HILO_REG, MD_REGS,   COP0_REGS, COP2_REGS, COP3_REGS, HI_AND_GR_REGS,   LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS,   COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS,   ST_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,   EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REGS, R1_REGS,   TWO_REGS, R2_REGS, EIGHT_REGS, R8_REGS,   ICALL_REGS, GENERAL_REGS, CARRY_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, BR_REGS, FP_REGS, ACC_REG,   SP_REG, RL_REGS, GR_REGS, AR_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,   M16_REGS, T_REG, M16_T_REGS, GR_REGS,   FP_REGS, HI_REG, LO_REG, HILO_REG,   MD_REGS, COP0_REGS, COP2_REGS, COP3_REGS,   HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS,   COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS,   ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, M16_NA_REGS, M16_REGS, T_REG,   M16_T_REGS, GR_REGS, FP_REGS, HI_REG,   LO_REG, HILO_REG, MD_REGS, COP0_REGS,   COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,   HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,   COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R2,   R0_1, INDEX_REGS, BASE_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, LR0_REGS, GENERAL_REGS,   BP_REGS, FC_REGS, CR_REGS, Q_REGS,   SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R24_REG,   R25_REG, R27_REG, GENERAL_REGS, FLOAT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   FPU_REGS, LO_REGS, STACK_REG, BASE_REGS,   HI_REGS, CC_REG, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REG, POINTER_X_REGS,   POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG, BASE_POINTER_REGS,   POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS, LD_REGS,   NO_LD_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R0R1_REGS, R2R3_REGS, EXT_LOW_REGS,   EXT_REGS, ADDR_REGS, INDEX_REGS, BK_REG,   SP_REG, RC_REG, COUNTER_REGS, INT_REGS,   GENERAL_REGS, DP_REG, ST_REG, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, FLOAT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, S_REGS,   INDEX_REGS, SP_REGS, A_REGS, SI_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, REPEAT_REGS, CR_REGS,   ACCUM_REGS, OTHER_FLAG_REGS, F0_REGS, F1_REGS,   BR_FLAG_REGS, FLAG_REGS, EVEN_REGS, GPR_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, A0H_REG,   A0L_REG, A0_REG, A1H_REG, ACCUM_HIGH_REGS,   A1L_REG, ACCUM_LOW_REGS, A1_REG, ACCUM_REGS,   X_REG, X_OR_ACCUM_LOW_REGS, X_OR_ACCUM_REGS, YH_REG,   YH_OR_ACCUM_HIGH_REGS, X_OR_YH_REGS, YL_REG, YL_OR_ACCUM_LOW_REGS,   X_OR_YL_REGS, X_OR_Y_REGS, Y_REG, ACCUM_OR_Y_REGS,   PH_REG, X_OR_PH_REGS, PL_REG, PL_OR_ACCUM_LOW_REGS,   X_OR_PL_REGS, YL_OR_PL_OR_ACCUM_LOW_REGS, P_REG, ACCUM_OR_P_REGS,   YL_OR_P_REGS, ACCUM_LOW_OR_YL_OR_P_REGS, Y_OR_P_REGS, ACCUM_Y_OR_P_REGS,   NO_FRAME_Y_ADDR_REGS, Y_ADDR_REGS, ACCUM_LOW_OR_Y_ADDR_REGS, ACCUM_OR_Y_ADDR_REGS,   X_OR_Y_ADDR_REGS, Y_OR_Y_ADDR_REGS, P_OR_Y_ADDR_REGS, NON_HIGH_YBASE_ELIGIBLE_REGS,   YBASE_ELIGIBLE_REGS, J_REG, J_OR_DAU_16_BIT_REGS, BMU_REGS,   NOHIGH_NON_ADDR_REGS, NON_ADDR_REGS, SLOW_MEM_LOAD_REGS, NOHIGH_NON_YBASE_REGS,   NO_ACCUM_NON_YBASE_REGS, NON_YBASE_REGS, YBASE_VIRT_REGS, ACCUM_LOW_OR_YBASE_REGS,   ACCUM_OR_YBASE_REGS, X_OR_YBASE_REGS, Y_OR_YBASE_REGS, ACCUM_LOW_YL_PL_OR_YBASE_REGS,   P_OR_YBASE_REGS, ACCUM_Y_P_OR_YBASE_REGS, Y_ADDR_OR_YBASE_REGS, YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS,   YBASE_OR_YBASE_ELIGIBLE_REGS, NO_HIGH_ALL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, MULTIPLY_32_REG, MULTIPLY_64_REG, LOW_REGS,   HIGH_REGS, REAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, ADDR_REGS, DATA_REGS,   FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   AREG, DREG, CREG, BREG,   SIREG, DIREG, AD_REGS, Q_REGS,   NON_Q_REGS, INDEX_REGS, LEGACY_REGS, GENERAL_REGS,   FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, SSE_REGS,   MMX_REGS, FP_TOP_SSE_REGS, FP_SECOND_SSE_REGS, FLOAT_SSE_REGS,   FLOAT_INT_REGS, INT_SSE_REGS, FLOAT_INT_SSE_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, FP_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GLOBAL_REGS,   LOCAL_REGS, LOCAL_OR_GLOBAL_REGS, FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, PR_REGS, BR_REGS,   AR_M_REGS, AR_I_REGS, ADDL_REGS, GR_REGS,   FR_REGS, GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, CARRY_REG, ACCUM_REGS,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   D_REGS, X_REGS, Y_REGS, SP_REGS,   DA_REGS, DB_REGS, Z_REGS, D8_REGS,   Q_REGS, D_OR_X_REGS, D_OR_Y_REGS, D_OR_SP_REGS,   X_OR_Y_REGS, A_REGS, X_OR_SP_REGS, Y_OR_SP_REGS,   X_OR_Y_OR_D_REGS, A_OR_D_REGS, A_OR_SP_REGS, H_REGS,   S_REGS, D_OR_S_REGS, X_OR_S_REGS, Y_OR_S_REGS,   SP_OR_S_REGS, D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS,   A_OR_S_REGS, D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS,   G_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   DATA_REGS, ADDR_REGS, FP_REGS, GENERAL_REGS,   DATA_OR_FP_REGS, ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS,   AGRF_REGS, XGRF_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, ONLYR1_REGS, LRW_REGS, GENERAL_REGS,   C_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, REMAINDER_REG, HIMULT_REG, SYSTEM_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,   ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,   DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, EXTENDED_REGS, DATA_OR_EXTENDED_REGS,   ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,   FLOAT_REG0, LONG_FLOAT_REG0, FLOAT_REGS, FP_REGS,   GEN_AND_FP_REGS, FRAME_POINTER_REG, STACK_POINTER_REG, GEN_AND_MEM_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,   GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,   SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,   GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS,   NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, OUT_REGS, STD_REGS, ARG_REGS,   SRC_REGS, DST_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R0_REGS, R15_REGS, BASE_REGS,   GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, BASE_REGS, GENERAL_REGS, FLOAT_REGS,   ALTIVEC_REGS, VRSAVE_REGS, NON_SPECIAL_REGS, MQ_REGS,   LINK_REGS, CTR_REGS, LINK_OR_CTR_REGS, SPECIAL_REGS,   SPEC_OR_GEN_REGS, CR0_REGS, CR_REGS, NON_FLOAT_REGS,   XER_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ADDR_REGS, GENERAL_REGS, FP_REGS, ADDR_FP_REGS,   GENERAL_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REGS, PR_REGS, T_REGS, MAC_REGS,   FPUL_REGS, SIBCALL_REGS, GENERAL_REGS, FP0_REGS,   FP_REGS, DF_REGS, FPSCR_REGS, GENERAL_FP_REGS,   TARGET_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   M16_NA_REGS, M16_REGS, T_REG, M16_T_REGS,   GR_REGS, FP_REGS, HI_REG, LO_REG,   HILO_REG, MD_REGS, COP0_REGS, COP2_REGS,   COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS,   HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,   ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, FPCC_REGS, I64_REGS,   GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, GENERAL_OR_FP_REGS,   GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REGS, R1_REGS, TWO_REGS, R2_REGS,   EIGHT_REGS, R8_REGS, ICALL_REGS, GENERAL_REGS,   CARRY_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, BR_REGS,   FP_REGS, ACC_REG, SP_REG, RL_REGS,   GR_REGS, AR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, M16_NA_REGS, M16_REGS, T_REG,   M16_T_REGS, GR_REGS, FP_REGS, HI_REG,   LO_REG, HILO_REG, MD_REGS, COP0_REGS,   COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,   HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,   COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,   M16_REGS, T_REG, M16_T_REGS, GR_REGS,   FP_REGS, HI_REG, LO_REG, HILO_REG,   MD_REGS, COP0_REGS, COP2_REGS, COP3_REGS,   HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS,   COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS,   ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R0_REG, R24_REG, R25_REG,   R27_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, FPA_REGS,   CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,   LO_REGS, STACK_REG, BASE_REGS, HI_REGS,   CC_REG, VFPCC_REG, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REG, POINTER_X_REGS,   POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG, BASE_POINTER_REGS,   POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS, LD_REGS,   NO_LD_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, IREGS, BREGS, LREGS,   MREGS, CIRCREGS, DAGREGS, EVEN_AREGS,   ODD_AREGS, AREGS, CCREGS, EVEN_DREGS,   ODD_DREGS, DREGS, PREGS_CLOBBERED, PREGS,   DPREGS, MOST_REGS, PROLOGUE_REGS, NON_A_CC_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0R1_REGS,   R2R3_REGS, EXT_LOW_REGS, EXT_REGS, ADDR_REGS,   INDEX_REGS, BK_REG, SP_REG, RC_REG,   COUNTER_REGS, INT_REGS, GENERAL_REGS, DP_REG,   ST_REG, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG,   MULTIPLY_64_REG, LOW_REGS, HIGH_REGS, REAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, ICC_REGS,   FCC_REGS, CC_REGS, ICR_REGS, FCR_REGS,   CR_REGS, LCR_REG, LR_REG, GR8_REGS,   GR9_REGS, GR89_REGS, FDPIC_REGS, FDPIC_FPTR_REGS,   FDPIC_CALL_REGS, SPR_REGS, QUAD_ACC_REGS, EVEN_ACC_REGS,   ACC_REGS, ACCG_REGS, QUAD_FPR_REGS, FEVEN_REGS,   FPR_REGS, QUAD_REGS, EVEN_REGS, GPR_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, COUNTER_REGS,   SOURCE_REGS, DESTINATION_REGS, GENERAL_REGS, MAC_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, AREG,   DREG, CREG, BREG, SIREG,   DIREG, AD_REGS, Q_REGS, NON_Q_REGS,   INDEX_REGS, LEGACY_REGS, GENERAL_REGS, FP_TOP_REG,   FP_SECOND_REG, FLOAT_REGS, SSE_REGS, MMX_REGS,   FP_TOP_SSE_REGS, FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS,   INT_SSE_REGS, FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, PR_REGS, BR_REGS,   AR_M_REGS, AR_I_REGS, ADDL_REGS, GR_REGS,   FR_REGS, GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, DPH_REGS, DPL_REGS,   DP_REGS, SP_REGS, IPH_REGS, IPL_REGS,   IP_REGS, DP_SP_REGS, PTR_REGS, NONPTR_REGS,   NONSP_REGS, GENERAL_REGS, ALL_REGS = GENERAL_REGS, LIM_REG_CLASSES,   NO_REGS, GR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, D_REGS,   X_REGS, Y_REGS, SP_REGS, DA_REGS,   DB_REGS, Z_REGS, D8_REGS, Q_REGS,   D_OR_X_REGS, D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS,   A_REGS, X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS,   A_OR_D_REGS, A_OR_SP_REGS, H_REGS, S_REGS,   D_OR_S_REGS, X_OR_S_REGS, Y_OR_S_REGS, Z_OR_S_REGS,   SP_OR_S_REGS, D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS,   A_OR_S_REGS, D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS,   G_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   DATA_REGS, ADDR_REGS, FP_REGS, GENERAL_REGS,   DATA_OR_FP_REGS, ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, ONLYR1_REGS, LRW_REGS, GENERAL_REGS,   C_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   M16_NA_REGS, M16_REGS, T_REG, M16_T_REGS,   PIC_FN_ADDR_REG, LEA_REGS, GR_REGS, FP_REGS,   HI_REG, LO_REG, MD_REGS, COP0_REGS,   COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,   HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,   ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, REMAINDER_REG,   HIMULT_REG, SYSTEM_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,   DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, EXTENDED_REGS, DATA_OR_EXTENDED_REGS,   ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, FP_REGS,   FP_ACC_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0,   FLOAT_REGS, LONG_REGS, FP_REGS, GEN_AND_FP_REGS,   FRAME_POINTER_REG, STACK_POINTER_REG, GEN_AND_MEM_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,   FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,   GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,   SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS,   FPU_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   BASE_REGS, GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS,   VRSAVE_REGS, VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,   NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,   LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,   CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, CC_REGS, ADDR_REGS,   GENERAL_REGS, ACCESS_REGS, ADDR_CC_REGS, GENERAL_CC_REGS,   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REGS, PR_REGS,   T_REGS, MAC_REGS, FPUL_REGS, SIBCALL_REGS,   GENERAL_REGS, FP0_REGS, FP_REGS, DF_HI_REGS,   DF_REGS, FPSCR_REGS, GENERAL_FP_REGS, TARGET_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, FPCC_REGS,   I64_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS,   GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R0_REGS, R1_REGS, TWO_REGS,   R2_REGS, EIGHT_REGS, R8_REGS, ICALL_REGS,   GENERAL_REGS, CARRY_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   BR_REGS, FP_REGS, ACC_REG, SP_REG,   RL_REGS, GR_REGS, AR_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REG, R24_REG,   R25_REG, R27_REG, GENERAL_REGS, FLOAT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS,   IWMMXT_REGS, LO_REGS, STACK_REG, BASE_REGS,   HI_REGS, CC_REG, VFPCC_REG, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0_REG,   POINTER_X_REGS, POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG,   BASE_POINTER_REGS, POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS,   LD_REGS, NO_LD_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, IREGS, BREGS,   LREGS, MREGS, CIRCREGS, DAGREGS,   EVEN_AREGS, ODD_AREGS, AREGS, CCREGS,   EVEN_DREGS, ODD_DREGS, DREGS, FDPIC_REGS,   FDPIC_FPTR_REGS, PREGS_CLOBBERED, PREGS, IPREGS,   DPREGS, MOST_REGS, LT_REGS, LC_REGS,   LB_REGS, PROLOGUE_REGS, NON_A_CC_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0R1_REGS, R2R3_REGS,   EXT_LOW_REGS, EXT_REGS, ADDR_REGS, INDEX_REGS,   BK_REG, SP_REG, RC_REG, COUNTER_REGS,   INT_REGS, GENERAL_REGS, DP_REG, ST_REG,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, MOF_REGS,   CC0_REGS, SPECIAL_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, LO_REGS, HI_REGS,   HILO_REGS, NOSP_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG, MULTIPLY_64_REG,   LOW_REGS, HIGH_REGS, REAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, ICC_REGS, FCC_REGS,   CC_REGS, ICR_REGS, FCR_REGS, CR_REGS,   LCR_REG, LR_REG, GR8_REGS, GR9_REGS,   GR89_REGS, FDPIC_REGS, FDPIC_FPTR_REGS, FDPIC_CALL_REGS,   SPR_REGS, QUAD_ACC_REGS, EVEN_ACC_REGS, ACC_REGS,   ACCG_REGS, QUAD_FPR_REGS, FEVEN_REGS, FPR_REGS,   QUAD_REGS, EVEN_REGS, GPR_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, COUNTER_REGS, SOURCE_REGS,   DESTINATION_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, AREG, DREG,   CREG, BREG, SIREG, DIREG,   AD_REGS, Q_REGS, NON_Q_REGS, INDEX_REGS,   LEGACY_REGS, GENERAL_REGS, FP_TOP_REG, FP_SECOND_REG,   FLOAT_REGS, SSE_REGS, MMX_REGS, FP_TOP_SSE_REGS,   FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS, INT_SSE_REGS,   FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS,   ADDL_REGS, GR_REGS, FP_REGS, FR_REGS,   GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, SP_REGS, FB_REGS, SB_REGS,   CR_REGS, R0_REGS, R1_REGS, R2_REGS,   R3_REGS, R02_REGS, HL_REGS, QI_REGS,   R23_REGS, R03_REGS, DI_REGS, A0_REGS,   A1_REGS, A_REGS, AD_REGS, PS_REGS,   SI_REGS, HI_REGS, RA_REGS, GENERAL_REGS,   FLG_REGS, HC_REGS, MEM_REGS, R02_A_MEM_REGS,   A_HL_MEM_REGS, R1_R3_A_MEM_REGS, R03_MEM_REGS, A_HI_MEM_REGS,   A_AD_CR_MEM_SI_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, D_REGS, X_REGS,   Y_REGS, SP_REGS, DA_REGS, DB_REGS,   Z_REGS, D8_REGS, Q_REGS, D_OR_X_REGS,   D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS, A_REGS,   X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS, A_OR_D_REGS,   A_OR_SP_REGS, H_REGS, S_REGS, D_OR_S_REGS,   X_OR_S_REGS, Y_OR_S_REGS, Z_OR_S_REGS, SP_OR_S_REGS,   D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS, A_OR_S_REGS,   D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS, G_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,   ADDR_REGS, FP_REGS, GENERAL_REGS, DATA_OR_FP_REGS,   ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ONLYR1_REGS, LRW_REGS, GENERAL_REGS, C_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,   M16_REGS, T_REG, M16_T_REGS, PIC_FN_ADDR_REG,   V1_REG, LEA_REGS, GR_REGS, FP_REGS,   HI_REG, LO_REG, MD_REGS, COP0_REGS,   COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,   HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,   ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, DSP_ACC_REGS,   ACC_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, REMAINDER_REG, HIMULT_REG, SYSTEM_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,   ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,   EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS,   SP_OR_ADDRESS_OR_EXTENDED_REGS, FP_REGS, FP_ACC_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,   FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,   GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,   SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS,   FPU_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   BASE_REGS, GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS,   VRSAVE_REGS, VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,   NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,   LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,   CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, CC_REGS, ADDR_REGS,   GENERAL_REGS, ACCESS_REGS, ADDR_CC_REGS, GENERAL_CC_REGS,   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, G16_REGS, G32_REGS,   T32_REGS, HI_REG, LO_REG, CE_REGS,   CN_REG, LC_REG, SC_REG, SP_REGS,   CR_REGS, CP1_REGS, CP2_REGS, CP3_REGS,   CPA_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REGS, PR_REGS, T_REGS, MAC_REGS,   FPUL_REGS, SIBCALL_REGS, GENERAL_REGS, FP0_REGS,   FP_REGS, DF_HI_REGS, DF_REGS, FPSCR_REGS,   GENERAL_FP_REGS, GENERAL_DF_REGS, TARGET_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, FPCC_REGS, I64_REGS,   GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, GENERAL_OR_FP_REGS,   GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REGS, R1_REGS, TWO_REGS, R2_REGS,   EIGHT_REGS, R8_REGS, ICALL_REGS, GENERAL_REGS,   CARRY_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, BR_REGS,   FP_REGS, ACC_REG, SP_REG, RL_REGS,   GR_REGS, AR_REGS, ALL_REGS, LIM_REG_CLASSES }
enum	rs6000_abi {   ABI_NONE, ABI_AIX, ABI_AIX_NODESC, ABI_V4,   ABI_DARWIN, ABI_NONE, ABI_AIX, ABI_AIX_NODESC,   ABI_V4, ABI_DARWIN, ABI_NONE, ABI_AIX,   ABI_V4, ABI_DARWIN, ABI_NONE, ABI_AIX,   ABI_V4, ABI_DARWIN }
enum	rs6000_builtins {   ALTIVEC_BUILTIN_ST_INTERNAL_4si, ALTIVEC_BUILTIN_LD_INTERNAL_4si, ALTIVEC_BUILTIN_ST_INTERNAL_8hi, ALTIVEC_BUILTIN_LD_INTERNAL_8hi,   ALTIVEC_BUILTIN_ST_INTERNAL_16qi, ALTIVEC_BUILTIN_LD_INTERNAL_16qi, ALTIVEC_BUILTIN_ST_INTERNAL_4sf, ALTIVEC_BUILTIN_LD_INTERNAL_4sf,   ALTIVEC_BUILTIN_VADDUBM, ALTIVEC_BUILTIN_VADDUHM, ALTIVEC_BUILTIN_VADDUWM, ALTIVEC_BUILTIN_VADDFP,   ALTIVEC_BUILTIN_VADDCUW, ALTIVEC_BUILTIN_VADDUBS, ALTIVEC_BUILTIN_VADDSBS, ALTIVEC_BUILTIN_VADDUHS,   ALTIVEC_BUILTIN_VADDSHS, ALTIVEC_BUILTIN_VADDUWS, ALTIVEC_BUILTIN_VADDSWS, ALTIVEC_BUILTIN_VAND,   ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VAVGUB, ALTIVEC_BUILTIN_VAVGSB, ALTIVEC_BUILTIN_VAVGUH,   ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW, ALTIVEC_BUILTIN_VAVGSW, ALTIVEC_BUILTIN_VCFUX,   ALTIVEC_BUILTIN_VCFSX, ALTIVEC_BUILTIN_VCTSXS, ALTIVEC_BUILTIN_VCTUXS, ALTIVEC_BUILTIN_VCMPBFP,   ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQFP,   ALTIVEC_BUILTIN_VCMPGEFP, ALTIVEC_BUILTIN_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTUH,   ALTIVEC_BUILTIN_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTFP,   ALTIVEC_BUILTIN_VEXPTEFP, ALTIVEC_BUILTIN_VLOGEFP, ALTIVEC_BUILTIN_VMADDFP, ALTIVEC_BUILTIN_VMAXUB,   ALTIVEC_BUILTIN_VMAXSB, ALTIVEC_BUILTIN_VMAXUH, ALTIVEC_BUILTIN_VMAXSH, ALTIVEC_BUILTIN_VMAXUW,   ALTIVEC_BUILTIN_VMAXSW, ALTIVEC_BUILTIN_VMAXFP, ALTIVEC_BUILTIN_VMHADDSHS, ALTIVEC_BUILTIN_VMHRADDSHS,   ALTIVEC_BUILTIN_VMLADDUHM, ALTIVEC_BUILTIN_VMRGHB, ALTIVEC_BUILTIN_VMRGHH, ALTIVEC_BUILTIN_VMRGHW,   ALTIVEC_BUILTIN_VMRGLB, ALTIVEC_BUILTIN_VMRGLH, ALTIVEC_BUILTIN_VMRGLW, ALTIVEC_BUILTIN_VMSUMUBM,   ALTIVEC_BUILTIN_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMUHS,   ALTIVEC_BUILTIN_VMSUMSHS, ALTIVEC_BUILTIN_VMINUB, ALTIVEC_BUILTIN_VMINSB, ALTIVEC_BUILTIN_VMINUH,   ALTIVEC_BUILTIN_VMINSH, ALTIVEC_BUILTIN_VMINUW, ALTIVEC_BUILTIN_VMINSW, ALTIVEC_BUILTIN_VMINFP,   ALTIVEC_BUILTIN_VMULEUB, ALTIVEC_BUILTIN_VMULESB, ALTIVEC_BUILTIN_VMULEUH, ALTIVEC_BUILTIN_VMULESH,   ALTIVEC_BUILTIN_VMULOUB, ALTIVEC_BUILTIN_VMULOSB, ALTIVEC_BUILTIN_VMULOUH, ALTIVEC_BUILTIN_VMULOSH,   ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR, ALTIVEC_BUILTIN_VOR, ALTIVEC_BUILTIN_VSEL_4SI,   ALTIVEC_BUILTIN_VSEL_4SF, ALTIVEC_BUILTIN_VSEL_8HI, ALTIVEC_BUILTIN_VSEL_16QI, ALTIVEC_BUILTIN_VPERM_4SI,   ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI, ALTIVEC_BUILTIN_VPERM_16QI, ALTIVEC_BUILTIN_VPKUHUM,   ALTIVEC_BUILTIN_VPKUWUM, ALTIVEC_BUILTIN_VPKPX, ALTIVEC_BUILTIN_VPKUHSS, ALTIVEC_BUILTIN_VPKSHSS,   ALTIVEC_BUILTIN_VPKUWSS, ALTIVEC_BUILTIN_VPKSWSS, ALTIVEC_BUILTIN_VPKUHUS, ALTIVEC_BUILTIN_VPKSHUS,   ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS, ALTIVEC_BUILTIN_VREFP, ALTIVEC_BUILTIN_VRFIM,   ALTIVEC_BUILTIN_VRFIN, ALTIVEC_BUILTIN_VRFIP, ALTIVEC_BUILTIN_VRFIZ, ALTIVEC_BUILTIN_VRLB,   ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW, ALTIVEC_BUILTIN_VRSQRTEFP, ALTIVEC_BUILTIN_VSLB,   ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW, ALTIVEC_BUILTIN_VSL, ALTIVEC_BUILTIN_VSLO,   ALTIVEC_BUILTIN_VSPLTB, ALTIVEC_BUILTIN_VSPLTH, ALTIVEC_BUILTIN_VSPLTW, ALTIVEC_BUILTIN_VSPLTISB,   ALTIVEC_BUILTIN_VSPLTISH, ALTIVEC_BUILTIN_VSPLTISW, ALTIVEC_BUILTIN_VSRB, ALTIVEC_BUILTIN_VSRH,   ALTIVEC_BUILTIN_VSRW, ALTIVEC_BUILTIN_VSRAB, ALTIVEC_BUILTIN_VSRAH, ALTIVEC_BUILTIN_VSRAW,   ALTIVEC_BUILTIN_VSR, ALTIVEC_BUILTIN_VSRO, ALTIVEC_BUILTIN_VSUBUBM, ALTIVEC_BUILTIN_VSUBUHM,   ALTIVEC_BUILTIN_VSUBUWM, ALTIVEC_BUILTIN_VSUBFP, ALTIVEC_BUILTIN_VSUBCUW, ALTIVEC_BUILTIN_VSUBUBS,   ALTIVEC_BUILTIN_VSUBSBS, ALTIVEC_BUILTIN_VSUBUHS, ALTIVEC_BUILTIN_VSUBSHS, ALTIVEC_BUILTIN_VSUBUWS,   ALTIVEC_BUILTIN_VSUBSWS, ALTIVEC_BUILTIN_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SHS,   ALTIVEC_BUILTIN_VSUM2SWS, ALTIVEC_BUILTIN_VSUMSWS, ALTIVEC_BUILTIN_VXOR, ALTIVEC_BUILTIN_VSLDOI_16QI,   ALTIVEC_BUILTIN_VSLDOI_8HI, ALTIVEC_BUILTIN_VSLDOI_4SI, ALTIVEC_BUILTIN_VSLDOI_4SF, ALTIVEC_BUILTIN_VUPKHSB,   ALTIVEC_BUILTIN_VUPKHPX, ALTIVEC_BUILTIN_VUPKHSH, ALTIVEC_BUILTIN_VUPKLSB, ALTIVEC_BUILTIN_VUPKLPX,   ALTIVEC_BUILTIN_VUPKLSH, ALTIVEC_BUILTIN_MTVSCR, ALTIVEC_BUILTIN_MFVSCR, ALTIVEC_BUILTIN_DSSALL,   ALTIVEC_BUILTIN_DSS, ALTIVEC_BUILTIN_LVSL, ALTIVEC_BUILTIN_LVSR, ALTIVEC_BUILTIN_DSTT,   ALTIVEC_BUILTIN_DSTST, ALTIVEC_BUILTIN_DSTSTT, ALTIVEC_BUILTIN_DST, ALTIVEC_BUILTIN_LVEBX,   ALTIVEC_BUILTIN_LVEHX, ALTIVEC_BUILTIN_LVEWX, ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_LVX,   ALTIVEC_BUILTIN_STVX, ALTIVEC_BUILTIN_STVEBX, ALTIVEC_BUILTIN_STVEHX, ALTIVEC_BUILTIN_STVEWX,   ALTIVEC_BUILTIN_STVXL, ALTIVEC_BUILTIN_VCMPBFP_P, ALTIVEC_BUILTIN_VCMPEQFP_P, ALTIVEC_BUILTIN_VCMPEQUB_P,   ALTIVEC_BUILTIN_VCMPEQUH_P, ALTIVEC_BUILTIN_VCMPEQUW_P, ALTIVEC_BUILTIN_VCMPGEFP_P, ALTIVEC_BUILTIN_VCMPGTFP_P,   ALTIVEC_BUILTIN_VCMPGTSB_P, ALTIVEC_BUILTIN_VCMPGTSH_P, ALTIVEC_BUILTIN_VCMPGTSW_P, ALTIVEC_BUILTIN_VCMPGTUB_P,   ALTIVEC_BUILTIN_VCMPGTUH_P, ALTIVEC_BUILTIN_VCMPGTUW_P, ALTIVEC_BUILTIN_ABSS_V4SI, ALTIVEC_BUILTIN_ABSS_V8HI,   ALTIVEC_BUILTIN_ABSS_V16QI, ALTIVEC_BUILTIN_ABS_V4SI, ALTIVEC_BUILTIN_ABS_V4SF, ALTIVEC_BUILTIN_ABS_V8HI,   ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_ST_INTERNAL_4si, ALTIVEC_BUILTIN_LD_INTERNAL_4si, ALTIVEC_BUILTIN_ST_INTERNAL_8hi,   ALTIVEC_BUILTIN_LD_INTERNAL_8hi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi, ALTIVEC_BUILTIN_LD_INTERNAL_16qi, ALTIVEC_BUILTIN_ST_INTERNAL_4sf,   ALTIVEC_BUILTIN_LD_INTERNAL_4sf, ALTIVEC_BUILTIN_VADDUBM, ALTIVEC_BUILTIN_VADDUHM, ALTIVEC_BUILTIN_VADDUWM,   ALTIVEC_BUILTIN_VADDFP, ALTIVEC_BUILTIN_VADDCUW, ALTIVEC_BUILTIN_VADDUBS, ALTIVEC_BUILTIN_VADDSBS,   ALTIVEC_BUILTIN_VADDUHS, ALTIVEC_BUILTIN_VADDSHS, ALTIVEC_BUILTIN_VADDUWS, ALTIVEC_BUILTIN_VADDSWS,   ALTIVEC_BUILTIN_VAND, ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VAVGUB, ALTIVEC_BUILTIN_VAVGSB,   ALTIVEC_BUILTIN_VAVGUH, ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW, ALTIVEC_BUILTIN_VAVGSW,   ALTIVEC_BUILTIN_VCFUX, ALTIVEC_BUILTIN_VCFSX, ALTIVEC_BUILTIN_VCTSXS, ALTIVEC_BUILTIN_VCTUXS,   ALTIVEC_BUILTIN_VCMPBFP, ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUW,   ALTIVEC_BUILTIN_VCMPEQFP, ALTIVEC_BUILTIN_VCMPGEFP, ALTIVEC_BUILTIN_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTSB,   ALTIVEC_BUILTIN_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTSW,   ALTIVEC_BUILTIN_VCMPGTFP, ALTIVEC_BUILTIN_VEXPTEFP, ALTIVEC_BUILTIN_VLOGEFP, ALTIVEC_BUILTIN_VMADDFP,   ALTIVEC_BUILTIN_VMAXUB, ALTIVEC_BUILTIN_VMAXSB, ALTIVEC_BUILTIN_VMAXUH, ALTIVEC_BUILTIN_VMAXSH,   ALTIVEC_BUILTIN_VMAXUW, ALTIVEC_BUILTIN_VMAXSW, ALTIVEC_BUILTIN_VMAXFP, ALTIVEC_BUILTIN_VMHADDSHS,   ALTIVEC_BUILTIN_VMHRADDSHS, ALTIVEC_BUILTIN_VMLADDUHM, ALTIVEC_BUILTIN_VMRGHB, ALTIVEC_BUILTIN_VMRGHH,   ALTIVEC_BUILTIN_VMRGHW, ALTIVEC_BUILTIN_VMRGLB, ALTIVEC_BUILTIN_VMRGLH, ALTIVEC_BUILTIN_VMRGLW,   ALTIVEC_BUILTIN_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMSHM,   ALTIVEC_BUILTIN_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMSHS, ALTIVEC_BUILTIN_VMINUB, ALTIVEC_BUILTIN_VMINSB,   ALTIVEC_BUILTIN_VMINUH, ALTIVEC_BUILTIN_VMINSH, ALTIVEC_BUILTIN_VMINUW, ALTIVEC_BUILTIN_VMINSW,   ALTIVEC_BUILTIN_VMINFP, ALTIVEC_BUILTIN_VMULEUB, ALTIVEC_BUILTIN_VMULESB, ALTIVEC_BUILTIN_VMULEUH,   ALTIVEC_BUILTIN_VMULESH, ALTIVEC_BUILTIN_VMULOUB, ALTIVEC_BUILTIN_VMULOSB, ALTIVEC_BUILTIN_VMULOUH,   ALTIVEC_BUILTIN_VMULOSH, ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR, ALTIVEC_BUILTIN_VOR,   ALTIVEC_BUILTIN_VSEL_4SI, ALTIVEC_BUILTIN_VSEL_4SF, ALTIVEC_BUILTIN_VSEL_8HI, ALTIVEC_BUILTIN_VSEL_16QI,   ALTIVEC_BUILTIN_VPERM_4SI, ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI, ALTIVEC_BUILTIN_VPERM_16QI,   ALTIVEC_BUILTIN_VPKUHUM, ALTIVEC_BUILTIN_VPKUWUM, ALTIVEC_BUILTIN_VPKPX, ALTIVEC_BUILTIN_VPKUHSS,   ALTIVEC_BUILTIN_VPKSHSS, ALTIVEC_BUILTIN_VPKUWSS, ALTIVEC_BUILTIN_VPKSWSS, ALTIVEC_BUILTIN_VPKUHUS,   ALTIVEC_BUILTIN_VPKSHUS, ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS, ALTIVEC_BUILTIN_VREFP,   ALTIVEC_BUILTIN_VRFIM, ALTIVEC_BUILTIN_VRFIN, ALTIVEC_BUILTIN_VRFIP, ALTIVEC_BUILTIN_VRFIZ,   ALTIVEC_BUILTIN_VRLB, ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW, ALTIVEC_BUILTIN_VRSQRTEFP,   ALTIVEC_BUILTIN_VSLB, ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW, ALTIVEC_BUILTIN_VSL,   ALTIVEC_BUILTIN_VSLO, ALTIVEC_BUILTIN_VSPLTB, ALTIVEC_BUILTIN_VSPLTH, ALTIVEC_BUILTIN_VSPLTW,   ALTIVEC_BUILTIN_VSPLTISB, ALTIVEC_BUILTIN_VSPLTISH, ALTIVEC_BUILTIN_VSPLTISW, ALTIVEC_BUILTIN_VSRB,   ALTIVEC_BUILTIN_VSRH, ALTIVEC_BUILTIN_VSRW, ALTIVEC_BUILTIN_VSRAB, ALTIVEC_BUILTIN_VSRAH,   ALTIVEC_BUILTIN_VSRAW, ALTIVEC_BUILTIN_VSR, ALTIVEC_BUILTIN_VSRO, ALTIVEC_BUILTIN_VSUBUBM,   ALTIVEC_BUILTIN_VSUBUHM, ALTIVEC_BUILTIN_VSUBUWM, ALTIVEC_BUILTIN_VSUBFP, ALTIVEC_BUILTIN_VSUBCUW,   ALTIVEC_BUILTIN_VSUBUBS, ALTIVEC_BUILTIN_VSUBSBS, ALTIVEC_BUILTIN_VSUBUHS, ALTIVEC_BUILTIN_VSUBSHS,   ALTIVEC_BUILTIN_VSUBUWS, ALTIVEC_BUILTIN_VSUBSWS, ALTIVEC_BUILTIN_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4SBS,   ALTIVEC_BUILTIN_VSUM4SHS, ALTIVEC_BUILTIN_VSUM2SWS, ALTIVEC_BUILTIN_VSUMSWS, ALTIVEC_BUILTIN_VXOR,   ALTIVEC_BUILTIN_VSLDOI_16QI, ALTIVEC_BUILTIN_VSLDOI_8HI, ALTIVEC_BUILTIN_VSLDOI_4SI, ALTIVEC_BUILTIN_VSLDOI_4SF,   ALTIVEC_BUILTIN_VUPKHSB, ALTIVEC_BUILTIN_VUPKHPX, ALTIVEC_BUILTIN_VUPKHSH, ALTIVEC_BUILTIN_VUPKLSB,   ALTIVEC_BUILTIN_VUPKLPX, ALTIVEC_BUILTIN_VUPKLSH, ALTIVEC_BUILTIN_MTVSCR, ALTIVEC_BUILTIN_MFVSCR,   ALTIVEC_BUILTIN_DSSALL, ALTIVEC_BUILTIN_DSS, ALTIVEC_BUILTIN_LVSL, ALTIVEC_BUILTIN_LVSR,   ALTIVEC_BUILTIN_DSTT, ALTIVEC_BUILTIN_DSTST, ALTIVEC_BUILTIN_DSTSTT, ALTIVEC_BUILTIN_DST,   ALTIVEC_BUILTIN_LVEBX, ALTIVEC_BUILTIN_LVEHX, ALTIVEC_BUILTIN_LVEWX, ALTIVEC_BUILTIN_LVXL,   ALTIVEC_BUILTIN_LVX, ALTIVEC_BUILTIN_STVX, ALTIVEC_BUILTIN_STVEBX, ALTIVEC_BUILTIN_STVEHX,   ALTIVEC_BUILTIN_STVEWX, ALTIVEC_BUILTIN_STVXL, ALTIVEC_BUILTIN_VCMPBFP_P, ALTIVEC_BUILTIN_VCMPEQFP_P,   ALTIVEC_BUILTIN_VCMPEQUB_P, ALTIVEC_BUILTIN_VCMPEQUH_P, ALTIVEC_BUILTIN_VCMPEQUW_P, ALTIVEC_BUILTIN_VCMPGEFP_P,   ALTIVEC_BUILTIN_VCMPGTFP_P, ALTIVEC_BUILTIN_VCMPGTSB_P, ALTIVEC_BUILTIN_VCMPGTSH_P, ALTIVEC_BUILTIN_VCMPGTSW_P,   ALTIVEC_BUILTIN_VCMPGTUB_P, ALTIVEC_BUILTIN_VCMPGTUH_P, ALTIVEC_BUILTIN_VCMPGTUW_P, ALTIVEC_BUILTIN_ABSS_V4SI,   ALTIVEC_BUILTIN_ABSS_V8HI, ALTIVEC_BUILTIN_ABSS_V16QI, ALTIVEC_BUILTIN_ABS_V4SI, ALTIVEC_BUILTIN_ABS_V4SF,   ALTIVEC_BUILTIN_ABS_V8HI, ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_ST_INTERNAL_4si, ALTIVEC_BUILTIN_LD_INTERNAL_4si,   ALTIVEC_BUILTIN_ST_INTERNAL_8hi, ALTIVEC_BUILTIN_LD_INTERNAL_8hi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi, ALTIVEC_BUILTIN_LD_INTERNAL_16qi,   ALTIVEC_BUILTIN_ST_INTERNAL_4sf, ALTIVEC_BUILTIN_LD_INTERNAL_4sf, ALTIVEC_BUILTIN_VADDUBM, ALTIVEC_BUILTIN_VADDUHM,   ALTIVEC_BUILTIN_VADDUWM, ALTIVEC_BUILTIN_VADDFP, ALTIVEC_BUILTIN_VADDCUW, ALTIVEC_BUILTIN_VADDUBS,   ALTIVEC_BUILTIN_VADDSBS, ALTIVEC_BUILTIN_VADDUHS, ALTIVEC_BUILTIN_VADDSHS, ALTIVEC_BUILTIN_VADDUWS,   ALTIVEC_BUILTIN_VADDSWS, ALTIVEC_BUILTIN_VAND, ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VAVGUB,   ALTIVEC_BUILTIN_VAVGSB, ALTIVEC_BUILTIN_VAVGUH, ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW,   ALTIVEC_BUILTIN_VAVGSW, ALTIVEC_BUILTIN_VCFUX, ALTIVEC_BUILTIN_VCFSX, ALTIVEC_BUILTIN_VCTSXS,   ALTIVEC_BUILTIN_VCTUXS, ALTIVEC_BUILTIN_VCMPBFP, ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH,   ALTIVEC_BUILTIN_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQFP, ALTIVEC_BUILTIN_VCMPGEFP, ALTIVEC_BUILTIN_VCMPGTUB,   ALTIVEC_BUILTIN_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTUW,   ALTIVEC_BUILTIN_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTFP, ALTIVEC_BUILTIN_VEXPTEFP, ALTIVEC_BUILTIN_VLOGEFP,   ALTIVEC_BUILTIN_VMADDFP, ALTIVEC_BUILTIN_VMAXUB, ALTIVEC_BUILTIN_VMAXSB, ALTIVEC_BUILTIN_VMAXUH,   ALTIVEC_BUILTIN_VMAXSH, ALTIVEC_BUILTIN_VMAXUW, ALTIVEC_BUILTIN_VMAXSW, ALTIVEC_BUILTIN_VMAXFP,   ALTIVEC_BUILTIN_VMHADDSHS, ALTIVEC_BUILTIN_VMHRADDSHS, ALTIVEC_BUILTIN_VMLADDUHM, ALTIVEC_BUILTIN_VMRGHB,   ALTIVEC_BUILTIN_VMRGHH, ALTIVEC_BUILTIN_VMRGHW, ALTIVEC_BUILTIN_VMRGLB, ALTIVEC_BUILTIN_VMRGLH,   ALTIVEC_BUILTIN_VMRGLW, ALTIVEC_BUILTIN_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMUHM,   ALTIVEC_BUILTIN_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMSHS, ALTIVEC_BUILTIN_VMINUB,   ALTIVEC_BUILTIN_VMINSB, ALTIVEC_BUILTIN_VMINUH, ALTIVEC_BUILTIN_VMINSH, ALTIVEC_BUILTIN_VMINUW,   ALTIVEC_BUILTIN_VMINSW, ALTIVEC_BUILTIN_VMINFP, ALTIVEC_BUILTIN_VMULEUB, ALTIVEC_BUILTIN_VMULESB,   ALTIVEC_BUILTIN_VMULEUH, ALTIVEC_BUILTIN_VMULESH, ALTIVEC_BUILTIN_VMULOUB, ALTIVEC_BUILTIN_VMULOSB,   ALTIVEC_BUILTIN_VMULOUH, ALTIVEC_BUILTIN_VMULOSH, ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR,   ALTIVEC_BUILTIN_VOR, ALTIVEC_BUILTIN_VSEL_4SI, ALTIVEC_BUILTIN_VSEL_4SF, ALTIVEC_BUILTIN_VSEL_8HI,   ALTIVEC_BUILTIN_VSEL_16QI, ALTIVEC_BUILTIN_VPERM_4SI, ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI,   ALTIVEC_BUILTIN_VPERM_16QI, ALTIVEC_BUILTIN_VPKUHUM, ALTIVEC_BUILTIN_VPKUWUM, ALTIVEC_BUILTIN_VPKPX,   ALTIVEC_BUILTIN_VPKUHSS, ALTIVEC_BUILTIN_VPKSHSS, ALTIVEC_BUILTIN_VPKUWSS, ALTIVEC_BUILTIN_VPKSWSS,   ALTIVEC_BUILTIN_VPKUHUS, ALTIVEC_BUILTIN_VPKSHUS, ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS,   ALTIVEC_BUILTIN_VREFP, ALTIVEC_BUILTIN_VRFIM, ALTIVEC_BUILTIN_VRFIN, ALTIVEC_BUILTIN_VRFIP,   ALTIVEC_BUILTIN_VRFIZ, ALTIVEC_BUILTIN_VRLB, ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW,   ALTIVEC_BUILTIN_VRSQRTEFP, ALTIVEC_BUILTIN_VSLB, ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW,   ALTIVEC_BUILTIN_VSL, ALTIVEC_BUILTIN_VSLO, ALTIVEC_BUILTIN_VSPLTB, ALTIVEC_BUILTIN_VSPLTH,   ALTIVEC_BUILTIN_VSPLTW, ALTIVEC_BUILTIN_VSPLTISB, ALTIVEC_BUILTIN_VSPLTISH, ALTIVEC_BUILTIN_VSPLTISW,   ALTIVEC_BUILTIN_VSRB, ALTIVEC_BUILTIN_VSRH, ALTIVEC_BUILTIN_VSRW, ALTIVEC_BUILTIN_VSRAB,   ALTIVEC_BUILTIN_VSRAH, ALTIVEC_BUILTIN_VSRAW, ALTIVEC_BUILTIN_VSR, ALTIVEC_BUILTIN_VSRO,   ALTIVEC_BUILTIN_VSUBUBM, ALTIVEC_BUILTIN_VSUBUHM, ALTIVEC_BUILTIN_VSUBUWM, ALTIVEC_BUILTIN_VSUBFP,   ALTIVEC_BUILTIN_VSUBCUW, ALTIVEC_BUILTIN_VSUBUBS, ALTIVEC_BUILTIN_VSUBSBS, ALTIVEC_BUILTIN_VSUBUHS,   ALTIVEC_BUILTIN_VSUBSHS, ALTIVEC_BUILTIN_VSUBUWS, ALTIVEC_BUILTIN_VSUBSWS, ALTIVEC_BUILTIN_VSUM4UBS,   ALTIVEC_BUILTIN_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SHS, ALTIVEC_BUILTIN_VSUM2SWS, ALTIVEC_BUILTIN_VSUMSWS,   ALTIVEC_BUILTIN_VXOR, ALTIVEC_BUILTIN_VSLDOI_16QI, ALTIVEC_BUILTIN_VSLDOI_8HI, ALTIVEC_BUILTIN_VSLDOI_4SI,   ALTIVEC_BUILTIN_VSLDOI_4SF, ALTIVEC_BUILTIN_VUPKHSB, ALTIVEC_BUILTIN_VUPKHPX, ALTIVEC_BUILTIN_VUPKHSH,   ALTIVEC_BUILTIN_VUPKLSB, ALTIVEC_BUILTIN_VUPKLPX, ALTIVEC_BUILTIN_VUPKLSH, ALTIVEC_BUILTIN_MTVSCR,   ALTIVEC_BUILTIN_MFVSCR, ALTIVEC_BUILTIN_DSSALL, ALTIVEC_BUILTIN_DSS, ALTIVEC_BUILTIN_LVSL,   ALTIVEC_BUILTIN_LVSR, ALTIVEC_BUILTIN_DSTT, ALTIVEC_BUILTIN_DSTST, ALTIVEC_BUILTIN_DSTSTT,   ALTIVEC_BUILTIN_DST, ALTIVEC_BUILTIN_LVEBX, ALTIVEC_BUILTIN_LVEHX, ALTIVEC_BUILTIN_LVEWX,   ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_LVX, ALTIVEC_BUILTIN_STVX, ALTIVEC_BUILTIN_STVEBX,   ALTIVEC_BUILTIN_STVEHX, ALTIVEC_BUILTIN_STVEWX, ALTIVEC_BUILTIN_STVXL, ALTIVEC_BUILTIN_VCMPBFP_P,   ALTIVEC_BUILTIN_VCMPEQFP_P, ALTIVEC_BUILTIN_VCMPEQUB_P, ALTIVEC_BUILTIN_VCMPEQUH_P, ALTIVEC_BUILTIN_VCMPEQUW_P,   ALTIVEC_BUILTIN_VCMPGEFP_P, ALTIVEC_BUILTIN_VCMPGTFP_P, ALTIVEC_BUILTIN_VCMPGTSB_P, ALTIVEC_BUILTIN_VCMPGTSH_P,   ALTIVEC_BUILTIN_VCMPGTSW_P, ALTIVEC_BUILTIN_VCMPGTUB_P, ALTIVEC_BUILTIN_VCMPGTUH_P, ALTIVEC_BUILTIN_VCMPGTUW_P,   ALTIVEC_BUILTIN_ABSS_V4SI, ALTIVEC_BUILTIN_ABSS_V8HI, ALTIVEC_BUILTIN_ABSS_V16QI, ALTIVEC_BUILTIN_ABS_V4SI,   ALTIVEC_BUILTIN_ABS_V4SF, ALTIVEC_BUILTIN_ABS_V8HI, ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_COMPILETIME_ERROR,   ALTIVEC_BUILTIN_MASK_FOR_LOAD, ALTIVEC_BUILTIN_MASK_FOR_STORE, SPE_BUILTIN_EVADDW, SPE_BUILTIN_EVAND,   SPE_BUILTIN_EVANDC, SPE_BUILTIN_EVDIVWS, SPE_BUILTIN_EVDIVWU, SPE_BUILTIN_EVEQV,   SPE_BUILTIN_EVFSADD, SPE_BUILTIN_EVFSDIV, SPE_BUILTIN_EVFSMUL, SPE_BUILTIN_EVFSSUB,   SPE_BUILTIN_EVLDDX, SPE_BUILTIN_EVLDHX, SPE_BUILTIN_EVLDWX, SPE_BUILTIN_EVLHHESPLATX,   SPE_BUILTIN_EVLHHOSSPLATX, SPE_BUILTIN_EVLHHOUSPLATX, SPE_BUILTIN_EVLWHEX, SPE_BUILTIN_EVLWHOSX,   SPE_BUILTIN_EVLWHOUX, SPE_BUILTIN_EVLWHSPLATX, SPE_BUILTIN_EVLWWSPLATX, SPE_BUILTIN_EVMERGEHI,   SPE_BUILTIN_EVMERGEHILO, SPE_BUILTIN_EVMERGELO, SPE_BUILTIN_EVMERGELOHI, SPE_BUILTIN_EVMHEGSMFAA,   SPE_BUILTIN_EVMHEGSMFAN, SPE_BUILTIN_EVMHEGSMIAA, SPE_BUILTIN_EVMHEGSMIAN, SPE_BUILTIN_EVMHEGUMIAA,   SPE_BUILTIN_EVMHEGUMIAN, SPE_BUILTIN_EVMHESMF, SPE_BUILTIN_EVMHESMFA, SPE_BUILTIN_EVMHESMFAAW,   SPE_BUILTIN_EVMHESMFANW, SPE_BUILTIN_EVMHESMI, SPE_BUILTIN_EVMHESMIA, SPE_BUILTIN_EVMHESMIAAW,   SPE_BUILTIN_EVMHESMIANW, SPE_BUILTIN_EVMHESSF, SPE_BUILTIN_EVMHESSFA, SPE_BUILTIN_EVMHESSFAAW,   SPE_BUILTIN_EVMHESSFANW, SPE_BUILTIN_EVMHESSIAAW, SPE_BUILTIN_EVMHESSIANW, SPE_BUILTIN_EVMHEUMI,   SPE_BUILTIN_EVMHEUMIA, SPE_BUILTIN_EVMHEUMIAAW, SPE_BUILTIN_EVMHEUMIANW, SPE_BUILTIN_EVMHEUSIAAW,   SPE_BUILTIN_EVMHEUSIANW, SPE_BUILTIN_EVMHOGSMFAA, SPE_BUILTIN_EVMHOGSMFAN, SPE_BUILTIN_EVMHOGSMIAA,   SPE_BUILTIN_EVMHOGSMIAN, SPE_BUILTIN_EVMHOGUMIAA, SPE_BUILTIN_EVMHOGUMIAN, SPE_BUILTIN_EVMHOSMF,   SPE_BUILTIN_EVMHOSMFA, SPE_BUILTIN_EVMHOSMFAAW, SPE_BUILTIN_EVMHOSMFANW, SPE_BUILTIN_EVMHOSMI,   SPE_BUILTIN_EVMHOSMIA, SPE_BUILTIN_EVMHOSMIAAW, SPE_BUILTIN_EVMHOSMIANW, SPE_BUILTIN_EVMHOSSF,   SPE_BUILTIN_EVMHOSSFA, SPE_BUILTIN_EVMHOSSFAAW, SPE_BUILTIN_EVMHOSSFANW, SPE_BUILTIN_EVMHOSSIAAW,   SPE_BUILTIN_EVMHOSSIANW, SPE_BUILTIN_EVMHOUMI, SPE_BUILTIN_EVMHOUMIA, SPE_BUILTIN_EVMHOUMIAAW,   SPE_BUILTIN_EVMHOUMIANW, SPE_BUILTIN_EVMHOUSIAAW, SPE_BUILTIN_EVMHOUSIANW, SPE_BUILTIN_EVMWHSMF,   SPE_BUILTIN_EVMWHSMFA, SPE_BUILTIN_EVMWHSMI, SPE_BUILTIN_EVMWHSMIA, SPE_BUILTIN_EVMWHSSF,   SPE_BUILTIN_EVMWHSSFA, SPE_BUILTIN_EVMWHUMI, SPE_BUILTIN_EVMWHUMIA, SPE_BUILTIN_EVMWLSMIAAW,   SPE_BUILTIN_EVMWLSMIANW, SPE_BUILTIN_EVMWLSSIAAW, SPE_BUILTIN_EVMWLSSIANW, SPE_BUILTIN_EVMWLUMI,   SPE_BUILTIN_EVMWLUMIA, SPE_BUILTIN_EVMWLUMIAAW, SPE_BUILTIN_EVMWLUMIANW, SPE_BUILTIN_EVMWLUSIAAW,   SPE_BUILTIN_EVMWLUSIANW, SPE_BUILTIN_EVMWSMF, SPE_BUILTIN_EVMWSMFA, SPE_BUILTIN_EVMWSMFAA,   SPE_BUILTIN_EVMWSMFAN, SPE_BUILTIN_EVMWSMI, SPE_BUILTIN_EVMWSMIA, SPE_BUILTIN_EVMWSMIAA,   SPE_BUILTIN_EVMWSMIAN, SPE_BUILTIN_EVMWHSSFAA, SPE_BUILTIN_EVMWSSF, SPE_BUILTIN_EVMWSSFA,   SPE_BUILTIN_EVMWSSFAA, SPE_BUILTIN_EVMWSSFAN, SPE_BUILTIN_EVMWUMI, SPE_BUILTIN_EVMWUMIA,   SPE_BUILTIN_EVMWUMIAA, SPE_BUILTIN_EVMWUMIAN, SPE_BUILTIN_EVNAND, SPE_BUILTIN_EVNOR,   SPE_BUILTIN_EVOR, SPE_BUILTIN_EVORC, SPE_BUILTIN_EVRLW, SPE_BUILTIN_EVSLW,   SPE_BUILTIN_EVSRWS, SPE_BUILTIN_EVSRWU, SPE_BUILTIN_EVSTDDX, SPE_BUILTIN_EVSTDHX,   SPE_BUILTIN_EVSTDWX, SPE_BUILTIN_EVSTWHEX, SPE_BUILTIN_EVSTWHOX, SPE_BUILTIN_EVSTWWEX,   SPE_BUILTIN_EVSTWWOX, SPE_BUILTIN_EVSUBFW, SPE_BUILTIN_EVXOR, SPE_BUILTIN_EVABS,   SPE_BUILTIN_EVADDSMIAAW, SPE_BUILTIN_EVADDSSIAAW, SPE_BUILTIN_EVADDUMIAAW, SPE_BUILTIN_EVADDUSIAAW,   SPE_BUILTIN_EVCNTLSW, SPE_BUILTIN_EVCNTLZW, SPE_BUILTIN_EVEXTSB, SPE_BUILTIN_EVEXTSH,   SPE_BUILTIN_EVFSABS, SPE_BUILTIN_EVFSCFSF, SPE_BUILTIN_EVFSCFSI, SPE_BUILTIN_EVFSCFUF,   SPE_BUILTIN_EVFSCFUI, SPE_BUILTIN_EVFSCTSF, SPE_BUILTIN_EVFSCTSI, SPE_BUILTIN_EVFSCTSIZ,   SPE_BUILTIN_EVFSCTUF, SPE_BUILTIN_EVFSCTUI, SPE_BUILTIN_EVFSCTUIZ, SPE_BUILTIN_EVFSNABS,   SPE_BUILTIN_EVFSNEG, SPE_BUILTIN_EVMRA, SPE_BUILTIN_EVNEG, SPE_BUILTIN_EVRNDW,   SPE_BUILTIN_EVSUBFSMIAAW, SPE_BUILTIN_EVSUBFSSIAAW, SPE_BUILTIN_EVSUBFUMIAAW, SPE_BUILTIN_EVSUBFUSIAAW,   SPE_BUILTIN_EVADDIW, SPE_BUILTIN_EVLDD, SPE_BUILTIN_EVLDH, SPE_BUILTIN_EVLDW,   SPE_BUILTIN_EVLHHESPLAT, SPE_BUILTIN_EVLHHOSSPLAT, SPE_BUILTIN_EVLHHOUSPLAT, SPE_BUILTIN_EVLWHE,   SPE_BUILTIN_EVLWHOS, SPE_BUILTIN_EVLWHOU, SPE_BUILTIN_EVLWHSPLAT, SPE_BUILTIN_EVLWWSPLAT,   SPE_BUILTIN_EVRLWI, SPE_BUILTIN_EVSLWI, SPE_BUILTIN_EVSRWIS, SPE_BUILTIN_EVSRWIU,   SPE_BUILTIN_EVSTDD, SPE_BUILTIN_EVSTDH, SPE_BUILTIN_EVSTDW, SPE_BUILTIN_EVSTWHE,   SPE_BUILTIN_EVSTWHO, SPE_BUILTIN_EVSTWWE, SPE_BUILTIN_EVSTWWO, SPE_BUILTIN_EVSUBIFW,   SPE_BUILTIN_EVCMPEQ, SPE_BUILTIN_EVCMPGTS, SPE_BUILTIN_EVCMPGTU, SPE_BUILTIN_EVCMPLTS,   SPE_BUILTIN_EVCMPLTU, SPE_BUILTIN_EVFSCMPEQ, SPE_BUILTIN_EVFSCMPGT, SPE_BUILTIN_EVFSCMPLT,   SPE_BUILTIN_EVFSTSTEQ, SPE_BUILTIN_EVFSTSTGT, SPE_BUILTIN_EVFSTSTLT, SPE_BUILTIN_EVSEL_CMPEQ,   SPE_BUILTIN_EVSEL_CMPGTS, SPE_BUILTIN_EVSEL_CMPGTU, SPE_BUILTIN_EVSEL_CMPLTS, SPE_BUILTIN_EVSEL_CMPLTU,   SPE_BUILTIN_EVSEL_FSCMPEQ, SPE_BUILTIN_EVSEL_FSCMPGT, SPE_BUILTIN_EVSEL_FSCMPLT, SPE_BUILTIN_EVSEL_FSTSTEQ,   SPE_BUILTIN_EVSEL_FSTSTGT, SPE_BUILTIN_EVSEL_FSTSTLT, SPE_BUILTIN_EVSPLATFI, SPE_BUILTIN_EVSPLATI,   SPE_BUILTIN_EVMWHSSMAA, SPE_BUILTIN_EVMWHSMFAA, SPE_BUILTIN_EVMWHSMIAA, SPE_BUILTIN_EVMWHUSIAA,   SPE_BUILTIN_EVMWHUMIAA, SPE_BUILTIN_EVMWHSSFAN, SPE_BUILTIN_EVMWHSSIAN, SPE_BUILTIN_EVMWHSMFAN,   SPE_BUILTIN_EVMWHSMIAN, SPE_BUILTIN_EVMWHUSIAN, SPE_BUILTIN_EVMWHUMIAN, SPE_BUILTIN_EVMWHGSSFAA,   SPE_BUILTIN_EVMWHGSMFAA, SPE_BUILTIN_EVMWHGSMIAA, SPE_BUILTIN_EVMWHGUMIAA, SPE_BUILTIN_EVMWHGSSFAN,   SPE_BUILTIN_EVMWHGSMFAN, SPE_BUILTIN_EVMWHGSMIAN, SPE_BUILTIN_EVMWHGUMIAN, SPE_BUILTIN_MTSPEFSCR,   SPE_BUILTIN_MFSPEFSCR, SPE_BUILTIN_BRINC, ALTIVEC_BUILTIN_ST_INTERNAL_4si, ALTIVEC_BUILTIN_LD_INTERNAL_4si,   ALTIVEC_BUILTIN_ST_INTERNAL_8hi, ALTIVEC_BUILTIN_LD_INTERNAL_8hi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi, ALTIVEC_BUILTIN_LD_INTERNAL_16qi,   ALTIVEC_BUILTIN_ST_INTERNAL_4sf, ALTIVEC_BUILTIN_LD_INTERNAL_4sf, ALTIVEC_BUILTIN_VADDUBM, ALTIVEC_BUILTIN_VADDUHM,   ALTIVEC_BUILTIN_VADDUWM, ALTIVEC_BUILTIN_VADDFP, ALTIVEC_BUILTIN_VADDCUW, ALTIVEC_BUILTIN_VADDUBS,   ALTIVEC_BUILTIN_VADDSBS, ALTIVEC_BUILTIN_VADDUHS, ALTIVEC_BUILTIN_VADDSHS, ALTIVEC_BUILTIN_VADDUWS,   ALTIVEC_BUILTIN_VADDSWS, ALTIVEC_BUILTIN_VAND, ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VAVGUB,   ALTIVEC_BUILTIN_VAVGSB, ALTIVEC_BUILTIN_VAVGUH, ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW,   ALTIVEC_BUILTIN_VAVGSW, ALTIVEC_BUILTIN_VCFUX, ALTIVEC_BUILTIN_VCFSX, ALTIVEC_BUILTIN_VCTSXS,   ALTIVEC_BUILTIN_VCTUXS, ALTIVEC_BUILTIN_VCMPBFP, ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH,   ALTIVEC_BUILTIN_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQFP, ALTIVEC_BUILTIN_VCMPGEFP, ALTIVEC_BUILTIN_VCMPGTUB,   ALTIVEC_BUILTIN_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTUW,   ALTIVEC_BUILTIN_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTFP, ALTIVEC_BUILTIN_VEXPTEFP, ALTIVEC_BUILTIN_VLOGEFP,   ALTIVEC_BUILTIN_VMADDFP, ALTIVEC_BUILTIN_VMAXUB, ALTIVEC_BUILTIN_VMAXSB, ALTIVEC_BUILTIN_VMAXUH,   ALTIVEC_BUILTIN_VMAXSH, ALTIVEC_BUILTIN_VMAXUW, ALTIVEC_BUILTIN_VMAXSW, ALTIVEC_BUILTIN_VMAXFP,   ALTIVEC_BUILTIN_VMHADDSHS, ALTIVEC_BUILTIN_VMHRADDSHS, ALTIVEC_BUILTIN_VMLADDUHM, ALTIVEC_BUILTIN_VMRGHB,   ALTIVEC_BUILTIN_VMRGHH, ALTIVEC_BUILTIN_VMRGHW, ALTIVEC_BUILTIN_VMRGLB, ALTIVEC_BUILTIN_VMRGLH,   ALTIVEC_BUILTIN_VMRGLW, ALTIVEC_BUILTIN_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMUHM,   ALTIVEC_BUILTIN_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMSHS, ALTIVEC_BUILTIN_VMINUB,   ALTIVEC_BUILTIN_VMINSB, ALTIVEC_BUILTIN_VMINUH, ALTIVEC_BUILTIN_VMINSH, ALTIVEC_BUILTIN_VMINUW,   ALTIVEC_BUILTIN_VMINSW, ALTIVEC_BUILTIN_VMINFP, ALTIVEC_BUILTIN_VMULEUB, ALTIVEC_BUILTIN_VMULESB,   ALTIVEC_BUILTIN_VMULEUH, ALTIVEC_BUILTIN_VMULESH, ALTIVEC_BUILTIN_VMULOUB, ALTIVEC_BUILTIN_VMULOSB,   ALTIVEC_BUILTIN_VMULOUH, ALTIVEC_BUILTIN_VMULOSH, ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR,   ALTIVEC_BUILTIN_VOR, ALTIVEC_BUILTIN_VSEL_4SI, ALTIVEC_BUILTIN_VSEL_4SF, ALTIVEC_BUILTIN_VSEL_8HI,   ALTIVEC_BUILTIN_VSEL_16QI, ALTIVEC_BUILTIN_VPERM_4SI, ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI,   ALTIVEC_BUILTIN_VPERM_16QI, ALTIVEC_BUILTIN_VPKUHUM, ALTIVEC_BUILTIN_VPKUWUM, ALTIVEC_BUILTIN_VPKPX,   ALTIVEC_BUILTIN_VPKUHSS, ALTIVEC_BUILTIN_VPKSHSS, ALTIVEC_BUILTIN_VPKUWSS, ALTIVEC_BUILTIN_VPKSWSS,   ALTIVEC_BUILTIN_VPKUHUS, ALTIVEC_BUILTIN_VPKSHUS, ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS,   ALTIVEC_BUILTIN_VREFP, ALTIVEC_BUILTIN_VRFIM, ALTIVEC_BUILTIN_VRFIN, ALTIVEC_BUILTIN_VRFIP,   ALTIVEC_BUILTIN_VRFIZ, ALTIVEC_BUILTIN_VRLB, ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW,   ALTIVEC_BUILTIN_VRSQRTEFP, ALTIVEC_BUILTIN_VSLB, ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW,   ALTIVEC_BUILTIN_VSL, ALTIVEC_BUILTIN_VSLO, ALTIVEC_BUILTIN_VSPLTB, ALTIVEC_BUILTIN_VSPLTH,   ALTIVEC_BUILTIN_VSPLTW, ALTIVEC_BUILTIN_VSPLTISB, ALTIVEC_BUILTIN_VSPLTISH, ALTIVEC_BUILTIN_VSPLTISW,   ALTIVEC_BUILTIN_VSRB, ALTIVEC_BUILTIN_VSRH, ALTIVEC_BUILTIN_VSRW, ALTIVEC_BUILTIN_VSRAB,   ALTIVEC_BUILTIN_VSRAH, ALTIVEC_BUILTIN_VSRAW, ALTIVEC_BUILTIN_VSR, ALTIVEC_BUILTIN_VSRO,   ALTIVEC_BUILTIN_VSUBUBM, ALTIVEC_BUILTIN_VSUBUHM, ALTIVEC_BUILTIN_VSUBUWM, ALTIVEC_BUILTIN_VSUBFP,   ALTIVEC_BUILTIN_VSUBCUW, ALTIVEC_BUILTIN_VSUBUBS, ALTIVEC_BUILTIN_VSUBSBS, ALTIVEC_BUILTIN_VSUBUHS,   ALTIVEC_BUILTIN_VSUBSHS, ALTIVEC_BUILTIN_VSUBUWS, ALTIVEC_BUILTIN_VSUBSWS, ALTIVEC_BUILTIN_VSUM4UBS,   ALTIVEC_BUILTIN_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SHS, ALTIVEC_BUILTIN_VSUM2SWS, ALTIVEC_BUILTIN_VSUMSWS,   ALTIVEC_BUILTIN_VXOR, ALTIVEC_BUILTIN_VSLDOI_16QI, ALTIVEC_BUILTIN_VSLDOI_8HI, ALTIVEC_BUILTIN_VSLDOI_4SI,   ALTIVEC_BUILTIN_VSLDOI_4SF, ALTIVEC_BUILTIN_VUPKHSB, ALTIVEC_BUILTIN_VUPKHPX, ALTIVEC_BUILTIN_VUPKHSH,   ALTIVEC_BUILTIN_VUPKLSB, ALTIVEC_BUILTIN_VUPKLPX, ALTIVEC_BUILTIN_VUPKLSH, ALTIVEC_BUILTIN_MTVSCR,   ALTIVEC_BUILTIN_MFVSCR, ALTIVEC_BUILTIN_DSSALL, ALTIVEC_BUILTIN_DSS, ALTIVEC_BUILTIN_LVSL,   ALTIVEC_BUILTIN_LVSR, ALTIVEC_BUILTIN_DSTT, ALTIVEC_BUILTIN_DSTST, ALTIVEC_BUILTIN_DSTSTT,   ALTIVEC_BUILTIN_DST, ALTIVEC_BUILTIN_LVEBX, ALTIVEC_BUILTIN_LVEHX, ALTIVEC_BUILTIN_LVEWX,   ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_LVX, ALTIVEC_BUILTIN_STVX, ALTIVEC_BUILTIN_STVEBX,   ALTIVEC_BUILTIN_STVEHX, ALTIVEC_BUILTIN_STVEWX, ALTIVEC_BUILTIN_STVXL, ALTIVEC_BUILTIN_VCMPBFP_P,   ALTIVEC_BUILTIN_VCMPEQFP_P, ALTIVEC_BUILTIN_VCMPEQUB_P, ALTIVEC_BUILTIN_VCMPEQUH_P, ALTIVEC_BUILTIN_VCMPEQUW_P,   ALTIVEC_BUILTIN_VCMPGEFP_P, ALTIVEC_BUILTIN_VCMPGTFP_P, ALTIVEC_BUILTIN_VCMPGTSB_P, ALTIVEC_BUILTIN_VCMPGTSH_P,   ALTIVEC_BUILTIN_VCMPGTSW_P, ALTIVEC_BUILTIN_VCMPGTUB_P, ALTIVEC_BUILTIN_VCMPGTUH_P, ALTIVEC_BUILTIN_VCMPGTUW_P,   ALTIVEC_BUILTIN_ABSS_V4SI, ALTIVEC_BUILTIN_ABSS_V8HI, ALTIVEC_BUILTIN_ABSS_V16QI, ALTIVEC_BUILTIN_ABS_V4SI,   ALTIVEC_BUILTIN_ABS_V4SF, ALTIVEC_BUILTIN_ABS_V8HI, ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_MASK_FOR_LOAD,   ALTIVEC_BUILTIN_MASK_FOR_STORE, ALTIVEC_BUILTIN_VEC_INIT_V4SI, ALTIVEC_BUILTIN_VEC_INIT_V8HI, ALTIVEC_BUILTIN_VEC_INIT_V16QI,   ALTIVEC_BUILTIN_VEC_INIT_V4SF, ALTIVEC_BUILTIN_VEC_SET_V4SI, ALTIVEC_BUILTIN_VEC_SET_V8HI, ALTIVEC_BUILTIN_VEC_SET_V16QI,   ALTIVEC_BUILTIN_VEC_SET_V4SF, ALTIVEC_BUILTIN_VEC_EXT_V4SI, ALTIVEC_BUILTIN_VEC_EXT_V8HI, ALTIVEC_BUILTIN_VEC_EXT_V16QI,   ALTIVEC_BUILTIN_VEC_EXT_V4SF, ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPGT_P,   ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_VEC_ADD,   ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VEC_ANDC,   ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VEC_CMPEQ,   ALTIVEC_BUILTIN_VEC_CMPEQUB, ALTIVEC_BUILTIN_VEC_CMPEQUH, ALTIVEC_BUILTIN_VEC_CMPEQUW, ALTIVEC_BUILTIN_VEC_CMPGE,   ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VEC_CTF,   ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_VEC_DSTST,   ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEC_FLOOR,   ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_VEC_LOGE,   ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_VEC_LVSL,   ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VEC_MAX,   ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VEC_MLADD,   ALTIVEC_BUILTIN_VEC_MPERM, ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VEC_MRGHB, ALTIVEC_BUILTIN_VEC_MRGHH,   ALTIVEC_BUILTIN_VEC_MRGHW, ALTIVEC_BUILTIN_VEC_MRGLB, ALTIVEC_BUILTIN_VEC_MRGLH, ALTIVEC_BUILTIN_VEC_MRGLW,   ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_VEC_MULE,   ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VEC_OR,   ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VEC_PACKSU,   ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VEC_ROUND,   ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VEC_SLD,   ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VEC_SPLAT_S16,   ALTIVEC_BUILTIN_VEC_SPLAT_S32, ALTIVEC_BUILTIN_VEC_SPLAT_S8, ALTIVEC_BUILTIN_VEC_SPLAT_U16, ALTIVEC_BUILTIN_VEC_SPLAT_U32,   ALTIVEC_BUILTIN_VEC_SPLAT_U8, ALTIVEC_BUILTIN_VEC_SPLTB, ALTIVEC_BUILTIN_VEC_SPLTH, ALTIVEC_BUILTIN_VEC_SPLTW,   ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VEC_SRO,   ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_VEC_STVEBX,   ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VEC_SUBC,   ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VEC_SUMS,   ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VEC_VADDFP,   ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VEC_VADDUBM,   ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VEC_VADDUWM,   ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VEC_VAVGSW,   ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VEC_VCFSX,   ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VEC_VCMPEQUH,   ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VEC_VCMPGTSH,   ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VEC_VCMPGTUW,   ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VEC_VMAXSW,   ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VEC_VMINFP,   ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VEC_VMINUB,   ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VEC_VMRGHH,   ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VEC_VMRGLW,   ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VEC_VMSUMUBM,   ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VEC_VMULESH,   ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VEC_VMULOSH,   ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VEC_VPKSHUS,   ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VEC_VPKUHUS,   ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VEC_VRLH,   ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VEC_VSLW,   ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VEC_VSRAB,   ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VEC_VSRH,   ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VEC_VSUBSHS,   ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VEC_VSUBUHM,   ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VEC_VSUM4SBS,   ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VEC_VUPKHSB,   ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VEC_VUPKLSH,   ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VEC_STEP, ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP, SPE_BUILTIN_EVADDW,   SPE_BUILTIN_EVAND, SPE_BUILTIN_EVANDC, SPE_BUILTIN_EVDIVWS, SPE_BUILTIN_EVDIVWU,   SPE_BUILTIN_EVEQV, SPE_BUILTIN_EVFSADD, SPE_BUILTIN_EVFSDIV, SPE_BUILTIN_EVFSMUL,   SPE_BUILTIN_EVFSSUB, SPE_BUILTIN_EVLDDX, SPE_BUILTIN_EVLDHX, SPE_BUILTIN_EVLDWX,   SPE_BUILTIN_EVLHHESPLATX, SPE_BUILTIN_EVLHHOSSPLATX, SPE_BUILTIN_EVLHHOUSPLATX, SPE_BUILTIN_EVLWHEX,   SPE_BUILTIN_EVLWHOSX, SPE_BUILTIN_EVLWHOUX, SPE_BUILTIN_EVLWHSPLATX, SPE_BUILTIN_EVLWWSPLATX,   SPE_BUILTIN_EVMERGEHI, SPE_BUILTIN_EVMERGEHILO, SPE_BUILTIN_EVMERGELO, SPE_BUILTIN_EVMERGELOHI,   SPE_BUILTIN_EVMHEGSMFAA, SPE_BUILTIN_EVMHEGSMFAN, SPE_BUILTIN_EVMHEGSMIAA, SPE_BUILTIN_EVMHEGSMIAN,   SPE_BUILTIN_EVMHEGUMIAA, SPE_BUILTIN_EVMHEGUMIAN, SPE_BUILTIN_EVMHESMF, SPE_BUILTIN_EVMHESMFA,   SPE_BUILTIN_EVMHESMFAAW, SPE_BUILTIN_EVMHESMFANW, SPE_BUILTIN_EVMHESMI, SPE_BUILTIN_EVMHESMIA,   SPE_BUILTIN_EVMHESMIAAW, SPE_BUILTIN_EVMHESMIANW, SPE_BUILTIN_EVMHESSF, SPE_BUILTIN_EVMHESSFA,   SPE_BUILTIN_EVMHESSFAAW, SPE_BUILTIN_EVMHESSFANW, SPE_BUILTIN_EVMHESSIAAW, SPE_BUILTIN_EVMHESSIANW,   SPE_BUILTIN_EVMHEUMI, SPE_BUILTIN_EVMHEUMIA, SPE_BUILTIN_EVMHEUMIAAW, SPE_BUILTIN_EVMHEUMIANW,   SPE_BUILTIN_EVMHEUSIAAW, SPE_BUILTIN_EVMHEUSIANW, SPE_BUILTIN_EVMHOGSMFAA, SPE_BUILTIN_EVMHOGSMFAN,   SPE_BUILTIN_EVMHOGSMIAA, SPE_BUILTIN_EVMHOGSMIAN, SPE_BUILTIN_EVMHOGUMIAA, SPE_BUILTIN_EVMHOGUMIAN,   SPE_BUILTIN_EVMHOSMF, SPE_BUILTIN_EVMHOSMFA, SPE_BUILTIN_EVMHOSMFAAW, SPE_BUILTIN_EVMHOSMFANW,   SPE_BUILTIN_EVMHOSMI, SPE_BUILTIN_EVMHOSMIA, SPE_BUILTIN_EVMHOSMIAAW, SPE_BUILTIN_EVMHOSMIANW,   SPE_BUILTIN_EVMHOSSF, SPE_BUILTIN_EVMHOSSFA, SPE_BUILTIN_EVMHOSSFAAW, SPE_BUILTIN_EVMHOSSFANW,   SPE_BUILTIN_EVMHOSSIAAW, SPE_BUILTIN_EVMHOSSIANW, SPE_BUILTIN_EVMHOUMI, SPE_BUILTIN_EVMHOUMIA,   SPE_BUILTIN_EVMHOUMIAAW, SPE_BUILTIN_EVMHOUMIANW, SPE_BUILTIN_EVMHOUSIAAW, SPE_BUILTIN_EVMHOUSIANW,   SPE_BUILTIN_EVMWHSMF, SPE_BUILTIN_EVMWHSMFA, SPE_BUILTIN_EVMWHSMI, SPE_BUILTIN_EVMWHSMIA,   SPE_BUILTIN_EVMWHSSF, SPE_BUILTIN_EVMWHSSFA, SPE_BUILTIN_EVMWHUMI, SPE_BUILTIN_EVMWHUMIA,   SPE_BUILTIN_EVMWLSMIAAW, SPE_BUILTIN_EVMWLSMIANW, SPE_BUILTIN_EVMWLSSIAAW, SPE_BUILTIN_EVMWLSSIANW,   SPE_BUILTIN_EVMWLUMI, SPE_BUILTIN_EVMWLUMIA, SPE_BUILTIN_EVMWLUMIAAW, SPE_BUILTIN_EVMWLUMIANW,   SPE_BUILTIN_EVMWLUSIAAW, SPE_BUILTIN_EVMWLUSIANW, SPE_BUILTIN_EVMWSMF, SPE_BUILTIN_EVMWSMFA,   SPE_BUILTIN_EVMWSMFAA, SPE_BUILTIN_EVMWSMFAN, SPE_BUILTIN_EVMWSMI, SPE_BUILTIN_EVMWSMIA,   SPE_BUILTIN_EVMWSMIAA, SPE_BUILTIN_EVMWSMIAN, SPE_BUILTIN_EVMWHSSFAA, SPE_BUILTIN_EVMWSSF,   SPE_BUILTIN_EVMWSSFA, SPE_BUILTIN_EVMWSSFAA, SPE_BUILTIN_EVMWSSFAN, SPE_BUILTIN_EVMWUMI,   SPE_BUILTIN_EVMWUMIA, SPE_BUILTIN_EVMWUMIAA, SPE_BUILTIN_EVMWUMIAN, SPE_BUILTIN_EVNAND,   SPE_BUILTIN_EVNOR, SPE_BUILTIN_EVOR, SPE_BUILTIN_EVORC, SPE_BUILTIN_EVRLW,   SPE_BUILTIN_EVSLW, SPE_BUILTIN_EVSRWS, SPE_BUILTIN_EVSRWU, SPE_BUILTIN_EVSTDDX,   SPE_BUILTIN_EVSTDHX, SPE_BUILTIN_EVSTDWX, SPE_BUILTIN_EVSTWHEX, SPE_BUILTIN_EVSTWHOX,   SPE_BUILTIN_EVSTWWEX, SPE_BUILTIN_EVSTWWOX, SPE_BUILTIN_EVSUBFW, SPE_BUILTIN_EVXOR,   SPE_BUILTIN_EVABS, SPE_BUILTIN_EVADDSMIAAW, SPE_BUILTIN_EVADDSSIAAW, SPE_BUILTIN_EVADDUMIAAW,   SPE_BUILTIN_EVADDUSIAAW, SPE_BUILTIN_EVCNTLSW, SPE_BUILTIN_EVCNTLZW, SPE_BUILTIN_EVEXTSB,   SPE_BUILTIN_EVEXTSH, SPE_BUILTIN_EVFSABS, SPE_BUILTIN_EVFSCFSF, SPE_BUILTIN_EVFSCFSI,   SPE_BUILTIN_EVFSCFUF, SPE_BUILTIN_EVFSCFUI, SPE_BUILTIN_EVFSCTSF, SPE_BUILTIN_EVFSCTSI,   SPE_BUILTIN_EVFSCTSIZ, SPE_BUILTIN_EVFSCTUF, SPE_BUILTIN_EVFSCTUI, SPE_BUILTIN_EVFSCTUIZ,   SPE_BUILTIN_EVFSNABS, SPE_BUILTIN_EVFSNEG, SPE_BUILTIN_EVMRA, SPE_BUILTIN_EVNEG,   SPE_BUILTIN_EVRNDW, SPE_BUILTIN_EVSUBFSMIAAW, SPE_BUILTIN_EVSUBFSSIAAW, SPE_BUILTIN_EVSUBFUMIAAW,   SPE_BUILTIN_EVSUBFUSIAAW, SPE_BUILTIN_EVADDIW, SPE_BUILTIN_EVLDD, SPE_BUILTIN_EVLDH,   SPE_BUILTIN_EVLDW, SPE_BUILTIN_EVLHHESPLAT, SPE_BUILTIN_EVLHHOSSPLAT, SPE_BUILTIN_EVLHHOUSPLAT,   SPE_BUILTIN_EVLWHE, SPE_BUILTIN_EVLWHOS, SPE_BUILTIN_EVLWHOU, SPE_BUILTIN_EVLWHSPLAT,   SPE_BUILTIN_EVLWWSPLAT, SPE_BUILTIN_EVRLWI, SPE_BUILTIN_EVSLWI, SPE_BUILTIN_EVSRWIS,   SPE_BUILTIN_EVSRWIU, SPE_BUILTIN_EVSTDD, SPE_BUILTIN_EVSTDH, SPE_BUILTIN_EVSTDW,   SPE_BUILTIN_EVSTWHE, SPE_BUILTIN_EVSTWHO, SPE_BUILTIN_EVSTWWE, SPE_BUILTIN_EVSTWWO,   SPE_BUILTIN_EVSUBIFW, SPE_BUILTIN_EVCMPEQ, SPE_BUILTIN_EVCMPGTS, SPE_BUILTIN_EVCMPGTU,   SPE_BUILTIN_EVCMPLTS, SPE_BUILTIN_EVCMPLTU, SPE_BUILTIN_EVFSCMPEQ, SPE_BUILTIN_EVFSCMPGT,   SPE_BUILTIN_EVFSCMPLT, SPE_BUILTIN_EVFSTSTEQ, SPE_BUILTIN_EVFSTSTGT, SPE_BUILTIN_EVFSTSTLT,   SPE_BUILTIN_EVSEL_CMPEQ, SPE_BUILTIN_EVSEL_CMPGTS, SPE_BUILTIN_EVSEL_CMPGTU, SPE_BUILTIN_EVSEL_CMPLTS,   SPE_BUILTIN_EVSEL_CMPLTU, SPE_BUILTIN_EVSEL_FSCMPEQ, SPE_BUILTIN_EVSEL_FSCMPGT, SPE_BUILTIN_EVSEL_FSCMPLT,   SPE_BUILTIN_EVSEL_FSTSTEQ, SPE_BUILTIN_EVSEL_FSTSTGT, SPE_BUILTIN_EVSEL_FSTSTLT, SPE_BUILTIN_EVSPLATFI,   SPE_BUILTIN_EVSPLATI, SPE_BUILTIN_EVMWHSSMAA, SPE_BUILTIN_EVMWHSMFAA, SPE_BUILTIN_EVMWHSMIAA,   SPE_BUILTIN_EVMWHUSIAA, SPE_BUILTIN_EVMWHUMIAA, SPE_BUILTIN_EVMWHSSFAN, SPE_BUILTIN_EVMWHSSIAN,   SPE_BUILTIN_EVMWHSMFAN, SPE_BUILTIN_EVMWHSMIAN, SPE_BUILTIN_EVMWHUSIAN, SPE_BUILTIN_EVMWHUMIAN,   SPE_BUILTIN_EVMWHGSSFAA, SPE_BUILTIN_EVMWHGSMFAA, SPE_BUILTIN_EVMWHGSMIAA, SPE_BUILTIN_EVMWHGUMIAA,   SPE_BUILTIN_EVMWHGSSFAN, SPE_BUILTIN_EVMWHGSMFAN, SPE_BUILTIN_EVMWHGSMIAN, SPE_BUILTIN_EVMWHGUMIAN,   SPE_BUILTIN_MTSPEFSCR, SPE_BUILTIN_MFSPEFSCR, SPE_BUILTIN_BRINC, RS6000_BUILTIN_COUNT }
enum	rs6000_builtin_type_index {   RS6000_BTI_NOT_OPAQUE, RS6000_BTI_opaque_V2SI, RS6000_BTI_opaque_V2SF, RS6000_BTI_opaque_p_V2SI,   RS6000_BTI_opaque_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V2SI, RS6000_BTI_V2SF,   RS6000_BTI_V4HI, RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V8HI,   RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_char,   RS6000_BTI_bool_short, RS6000_BTI_bool_int, RS6000_BTI_pixel, RS6000_BTI_bool_V16QI,   RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_pixel_V8HI, RS6000_BTI_long,   RS6000_BTI_unsigned_long, RS6000_BTI_INTQI, RS6000_BTI_UINTQI, RS6000_BTI_INTHI,   RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_float,   RS6000_BTI_void, RS6000_BTI_MAX }
Functions/Subroutines
	GTY (()) rtx rs6000_compare_op0
Variables
enum processor_type	rs6000_cpu
struct rs6000_cpu_select	rs6000_select []
const char *	rs6000_debug_name
int	rs6000_debug_stack
int	rs6000_debug_arg
const char *	rs6000_traceback_name
int	rs6000_long_double_type_size
int	rs6000_ieeequad
int	rs6000_altivec_abi
int	rs6000_spe_abi
int	rs6000_float_gprs
int	rs6000_alignment_flags
const char *	rs6000_sched_insert_nops_str
enum rs6000_nop_insertion	rs6000_sched_insert_nops
enum rs6000_abi	rs6000_current_abi
int	rs6000_compare_fp_p
int	toc_initialized
char	rs6000_reg_names [][8]
int	flag_pic
int	optimize
int	flag_expensive_optimizations
int	frame_pointer_needed

---

Define Documentation

#define ACCUMULATE_OUTGOING_ARGS   1

Definition at line 1255 of file rs6000.h.

#define ADDITIONAL_REGISTER_NAMES

Value:

{{"r0",    0}, {"r1",    1}, {"r2",    2}, {"r3",    3},  \
  {"r4",    4}, {"r5",    5}, {"r6",    6}, {"r7",    7}, \
  {"r8",    8}, {"r9",    9}, {"r10",  10}, {"r11",  11}, \
  {"r12",  12}, {"r13",  13}, {"r14",  14}, {"r15",  15}, \
  {"r16",  16}, {"r17",  17}, {"r18",  18}, {"r19",  19}, \
  {"r20",  20}, {"r21",  21}, {"r22",  22}, {"r23",  23}, \
  {"r24",  24}, {"r25",  25}, {"r26",  26}, {"r27",  27}, \
  {"r28",  28}, {"r29",  29}, {"r30",  30}, {"r31",  31}, \
  {"fr0",  32}, {"fr1",  33}, {"fr2",  34}, {"fr3",  35}, \
  {"fr4",  36}, {"fr5",  37}, {"fr6",  38}, {"fr7",  39}, \
  {"fr8",  40}, {"fr9",  41}, {"fr10", 42}, {"fr11", 43}, \
  {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
  {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
  {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
  {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
  {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
  {"v0",   77}, {"v1",   78}, {"v2",   79}, {"v3",   80},       \
  {"v4",   81}, {"v5",   82}, {"v6",   83}, {"v7",   84},       \
  {"v8",   85}, {"v9",   86}, {"v10",  87}, {"v11",  88},       \
  {"v12",  89}, {"v13",  90}, {"v14",  91}, {"v15",  92},       \
  {"v16",  93}, {"v17",  94}, {"v18",  95}, {"v19",  96},       \
  {"v20",  97}, {"v21",  98}, {"v22",  99}, {"v23",  100},  \
  {"v24",  101},{"v25",  102},{"v26",  103},{"v27",  104},      \
  {"v28",  105},{"v29",  106},{"v30",  107},{"v31",  108},      \
  {"vrsave", 109}, {"vscr", 110},       \
  {"spe_acc", 111}, {"spefscr", 112},       \
  /* no additional names for: mq, lr, ctr, ap */    \
  {"cr0",  68}, {"cr1",  69}, {"cr2",  70}, {"cr3",  71}, \
  {"cr4",  72}, {"cr5",  73}, {"cr6",  74}, {"cr7",  75}, \
  {"cc",   68}, {"sp",    1}, {"toc",   2} }

Definition at line 2150 of file rs6000.h.

#define ALTIVEC_ARG_MAX_REG   (ALTIVEC_ARG_MIN_REG + 11)

Definition at line 1308 of file rs6000.h.

#define ALTIVEC_ARG_MIN_REG   (FIRST_ALTIVEC_REGNO + 2)

Definition at line 1307 of file rs6000.h.

#define ALTIVEC_ARG_NUM_REG   (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)

Definition at line 1309 of file rs6000.h.

#define ALTIVEC_ARG_RETURN   (FIRST_ALTIVEC_REGNO + 2)

Definition at line 1314 of file rs6000.h.

#define ALTIVEC_REGNO_P

(

N

)

((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)

Definition at line 802 of file rs6000.h.

#define ALTIVEC_VECTOR_MODE

(

MODE

)

Value:

((MODE) == V16QImode    \
    || (MODE) == V8HImode   \
    || (MODE) == V4SFmode   \
    || (MODE) == V4SImode)

Definition at line 814 of file rs6000.h.

#define ARG_POINTER_CFA_OFFSET

(

FNDECL

)

0

Definition at line 1236 of file rs6000.h.

#define ARG_POINTER_REGNUM   67

Definition at line 927 of file rs6000.h.

#define ASM_APP_OFF   ""

Definition at line 2018 of file rs6000.h.

#define ASM_APP_ON   ""

Definition at line 2013 of file rs6000.h.

#define ASM_COMMENT_START   " #"

Definition at line 1896 of file rs6000.h.

#define ASM_CPU_SPEC   "%{!mcpu*: \ %{mpower: %{!mpower2: -mpwr}} \ %{mpower2: -mpwrx} \ %{mpowerpc64*: -mppc64} \ %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ %{mno-power: %{!mpowerpc*: -mcom}} \ %{!mno-power: %{!mpower*: %(asm_default)}}} \%{mcpu=common: -mcom} \%{mcpu=power: -mpwr} \%{mcpu=power2: -mpwrx} \%{mcpu=power3: -mppc64} \%{mcpu=power4: -mpower4} \%{mcpu=power5: -mpower4} \%{mcpu=power5+: -mpower4} \%{mcpu=power6: -mpower4 -maltivec} \%{mcpu=powerpc: -mppc} \%{mcpu=rios: -mpwr} \%{mcpu=rios1: -mpwr} \%{mcpu=rios2: -mpwrx} \%{mcpu=rsc: -mpwr} \%{mcpu=rsc1: -mpwr} \%{mcpu=rs64a: -mppc64} \%{mcpu=401: -mppc} \%{mcpu=403: -m403} \%{mcpu=405: -m405} \%{mcpu=405fp: -m405} \%{mcpu=440: -m440} \%{mcpu=440fp: -m440} \%{mcpu=505: -mppc} \%{mcpu=601: -m601} \%{mcpu=602: -mppc} \%{mcpu=603: -mppc} \%{mcpu=603e: -mppc} \%{mcpu=ec603e: -mppc} \%{mcpu=604: -mppc} \%{mcpu=604e: -mppc} \%{mcpu=620: -mppc64} \%{mcpu=630: -mppc64} \%{mcpu=740: -mppc} \%{mcpu=750: -mppc} \%{mcpu=G3: -mppc} \%{mcpu=7400: -mppc -maltivec} \%{mcpu=7450: -mppc -maltivec} \%{mcpu=G4: -mppc -maltivec} \%{mcpu=801: -mppc} \%{mcpu=821: -mppc} \%{mcpu=823: -mppc} \%{mcpu=860: -mppc} \%{mcpu=970: -mpower4 -maltivec} \%{mcpu=G5: -mpower4 -maltivec} \%{mcpu=8540: -me500} \%{maltivec: -maltivec} \-many"

Definition at line 62 of file rs6000.h.

#define ASM_DEFAULT_SPEC   ""

Definition at line 119 of file rs6000.h.

#define ASM_OUTPUT_ADDR_DIFF_ELT	(	FILE,
		BODY,
		VALUE,
		REL		)

Value:

do { char buf[100];         \
       fputs ("\t.long ", FILE);      \
       ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
       assemble_name (FILE, buf);     \
       putc ('-', FILE);        \
       ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
       assemble_name (FILE, buf);     \
       putc ('\n', FILE);       \
     } while (0)

Definition at line 2188 of file rs6000.h.

#define ASM_OUTPUT_ALIGN	(	FILE,
		LOG		)

Value:

if ((LOG) != 0)     \
    fprintf (FILE, "\t.align %d\n", (LOG))

Definition at line 2203 of file rs6000.h.

#define ASM_OUTPUT_DEF_FROM_DECLS	(	FILE,
		DECL,
		TARGET		)

Definition at line 1975 of file rs6000.h.

#define ASM_OUTPUT_SPECIAL_POOL_ENTRY	(	FILE,
		X,
		MODE,
		ALIGN,
		LABELNO,
		WIN		)

Value:

{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE))        \
    {                   \
      output_toc (FILE, X, LABELNO, MODE);          \
      goto WIN;                 \
    }                   \
}

Definition at line 1906 of file rs6000.h.

#define ASSEMBLER_DIALECT   (TARGET_NEW_MNEMONICS ? 1 : 0)

Definition at line 235 of file rs6000.h.

#define BASE_REG_CLASS   BASE_REGS

Definition at line 1078 of file rs6000.h.

#define BIGGEST_ALIGNMENT   128

Definition at line 501 of file rs6000.h.

#define BITS_BIG_ENDIAN   1

Definition at line 401 of file rs6000.h.

#define bool_char_type_node   (rs6000_builtin_types[RS6000_BTI_bool_char])

Definition at line 2970 of file rs6000.h.

Referenced by rs6000_init_builtins(), and rs6000_mangle_fundamental_type().

#define bool_int_type_node   (rs6000_builtin_types[RS6000_BTI_bool_int])

Definition at line 2972 of file rs6000.h.

Referenced by rs6000_init_builtins(), and rs6000_mangle_fundamental_type().

#define bool_short_type_node   (rs6000_builtin_types[RS6000_BTI_bool_short])

Definition at line 2971 of file rs6000.h.

Referenced by rs6000_init_builtins(), and rs6000_mangle_fundamental_type().

#define bool_V16QI_type_node   (rs6000_builtin_types[RS6000_BTI_bool_V16QI])

Definition at line 2974 of file rs6000.h.

Referenced by rs6000_handle_altivec_attribute(), and rs6000_init_builtins().

#define bool_V4SI_type_node   (rs6000_builtin_types[RS6000_BTI_bool_V4SI])

Definition at line 2976 of file rs6000.h.

Referenced by rs6000_handle_altivec_attribute(), and rs6000_init_builtins().

#define bool_V8HI_type_node   (rs6000_builtin_types[RS6000_BTI_bool_V8HI])

Definition at line 2975 of file rs6000.h.

Referenced by rs6000_handle_altivec_attribute(), and rs6000_init_builtins().

#define BRANCH_COST   3

Definition at line 880 of file rs6000.h.

#define BYTES_BIG_ENDIAN   1

Definition at line 405 of file rs6000.h.

#define CALL_LIBCALL   0x00000010

Definition at line 1322 of file rs6000.h.

#define CALL_LONG   0x00000008

Definition at line 1321 of file rs6000.h.

#define CALL_NORMAL   0x00000000

Definition at line 1317 of file rs6000.h.

#define CALL_REALLY_USED_REGISTERS

Value:

{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1,    \
   /* AltiVec registers.  */         \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0              \
   , 0, 0, 0                                       \
}

Definition at line 685 of file rs6000.h.

#define CALL_USED_REGISTERS

Value:

{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1,    \
   /* AltiVec registers.  */         \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1              \
   , 1, 1, 1                                       \
}

Definition at line 666 of file rs6000.h.

#define CALL_V4_CLEAR_FP_ARGS   0x00000002

Definition at line 1319 of file rs6000.h.

#define CALL_V4_SET_FP_ARGS   0x00000004

Definition at line 1320 of file rs6000.h.

#define CAN_DEBUG_WITHOUT_FP

Definition at line 353 of file rs6000.h.

#define CAN_ELIMINATE	(	FROM,
		TO		)

Value:

((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM   \
  ? ! frame_pointer_needed            \
  : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM        \
  ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0  \
  : 1)

Definition at line 1551 of file rs6000.h.

#define CANNOT_CHANGE_MODE_CLASS	(	FROM,
		TO,
		CLASS		)

Value:

(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)       \
   ? ((GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8   \
       || TARGET_IEEEQUAD)            \
      && reg_classes_intersect_p (FLOAT_REGS, CLASS))     \
   : (((TARGET_E500_DOUBLE            \
  && ((((TO) == DFmode) + ((FROM) == DFmode)) == 1    \
      || (((TO) == DImode) + ((FROM) == DImode)) == 1))   \
       || (TARGET_SPE             \
     && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1))  \
      && reg_classes_intersect_p (GENERAL_REGS, CLASS)))

Definition at line 1137 of file rs6000.h.

#define CASE_VECTOR_MODE   SImode

Definition at line 1774 of file rs6000.h.

#define CASE_VECTOR_PC_RELATIVE   1

Definition at line 1780 of file rs6000.h.

#define CLASS_MAX_NREGS	(	CLASS,
		MODE		)

Value:

(((CLASS) == FLOAT_REGS)            \
  ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
  : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
  ? 1                                                                   \
  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

Definition at line 1128 of file rs6000.h.

#define CLZ_DEFINED_VALUE_AT_ZERO	(	MODE,
		VALUE		)	((VALUE) = ((MODE) == SImode ? 32 : 64))

Definition at line 1824 of file rs6000.h.

#define CONDITIONAL_REGISTER_USAGE   rs6000_conditional_register_usage ()

Definition at line 903 of file rs6000.h.

#define CONSTANT_ADDRESS_P

(

X

)

Value:

(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF    \
   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST    \
   || GET_CODE (X) == HIGH)

Definition at line 1598 of file rs6000.h.

#define CONSTANT_ALIGNMENT	(	EXP,
		ALIGN		)

Value:

(TREE_CODE (EXP) == STRING_CST                           \
   && (ALIGN) < BITS_PER_WORD                                    \
   ? BITS_PER_WORD                                               \
   : (ALIGN))

Definition at line 539 of file rs6000.h.

#define COUNT_REGISTER_REGNUM   66

Definition at line 936 of file rs6000.h.

#define CPP_DEFAULT_SPEC   ""

Definition at line 117 of file rs6000.h.

#define CR0_REGNO   68

Definition at line 699 of file rs6000.h.

#define CR1_REGNO   69

Definition at line 700 of file rs6000.h.

#define CR2_REGNO   70

Definition at line 701 of file rs6000.h.

#define CR3_REGNO   71

Definition at line 702 of file rs6000.h.

#define CR4_REGNO   72

Definition at line 703 of file rs6000.h.

#define CR_REGNO_NOT_CR0_P

(

N

)

((N) >= 69 && (N) <= 75)

Definition at line 789 of file rs6000.h.

#define CR_REGNO_P

(

N

)

((N) >= 68 && (N) <= 75)

Definition at line 786 of file rs6000.h.

#define CTZ_DEFINED_VALUE_AT_ZERO	(	MODE,
		VALUE		)	((VALUE) = -1)

Definition at line 1828 of file rs6000.h.

#define DATA_ALIGNMENT	(	TYPE,
		ALIGN		)

Value:

(TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128)  \
   : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
   : TREE_CODE (TYPE) == ARRAY_TYPE   \
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode  \
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))

Definition at line 548 of file rs6000.h.

#define DBX_REGISTER_NUMBER

(

REGNO

)

rs6000_dbx_register_number (REGNO)

Definition at line 619 of file rs6000.h.

#define DEFAULT_PCC_STRUCT_RETURN   0

Definition at line 1282 of file rs6000.h.

#define DEFAULT_SIGNED_CHAR   0

Definition at line 1783 of file rs6000.h.

#define DOT_SYMBOLS   1

Definition at line 46 of file rs6000.h.

#define DOUBLE_TYPE_SIZE   64

Definition at line 468 of file rs6000.h.

#define DRAFT_V4_STRUCT_RET   0

Definition at line 1279 of file rs6000.h.

#define DWARF2_FRAME_REG_OUT	(	REGNO,
		FOR_EH		)

Value:

((FOR_EH) ? (REGNO)       \
   : (REGNO) == CR2_REGNO ? 64      \
   : DBX_REGISTER_NUMBER (REGNO))

Definition at line 631 of file rs6000.h.

#define DWARF_CIE_DATA_ALIGNMENT   (-((int) (TARGET_32BIT ? 4 : 8)))

Definition at line 1166 of file rs6000.h.

#define DWARF_FRAME_REGISTERS   ((FIRST_PSEUDO_REGISTER - 1) + 32)

Definition at line 600 of file rs6000.h.

#define DWARF_FRAME_REGNUM

(

REGNO

)

(REGNO)

Definition at line 622 of file rs6000.h.

#define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)

Definition at line 2212 of file rs6000.h.

#define DWARF_REG_TO_UNWIND_COLUMN

(

r

)

((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))

Definition at line 615 of file rs6000.h.

#define EASY_VECTOR_15

(

n

)

((n) >= -16 && (n) <= 15)

Definition at line 1619 of file rs6000.h.

#define EASY_VECTOR_15_ADD_SELF

(

n

)

Value:

(!EASY_VECTOR_15((n)) \
            && EASY_VECTOR_15((n) >> 1) \
            && ((n) & 1) == 0)

Definition at line 1620 of file rs6000.h.

#define EH_RETURN_DATA_REGNO

(

N

)

((N) < 4 ? (N) + 3 : INVALID_REGNUM)

Definition at line 2215 of file rs6000.h.

#define EH_RETURN_STACKADJ_RTX   gen_rtx_REG (Pmode, 10)

Definition at line 2216 of file rs6000.h.

#define ELIMINABLE_REGS

Value:

{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},  \
 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},   \
 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},  \
 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},   \
 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},  \
 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }

Definition at line 1534 of file rs6000.h.

#define EMPTY_FIELD_BOUNDARY   32

Definition at line 513 of file rs6000.h.

#define EPILOGUE_USES

(

REGNO

)

Value:

((reload_completed && (REGNO) == LINK_REGISTER_REGNUM)  \
   || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO)   \
   || (current_function_calls_eh_return       \
       && TARGET_AIX            \
       && (REGNO) == 2))

Definition at line 1471 of file rs6000.h.

#define EXIT_IGNORE_STACK   1

Definition at line 1464 of file rs6000.h.

#define EXPAND_BUILTIN_VA_START	(	valist,
		nextarg		)	rs6000_va_start (valist, nextarg)

Definition at line 1446 of file rs6000.h.

#define EXTRA_SPECS

Value:

{ "cpp_default",    CPP_DEFAULT_SPEC },     \
  { "asm_cpu",      ASM_CPU_SPEC },       \
  { "asm_default",    ASM_DEFAULT_SPEC },     \
  SUBTARGET_EXTRA_SPECS

Definition at line 133 of file rs6000.h.

#define FIRST_ALTIVEC_REGNO   77

Definition at line 706 of file rs6000.h.

#define FIRST_PARM_OFFSET

(

FNDECL

)

RS6000_SAVE_AREA

Definition at line 1231 of file rs6000.h.

#define FIRST_PSEUDO_REGISTER   114

Definition at line 594 of file rs6000.h.

#define FIRST_SAVED_ALTIVEC_REGNO   (FIRST_ALTIVEC_REGNO+20)

Definition at line 714 of file rs6000.h.

#define FIRST_SAVED_FP_REGNO   (14+32)

Definition at line 715 of file rs6000.h.

#define FIRST_SAVED_GP_REGNO   13

Definition at line 716 of file rs6000.h.

#define FIXED_REGISTERS

Value:

{0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1,    \
   /* AltiVec registers.  */         \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1              \
   , 1, 1, 1                                       \
}

Definition at line 646 of file rs6000.h.

#define FIXED_SCRATCH   (TARGET_SPE ? 14 : 11)

Definition at line 898 of file rs6000.h.

#define float_type_internal_node   (rs6000_builtin_types[RS6000_BTI_float])

Definition at line 2987 of file rs6000.h.

Referenced by rs6000_init_builtins().

#define FLOAT_TYPE_SIZE   32

Definition at line 463 of file rs6000.h.

#define FP_ARG_AIX_MAX_REG   45

Definition at line 1299 of file rs6000.h.

#define FP_ARG_MAX_REG

Value:

((DEFAULT_ABI == ABI_AIX        \
       || DEFAULT_ABI == ABI_DARWIN)      \
      ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)

Definition at line 1301 of file rs6000.h.

#define FP_ARG_MIN_REG   33

Definition at line 1298 of file rs6000.h.

#define FP_ARG_NUM_REG   (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)

Definition at line 1304 of file rs6000.h.

#define FP_ARG_RETURN   FP_ARG_MIN_REG

Definition at line 1313 of file rs6000.h.

#define FP_ARG_V4_MAX_REG   40

Definition at line 1300 of file rs6000.h.

#define FP_REGNO_P

(

N

)

((N) >= 32 && (N) <= 63)

Definition at line 783 of file rs6000.h.

#define FRAME_GROWS_DOWNWARD   (flag_stack_protect != 0)

Definition at line 1175 of file rs6000.h.

#define FRAME_POINTER_REGNUM   113

Definition at line 918 of file rs6000.h.

#define FRAME_POINTER_REQUIRED   0

Definition at line 924 of file rs6000.h.

#define FUNCTION_ARG	(	CUM,
		MODE,
		TYPE,
		NAMED		)	function_arg (&CUM, MODE, TYPE, NAMED)

Definition at line 1427 of file rs6000.h.

#define FUNCTION_ARG_ADVANCE	(	CUM,
		MODE,
		TYPE,
		NAMED		)	function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)

Definition at line 1402 of file rs6000.h.

#define FUNCTION_ARG_BOUNDARY	(	MODE,
		TYPE		)	function_arg_boundary (MODE, TYPE)

Definition at line 1442 of file rs6000.h.

#define FUNCTION_ARG_PADDING	(	MODE,
		TYPE		)	function_arg_padding (MODE, TYPE)

Definition at line 1436 of file rs6000.h.

#define FUNCTION_ARG_REGNO_P

(

N

)

Value:

((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG     \
   || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
       && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)       \
   || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG     \
       && TARGET_HARD_FLOAT && TARGET_FPRS))

Definition at line 1340 of file rs6000.h.

#define FUNCTION_BOUNDARY   32

Definition at line 498 of file rs6000.h.

#define FUNCTION_MODE   SImode

Definition at line 1840 of file rs6000.h.

#define FUNCTION_PROFILER	(	FILE,
		LABELNO		)	output_function_profiler ((FILE), (LABELNO));

Definition at line 1455 of file rs6000.h.

#define FUNCTION_VALUE	(	VALTYPE,
		FUNC		)	rs6000_function_value ((VALTYPE), (FUNC))

Definition at line 1271 of file rs6000.h.

#define FUNCTION_VALUE_REGNO_P

(

N

)

Value:

((N) == GP_ARG_RETURN             \
   || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS)  \
   || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))

Definition at line 1332 of file rs6000.h.

#define GO_IF_LEGITIMATE_ADDRESS	(	MODE,
		X,
		ADDR		)

Value:

{ if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG))  \
    goto ADDR;              \
}

Definition at line 1676 of file rs6000.h.

#define GO_IF_MODE_DEPENDENT_ADDRESS	(	ADDR,
		LABEL		)

Value:

do {                \
  if (rs6000_mode_dependent_address (ADDR))     \
    goto LABEL;             \
} while (0)

Definition at line 1732 of file rs6000.h.

#define GP_ARG_MAX_REG   10

Definition at line 1294 of file rs6000.h.

#define GP_ARG_MIN_REG   3

Definition at line 1293 of file rs6000.h.

#define GP_ARG_NUM_REG   (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)

Definition at line 1295 of file rs6000.h.

#define GP_ARG_RETURN   GP_ARG_MIN_REG

Definition at line 1312 of file rs6000.h.

#define HARD_FRAME_POINTER_REGNUM   31

Definition at line 915 of file rs6000.h.

#define HARD_REGNO_CALL_PART_CLOBBERED	(	REGNO,
		MODE		)

Value:

((TARGET_32BIT && TARGET_POWERPC64      \
    && (GET_MODE_SIZE (MODE) > 4)  \
    && INT_REGNO_P (REGNO)) ? 1 : 0)

Definition at line 809 of file rs6000.h.

#define HARD_REGNO_MODE_OK	(	REGNO,
		MODE		)	rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]

Definition at line 832 of file rs6000.h.

#define HARD_REGNO_NREGS	(	REGNO,
		MODE		)	rs6000_hard_regno_nregs ((REGNO), (MODE))

Definition at line 807 of file rs6000.h.

#define HARD_REGNO_RENAME_OK	(	SRC,
		DST		)	(! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])

Definition at line 861 of file rs6000.h.

#define HAVE_AS_TLS   0

Definition at line 172 of file rs6000.h.

#define HAVE_PRE_DECREMENT   1

Definition at line 1565 of file rs6000.h.

#define HAVE_PRE_INCREMENT   1

Definition at line 1566 of file rs6000.h.

#define INCOMING_RETURN_ADDR_RTX   gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)

Definition at line 2211 of file rs6000.h.

#define INDEX_REG_CLASS   GENERAL_REGS

Definition at line 1077 of file rs6000.h.

#define INIT_CUMULATIVE_ARGS	(	CUM,
		FNTYPE,
		LIBNAME,
		INDIRECT,
		N_NAMED_ARGS		)	init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)

Definition at line 1384 of file rs6000.h.

#define INIT_CUMULATIVE_INCOMING_ARGS	(	CUM,
		FNTYPE,
		LIBNAME		)	init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)

Definition at line 1390 of file rs6000.h.

#define INIT_CUMULATIVE_LIBCALL_ARGS	(	CUM,
		MODE,
		LIBNAME		)	init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)

Definition at line 1395 of file rs6000.h.

#define INITIAL_ELIMINATION_OFFSET	(	FROM,
		TO,
		OFFSET		)	((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))

Definition at line 1560 of file rs6000.h.

#define INITIALIZE_TRAMPOLINE	(	ADDR,
		FNADDR,
		CXT		)	rs6000_initialize_trampoline (ADDR, FNADDR, CXT)

Definition at line 1489 of file rs6000.h.

#define INT_REG_OK_FOR_BASE_P	(	X,
		STRICT		)

Value:

((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER)    \
   || REGNO_OK_FOR_BASE_P (REGNO (X)))

Definition at line 1651 of file rs6000.h.

#define INT_REG_OK_FOR_INDEX_P	(	X,
		STRICT		)

Value:

((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER)    \
   || REGNO_OK_FOR_INDEX_P (REGNO (X)))

Definition at line 1645 of file rs6000.h.

#define INT_REGNO_P

(

N

)

((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)

Definition at line 792 of file rs6000.h.

#define INT_TYPE_SIZE   32

Definition at line 448 of file rs6000.h.

#define intHI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_INTHI])

Definition at line 2983 of file rs6000.h.

Referenced by rs6000_init_builtins().

#define intQI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_INTQI])

Definition at line 2981 of file rs6000.h.

Referenced by rs6000_init_builtins().

#define intSI_type_internal_node   (rs6000_builtin_types[RS6000_BTI_INTSI])

Definition at line 2985 of file rs6000.h.

Referenced by rs6000_init_builtins().

#define LAST_ALTIVEC_REGNO   108

Definition at line 707 of file rs6000.h.

#define LEGITIMATE_CONSTANT_P

(

X

)

Value:

(((GET_CODE (X) != CONST_DOUBLE       \
     && GET_CODE (X) != CONST_VECTOR)       \
    || GET_MODE (X) == VOIDmode         \
    || (TARGET_POWERPC64 && GET_MODE (X) == DImode)   \
    || easy_fp_constant (X, GET_MODE (X))     \
    || easy_vector_constant (X, GET_MODE (X)))      \
   && !rs6000_tls_referenced_p (X))

Definition at line 1610 of file rs6000.h.

#define LEGITIMIZE_ADDRESS	(	X,
		OLDX,
		MODE,
		WIN		)

Value:

{  rtx result = rs6000_legitimize_address (X, OLDX, MODE);  \
   if (result != NULL_RTX)          \
     {                \
       (X) = result;            \
       goto WIN;            \
     }                \
}

Definition at line 1704 of file rs6000.h.

#define LEGITIMIZE_RELOAD_ADDRESS	(	X,
		MODE,
		OPNUM,
		TYPE,
		IND_LEVELS,
		WIN		)

Value:

do {                       \
  int win;                     \
  (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM),        \
      (int)(TYPE), (IND_LEVELS), &win);        \
  if ( win )                     \
    goto WIN;                    \
} while (0)

Definition at line 1720 of file rs6000.h.

#define LIBCALL_VALUE

(

MODE

)

rs6000_libcall_value ((MODE))

Definition at line 1276 of file rs6000.h.

#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE   64

Definition at line 480 of file rs6000.h.

#define LINK_REGISTER_REGNUM   65

Definition at line 933 of file rs6000.h.

#define LOAD_EXTEND_OP

(

MODE

)

ZERO_EXTEND

Definition at line 1814 of file rs6000.h.

#define LOCAL_ALIGNMENT	(	TYPE,
		ALIGN		)

Value:

((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 :  \
    (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
    (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE \
     && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) ? 64 : ALIGN)

Definition at line 506 of file rs6000.h.

#define LOGICAL_OP_NON_SHORT_CIRCUIT   0

Definition at line 885 of file rs6000.h.

#define LONG_DOUBLE_TYPE_SIZE   rs6000_long_double_type_size

Definition at line 473 of file rs6000.h.

#define long_integer_type_internal_node   (rs6000_builtin_types[RS6000_BTI_long])

Definition at line 2979 of file rs6000.h.

Referenced by rs6000_init_builtins().

#define LONG_LONG_TYPE_SIZE   64

Definition at line 458 of file rs6000.h.

#define LONG_TYPE_SIZE   (TARGET_32BIT ? 32 : 64)

Definition at line 453 of file rs6000.h.

#define long_unsigned_type_internal_node   (rs6000_builtin_types[RS6000_BTI_unsigned_long])

Definition at line 2980 of file rs6000.h.

Referenced by rs6000_init_builtins().

#define MASK_ALIGN_NATURAL   0x00000001

Definition at line 315 of file rs6000.h.

#define MASK_ALIGN_POWER   0x00000000

Definition at line 314 of file rs6000.h.

#define MAX_BITS_PER_WORD   64

Definition at line 414 of file rs6000.h.

#define MAX_CR_REGNO   75

Definition at line 704 of file rs6000.h.

#define MAX_FIXED_MODE_SIZE   GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)

Definition at line 1794 of file rs6000.h.

#define MAX_MOVE_MAX   8

Definition at line 1799 of file rs6000.h.

#define MAX_REGS_PER_ADDRESS   2

Definition at line 1594 of file rs6000.h.

#define MAYBE_R2_AVAILABLE   2,

Definition at line 754 of file rs6000.h.

#define MAYBE_R2_FIXED

Definition at line 755 of file rs6000.h.

#define MEMBER_TYPE_FORCES_BLK	(	FIELD,
		MODE		)

Value:

((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
   || (TARGET_E500_DOUBLE && (MODE) == DFmode))

Definition at line 530 of file rs6000.h.

#define MEMORY_MOVE_COST   rs6000_memory_move_cost

Definition at line 872 of file rs6000.h.

#define MIN_UNITS_PER_WORD   4

Definition at line 421 of file rs6000.h.

#define MODES_TIEABLE_P	(	MODE1,
		MODE2		)

Value:

(SCALAR_FLOAT_MODE_P (MODE1)      \
   ? SCALAR_FLOAT_MODE_P (MODE2)    \
   : SCALAR_FLOAT_MODE_P (MODE2)    \
   ? SCALAR_FLOAT_MODE_P (MODE1)    \
   : GET_MODE_CLASS (MODE1) == MODE_CC    \
   ? GET_MODE_CLASS (MODE2) == MODE_CC    \
   : GET_MODE_CLASS (MODE2) == MODE_CC    \
   ? GET_MODE_CLASS (MODE1) == MODE_CC    \
   : SPE_VECTOR_MODE (MODE1)      \
   ? SPE_VECTOR_MODE (MODE2)      \
   : SPE_VECTOR_MODE (MODE2)      \
   ? SPE_VECTOR_MODE (MODE1)      \
   : ALTIVEC_VECTOR_MODE (MODE1)    \
   ? ALTIVEC_VECTOR_MODE (MODE2)    \
   : ALTIVEC_VECTOR_MODE (MODE2)    \
   ? ALTIVEC_VECTOR_MODE (MODE1)    \
   : 1)

Definition at line 839 of file rs6000.h.

#define MOVE_MAX   (! TARGET_POWERPC64 ? 4 : 8)

Definition at line 1798 of file rs6000.h.

#define MQ_REGNO   64

Definition at line 698 of file rs6000.h.

#define N_REG_CLASSES   (int) LIM_REG_CLASSES

Definition at line 994 of file rs6000.h.

#define NO_FUNCTION_CSE

Definition at line 1846 of file rs6000.h.

#define OBJECT_ELF   2

Definition at line 31 of file rs6000.h.

#define OBJECT_MACHO   4

Definition at line 33 of file rs6000.h.

#define OBJECT_PEF   3

Definition at line 32 of file rs6000.h.

#define OBJECT_XCOFF   1

Definition at line 30 of file rs6000.h.

#define opaque_p_V2SI_type_node   (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])

Definition at line 2958 of file rs6000.h.

Referenced by is_ev64_opaque_type(), rs6000_init_builtins(), rs6000_is_opaque_type(), and spe_init_builtins().

#define opaque_V2SF_type_node   (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])

Definition at line 2957 of file rs6000.h.

Referenced by is_ev64_opaque_type(), rs6000_common_init_builtins(), rs6000_init_builtins(), rs6000_is_opaque_type(), and spe_init_builtins().

#define opaque_V2SI_type_node   (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])

Definition at line 2956 of file rs6000.h.

Referenced by is_ev64_opaque_type(), rs6000_common_init_builtins(), rs6000_init_builtins(), rs6000_is_opaque_type(), and spe_init_builtins().

#define opaque_V4SI_type_node   (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])

Definition at line 2959 of file rs6000.h.

Referenced by altivec_init_builtins(), rs6000_common_init_builtins(), rs6000_init_builtins(), and rs6000_is_opaque_type().

#define OPTIMIZATION_OPTIONS	(	LEVEL,
		SIZE		)	optimization_options(LEVEL,SIZE)

Definition at line 350 of file rs6000.h.

#define OPTION_DEFAULT_SPECS

Value:

{"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
  {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }

Definition at line 267 of file rs6000.h.

#define OUTGOING_REG_PARM_STACK_SPACE

Definition at line 1245 of file rs6000.h.

#define OVERRIDE_OPTIONS   rs6000_override_options (TARGET_CPU_DEFAULT)

Definition at line 347 of file rs6000.h.

#define PAD_VARARGS_DOWN   (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)

Definition at line 1449 of file rs6000.h.

#define PARM_BOUNDARY   (TARGET_32BIT ? 32 : 64)

Definition at line 491 of file rs6000.h.

#define PCC_BITFIELD_TYPE_MATTERS   1

Definition at line 535 of file rs6000.h.

#define PIC_OFFSET_TABLE_REGNUM   (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)

Definition at line 1747 of file rs6000.h.

#define pixel_type_node   (rs6000_builtin_types[RS6000_BTI_pixel])

Definition at line 2973 of file rs6000.h.

Referenced by rs6000_init_builtins(), and rs6000_mangle_fundamental_type().

#define pixel_V8HI_type_node   (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])

Definition at line 2977 of file rs6000.h.

Referenced by rs6000_handle_altivec_attribute(), and rs6000_init_builtins().

#define Pmode   (TARGET_32BIT ? SImode : DImode)

Definition at line 1833 of file rs6000.h.

#define POINTER_SIZE   (TARGET_32BIT ? 32 : 64)

Definition at line 488 of file rs6000.h.

#define PPC405_ERRATUM77   0

Definition at line 57 of file rs6000.h.

Referenced by emit_store_conditional(), and rs6000_file_start().

#define PRE_GCC3_DWARF_FRAME_REGISTERS   77

Definition at line 597 of file rs6000.h.

#define PREFERRED_RELOAD_CLASS	(	X,
		CLASS		)

Value:

((CONSTANT_P (X)          \
    && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
   ? NO_REGS            \
   : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT   \
      && (CLASS) == NON_SPECIAL_REGS)     \
   ? GENERAL_REGS         \
   : (CLASS))

Definition at line 1098 of file rs6000.h.

#define PRINT_OPERAND	(	FILE,
		X,
		CODE		)	print_operand (FILE, X, CODE)

Definition at line 2222 of file rs6000.h.

#define PRINT_OPERAND_ADDRESS	(	FILE,
		ADDR		)	print_operand_address (FILE, ADDR)

Definition at line 2231 of file rs6000.h.

#define PRINT_OPERAND_PUNCT_VALID_P

(

CODE

)

((CODE) == '.' || (CODE) == '&')

Definition at line 2226 of file rs6000.h.

#define PROCESSOR_COMMON   PROCESSOR_PPC601

Definition at line 224 of file rs6000.h.

#define PROCESSOR_DEFAULT   PROCESSOR_RIOS1

Definition at line 230 of file rs6000.h.

#define PROCESSOR_DEFAULT64   PROCESSOR_RS64A

Definition at line 231 of file rs6000.h.

#define PROCESSOR_POWER   PROCESSOR_RIOS1

Definition at line 225 of file rs6000.h.

#define PROCESSOR_POWERPC   PROCESSOR_PPC604

Definition at line 226 of file rs6000.h.

#define PROCESSOR_POWERPC64   PROCESSOR_RS64A

Definition at line 227 of file rs6000.h.

#define PROMOTE_MODE	(	MODE,
		UNSIGNEDP,
		TYPE		)

Value:

if (GET_MODE_CLASS (MODE) == MODE_INT   \
      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
    (MODE) = TARGET_32BIT ? SImode : DImode;

Definition at line 393 of file rs6000.h.

#define PTRDIFF_TYPE   "int"

Definition at line 428 of file rs6000.h.

#define REG_ALLOC_ORDER

Value:

{32,                \
   45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34,    \
   33,                \
   63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51,    \
   50, 49, 48, 47, 46,            \
   75, 74, 69, 68, 72, 71, 70,          \
   0, MAYBE_R2_AVAILABLE          \
   9, 11, 10, 8, 7, 6, 5, 4,          \
   3,               \
   31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,    \
   18, 17, 16, 15, 14, 13, 12,          \
   64, 66, 65,              \
   73, 1, MAYBE_R2_FIXED 67, 76,        \
   /* AltiVec registers.  */          \
   77, 78,              \
   90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80,      \
   79,                \
   96, 95, 94, 93, 92, 91,          \
   108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
   109, 110,              \
   111, 112, 113            \
}

Definition at line 758 of file rs6000.h.

#define REG_CLASS_CONTENTS

Value:

{                      \
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */      \
  { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */      \
  { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */     \
  { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */       \
  { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */     \
  { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */      \
  { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */      \
  { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */     \
  { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */     \
  { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
  { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */      \
  { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */      \
  { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */       \
  { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
  { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */     \
  { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
  { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */       \
  { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */      \
  { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */   \
  { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */       \
  { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff }  /* ALL_REGS */       \
}

Definition at line 1027 of file rs6000.h.

#define REG_CLASS_NAMES

Value:

{                 \
  "NO_REGS",                \
  "BASE_REGS",                \
  "GENERAL_REGS",             \
  "FLOAT_REGS",               \
  "ALTIVEC_REGS",             \
  "VRSAVE_REGS",              \
  "VSCR_REGS",                \
  "SPE_ACC_REGS",                                                       \
  "SPEFSCR_REGS",                                                       \
  "NON_SPECIAL_REGS",             \
  "MQ_REGS",                \
  "LINK_REGS",                \
  "CTR_REGS",               \
  "LINK_OR_CTR_REGS",             \
  "SPECIAL_REGS",             \
  "SPEC_OR_GEN_REGS",             \
  "CR0_REGS",               \
  "CR_REGS",                \
  "NON_FLOAT_REGS",             \
  "XER_REGS",               \
  "ALL_REGS"                \
}

Definition at line 998 of file rs6000.h.

#define REG_OK_FOR_BASE_P

(

X

)

INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)

Definition at line 1656 of file rs6000.h.

#define REG_OK_FOR_INDEX_P

(

X

)

INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)

Definition at line 1655 of file rs6000.h.

#define REG_OK_STRICT_FLAG   0

Definition at line 1640 of file rs6000.h.

#define REG_PARM_STACK_SPACE

(

FNDECL

)

RS6000_REG_SAVE

Definition at line 1241 of file rs6000.h.

#define REGISTER_MOVE_COST   rs6000_register_move_cost

Definition at line 867 of file rs6000.h.

#define REGISTER_NAMES

Definition at line 2025 of file rs6000.h.

 

#define REGISTER_TARGET_PRAGMAS

(

)

Value:

do {        \
  c_register_pragma (0, "longcall", rs6000_pragma_longcall);  \
  targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
} while (0)

Definition at line 356 of file rs6000.h.

#define REGNO_OK_FOR_BASE_P

(

REGNO

)

Value:

((REGNO) < FIRST_PSEUDO_REGISTER        \
 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67    \
   || (REGNO) == FRAME_POINTER_REGNUM       \
 : (reg_renumber[REGNO] > 0         \
    && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67  \
  || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))

Definition at line 1584 of file rs6000.h.

#define REGNO_OK_FOR_INDEX_P

(

REGNO

)

Value:

((REGNO) < FIRST_PSEUDO_REGISTER        \
 ? (REGNO) <= 31 || (REGNO) == 67       \
   || (REGNO) == FRAME_POINTER_REGNUM       \
 : (reg_renumber[REGNO] >= 0          \
    && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67  \
  || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))

Definition at line 1576 of file rs6000.h.

#define REGNO_REG_CLASS

(

REGNO

)

Value:

((REGNO) == 0 ? GENERAL_REGS      \
  : (REGNO) < 32 ? BASE_REGS      \
  : FP_REGNO_P (REGNO) ? FLOAT_REGS   \
  : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS  \
  : (REGNO) == CR0_REGNO ? CR0_REGS   \
  : CR_REGNO_P (REGNO) ? CR_REGS    \
  : (REGNO) == MQ_REGNO ? MQ_REGS   \
  : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
  : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
  : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
  : (REGNO) == XER_REGNO ? XER_REGS   \
  : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
  : (REGNO) == VSCR_REGNO ? VRSAVE_REGS   \
  : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
  : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
  : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
  : NO_REGS)

Definition at line 1057 of file rs6000.h.

#define RETURN_ADDR_RTX	(	COUNT,
		FRAME		)	(rs6000_return_addr (COUNT, FRAME))

Definition at line 1514 of file rs6000.h.

#define RETURN_ADDRESS_OFFSET

Value:

((DEFAULT_ABI == ABI_AIX            \
   || DEFAULT_ABI == ABI_DARWIN)  ? (TARGET_32BIT ? 8 : 16) : \
  (DEFAULT_ABI == ABI_V4)   ? 4 :       \
  (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))

Definition at line 1505 of file rs6000.h.

#define RETURN_POPS_ARGS	(	FUNDECL,
		FUNTYPE,
		SIZE		)	0

Definition at line 1264 of file rs6000.h.

#define REVERSE_CONDITION	(	CODE,
		MODE		)	rs6000_reverse_condition (MODE, CODE)

Definition at line 1882 of file rs6000.h.

#define REVERSIBLE_CC_MODE

(

MODE

)

1

Definition at line 1879 of file rs6000.h.

#define RS6000_ALIGN

(