Open64: osprey/kg++fe/gnu/i386/insn-emit.c Source File

00001 /*
00002  * Copyright 2003, 2004 PathScale, Inc.  All Rights Reserved.
00003  */
00004 
00005 /* Generated automatically by the program `genemit'
00006 from the machine description file `md'.  */
00007 
00008 #include "config.h"
00009 #include "system.h"
00010 #include "rtl.h"
00011 #include "tm_p.h"
00012 #include "function.h"
00013 #include "expr.h"
00014 #include "optabs.h"
00015 #include "real.h"
00016 #include "flags.h"
00017 #include "output.h"
00018 #include "insn-config.h"
00019 #include "hard-reg-set.h"
00020 #include "recog.h"
00021 #include "resource.h"
00022 #include "reload.h"
00023 #include "toplev.h"
00024 #include "ggc.h"
00025 
00026 #define FAIL return (end_sequence (), _val)
00027 #define DONE return (_val = get_insns (), end_sequence (), _val)
00028 
00029 /* ../../gcc/gcc/config/i386/i386.md:444 */
00030 rtx
00031 gen_cmpdi_ccno_1_rex64 (operand0, operand1)
00032      rtx operand0;
00033      rtx operand1;
00034 {
00035   return gen_rtx_SET (VOIDmode,
00036   gen_rtx_REG (VOIDmode,
00037   17),
00038   gen_rtx_COMPARE (VOIDmode,
00039   operand0,
00040   operand1));
00041 }
00042 
00043 /* ../../gcc/gcc/config/i386/i386.md:473 */
00044 rtx
00045 gen_cmpdi_1_insn_rex64 (operand0, operand1)
00046      rtx operand0;
00047      rtx operand1;
00048 {
00049   return gen_rtx_SET (VOIDmode,
00050   gen_rtx_REG (VOIDmode,
00051   17),
00052   gen_rtx_COMPARE (VOIDmode,
00053   operand0,
00054   operand1));
00055 }
00056 
00057 /* ../../gcc/gcc/config/i386/i386.md:641 */
00058 rtx
00059 gen_cmpqi_ext_3_insn (operand0, operand1)
00060      rtx operand0;
00061      rtx operand1;
00062 {
00063   return gen_rtx_SET (VOIDmode,
00064   gen_rtx_REG (VOIDmode,
00065   17),
00066   gen_rtx_COMPARE (VOIDmode,
00067   gen_rtx_SUBREG (QImode,
00068   gen_rtx_ZERO_EXTRACT (SImode,
00069   operand0,
00070   GEN_INT (8LL),
00071   GEN_INT (8LL)),
00072   0),
00073   operand1));
00074 }
00075 
00076 /* ../../gcc/gcc/config/i386/i386.md:655 */
00077 rtx
00078 gen_cmpqi_ext_3_insn_rex64 (operand0, operand1)
00079      rtx operand0;
00080      rtx operand1;
00081 {
00082   return gen_rtx_SET (VOIDmode,
00083   gen_rtx_REG (VOIDmode,
00084   17),
00085   gen_rtx_COMPARE (VOIDmode,
00086   gen_rtx_SUBREG (QImode,
00087   gen_rtx_ZERO_EXTRACT (SImode,
00088   operand0,
00089   GEN_INT (8LL),
00090   GEN_INT (8LL)),
00091   0),
00092   operand1));
00093 }
00094 
00095 /* ../../gcc/gcc/config/i386/i386.md:927 */
00096 rtx
00097 gen_x86_fnstsw_1 (operand0)
00098      rtx operand0;
00099 {
00100   return gen_rtx_SET (VOIDmode,
00101   operand0,
00102   gen_rtx_UNSPEC (HImode,
00103   gen_rtvec (1,
00104     gen_rtx_REG (VOIDmode,
00105   18)),
00106   24));
00107 }
00108 
00109 /* ../../gcc/gcc/config/i386/i386.md:940 */
00110 rtx
00111 gen_x86_sahf_1 (operand0)
00112      rtx operand0;
00113 {
00114   return gen_rtx_SET (VOIDmode,
00115   gen_rtx_REG (CCmode,
00116   17),
00117   gen_rtx_UNSPEC (CCmode,
00118   gen_rtvec (1,
00119     operand0),
00120   25));
00121 }
00122 
00123 /* ../../gcc/gcc/config/i386/i386.md:1080 */
00124 rtx
00125 gen_popsi1 (operand0)
00126      rtx operand0;
00127 {
00128   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00129     gen_rtx_SET (VOIDmode,
00130   operand0,
00131   gen_rtx_MEM (SImode,
00132   gen_rtx_REG (SImode,
00133   7))),
00134     gen_rtx_SET (VOIDmode,
00135   gen_rtx_REG (SImode,
00136   7),
00137   gen_rtx_PLUS (SImode,
00138   gen_rtx_REG (SImode,
00139   7),
00140   GEN_INT (4LL)))));
00141 }
00142 
00143 /* ../../gcc/gcc/config/i386/i386.md:1684 */
00144 rtx
00145 gen_movsi_insv_1 (operand0, operand1)
00146      rtx operand0;
00147      rtx operand1;
00148 {
00149   return gen_rtx_SET (VOIDmode,
00150   gen_rtx_ZERO_EXTRACT (SImode,
00151   operand0,
00152   GEN_INT (8LL),
00153   GEN_INT (8LL)),
00154   operand1);
00155 }
00156 
00157 /* ../../gcc/gcc/config/i386/i386.md:1728 */
00158 rtx
00159 gen_pushdi2_rex64 (operand0, operand1)
00160      rtx operand0;
00161      rtx operand1;
00162 {
00163   return gen_rtx_SET (VOIDmode,
00164   operand0,
00165   operand1);
00166 }
00167 
00168 /* ../../gcc/gcc/config/i386/i386.md:1801 */
00169 rtx
00170 gen_popdi1 (operand0)
00171      rtx operand0;
00172 {
00173   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00174     gen_rtx_SET (VOIDmode,
00175   operand0,
00176   gen_rtx_MEM (DImode,
00177   gen_rtx_REG (DImode,
00178   7))),
00179     gen_rtx_SET (VOIDmode,
00180   gen_rtx_REG (DImode,
00181   7),
00182   gen_rtx_PLUS (DImode,
00183   gen_rtx_REG (DImode,
00184   7),
00185   GEN_INT (8LL)))));
00186 }
00187 
00188 /* ../../gcc/gcc/config/i386/i386.md:2819 */
00189 rtx
00190 gen_swapxf (operand0, operand1)
00191      rtx operand0;
00192      rtx operand1;
00193 {
00194   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00195     gen_rtx_SET (VOIDmode,
00196   operand0,
00197   operand1),
00198     gen_rtx_SET (VOIDmode,
00199   operand1,
00200   operand0)));
00201 }
00202 
00203 /* ../../gcc/gcc/config/i386/i386.md:2834 */
00204 rtx
00205 gen_swaptf (operand0, operand1)
00206      rtx operand0;
00207      rtx operand1;
00208 {
00209   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00210     gen_rtx_SET (VOIDmode,
00211   operand0,
00212   operand1),
00213     gen_rtx_SET (VOIDmode,
00214   operand1,
00215   operand0)));
00216 }
00217 
00218 /* ../../gcc/gcc/config/i386/i386.md:2864 */
00219 rtx
00220 gen_zero_extendhisi2_and (operand0, operand1)
00221      rtx operand0;
00222      rtx operand1;
00223 {
00224   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00225     gen_rtx_SET (VOIDmode,
00226   operand0,
00227   gen_rtx_ZERO_EXTEND (SImode,
00228   operand1)),
00229     gen_rtx_CLOBBER (VOIDmode,
00230   gen_rtx_REG (CCmode,
00231   17))));
00232 }
00233 
00234 /* ../../gcc/gcc/config/i386/i386.md:3043 */
00235 rtx
00236 gen_zero_extendsidi2_32 (operand0, operand1)
00237      rtx operand0;
00238      rtx operand1;
00239 {
00240   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00241     gen_rtx_SET (VOIDmode,
00242   operand0,
00243   gen_rtx_ZERO_EXTEND (DImode,
00244   operand1)),
00245     gen_rtx_CLOBBER (VOIDmode,
00246   gen_rtx_REG (CCmode,
00247   17))));
00248 }
00249 
00250 /* ../../gcc/gcc/config/i386/i386.md:3051 */
00251 rtx
00252 gen_zero_extendsidi2_rex64 (operand0, operand1)
00253      rtx operand0;
00254      rtx operand1;
00255 {
00256   return gen_rtx_SET (VOIDmode,
00257   operand0,
00258   gen_rtx_ZERO_EXTEND (DImode,
00259   operand1));
00260 }
00261 
00262 /* ../../gcc/gcc/config/i386/i386.md:3086 */
00263 rtx
00264 gen_zero_extendhidi2 (operand0, operand1)
00265      rtx operand0;
00266      rtx operand1;
00267 {
00268   return gen_rtx_SET (VOIDmode,
00269   operand0,
00270   gen_rtx_ZERO_EXTEND (DImode,
00271   operand1));
00272 }
00273 
00274 /* ../../gcc/gcc/config/i386/i386.md:3096 */
00275 rtx
00276 gen_zero_extendqidi2 (operand0, operand1)
00277      rtx operand0;
00278      rtx operand1;
00279 {
00280   return gen_rtx_SET (VOIDmode,
00281   operand0,
00282   gen_rtx_ZERO_EXTEND (DImode,
00283   operand1));
00284 }
00285 
00286 /* ../../gcc/gcc/config/i386/i386.md:3130 */
00287 rtx
00288 gen_extendsidi2_rex64 (operand0, operand1)
00289      rtx operand0;
00290      rtx operand1;
00291 {
00292   return gen_rtx_SET (VOIDmode,
00293   operand0,
00294   gen_rtx_SIGN_EXTEND (DImode,
00295   operand1));
00296 }
00297 
00298 /* ../../gcc/gcc/config/i386/i386.md:3142 */
00299 rtx
00300 gen_extendhidi2 (operand0, operand1)
00301      rtx operand0;
00302      rtx operand1;
00303 {
00304   return gen_rtx_SET (VOIDmode,
00305   operand0,
00306   gen_rtx_SIGN_EXTEND (DImode,
00307   operand1));
00308 }
00309 
00310 /* ../../gcc/gcc/config/i386/i386.md:3150 */
00311 rtx
00312 gen_extendqidi2 (operand0, operand1)
00313      rtx operand0;
00314      rtx operand1;
00315 {
00316   return gen_rtx_SET (VOIDmode,
00317   operand0,
00318   gen_rtx_SIGN_EXTEND (DImode,
00319   operand1));
00320 }
00321 
00322 /* ../../gcc/gcc/config/i386/i386.md:3232 */
00323 rtx
00324 gen_extendhisi2 (operand0, operand1)
00325      rtx operand0;
00326      rtx operand1;
00327 {
00328   return gen_rtx_SET (VOIDmode,
00329   operand0,
00330   gen_rtx_SIGN_EXTEND (SImode,
00331   operand1));
00332 }
00333 
00334 /* ../../gcc/gcc/config/i386/i386.md:3285 */
00335 rtx
00336 gen_extendqihi2 (operand0, operand1)
00337      rtx operand0;
00338      rtx operand1;
00339 {
00340   return gen_rtx_SET (VOIDmode,
00341   operand0,
00342   gen_rtx_SIGN_EXTEND (HImode,
00343   operand1));
00344 }
00345 
00346 /* ../../gcc/gcc/config/i386/i386.md:3311 */
00347 rtx
00348 gen_extendqisi2 (operand0, operand1)
00349      rtx operand0;
00350      rtx operand1;
00351 {
00352   return gen_rtx_SET (VOIDmode,
00353   operand0,
00354   gen_rtx_SIGN_EXTEND (SImode,
00355   operand1));
00356 }
00357 
00358 /* ../../gcc/gcc/config/i386/i386.md:3744 */
00359 rtx
00360 gen_truncdfsf2_3 (operand0, operand1)
00361      rtx operand0;
00362      rtx operand1;
00363 {
00364   return gen_rtx_SET (VOIDmode,
00365   operand0,
00366   gen_rtx_FLOAT_TRUNCATE (SFmode,
00367   operand1));
00368 }
00369 
00370 /* ../../gcc/gcc/config/i386/i386.md:3758 */
00371 rtx
00372 gen_truncdfsf2_sse_only (operand0, operand1)
00373      rtx operand0;
00374      rtx operand1;
00375 {
00376   return gen_rtx_SET (VOIDmode,
00377   operand0,
00378   gen_rtx_FLOAT_TRUNCATE (SFmode,
00379   operand1));
00380 }
00381 
00382 /* ../../gcc/gcc/config/i386/i386.md:4122 */
00383 rtx
00384 gen_fix_truncdi_nomemory (operand0, operand1, operand2, operand3, operand4)
00385      rtx operand0;
00386      rtx operand1;
00387      rtx operand2;
00388      rtx operand3;
00389      rtx operand4;
00390 {
00391   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (5,
00392     gen_rtx_SET (VOIDmode,
00393   operand0,
00394   gen_rtx_FIX (DImode,
00395   operand1)),
00396     gen_rtx_USE (VOIDmode,
00397   operand2),
00398     gen_rtx_USE (VOIDmode,
00399   operand3),
00400     gen_rtx_CLOBBER (VOIDmode,
00401   operand4),
00402     gen_rtx_CLOBBER (VOIDmode,
00403   gen_rtx_SCRATCH (DFmode))));
00404 }
00405 
00406 /* ../../gcc/gcc/config/i386/i386.md:4134 */
00407 rtx
00408 gen_fix_truncdi_memory (operand0, operand1, operand2, operand3)
00409      rtx operand0;
00410      rtx operand1;
00411      rtx operand2;
00412      rtx operand3;
00413 {
00414   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
00415     gen_rtx_SET (VOIDmode,
00416   operand0,
00417   gen_rtx_FIX (DImode,
00418   operand1)),
00419     gen_rtx_USE (VOIDmode,
00420   operand2),
00421     gen_rtx_USE (VOIDmode,
00422   operand3),
00423     gen_rtx_CLOBBER (VOIDmode,
00424   gen_rtx_SCRATCH (DFmode))));
00425 }
00426 
00427 /* ../../gcc/gcc/config/i386/i386.md:4175 */
00428 rtx
00429 gen_fix_truncsfdi_sse (operand0, operand1)
00430      rtx operand0;
00431      rtx operand1;
00432 {
00433   return gen_rtx_SET (VOIDmode,
00434   operand0,
00435   gen_rtx_FIX (DImode,
00436   operand1));
00437 }
00438 
00439 /* ../../gcc/gcc/config/i386/i386.md:4182 */
00440 rtx
00441 gen_fix_truncdfdi_sse (operand0, operand1)
00442      rtx operand0;
00443      rtx operand1;
00444 {
00445   return gen_rtx_SET (VOIDmode,
00446   operand0,
00447   gen_rtx_FIX (DImode,
00448   operand1));
00449 }
00450 
00451 /* ../../gcc/gcc/config/i386/i386.md:4261 */
00452 rtx
00453 gen_fix_truncsi_nomemory (operand0, operand1, operand2, operand3, operand4)
00454      rtx operand0;
00455      rtx operand1;
00456      rtx operand2;
00457      rtx operand3;
00458      rtx operand4;
00459 {
00460   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
00461     gen_rtx_SET (VOIDmode,
00462   operand0,
00463   gen_rtx_FIX (SImode,
00464   operand1)),
00465     gen_rtx_USE (VOIDmode,
00466   operand2),
00467     gen_rtx_USE (VOIDmode,
00468   operand3),
00469     gen_rtx_CLOBBER (VOIDmode,
00470   operand4)));
00471 }
00472 
00473 /* ../../gcc/gcc/config/i386/i386.md:4272 */
00474 rtx
00475 gen_fix_truncsi_memory (operand0, operand1, operand2, operand3)
00476      rtx operand0;
00477      rtx operand1;
00478      rtx operand2;
00479      rtx operand3;
00480 {
00481   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00482     gen_rtx_SET (VOIDmode,
00483   operand0,
00484   gen_rtx_FIX (SImode,
00485   operand1)),
00486     gen_rtx_USE (VOIDmode,
00487   operand2),
00488     gen_rtx_USE (VOIDmode,
00489   operand3)));
00490 }
00491 
00492 /* ../../gcc/gcc/config/i386/i386.md:4283 */
00493 rtx
00494 gen_fix_truncsfsi_sse (operand0, operand1)
00495      rtx operand0;
00496      rtx operand1;
00497 {
00498   return gen_rtx_SET (VOIDmode,
00499   operand0,
00500   gen_rtx_FIX (SImode,
00501   operand1));
00502 }
00503 
00504 /* ../../gcc/gcc/config/i386/i386.md:4290 */
00505 rtx
00506 gen_fix_truncdfsi_sse (operand0, operand1)
00507      rtx operand0;
00508      rtx operand1;
00509 {
00510   return gen_rtx_SET (VOIDmode,
00511   operand0,
00512   gen_rtx_FIX (SImode,
00513   operand1));
00514 }
00515 
00516 /* ../../gcc/gcc/config/i386/i386.md:4376 */
00517 rtx
00518 gen_fix_trunchi_nomemory (operand0, operand1, operand2, operand3, operand4)
00519      rtx operand0;
00520      rtx operand1;
00521      rtx operand2;
00522      rtx operand3;
00523      rtx operand4;
00524 {
00525   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
00526     gen_rtx_SET (VOIDmode,
00527   operand0,
00528   gen_rtx_FIX (HImode,
00529   operand1)),
00530     gen_rtx_USE (VOIDmode,
00531   operand2),
00532     gen_rtx_USE (VOIDmode,
00533   operand3),
00534     gen_rtx_CLOBBER (VOIDmode,
00535   operand4)));
00536 }
00537 
00538 /* ../../gcc/gcc/config/i386/i386.md:4387 */
00539 rtx
00540 gen_fix_trunchi_memory (operand0, operand1, operand2, operand3)
00541      rtx operand0;
00542      rtx operand1;
00543      rtx operand2;
00544      rtx operand3;
00545 {
00546   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00547     gen_rtx_SET (VOIDmode,
00548   operand0,
00549   gen_rtx_FIX (HImode,
00550   operand1)),
00551     gen_rtx_USE (VOIDmode,
00552   operand2),
00553     gen_rtx_USE (VOIDmode,
00554   operand3)));
00555 }
00556 
00557 /* ../../gcc/gcc/config/i386/i386.md:4424 */
00558 rtx
00559 gen_x86_fnstcw_1 (operand0)
00560      rtx operand0;
00561 {
00562   return gen_rtx_SET (VOIDmode,
00563   operand0,
00564   gen_rtx_UNSPEC (HImode,
00565   gen_rtvec (1,
00566     gen_rtx_REG (HImode,
00567   18)),
00568   26));
00569 }
00570 
00571 /* ../../gcc/gcc/config/i386/i386.md:4434 */
00572 rtx
00573 gen_x86_fldcw_1 (operand0)
00574      rtx operand0;
00575 {
00576   return gen_rtx_SET (VOIDmode,
00577   gen_rtx_REG (HImode,
00578   18),
00579   gen_rtx_UNSPEC (HImode,
00580   gen_rtvec (1,
00581     operand0),
00582   28));
00583 }
00584 
00585 /* ../../gcc/gcc/config/i386/i386.md:4450 */
00586 rtx
00587 gen_floathisf2 (operand0, operand1)
00588      rtx operand0;
00589      rtx operand1;
00590 {
00591   return gen_rtx_SET (VOIDmode,
00592   operand0,
00593   gen_rtx_FLOAT (SFmode,
00594   operand1));
00595 }
00596 
00597 /* ../../gcc/gcc/config/i386/i386.md:4526 */
00598 rtx
00599 gen_floathidf2 (operand0, operand1)
00600      rtx operand0;
00601      rtx operand1;
00602 {
00603   return gen_rtx_SET (VOIDmode,
00604   operand0,
00605   gen_rtx_FLOAT (DFmode,
00606   operand1));
00607 }
00608 
00609 /* ../../gcc/gcc/config/i386/i386.md:4602 */
00610 rtx
00611 gen_floathixf2 (operand0, operand1)
00612      rtx operand0;
00613      rtx operand1;
00614 {
00615   return gen_rtx_SET (VOIDmode,
00616   operand0,
00617   gen_rtx_FLOAT (XFmode,
00618   operand1));
00619 }
00620 
00621 /* ../../gcc/gcc/config/i386/i386.md:4613 */
00622 rtx
00623 gen_floathitf2 (operand0, operand1)
00624      rtx operand0;
00625      rtx operand1;
00626 {
00627   return gen_rtx_SET (VOIDmode,
00628   operand0,
00629   gen_rtx_FLOAT (TFmode,
00630   operand1));
00631 }
00632 
00633 /* ../../gcc/gcc/config/i386/i386.md:4624 */
00634 rtx
00635 gen_floatsixf2 (operand0, operand1)
00636      rtx operand0;
00637      rtx operand1;
00638 {
00639   return gen_rtx_SET (VOIDmode,
00640   operand0,
00641   gen_rtx_FLOAT (XFmode,
00642   operand1));
00643 }
00644 
00645 /* ../../gcc/gcc/config/i386/i386.md:4635 */
00646 rtx
00647 gen_floatsitf2 (operand0, operand1)
00648      rtx operand0;
00649      rtx operand1;
00650 {
00651   return gen_rtx_SET (VOIDmode,
00652   operand0,
00653   gen_rtx_FLOAT (TFmode,
00654   operand1));
00655 }
00656 
00657 /* ../../gcc/gcc/config/i386/i386.md:4646 */
00658 rtx
00659 gen_floatdixf2 (operand0, operand1)
00660      rtx operand0;
00661      rtx operand1;
00662 {
00663   return gen_rtx_SET (VOIDmode,
00664   operand0,
00665   gen_rtx_FLOAT (XFmode,
00666   operand1));
00667 }
00668 
00669 /* ../../gcc/gcc/config/i386/i386.md:4657 */
00670 rtx
00671 gen_floatditf2 (operand0, operand1)
00672      rtx operand0;
00673      rtx operand1;
00674 {
00675   return gen_rtx_SET (VOIDmode,
00676   operand0,
00677   gen_rtx_FLOAT (TFmode,
00678   operand1));
00679 }
00680 
00681 /* ../../gcc/gcc/config/i386/i386.md:4787 */
00682 rtx
00683 gen_addqi3_cc (operand0, operand1, operand2)
00684      rtx operand0;
00685      rtx operand1;
00686      rtx operand2;
00687 {
00688   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00689     gen_rtx_SET (VOIDmode,
00690   gen_rtx_REG (CCmode,
00691   17),
00692   gen_rtx_UNSPEC (CCmode,
00693   gen_rtvec (2,
00694     operand1,
00695     operand2),
00696   27)),
00697     gen_rtx_SET (VOIDmode,
00698   operand0,
00699   gen_rtx_PLUS (QImode,
00700   operand1,
00701   operand2))));
00702 }
00703 
00704 /* ../../gcc/gcc/config/i386/i386.md:5352 */
00705 rtx
00706 gen_addsi_1_zext (operand0, operand1, operand2)
00707      rtx operand0;
00708      rtx operand1;
00709      rtx operand2;
00710 {
00711   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00712     gen_rtx_SET (VOIDmode,
00713   operand0,
00714   gen_rtx_ZERO_EXTEND (DImode,
00715   gen_rtx_PLUS (SImode,
00716   operand1,
00717   operand2))),
00718     gen_rtx_CLOBBER (VOIDmode,
00719   gen_rtx_REG (CCmode,
00720   17))));
00721 }
00722 
00723 /* ../../gcc/gcc/config/i386/i386.md:6223 */
00724 rtx
00725 gen_addqi_ext_1 (operand0, operand1, operand2)
00726      rtx operand0;
00727      rtx operand1;
00728      rtx operand2;
00729 {
00730   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00731     gen_rtx_SET (VOIDmode,
00732   gen_rtx_ZERO_EXTRACT (SImode,
00733   operand0,
00734   GEN_INT (8LL),
00735   GEN_INT (8LL)),
00736   gen_rtx_PLUS (SImode,
00737   gen_rtx_ZERO_EXTRACT (SImode,
00738   operand1,
00739   GEN_INT (8LL),
00740   GEN_INT (8LL)),
00741   operand2)),
00742     gen_rtx_CLOBBER (VOIDmode,
00743   gen_rtx_REG (CCmode,
00744   17))));
00745 }
00746 
00747 /* ../../gcc/gcc/config/i386/i386.md:6377 */
00748 rtx
00749 gen_subdi3_carry_rex64 (operand0, operand1, operand2)
00750      rtx operand0;
00751      rtx operand1;
00752      rtx operand2;
00753 {
00754   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00755     gen_rtx_SET (VOIDmode,
00756   operand0,
00757   gen_rtx_MINUS (DImode,
00758   operand1,
00759   gen_rtx_PLUS (DImode,
00760   gen_rtx_LTU (DImode,
00761   gen_rtx_REG (CCmode,
00762   17),
00763   const0_rtx),
00764   operand2))),
00765     gen_rtx_CLOBBER (VOIDmode,
00766   gen_rtx_REG (CCmode,
00767   17))));
00768 }
00769 
00770 /* ../../gcc/gcc/config/i386/i386.md:6427 */
00771 rtx
00772 gen_subsi3_carry (operand0, operand1, operand2)
00773      rtx operand0;
00774      rtx operand1;
00775      rtx operand2;
00776 {
00777   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00778     gen_rtx_SET (VOIDmode,
00779   operand0,
00780   gen_rtx_MINUS (SImode,
00781   operand1,
00782   gen_rtx_PLUS (SImode,
00783   gen_rtx_LTU (SImode,
00784   gen_rtx_REG (CCmode,
00785   17),
00786   const0_rtx),
00787   operand2))),
00788     gen_rtx_CLOBBER (VOIDmode,
00789   gen_rtx_REG (CCmode,
00790   17))));
00791 }
00792 
00793 /* ../../gcc/gcc/config/i386/i386.md:6440 */
00794 rtx
00795 gen_subsi3_carry_zext (operand0, operand1, operand2)
00796      rtx operand0;
00797      rtx operand1;
00798      rtx operand2;
00799 {
00800   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00801     gen_rtx_SET (VOIDmode,
00802   operand0,
00803   gen_rtx_ZERO_EXTEND (DImode,
00804   gen_rtx_MINUS (SImode,
00805   operand1,
00806   gen_rtx_PLUS (SImode,
00807   gen_rtx_LTU (SImode,
00808   gen_rtx_REG (CCmode,
00809   17),
00810   const0_rtx),
00811   operand2)))),
00812     gen_rtx_CLOBBER (VOIDmode,
00813   gen_rtx_REG (CCmode,
00814   17))));
00815 }
00816 
00817 /* ../../gcc/gcc/config/i386/i386.md:7129 */
00818 rtx
00819 gen_divqi3 (operand0, operand1, operand2)
00820      rtx operand0;
00821      rtx operand1;
00822      rtx operand2;
00823 {
00824   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00825     gen_rtx_SET (VOIDmode,
00826   operand0,
00827   gen_rtx_DIV (QImode,
00828   operand1,
00829   operand2)),
00830     gen_rtx_CLOBBER (VOIDmode,
00831   gen_rtx_REG (CCmode,
00832   17))));
00833 }
00834 
00835 /* ../../gcc/gcc/config/i386/i386.md:7140 */
00836 rtx
00837 gen_udivqi3 (operand0, operand1, operand2)
00838      rtx operand0;
00839      rtx operand1;
00840      rtx operand2;
00841 {
00842   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00843     gen_rtx_SET (VOIDmode,
00844   operand0,
00845   gen_rtx_UDIV (QImode,
00846   operand1,
00847   operand2)),
00848     gen_rtx_CLOBBER (VOIDmode,
00849   gen_rtx_REG (CCmode,
00850   17))));
00851 }
00852 
00853 /* ../../gcc/gcc/config/i386/i386.md:7352 */
00854 rtx
00855 gen_divmodhi4 (operand0, operand1, operand2, operand3)
00856      rtx operand0;
00857      rtx operand1;
00858      rtx operand2;
00859      rtx operand3;
00860 {
00861   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00862     gen_rtx_SET (VOIDmode,
00863   operand0,
00864   gen_rtx_DIV (HImode,
00865   operand1,
00866   operand2)),
00867     gen_rtx_SET (VOIDmode,
00868   operand3,
00869   gen_rtx_MOD (HImode,
00870   operand1,
00871   operand2)),
00872     gen_rtx_CLOBBER (VOIDmode,
00873   gen_rtx_REG (CCmode,
00874   17))));
00875 }
00876 
00877 /* ../../gcc/gcc/config/i386/i386.md:7365 */
00878 rtx
00879 gen_udivmoddi4 (operand0, operand1, operand2, operand3)
00880      rtx operand0;
00881      rtx operand1;
00882      rtx operand2;
00883      rtx operand3;
00884 {
00885   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00886     gen_rtx_SET (VOIDmode,
00887   operand0,
00888   gen_rtx_UDIV (DImode,
00889   operand1,
00890   operand2)),
00891     gen_rtx_SET (VOIDmode,
00892   operand3,
00893   gen_rtx_UMOD (DImode,
00894   operand1,
00895   operand2)),
00896     gen_rtx_CLOBBER (VOIDmode,
00897   gen_rtx_REG (CCmode,
00898   17))));
00899 }
00900 
00901 /* ../../gcc/gcc/config/i386/i386.md:7409 */
00902 rtx
00903 gen_udivmodsi4 (operand0, operand1, operand2, operand3)
00904      rtx operand0;
00905      rtx operand1;
00906      rtx operand2;
00907      rtx operand3;
00908 {
00909   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00910     gen_rtx_SET (VOIDmode,
00911   operand0,
00912   gen_rtx_UDIV (SImode,
00913   operand1,
00914   operand2)),
00915     gen_rtx_SET (VOIDmode,
00916   operand3,
00917   gen_rtx_UMOD (SImode,
00918   operand1,
00919   operand2)),
00920     gen_rtx_CLOBBER (VOIDmode,
00921   gen_rtx_REG (CCmode,
00922   17))));
00923 }
00924 
00925 /* ../../gcc/gcc/config/i386/i386.md:7522 */
00926 rtx
00927 gen_testsi_1 (operand0, operand1)
00928      rtx operand0;
00929      rtx operand1;
00930 {
00931   return gen_rtx_SET (VOIDmode,
00932   gen_rtx_REG (VOIDmode,
00933   17),
00934   gen_rtx_COMPARE (VOIDmode,
00935   gen_rtx_AND (SImode,
00936   operand0,
00937   operand1),
00938   const0_rtx));
00939 }
00940 
00941 /* ../../gcc/gcc/config/i386/i386.md:8113 */
00942 rtx
00943 gen_andqi_ext_0 (operand0, operand1, operand2)
00944      rtx operand0;
00945      rtx operand1;
00946      rtx operand2;
00947 {
00948   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00949     gen_rtx_SET (VOIDmode,
00950   gen_rtx_ZERO_EXTRACT (SImode,
00951   operand0,
00952   GEN_INT (8LL),
00953   GEN_INT (8LL)),
00954   gen_rtx_AND (SImode,
00955   gen_rtx_ZERO_EXTRACT (SImode,
00956   operand1,
00957   GEN_INT (8LL),
00958   GEN_INT (8LL)),
00959   operand2)),
00960     gen_rtx_CLOBBER (VOIDmode,
00961   gen_rtx_REG (CCmode,
00962   17))));
00963 }
00964 
00965 /* ../../gcc/gcc/config/i386/i386.md:8519 */
00966 rtx
00967 gen_iorqi_ext_0 (operand0, operand1, operand2)
00968      rtx operand0;
00969      rtx operand1;
00970      rtx operand2;
00971 {
00972   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00973     gen_rtx_SET (VOIDmode,
00974   gen_rtx_ZERO_EXTRACT (SImode,
00975   operand0,
00976   GEN_INT (8LL),
00977   GEN_INT (8LL)),
00978   gen_rtx_IOR (SImode,
00979   gen_rtx_ZERO_EXTRACT (SImode,
00980   operand1,
00981   GEN_INT (8LL),
00982   GEN_INT (8LL)),
00983   operand2)),
00984     gen_rtx_CLOBBER (VOIDmode,
00985   gen_rtx_REG (CCmode,
00986   17))));
00987 }
00988 
00989 /* ../../gcc/gcc/config/i386/i386.md:8857 */
00990 rtx
00991 gen_xorqi_ext_0 (operand0, operand1, operand2)
00992      rtx operand0;
00993      rtx operand1;
00994      rtx operand2;
00995 {
00996   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00997     gen_rtx_SET (VOIDmode,
00998   gen_rtx_ZERO_EXTRACT (SImode,
00999   operand0,
01000   GEN_INT (8LL),
01001   GEN_INT (8LL)),
01002   gen_rtx_XOR (SImode,
01003   gen_rtx_ZERO_EXTRACT (SImode,
01004   operand1,
01005   GEN_INT (8LL),
01006   GEN_INT (8LL)),
01007   operand2)),
01008     gen_rtx_CLOBBER (VOIDmode,
01009   gen_rtx_REG (CCmode,
01010   17))));
01011 }
01012 
01013 /* ../../gcc/gcc/config/i386/i386.md:9284 */
01014 rtx
01015 gen_negsf2_memory (operand0, operand1)
01016      rtx operand0;
01017      rtx operand1;
01018 {
01019   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01020     gen_rtx_SET (VOIDmode,
01021   operand0,
01022   gen_rtx_NEG (SFmode,
01023   operand1)),
01024     gen_rtx_CLOBBER (VOIDmode,
01025   gen_rtx_REG (CCmode,
01026   17))));
01027 }
01028 
01029 /* ../../gcc/gcc/config/i386/i386.md:9291 */
01030 rtx
01031 gen_negsf2_ifs (operand0, operand1, operand2)
01032      rtx operand0;
01033      rtx operand1;
01034      rtx operand2;
01035 {
01036   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01037     gen_rtx_SET (VOIDmode,
01038   operand0,
01039   gen_rtx_NEG (SFmode,
01040   operand1)),
01041     gen_rtx_USE (VOIDmode,
01042   operand2),
01043     gen_rtx_CLOBBER (VOIDmode,
01044   gen_rtx_REG (CCmode,
01045   17))));
01046 }
01047 
01048 /* ../../gcc/gcc/config/i386/i386.md:9423 */
01049 rtx
01050 gen_negdf2_memory (operand0, operand1)
01051      rtx operand0;
01052      rtx operand1;
01053 {
01054   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01055     gen_rtx_SET (VOIDmode,
01056   operand0,
01057   gen_rtx_NEG (DFmode,
01058   operand1)),
01059     gen_rtx_CLOBBER (VOIDmode,
01060   gen_rtx_REG (CCmode,
01061   17))));
01062 }
01063 
01064 /* ../../gcc/gcc/config/i386/i386.md:9430 */
01065 rtx
01066 gen_negdf2_ifs (operand0, operand1, operand2)
01067      rtx operand0;
01068      rtx operand1;
01069      rtx operand2;
01070 {
01071   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01072     gen_rtx_SET (VOIDmode,
01073   operand0,
01074   gen_rtx_NEG (DFmode,
01075   operand1)),
01076     gen_rtx_USE (VOIDmode,
01077   operand2),
01078     gen_rtx_CLOBBER (VOIDmode,
01079   gen_rtx_REG (CCmode,
01080   17))));
01081 }
01082 
01083 /* ../../gcc/gcc/config/i386/i386.md:9744 */
01084 rtx
01085 gen_abssf2_memory (operand0, operand1)
01086      rtx operand0;
01087      rtx operand1;
01088 {
01089   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01090     gen_rtx_SET (VOIDmode,
01091   operand0,
01092   gen_rtx_ABS (SFmode,
01093   operand1)),
01094     gen_rtx_CLOBBER (VOIDmode,
01095   gen_rtx_REG (CCmode,
01096   17))));
01097 }
01098 
01099 /* ../../gcc/gcc/config/i386/i386.md:9751 */
01100 rtx
01101 gen_abssf2_ifs (operand0, operand1, operand2)
01102      rtx operand0;
01103      rtx operand1;
01104      rtx operand2;
01105 {
01106   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01107     gen_rtx_SET (VOIDmode,
01108   operand0,
01109   gen_rtx_ABS (SFmode,
01110   operand1)),
01111     gen_rtx_USE (VOIDmode,
01112   operand2),
01113     gen_rtx_CLOBBER (VOIDmode,
01114   gen_rtx_REG (CCmode,
01115   17))));
01116 }
01117 
01118 /* ../../gcc/gcc/config/i386/i386.md:9872 */
01119 rtx
01120 gen_absdf2_memory (operand0, operand1)
01121      rtx operand0;
01122      rtx operand1;
01123 {
01124   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01125     gen_rtx_SET (VOIDmode,
01126   operand0,
01127   gen_rtx_ABS (DFmode,
01128   operand1)),
01129     gen_rtx_CLOBBER (VOIDmode,
01130   gen_rtx_REG (CCmode,
01131   17))));
01132 }
01133 
01134 /* ../../gcc/gcc/config/i386/i386.md:9879 */
01135 rtx
01136 gen_absdf2_ifs (operand0, operand1, operand2)
01137      rtx operand0;
01138      rtx operand1;
01139      rtx operand2;
01140 {
01141   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01142     gen_rtx_SET (VOIDmode,
01143   operand0,
01144   gen_rtx_ABS (DFmode,
01145   operand1)),
01146     gen_rtx_USE (VOIDmode,
01147   operand2),
01148     gen_rtx_CLOBBER (VOIDmode,
01149   gen_rtx_REG (CCmode,
01150   17))));
01151 }
01152 
01153 /* ../../gcc/gcc/config/i386/i386.md:10466 */
01154 rtx
01155 gen_ashldi3_1 (operand0, operand1, operand2)
01156      rtx operand0;
01157      rtx operand1;
01158      rtx operand2;
01159 {
01160   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01161     gen_rtx_SET (VOIDmode,
01162   operand0,
01163   gen_rtx_ASHIFT (DImode,
01164   operand1,
01165   operand2)),
01166     gen_rtx_CLOBBER (VOIDmode,
01167   gen_rtx_SCRATCH (SImode)),
01168     gen_rtx_CLOBBER (VOIDmode,
01169   gen_rtx_REG (CCmode,
01170   17))));
01171 }
01172 
01173 /* ../../gcc/gcc/config/i386/i386.md:10504 */
01174 rtx
01175 gen_x86_shld_1 (operand0, operand1, operand2)
01176      rtx operand0;
01177      rtx operand1;
01178      rtx operand2;
01179 {
01180   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01181     gen_rtx_SET (VOIDmode,
01182   operand0,
01183   gen_rtx_IOR (SImode,
01184   gen_rtx_ASHIFT (SImode,
01185   operand0,
01186   operand2),
01187   gen_rtx_LSHIFTRT (SImode,
01188   operand1,
01189   gen_rtx_MINUS (QImode,
01190   GEN_INT (32LL),
01191   operand2)))),
01192     gen_rtx_CLOBBER (VOIDmode,
01193   gen_rtx_REG (CCmode,
01194   17))));
01195 }
01196 
01197 /* ../../gcc/gcc/config/i386/i386.md:11098 */
01198 rtx
01199 gen_ashrdi3_63_rex64 (operand0, operand1, operand2)
01200      rtx operand0;
01201      rtx operand1;
01202      rtx operand2;
01203 {
01204   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01205     gen_rtx_SET (VOIDmode,
01206   operand0,
01207   gen_rtx_ASHIFTRT (DImode,
01208   operand1,
01209   operand2)),
01210     gen_rtx_CLOBBER (VOIDmode,
01211   gen_rtx_REG (CCmode,
01212   17))));
01213 }
01214 
01215 /* ../../gcc/gcc/config/i386/i386.md:11179 */
01216 rtx
01217 gen_ashrdi3_1 (operand0, operand1, operand2)
01218      rtx operand0;
01219      rtx operand1;
01220      rtx operand2;
01221 {
01222   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01223     gen_rtx_SET (VOIDmode,
01224   operand0,
01225   gen_rtx_ASHIFTRT (DImode,
01226   operand1,
01227   operand2)),
01228     gen_rtx_CLOBBER (VOIDmode,
01229   gen_rtx_SCRATCH (SImode)),
01230     gen_rtx_CLOBBER (VOIDmode,
01231   gen_rtx_REG (CCmode,
01232   17))));
01233 }
01234 
01235 /* ../../gcc/gcc/config/i386/i386.md:11217 */
01236 rtx
01237 gen_x86_shrd_1 (operand0, operand1, operand2)
01238      rtx operand0;
01239      rtx operand1;
01240      rtx operand2;
01241 {
01242   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01243     gen_rtx_SET (VOIDmode,
01244   operand0,
01245   gen_rtx_IOR (SImode,
01246   gen_rtx_ASHIFTRT (SImode,
01247   operand0,
01248   operand2),
01249   gen_rtx_ASHIFT (SImode,
01250   operand1,
01251   gen_rtx_MINUS (QImode,
01252   GEN_INT (32LL),
01253   operand2)))),
01254     gen_rtx_CLOBBER (VOIDmode,
01255   gen_rtx_REG (CCmode,
01256   17))));
01257 }
01258 
01259 /* ../../gcc/gcc/config/i386/i386.md:11262 */
01260 rtx
01261 gen_ashrsi3_31 (operand0, operand1, operand2)
01262      rtx operand0;
01263      rtx operand1;
01264      rtx operand2;
01265 {
01266   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01267     gen_rtx_SET (VOIDmode,
01268   operand0,
01269   gen_rtx_ASHIFTRT (SImode,
01270   operand1,
01271   operand2)),
01272     gen_rtx_CLOBBER (VOIDmode,
01273   gen_rtx_REG (CCmode,
01274   17))));
01275 }
01276 
01277 /* ../../gcc/gcc/config/i386/i386.md:11675 */
01278 rtx
01279 gen_lshrdi3_1 (operand0, operand1, operand2)
01280      rtx operand0;
01281      rtx operand1;
01282      rtx operand2;
01283 {
01284   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01285     gen_rtx_SET (VOIDmode,
01286   operand0,
01287   gen_rtx_LSHIFTRT (DImode,
01288   operand1,
01289   operand2)),
01290     gen_rtx_CLOBBER (VOIDmode,
01291   gen_rtx_SCRATCH (SImode)),
01292     gen_rtx_CLOBBER (VOIDmode,
01293   gen_rtx_REG (CCmode,
01294   17))));
01295 }
01296 
01297 /* ../../gcc/gcc/config/i386/i386.md:12571 */
01298 rtx
01299 gen_setcc_2 (operand0, operand1)
01300      rtx operand0;
01301      rtx operand1;
01302 {
01303   return gen_rtx_SET (VOIDmode,
01304   gen_rtx_STRICT_LOW_PART (VOIDmode,
01305   operand0),
01306   gen_rtx (GET_CODE (operand1), QImode,
01307     gen_rtx_REG (VOIDmode,
01308   17),
01309     const0_rtx));
01310 }
01311 
01312 /* ../../gcc/gcc/config/i386/i386.md:13117 */
01313 rtx
01314 gen_jump (operand0)
01315      rtx operand0;
01316 {
01317   return gen_rtx_SET (VOIDmode,
01318   pc_rtx,
01319   gen_rtx_LABEL_REF (VOIDmode,
01320   operand0));
01321 }
01322 
01323 /* ../../gcc/gcc/config/i386/i386.md:13227 */
01324 rtx
01325 gen_doloop_end_internal (operand0, operand1, operand2)
01326      rtx operand0;
01327      rtx operand1;
01328      rtx operand2;
01329 {
01330   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
01331     gen_rtx_SET (VOIDmode,
01332   pc_rtx,
01333   gen_rtx_IF_THEN_ELSE (VOIDmode,
01334   gen_rtx_NE (VOIDmode,
01335   operand1,
01336   const1_rtx),
01337   gen_rtx_LABEL_REF (VOIDmode,
01338   operand0),
01339   pc_rtx)),
01340     gen_rtx_SET (VOIDmode,
01341   operand2,
01342   gen_rtx_PLUS (SImode,
01343   operand1,
01344   constm1_rtx)),
01345     gen_rtx_CLOBBER (VOIDmode,
01346   gen_rtx_SCRATCH (SImode)),
01347     gen_rtx_CLOBBER (VOIDmode,
01348   gen_rtx_REG (CCmode,
01349   17))));
01350 }
01351 
01352 /* ../../gcc/gcc/config/i386/i386.md:13536 */
01353 rtx
01354 gen_blockage (operand0)
01355      rtx operand0;
01356 {
01357   return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
01358   gen_rtvec (1,
01359     operand0),
01360   0);
01361 }
01362 
01363 /* ../../gcc/gcc/config/i386/i386.md:13558 */
01364 rtx
01365 gen_return_internal ()
01366 {
01367   return gen_rtx_RETURN (VOIDmode);
01368 }
01369 
01370 /* ../../gcc/gcc/config/i386/i386.md:13566 */
01371 rtx
01372 gen_return_pop_internal (operand0)
01373      rtx operand0;
01374 {
01375   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01376     gen_rtx_RETURN (VOIDmode),
01377     gen_rtx_USE (VOIDmode,
01378   operand0)));
01379 }
01380 
01381 /* ../../gcc/gcc/config/i386/i386.md:13575 */
01382 rtx
01383 gen_return_indirect_internal (operand0)
01384      rtx operand0;
01385 {
01386   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01387     gen_rtx_RETURN (VOIDmode),
01388     gen_rtx_USE (VOIDmode,
01389   operand0)));
01390 }
01391 
01392 /* ../../gcc/gcc/config/i386/i386.md:13583 */
01393 rtx
01394 gen_nop ()
01395 {
01396   return const0_rtx;
01397 }
01398 
01399 /* ../../gcc/gcc/config/i386/i386.md:13597 */
01400 rtx
01401 gen_set_got (operand0)
01402      rtx operand0;
01403 {
01404   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01405     gen_rtx_SET (VOIDmode,
01406   operand0,
01407   gen_rtx_UNSPEC (SImode,
01408   gen_rtvec (1,
01409     const0_rtx),
01410   12)),
01411     gen_rtx_CLOBBER (VOIDmode,
01412   gen_rtx_REG (CCmode,
01413   17))));
01414 }
01415 
01416 /* ../../gcc/gcc/config/i386/i386.md:13638 */
01417 rtx
01418 gen_eh_return_si (operand0)
01419      rtx operand0;
01420 {
01421   return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
01422   gen_rtvec (1,
01423     operand0),
01424   13);
01425 }
01426 
01427 /* ../../gcc/gcc/config/i386/i386.md:13647 */
01428 rtx
01429 gen_eh_return_di (operand0)
01430      rtx operand0;
01431 {
01432   return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
01433   gen_rtvec (1,
01434     operand0),
01435   13);
01436 }
01437 
01438 /* ../../gcc/gcc/config/i386/i386.md:13656 */
01439 rtx
01440 gen_leave ()
01441 {
01442   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01443     gen_rtx_SET (VOIDmode,
01444   gen_rtx_REG (SImode,
01445   7),
01446   gen_rtx_PLUS (SImode,
01447   gen_rtx_REG (SImode,
01448   6),
01449   GEN_INT (4LL))),
01450     gen_rtx_SET (VOIDmode,
01451   gen_rtx_REG (SImode,
01452   6),
01453   gen_rtx_MEM (SImode,
01454   gen_rtx_REG (SImode,
01455   6))),
01456     gen_rtx_CLOBBER (VOIDmode,
01457   gen_rtx_MEM (BLKmode,
01458   gen_rtx_SCRATCH (VOIDmode)))));
01459 }
01460 
01461 /* ../../gcc/gcc/config/i386/i386.md:13668 */
01462 rtx
01463 gen_leave_rex64 ()
01464 {
01465   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
01466     gen_rtx_SET (VOIDmode,
01467   gen_rtx_REG (DImode,
01468   7),
01469   gen_rtx_PLUS (DImode,
01470   gen_rtx_REG (DImode,
01471   6),
01472   GEN_INT (8LL))),
01473     gen_rtx_SET (VOIDmode,
01474   gen_rtx_REG (DImode,
01475   6),
01476   gen_rtx_MEM (DImode,
01477   gen_rtx_REG (DImode,
01478   6))),
01479     gen_rtx_CLOBBER (VOIDmode,
01480   gen_rtx_MEM (BLKmode,
01481   gen_rtx_SCRATCH (VOIDmode)))));
01482 }
01483 
01484 /* ../../gcc/gcc/config/i386/i386.md:13766 */
01485 rtx
01486 gen_ffssi_1 (operand0, operand1)
01487      rtx operand0;
01488      rtx operand1;
01489 {
01490   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01491     gen_rtx_SET (VOIDmode,
01492   gen_rtx_REG (CCZmode,
01493   17),
01494   gen_rtx_COMPARE (CCZmode,
01495   operand1,
01496   const0_rtx)),
01497     gen_rtx_SET (VOIDmode,
01498   operand0,
01499   gen_rtx_UNSPEC (SImode,
01500   gen_rtvec (1,
01501     operand1),
01502   23))));
01503 }
01504 
01505 /* ../../gcc/gcc/config/i386/i386.md:14678 */
01506 rtx
01507 gen_sqrtsf2_1 (operand0, operand1)
01508      rtx operand0;
01509      rtx operand1;
01510 {
01511   return gen_rtx_SET (VOIDmode,
01512   operand0,
01513   gen_rtx_SQRT (SFmode,
01514   operand1));
01515 }
01516 
01517 /* ../../gcc/gcc/config/i386/i386.md:14690 */
01518 rtx
01519 gen_sqrtsf2_1_sse_only (operand0, operand1)
01520      rtx operand0;
01521      rtx operand1;
01522 {
01523   return gen_rtx_SET (VOIDmode,
01524   operand0,
01525   gen_rtx_SQRT (SFmode,
01526   operand1));
01527 }
01528 
01529 /* ../../gcc/gcc/config/i386/i386.md:14699 */
01530 rtx
01531 gen_sqrtsf2_i387 (operand0, operand1)
01532      rtx operand0;
01533      rtx operand1;
01534 {
01535   return gen_rtx_SET (VOIDmode,
01536   operand0,
01537   gen_rtx_SQRT (SFmode,
01538   operand1));
01539 }
01540 
01541 /* ../../gcc/gcc/config/i386/i386.md:14719 */
01542 rtx
01543 gen_sqrtdf2_1 (operand0, operand1)
01544      rtx operand0;
01545      rtx operand1;
01546 {
01547   return gen_rtx_SET (VOIDmode,
01548   operand0,
01549   gen_rtx_SQRT (DFmode,
01550   operand1));
01551 }
01552 
01553 /* ../../gcc/gcc/config/i386/i386.md:14731 */
01554 rtx
01555 gen_sqrtdf2_1_sse_only (operand0, operand1)
01556      rtx operand0;
01557      rtx operand1;
01558 {
01559   return gen_rtx_SET (VOIDmode,
01560   operand0,
01561   gen_rtx_SQRT (DFmode,
01562   operand1));
01563 }
01564 
01565 /* ../../gcc/gcc/config/i386/i386.md:14740 */
01566 rtx
01567 gen_sqrtdf2_i387 (operand0, operand1)
01568      rtx operand0;
01569      rtx operand1;
01570 {
01571   return gen_rtx_SET (VOIDmode,
01572   operand0,
01573   gen_rtx_SQRT (DFmode,
01574   operand1));
01575 }
01576 
01577 /* ../../gcc/gcc/config/i386/i386.md:14761 */
01578 rtx
01579 gen_sqrtxf2 (operand0, operand1)
01580      rtx operand0;
01581      rtx operand1;
01582 {
01583   return gen_rtx_SET (VOIDmode,
01584   operand0,
01585   gen_rtx_SQRT (XFmode,
01586   operand1));
01587 }
01588 
01589 /* ../../gcc/gcc/config/i386/i386.md:14771 */
01590 rtx
01591 gen_sqrttf2 (operand0, operand1)
01592      rtx operand0;
01593      rtx operand1;
01594 {
01595   return gen_rtx_SET (VOIDmode,
01596   operand0,
01597   gen_rtx_SQRT (TFmode,
01598   operand1));
01599 }
01600 
01601 /* ../../gcc/gcc/config/i386/i386.md:14821 */
01602 rtx
01603 gen_sindf2 (operand0, operand1)
01604      rtx operand0;
01605      rtx operand1;
01606 {
01607   return gen_rtx_SET (VOIDmode,
01608   operand0,
01609   gen_rtx_UNSPEC (DFmode,
01610   gen_rtvec (1,
01611     operand1),
01612   21));
01613 }
01614 
01615 /* ../../gcc/gcc/config/i386/i386.md:14830 */
01616 rtx
01617 gen_sinsf2 (operand0, operand1)
01618      rtx operand0;
01619      rtx operand1;
01620 {
01621   return gen_rtx_SET (VOIDmode,
01622   operand0,
01623   gen_rtx_UNSPEC (SFmode,
01624   gen_rtvec (1,
01625     operand1),
01626   21));
01627 }
01628 
01629 /* ../../gcc/gcc/config/i386/i386.md:14850 */
01630 rtx
01631 gen_sinxf2 (operand0, operand1)
01632      rtx operand0;
01633      rtx operand1;
01634 {
01635   return gen_rtx_SET (VOIDmode,
01636   operand0,
01637   gen_rtx_UNSPEC (XFmode,
01638   gen_rtvec (1,
01639     operand1),
01640   21));
01641 }
01642 
01643 /* ../../gcc/gcc/config/i386/i386.md:14859 */
01644 rtx
01645 gen_sintf2 (operand0, operand1)
01646      rtx operand0;
01647      rtx operand1;
01648 {
01649   return gen_rtx_SET (VOIDmode,
01650   operand0,
01651   gen_rtx_UNSPEC (TFmode,
01652   gen_rtvec (1,
01653     operand1),
01654   21));
01655 }
01656 
01657 /* ../../gcc/gcc/config/i386/i386.md:14868 */
01658 rtx
01659 gen_cosdf2 (operand0, operand1)
01660      rtx operand0;
01661      rtx operand1;
01662 {
01663   return gen_rtx_SET (VOIDmode,
01664   operand0,
01665   gen_rtx_UNSPEC (DFmode,
01666   gen_rtvec (1,
01667     operand1),
01668   22));
01669 }
01670 
01671 /* ../../gcc/gcc/config/i386/i386.md:14877 */
01672 rtx
01673 gen_cossf2 (operand0, operand1)
01674      rtx operand0;
01675      rtx operand1;
01676 {
01677   return gen_rtx_SET (VOIDmode,
01678   operand0,
01679   gen_rtx_UNSPEC (SFmode,
01680   gen_rtvec (1,
01681     operand1),
01682   22));
01683 }
01684 
01685 /* ../../gcc/gcc/config/i386/i386.md:14897 */
01686 rtx
01687 gen_cosxf2 (operand0, operand1)
01688      rtx operand0;
01689      rtx operand1;
01690 {
01691   return gen_rtx_SET (VOIDmode,
01692   operand0,
01693   gen_rtx_UNSPEC (XFmode,
01694   gen_rtvec (1,
01695     operand1),
01696   22));
01697 }
01698 
01699 /* ../../gcc/gcc/config/i386/i386.md:14906 */
01700 rtx
01701 gen_costf2 (operand0, operand1)
01702      rtx operand0;
01703      rtx operand1;
01704 {
01705   return gen_rtx_SET (VOIDmode,
01706   operand0,
01707   gen_rtx_UNSPEC (TFmode,
01708   gen_rtvec (1,
01709     operand1),
01710   22));
01711 }
01712 
01713 /* ../../gcc/gcc/config/i386/i386.md:14917 */
01714 rtx
01715 gen_cld ()
01716 {
01717   return gen_rtx_SET (VOIDmode,
01718   gen_rtx_REG (SImode,
01719   19),
01720   const0_rtx);
01721 }
01722 
01723 /* ../../gcc/gcc/config/i386/i386.md:15115 */
01724 rtx
01725 gen_strmovdi_rex_1 (operand0, operand1, operand2, operand3)
01726      rtx operand0;
01727      rtx operand1;
01728      rtx operand2;
01729      rtx operand3;
01730 {
01731   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
01732     gen_rtx_SET (VOIDmode,
01733   gen_rtx_MEM (DImode,
01734   operand2),
01735   gen_rtx_MEM (DImode,
01736   operand3)),
01737     gen_rtx_SET (VOIDmode,
01738   operand0,
01739   gen_rtx_PLUS (DImode,
01740   operand2,
01741   GEN_INT (8LL))),
01742     gen_rtx_SET (VOIDmode,
01743   operand1,
01744   gen_rtx_PLUS (DImode,
01745   operand3,
01746   GEN_INT (8LL))),
01747     gen_rtx_USE (VOIDmode,
01748   gen_rtx_REG (SImode,
01749   19))));
01750 }
01751 
01752 /* ../../gcc/gcc/config/i386/i386.md:15131 */
01753 rtx
01754 gen_strmovsi_1 (operand0, operand1, operand2, operand3)
01755      rtx operand0;
01756      rtx operand1;
01757      rtx operand2;
01758      rtx operand3;
01759 {
01760   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
01761     gen_rtx_SET (VOIDmode,
01762   gen_rtx_MEM (SImode,
01763   operand2),
01764   gen_rtx_MEM (SImode,
01765   operand3)),
01766     gen_rtx_SET (VOIDmode,
01767   operand0,
01768   gen_rtx_PLUS (SImode,
01769   operand2,
01770   GEN_INT (4LL))),
01771     gen_rtx_SET (VOIDmode,
01772   operand1,
01773   gen_rtx_PLUS (SImode,
01774   operand3,
01775   GEN_INT (4LL))),
01776     gen_rtx_USE (VOIDmode,
01777   gen_rtx_REG (SImode,
01778   19))));
01779 }
01780 
01781 /* ../../gcc/gcc/config/i386/i386.md:15147 */
01782 rtx
01783 gen_strmovsi_rex_1 (operand0, operand1, operand2, operand3)
01784      rtx operand0;
01785      rtx operand1;
01786      rtx operand2;
01787      rtx operand3;
01788 {
01789   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
01790     gen_rtx_SET (VOIDmode,
01791   gen_rtx_MEM (SImode,
01792   operand2),
01793   gen_rtx_MEM (SImode,
01794   operand3)),
01795     gen_rtx_SET (VOIDmode,
01796   operand0,
01797   gen_rtx_PLUS (DImode,
01798   operand2,
01799   GEN_INT (4LL))),
01800     gen_rtx_SET (VOIDmode,
01801   operand1,
01802   gen_rtx_PLUS (DImode,
01803   operand3,
01804   GEN_INT (4LL))),
01805     gen_rtx_USE (VOIDmode,
01806   gen_rtx_REG (SImode,
01807   19))));
01808 }
01809 
01810 /* ../../gcc/gcc/config/i386/i386.md:15163 */
01811 rtx
01812 gen_strmovhi_1 (operand0, operand1, operand2, operand3)
01813      rtx operand0;
01814      rtx operand1;
01815      rtx operand2;
01816      rtx operand3;
01817 {
01818   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
01819     gen_rtx_SET (VOIDmode,
01820   gen_rtx_MEM (HImode,
01821   operand2),
01822   gen_rtx_MEM (HImode,
01823   operand3)),
01824     gen_rtx_SET (VOIDmode,
01825   operand0,
01826   gen_rtx_PLUS (SImode,
01827   operand2,
01828   GEN_INT (2LL))),
01829     gen_rtx_SET (VOIDmode,
01830   operand1,
01831   gen_rtx_PLUS (SImode,
01832   operand3,
01833   GEN_INT (2LL))),
01834     gen_rtx_USE (VOIDmode,
01835   gen_rtx_REG (SImode,
01836   19))));
01837 }
01838 
01839 /* ../../gcc/gcc/config/i386/i386.md:15179 */
01840 rtx
01841 gen_strmovhi_rex_1 (operand0, operand1, operand2, operand3)
01842      rtx operand0;
01843      rtx operand1;
01844      rtx operand2;
01845      rtx operand3;
01846 {
01847   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
01848     gen_rtx_SET (VOIDmode,
01849   gen_rtx_MEM (HImode,
01850   operand2),
01851   gen_rtx_MEM (HImode,
01852   operand3)),
01853     gen_rtx_SET (VOIDmode,
01854   operand0,
01855   gen_rtx_PLUS (DImode,
01856   operand2,
01857   GEN_INT (2LL))),
01858     gen_rtx_SET (VOIDmode,
01859   operand1,
01860   gen_rtx_PLUS (DImode,
01861   operand3,
01862   GEN_INT (2LL))),
01863     gen_rtx_USE (VOIDmode,
01864   gen_rtx_REG (SImode,
01865   19))));
01866 }
01867 
01868 /* ../../gcc/gcc/config/i386/i386.md:15195 */
01869 rtx
01870 gen_strmovqi_1 (operand0, operand1, operand2, operand3)
01871      rtx operand0;
01872      rtx operand1;
01873      rtx operand2;
01874      rtx operand3;
01875 {
01876   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
01877     gen_rtx_SET (VOIDmode,
01878   gen_rtx_MEM (QImode,
01879   operand2),
01880   gen_rtx_MEM (QImode,
01881   operand3)),
01882     gen_rtx_SET (VOIDmode,
01883   operand0,
01884   gen_rtx_PLUS (SImode,
01885   operand2,
01886   const1_rtx)),
01887     gen_rtx_SET (VOIDmode,
01888   operand1,
01889   gen_rtx_PLUS (SImode,
01890   operand3,
01891   const1_rtx)),
01892     gen_rtx_USE (VOIDmode,
01893   gen_rtx_REG (SImode,
01894   19))));
01895 }
01896 
01897 /* ../../gcc/gcc/config/i386/i386.md:15211 */
01898 rtx
01899 gen_strmovqi_rex_1 (operand0, operand1, operand2, operand3)
01900      rtx operand0;
01901      rtx operand1;
01902      rtx operand2;
01903      rtx operand3;
01904 {
01905   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
01906     gen_rtx_SET (VOIDmode,
01907   gen_rtx_MEM (QImode,
01908   operand2),
01909   gen_rtx_MEM (QImode,
01910   operand3)),
01911     gen_rtx_SET (VOIDmode,
01912   operand0,
01913   gen_rtx_PLUS (DImode,
01914   operand2,
01915   const1_rtx)),
01916     gen_rtx_SET (VOIDmode,
01917   operand1,
01918   gen_rtx_PLUS (DImode,
01919   operand3,
01920   const1_rtx)),
01921     gen_rtx_USE (VOIDmode,
01922   gen_rtx_REG (SImode,
01923   19))));
01924 }
01925 
01926 /* ../../gcc/gcc/config/i386/i386.md:15227 */
01927 rtx
01928 gen_rep_movdi_rex64 (operand0, operand1, operand2, operand3, operand4, operand5)
01929      rtx operand0;
01930      rtx operand1;
01931      rtx operand2;
01932      rtx operand3;
01933      rtx operand4;
01934      rtx operand5;
01935 {
01936   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
01937     gen_rtx_SET (VOIDmode,
01938   operand2,
01939   const0_rtx),
01940     gen_rtx_SET (VOIDmode,
01941   operand0,
01942   gen_rtx_PLUS (DImode,
01943   gen_rtx_ASHIFT (DImode,
01944   operand5,
01945   GEN_INT (3LL)),
01946   operand3)),
01947     gen_rtx_SET (VOIDmode,
01948   operand1,
01949   gen_rtx_PLUS (DImode,
01950   gen_rtx_ASHIFT (DImode,
01951   operand5,
01952   GEN_INT (3LL)),
01953   operand4)),
01954     gen_rtx_SET (VOIDmode,
01955   gen_rtx_MEM (BLKmode,
01956   operand3),
01957   gen_rtx_MEM (BLKmode,
01958   operand4)),
01959     gen_rtx_USE (VOIDmode,
01960   operand5),
01961     gen_rtx_USE (VOIDmode,
01962   gen_rtx_REG (SImode,
01963   19))));
01964 }
01965 
01966 /* ../../gcc/gcc/config/i386/i386.md:15247 */
01967 rtx
01968 gen_rep_movsi (operand0, operand1, operand2, operand3, operand4, operand5)
01969      rtx operand0;
01970      rtx operand1;
01971      rtx operand2;
01972      rtx operand3;
01973      rtx operand4;
01974      rtx operand5;
01975 {
01976   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
01977     gen_rtx_SET (VOIDmode,
01978   operand2,
01979   const0_rtx),
01980     gen_rtx_SET (VOIDmode,
01981   operand0,
01982   gen_rtx_PLUS (SImode,
01983   gen_rtx_ASHIFT (SImode,
01984   operand5,
01985   GEN_INT (2LL)),
01986   operand3)),
01987     gen_rtx_SET (VOIDmode,
01988   operand1,
01989   gen_rtx_PLUS (SImode,
01990   gen_rtx_ASHIFT (SImode,
01991   operand5,
01992   GEN_INT (2LL)),
01993   operand4)),
01994     gen_rtx_SET (VOIDmode,
01995   gen_rtx_MEM (BLKmode,
01996   operand3),
01997   gen_rtx_MEM (BLKmode,
01998   operand4)),
01999     gen_rtx_USE (VOIDmode,
02000   operand5),
02001     gen_rtx_USE (VOIDmode,
02002   gen_rtx_REG (SImode,
02003   19))));
02004 }
02005 
02006 /* ../../gcc/gcc/config/i386/i386.md:15267 */
02007 rtx
02008 gen_rep_movsi_rex64 (operand0, operand1, operand2, operand3, operand4, operand5)
02009      rtx operand0;
02010      rtx operand1;
02011      rtx operand2;
02012      rtx operand3;
02013      rtx operand4;
02014      rtx operand5;
02015 {
02016   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
02017     gen_rtx_SET (VOIDmode,
02018   operand2,
02019   const0_rtx),
02020     gen_rtx_SET (VOIDmode,
02021   operand0,
02022   gen_rtx_PLUS (DImode,
02023   gen_rtx_ASHIFT (DImode,
02024   operand5,
02025   GEN_INT (2LL)),
02026   operand3)),
02027     gen_rtx_SET (VOIDmode,
02028   operand1,
02029   gen_rtx_PLUS (DImode,
02030   gen_rtx_ASHIFT (DImode,
02031   operand5,
02032   GEN_INT (2LL)),
02033   operand4)),
02034     gen_rtx_SET (VOIDmode,
02035   gen_rtx_MEM (BLKmode,
02036   operand3),
02037   gen_rtx_MEM (BLKmode,
02038   operand4)),
02039     gen_rtx_USE (VOIDmode,
02040   operand5),
02041     gen_rtx_USE (VOIDmode,
02042   gen_rtx_REG (SImode,
02043   19))));
02044 }
02045 
02046 /* ../../gcc/gcc/config/i386/i386.md:15287 */
02047 rtx
02048 gen_rep_movqi (operand0, operand1, operand2, operand3, operand4, operand5)
02049      rtx operand0;
02050      rtx operand1;
02051      rtx operand2;
02052      rtx operand3;
02053      rtx operand4;
02054      rtx operand5;
02055 {
02056   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
02057     gen_rtx_SET (VOIDmode,
02058   operand2,
02059   const0_rtx),
02060     gen_rtx_SET (VOIDmode,
02061   operand0,
02062   gen_rtx_PLUS (SImode,
02063   operand3,
02064   operand5)),
02065     gen_rtx_SET (VOIDmode,
02066   operand1,
02067   gen_rtx_PLUS (SImode,
02068   operand4,
02069   operand5)),
02070     gen_rtx_SET (VOIDmode,
02071   gen_rtx_MEM (BLKmode,
02072   operand3),
02073   gen_rtx_MEM (BLKmode,
02074   operand4)),
02075     gen_rtx_USE (VOIDmode,
02076   operand5),
02077     gen_rtx_USE (VOIDmode,
02078   gen_rtx_REG (SImode,
02079   19))));
02080 }
02081 
02082 /* ../../gcc/gcc/config/i386/i386.md:15305 */
02083 rtx
02084 gen_rep_movqi_rex64 (operand0, operand1, operand2, operand3, operand4, operand5)
02085      rtx operand0;
02086      rtx operand1;
02087      rtx operand2;
02088      rtx operand3;
02089      rtx operand4;
02090      rtx operand5;
02091 {
02092   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
02093     gen_rtx_SET (VOIDmode,
02094   operand2,
02095   const0_rtx),
02096     gen_rtx_SET (VOIDmode,
02097   operand0,
02098   gen_rtx_PLUS (DImode,
02099   operand3,
02100   operand5)),
02101     gen_rtx_SET (VOIDmode,
02102   operand1,
02103   gen_rtx_PLUS (DImode,
02104   operand4,
02105   operand5)),
02106     gen_rtx_SET (VOIDmode,
02107   gen_rtx_MEM (BLKmode,
02108   operand3),
02109   gen_rtx_MEM (BLKmode,
02110   operand4)),
02111     gen_rtx_USE (VOIDmode,
02112   operand5),
02113     gen_rtx_USE (VOIDmode,
02114   gen_rtx_REG (SImode,
02115   19))));
02116 }
02117 
02118 /* ../../gcc/gcc/config/i386/i386.md:15463 */
02119 rtx
02120 gen_strsetdi_rex_1 (operand0, operand1, operand2)
02121      rtx operand0;
02122      rtx operand1;
02123      rtx operand2;
02124 {
02125   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02126     gen_rtx_SET (VOIDmode,
02127   gen_rtx_MEM (SImode,
02128   operand1),
02129   operand2),
02130     gen_rtx_SET (VOIDmode,
02131   operand0,
02132   gen_rtx_PLUS (DImode,
02133   operand1,
02134   GEN_INT (8LL))),
02135     gen_rtx_USE (VOIDmode,
02136   gen_rtx_REG (SImode,
02137   19))));
02138 }
02139 
02140 /* ../../gcc/gcc/config/i386/i386.md:15476 */
02141 rtx
02142 gen_strsetsi_1 (operand0, operand1, operand2)
02143      rtx operand0;
02144      rtx operand1;
02145      rtx operand2;
02146 {
02147   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02148     gen_rtx_SET (VOIDmode,
02149   gen_rtx_MEM (SImode,
02150   operand1),
02151   operand2),
02152     gen_rtx_SET (VOIDmode,
02153   operand0,
02154   gen_rtx_PLUS (SImode,
02155   operand1,
02156   GEN_INT (4LL))),
02157     gen_rtx_USE (VOIDmode,
02158   gen_rtx_REG (SImode,
02159   19))));
02160 }
02161 
02162 /* ../../gcc/gcc/config/i386/i386.md:15489 */
02163 rtx
02164 gen_strsetsi_rex_1 (operand0, operand1, operand2)
02165      rtx operand0;
02166      rtx operand1;
02167      rtx operand2;
02168 {
02169   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02170     gen_rtx_SET (VOIDmode,
02171   gen_rtx_MEM (SImode,
02172   operand1),
02173   operand2),
02174     gen_rtx_SET (VOIDmode,
02175   operand0,
02176   gen_rtx_PLUS (DImode,
02177   operand1,
02178   GEN_INT (4LL))),
02179     gen_rtx_USE (VOIDmode,
02180   gen_rtx_REG (SImode,
02181   19))));
02182 }
02183 
02184 /* ../../gcc/gcc/config/i386/i386.md:15502 */
02185 rtx
02186 gen_strsethi_1 (operand0, operand1, operand2)
02187      rtx operand0;
02188      rtx operand1;
02189      rtx operand2;
02190 {
02191   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02192     gen_rtx_SET (VOIDmode,
02193   gen_rtx_MEM (HImode,
02194   operand1),
02195   operand2),
02196     gen_rtx_SET (VOIDmode,
02197   operand0,
02198   gen_rtx_PLUS (SImode,
02199   operand1,
02200   GEN_INT (2LL))),
02201     gen_rtx_USE (VOIDmode,
02202   gen_rtx_REG (SImode,
02203   19))));
02204 }
02205 
02206 /* ../../gcc/gcc/config/i386/i386.md:15515 */
02207 rtx
02208 gen_strsethi_rex_1 (operand0, operand1, operand2)
02209      rtx operand0;
02210      rtx operand1;
02211      rtx operand2;
02212 {
02213   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02214     gen_rtx_SET (VOIDmode,
02215   gen_rtx_MEM (HImode,
02216   operand1),
02217   operand2),
02218     gen_rtx_SET (VOIDmode,
02219   operand0,
02220   gen_rtx_PLUS (DImode,
02221   operand1,
02222   GEN_INT (2LL))),
02223     gen_rtx_USE (VOIDmode,
02224   gen_rtx_REG (SImode,
02225   19))));
02226 }
02227 
02228 /* ../../gcc/gcc/config/i386/i386.md:15528 */
02229 rtx
02230 gen_strsetqi_1 (operand0, operand1, operand2)
02231      rtx operand0;
02232      rtx operand1;
02233      rtx operand2;
02234 {
02235   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02236     gen_rtx_SET (VOIDmode,
02237   gen_rtx_MEM (QImode,
02238   operand1),
02239   operand2),
02240     gen_rtx_SET (VOIDmode,
02241   operand0,
02242   gen_rtx_PLUS (SImode,
02243   operand1,
02244   const1_rtx)),
02245     gen_rtx_USE (VOIDmode,
02246   gen_rtx_REG (SImode,
02247   19))));
02248 }
02249 
02250 /* ../../gcc/gcc/config/i386/i386.md:15541 */
02251 rtx
02252 gen_strsetqi_rex_1 (operand0, operand1, operand2)
02253      rtx operand0;
02254      rtx operand1;
02255      rtx operand2;
02256 {
02257   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02258     gen_rtx_SET (VOIDmode,
02259   gen_rtx_MEM (QImode,
02260   operand1),
02261   operand2),
02262     gen_rtx_SET (VOIDmode,
02263   operand0,
02264   gen_rtx_PLUS (DImode,
02265   operand1,
02266   const1_rtx)),
02267     gen_rtx_USE (VOIDmode,
02268   gen_rtx_REG (SImode,
02269   19))));
02270 }
02271 
02272 /* ../../gcc/gcc/config/i386/i386.md:15554 */
02273 rtx
02274 gen_rep_stosdi_rex64 (operand0, operand1, operand2, operand3, operand4)
02275      rtx operand0;
02276      rtx operand1;
02277      rtx operand2;
02278      rtx operand3;
02279      rtx operand4;
02280 {
02281   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
02282     gen_rtx_SET (VOIDmode,
02283   operand1,
02284   const0_rtx),
02285     gen_rtx_SET (VOIDmode,
02286   operand0,
02287   gen_rtx_PLUS (DImode,
02288   gen_rtx_ASHIFT (DImode,
02289   operand4,
02290   GEN_INT (3LL)),
02291   operand3)),
02292     gen_rtx_SET (VOIDmode,
02293   gen_rtx_MEM (BLKmode,
02294   operand3),
02295   const0_rtx),
02296     gen_rtx_USE (VOIDmode,
02297   operand2),
02298     gen_rtx_USE (VOIDmode,
02299   operand4),
02300     gen_rtx_USE (VOIDmode,
02301   gen_rtx_REG (SImode,
02302   19))));
02303 }
02304 
02305 /* ../../gcc/gcc/config/i386/i386.md:15572 */
02306 rtx
02307 gen_rep_stossi (operand0, operand1, operand2, operand3, operand4)
02308      rtx operand0;
02309      rtx operand1;
02310      rtx operand2;
02311      rtx operand3;
02312      rtx operand4;
02313 {
02314   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
02315     gen_rtx_SET (VOIDmode,
02316   operand1,
02317   const0_rtx),
02318     gen_rtx_SET (VOIDmode,
02319   operand0,
02320   gen_rtx_PLUS (SImode,
02321   gen_rtx_ASHIFT (SImode,
02322   operand4,
02323   GEN_INT (2LL)),
02324   operand3)),
02325     gen_rtx_SET (VOIDmode,
02326   gen_rtx_MEM (BLKmode,
02327   operand3),
02328   const0_rtx),
02329     gen_rtx_USE (VOIDmode,
02330   operand2),
02331     gen_rtx_USE (VOIDmode,
02332   operand4),
02333     gen_rtx_USE (VOIDmode,
02334   gen_rtx_REG (SImode,
02335   19))));
02336 }
02337 
02338 /* ../../gcc/gcc/config/i386/i386.md:15590 */
02339 rtx
02340 gen_rep_stossi_rex64 (operand0, operand1, operand2, operand3, operand4)
02341      rtx operand0;
02342      rtx operand1;
02343      rtx operand2;
02344      rtx operand3;
02345      rtx operand4;
02346 {
02347   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
02348     gen_rtx_SET (VOIDmode,
02349   operand1,
02350   const0_rtx),
02351     gen_rtx_SET (VOIDmode,
02352   operand0,
02353   gen_rtx_PLUS (DImode,
02354   gen_rtx_ASHIFT (DImode,
02355   operand4,
02356   GEN_INT (2LL)),
02357   operand3)),
02358     gen_rtx_SET (VOIDmode,
02359   gen_rtx_MEM (BLKmode,
02360   operand3),
02361   const0_rtx),
02362     gen_rtx_USE (VOIDmode,
02363   operand2),
02364     gen_rtx_USE (VOIDmode,
02365   operand4),
02366     gen_rtx_USE (VOIDmode,
02367   gen_rtx_REG (SImode,
02368   19))));
02369 }
02370 
02371 /* ../../gcc/gcc/config/i386/i386.md:15608 */
02372 rtx
02373 gen_rep_stosqi (operand0, operand1, operand2, operand3, operand4)
02374      rtx operand0;
02375      rtx operand1;
02376      rtx operand2;
02377      rtx operand3;
02378      rtx operand4;
02379 {
02380   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
02381     gen_rtx_SET (VOIDmode,
02382   operand1,
02383   const0_rtx),
02384     gen_rtx_SET (VOIDmode,
02385   operand0,
02386   gen_rtx_PLUS (SImode,
02387   operand3,
02388   operand4)),
02389     gen_rtx_SET (VOIDmode,
02390   gen_rtx_MEM (BLKmode,
02391   operand3),
02392   const0_rtx),
02393     gen_rtx_USE (VOIDmode,
02394   operand2),
02395     gen_rtx_USE (VOIDmode,
02396   operand4),
02397     gen_rtx_USE (VOIDmode,
02398   gen_rtx_REG (SImode,
02399   19))));
02400 }
02401 
02402 /* ../../gcc/gcc/config/i386/i386.md:15625 */
02403 rtx
02404 gen_rep_stosqi_rex64 (operand0, operand1, operand2, operand3, operand4)
02405      rtx operand0;
02406      rtx operand1;
02407      rtx operand2;
02408      rtx operand3;
02409      rtx operand4;
02410 {
02411   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (6,
02412     gen_rtx_SET (VOIDmode,
02413   operand1,
02414   const0_rtx),
02415     gen_rtx_SET (VOIDmode,
02416   operand0,
02417   gen_rtx_PLUS (DImode,
02418   operand3,
02419   operand4)),
02420     gen_rtx_SET (VOIDmode,
02421   gen_rtx_MEM (BLKmode,
02422   operand3),
02423   const0_rtx),
02424     gen_rtx_USE (VOIDmode,
02425   operand2),
02426     gen_rtx_USE (VOIDmode,
02427   operand4),
02428     gen_rtx_USE (VOIDmode,
02429   gen_rtx_REG (DImode,
02430   19))));
02431 }
02432 
02433 /* ../../gcc/gcc/config/i386/i386.md:15726 */
02434 rtx
02435 gen_cmpstrqi_nz_1 (operand0, operand1, operand2, operand3, operand4, operand5, operand6)
02436      rtx operand0;
02437      rtx operand1;
02438      rtx operand2;
02439      rtx operand3;
02440      rtx operand4;
02441      rtx operand5;
02442      rtx operand6;
02443 {
02444   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (7,
02445     gen_rtx_SET (VOIDmode,
02446   gen_rtx_REG (CCmode,
02447   17),
02448   gen_rtx_COMPARE (CCmode,
02449   gen_rtx_MEM (BLKmode,
02450   operand4),
02451   gen_rtx_MEM (BLKmode,
02452   operand5))),
02453     gen_rtx_USE (VOIDmode,
02454   operand6),
02455     gen_rtx_USE (VOIDmode,
02456   operand3),
02457     gen_rtx_USE (VOIDmode,
02458   gen_rtx_REG (SImode,
02459   19)),
02460     gen_rtx_CLOBBER (VOIDmode,
02461   operand0),
02462     gen_rtx_CLOBBER (VOIDmode,
02463   operand1),
02464     gen_rtx_CLOBBER (VOIDmode,
02465   operand2)));
02466 }
02467 
02468 /* ../../gcc/gcc/config/i386/i386.md:15742 */
02469 rtx
02470 gen_cmpstrqi_nz_rex_1 (operand0, operand1, operand2, operand3, operand4, operand5, operand6)
02471      rtx operand0;
02472      rtx operand1;
02473      rtx operand2;
02474      rtx operand3;
02475      rtx operand4;
02476      rtx operand5;
02477      rtx operand6;
02478 {
02479   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (7,
02480     gen_rtx_SET (VOIDmode,
02481   gen_rtx_REG (CCmode,
02482   17),
02483   gen_rtx_COMPARE (CCmode,
02484   gen_rtx_MEM (BLKmode,
02485   operand4),
02486   gen_rtx_MEM (BLKmode,
02487   operand5))),
02488     gen_rtx_USE (VOIDmode,
02489   operand6),
02490     gen_rtx_USE (VOIDmode,
02491   operand3),
02492     gen_rtx_USE (VOIDmode,
02493   gen_rtx_REG (SImode,
02494   19)),
02495     gen_rtx_CLOBBER (VOIDmode,
02496   operand0),
02497     gen_rtx_CLOBBER (VOIDmode,
02498   operand1),
02499     gen_rtx_CLOBBER (VOIDmode,
02500   operand2)));
02501 }
02502 
02503 /* ../../gcc/gcc/config/i386/i386.md:15760 */
02504 rtx
02505 gen_cmpstrqi_1 (operand0, operand1, operand2, operand3, operand4, operand5, operand6)
02506      rtx operand0;
02507      rtx operand1;
02508      rtx operand2;
02509      rtx operand3;
02510      rtx operand4;
02511      rtx operand5;
02512      rtx operand6;
02513 {
02514   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (7,
02515     gen_rtx_SET (VOIDmode,
02516   gen_rtx_REG (CCmode,
02517   17),
02518   gen_rtx_IF_THEN_ELSE (CCmode,
02519   gen_rtx_NE (VOIDmode,
02520   operand6,
02521   const0_rtx),
02522   gen_rtx_COMPARE (CCmode,
02523   gen_rtx_MEM (BLKmode,
02524   operand4),
02525   gen_rtx_MEM (BLKmode,
02526   operand5)),
02527   const0_rtx)),
02528     gen_rtx_USE (VOIDmode,
02529   operand3),
02530     gen_rtx_USE (VOIDmode,
02531   gen_rtx_REG (CCmode,
02532   17)),
02533     gen_rtx_USE (VOIDmode,
02534   gen_rtx_REG (SImode,
02535   19)),
02536     gen_rtx_CLOBBER (VOIDmode,
02537   operand0),
02538     gen_rtx_CLOBBER (VOIDmode,
02539   operand1),
02540     gen_rtx_CLOBBER (VOIDmode,
02541   operand2)));
02542 }
02543 
02544 /* ../../gcc/gcc/config/i386/i386.md:15779 */
02545 rtx
02546 gen_cmpstrqi_rex_1 (operand0, operand1, operand2, operand3, operand4, operand5, operand6)
02547      rtx operand0;
02548      rtx operand1;
02549      rtx operand2;
02550      rtx operand3;
02551      rtx operand4;
02552      rtx operand5;
02553      rtx operand6;
02554 {
02555   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (7,
02556     gen_rtx_SET (VOIDmode,
02557   gen_rtx_REG (CCmode,
02558   17),
02559   gen_rtx_IF_THEN_ELSE (CCmode,
02560   gen_rtx_NE (VOIDmode,
02561   operand6,
02562   const0_rtx),
02563   gen_rtx_COMPARE (CCmode,
02564   gen_rtx_MEM (BLKmode,
02565   operand4),
02566   gen_rtx_MEM (BLKmode,
02567   operand5)),
02568   const0_rtx)),
02569     gen_rtx_USE (VOIDmode,
02570   operand3),
02571     gen_rtx_USE (VOIDmode,
02572   gen_rtx_REG (CCmode,
02573   17)),
02574     gen_rtx_USE (VOIDmode,
02575   gen_rtx_REG (SImode,
02576   19)),
02577     gen_rtx_CLOBBER (VOIDmode,
02578   operand0),
02579     gen_rtx_CLOBBER (VOIDmode,
02580   operand1),
02581     gen_rtx_CLOBBER (VOIDmode,
02582   operand2)));
02583 }
02584 
02585 /* ../../gcc/gcc/config/i386/i386.md:15824 */
02586 rtx
02587 gen_strlenqi_1 (operand0, operand1, operand2, operand3, operand4, operand5)
02588      rtx operand0;
02589      rtx operand1;
02590      rtx operand2;
02591      rtx operand3;
02592      rtx operand4;
02593      rtx operand5;
02594 {
02595   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
02596     gen_rtx_SET (VOIDmode,
02597   operand0,
02598   gen_rtx_UNSPEC (SImode,
02599   gen_rtvec (4,
02600     gen_rtx_MEM (BLKmode,
02601   operand5),
02602     operand2,
02603     operand3,
02604     operand4),
02605   20)),
02606     gen_rtx_USE (VOIDmode,
02607   gen_rtx_REG (SImode,
02608   19)),
02609     gen_rtx_CLOBBER (VOIDmode,
02610   operand1),
02611     gen_rtx_CLOBBER (VOIDmode,
02612   gen_rtx_REG (CCmode,
02613   17))));
02614 }
02615 
02616 /* ../../gcc/gcc/config/i386/i386.md:15839 */
02617 rtx
02618 gen_strlenqi_rex_1 (operand0, operand1, operand2, operand3, operand4, operand5)
02619      rtx operand0;
02620      rtx operand1;
02621      rtx operand2;
02622      rtx operand3;
02623      rtx operand4;
02624      rtx operand5;
02625 {
02626   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
02627     gen_rtx_SET (VOIDmode,
02628   operand0,
02629   gen_rtx_UNSPEC (DImode,
02630   gen_rtvec (4,
02631     gen_rtx_MEM (BLKmode,
02632   operand5),
02633     operand2,
02634     operand3,
02635     operand4),
02636   20)),
02637     gen_rtx_USE (VOIDmode,
02638   gen_rtx_REG (SImode,
02639   19)),
02640     gen_rtx_CLOBBER (VOIDmode,
02641   operand1),
02642     gen_rtx_CLOBBER (VOIDmode,
02643   gen_rtx_REG (CCmode,
02644   17))));
02645 }
02646 
02647 /* ../../gcc/gcc/config/i386/i386.md:15949 */
02648 rtx
02649 gen_x86_movdicc_0_m1_rex64 (operand0)
02650      rtx operand0;
02651 {
02652   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02653     gen_rtx_SET (VOIDmode,
02654   operand0,
02655   gen_rtx_IF_THEN_ELSE (DImode,
02656   gen_rtx_LTU (VOIDmode,
02657   gen_rtx_REG (CCmode,
02658   17),
02659   const0_rtx),
02660   constm1_rtx,
02661   const0_rtx)),
02662     gen_rtx_CLOBBER (VOIDmode,
02663   gen_rtx_REG (CCmode,
02664   17))));
02665 }
02666 
02667 /* ../../gcc/gcc/config/i386/i386.md:15992 */
02668 rtx
02669 gen_x86_movsicc_0_m1 (operand0)
02670      rtx operand0;
02671 {
02672   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02673     gen_rtx_SET (VOIDmode,
02674   operand0,
02675   gen_rtx_IF_THEN_ELSE (SImode,
02676   gen_rtx_LTU (VOIDmode,
02677   gen_rtx_REG (CCmode,
02678   17),
02679   const0_rtx),
02680   constm1_rtx,
02681   const0_rtx)),
02682     gen_rtx_CLOBBER (VOIDmode,
02683   gen_rtx_REG (CCmode,
02684   17))));
02685 }
02686 
02687 /* ../../gcc/gcc/config/i386/i386.md:16565 */
02688 rtx
02689 gen_pro_epilogue_adjust_stack_rex64 (operand0, operand1, operand2)
02690      rtx operand0;
02691      rtx operand1;
02692      rtx operand2;
02693 {
02694   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02695     gen_rtx_SET (VOIDmode,
02696   operand0,
02697   gen_rtx_PLUS (DImode,
02698   operand1,
02699   operand2)),
02700     gen_rtx_CLOBBER (VOIDmode,
02701   gen_rtx_REG (CCmode,
02702   17)),
02703     gen_rtx_CLOBBER (VOIDmode,
02704   gen_rtx_MEM (BLKmode,
02705   gen_rtx_SCRATCH (VOIDmode)))));
02706 }
02707 
02708 /* ../../gcc/gcc/config/i386/i386.md:16615 */
02709 rtx
02710 gen_sse_movsfcc (operand0, operand1, operand2, operand3, operand4, operand5)
02711      rtx operand0;
02712      rtx operand1;
02713      rtx operand2;
02714      rtx operand3;
02715      rtx operand4;
02716      rtx operand5;
02717 {
02718   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02719     gen_rtx_SET (VOIDmode,
02720   operand0,
02721   gen_rtx_IF_THEN_ELSE (SFmode,
02722   gen_rtx (GET_CODE (operand1), VOIDmode,
02723     operand4,
02724     operand5),
02725   operand2,
02726   operand3)),
02727     gen_rtx_CLOBBER (VOIDmode,
02728   gen_rtx_SCRATCH (SFmode)),
02729     gen_rtx_CLOBBER (VOIDmode,
02730   gen_rtx_REG (CCmode,
02731   17))));
02732 }
02733 
02734 /* ../../gcc/gcc/config/i386/i386.md:16630 */
02735 rtx
02736 gen_sse_movsfcc_eq (operand0, operand1, operand2, operand3, operand4)
02737      rtx operand0;
02738      rtx operand1;
02739      rtx operand2;
02740      rtx operand3;
02741      rtx operand4;
02742 {
02743   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02744     gen_rtx_SET (VOIDmode,
02745   operand0,
02746   gen_rtx_IF_THEN_ELSE (SFmode,
02747   gen_rtx_EQ (VOIDmode,
02748   operand3,
02749   operand4),
02750   operand1,
02751   operand2)),
02752     gen_rtx_CLOBBER (VOIDmode,
02753   gen_rtx_SCRATCH (SFmode)),
02754     gen_rtx_CLOBBER (VOIDmode,
02755   gen_rtx_REG (CCmode,
02756   17))));
02757 }
02758 
02759 /* ../../gcc/gcc/config/i386/i386.md:16642 */
02760 rtx
02761 gen_sse_movdfcc (operand0, operand1, operand2, operand3, operand4, operand5)
02762      rtx operand0;
02763      rtx operand1;
02764      rtx operand2;
02765      rtx operand3;
02766      rtx operand4;
02767      rtx operand5;
02768 {
02769   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02770     gen_rtx_SET (VOIDmode,
02771   operand0,
02772   gen_rtx_IF_THEN_ELSE (DFmode,
02773   gen_rtx (GET_CODE (operand1), VOIDmode,
02774     operand4,
02775     operand5),
02776   operand2,
02777   operand3)),
02778     gen_rtx_CLOBBER (VOIDmode,
02779   gen_rtx_SCRATCH (DFmode)),
02780     gen_rtx_CLOBBER (VOIDmode,
02781   gen_rtx_REG (CCmode,
02782   17))));
02783 }
02784 
02785 /* ../../gcc/gcc/config/i386/i386.md:16657 */
02786 rtx
02787 gen_sse_movdfcc_eq (operand0, operand1, operand2, operand3, operand4)
02788      rtx operand0;
02789      rtx operand1;
02790      rtx operand2;
02791      rtx operand3;
02792      rtx operand4;
02793 {
02794   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02795     gen_rtx_SET (VOIDmode,
02796   operand0,
02797   gen_rtx_IF_THEN_ELSE (DFmode,
02798   gen_rtx_EQ (VOIDmode,
02799   operand3,
02800   operand4),
02801   operand1,
02802   operand2)),
02803     gen_rtx_CLOBBER (VOIDmode,
02804   gen_rtx_SCRATCH (DFmode)),
02805     gen_rtx_CLOBBER (VOIDmode,
02806   gen_rtx_REG (CCmode,
02807   17))));
02808 }
02809 
02810 /* ../../gcc/gcc/config/i386/i386.md:16859 */
02811 rtx
02812 gen_allocate_stack_worker_1 (operand0)
02813      rtx operand0;
02814 {
02815   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
02816     gen_rtx_UNSPEC (SImode,
02817   gen_rtvec (1,
02818     operand0),
02819   10),
02820     gen_rtx_SET (VOIDmode,
02821   gen_rtx_REG (SImode,
02822   7),
02823   gen_rtx_MINUS (SImode,
02824   gen_rtx_REG (SImode,
02825   7),
02826   operand0)),
02827     gen_rtx_CLOBBER (VOIDmode,
02828   operand0),
02829     gen_rtx_CLOBBER (VOIDmode,
02830   gen_rtx_REG (CCmode,
02831   17))));
02832 }
02833 
02834 /* ../../gcc/gcc/config/i386/i386.md:16869 */
02835 rtx
02836 gen_allocate_stack_worker_rex64 (operand0)
02837      rtx operand0;
02838 {
02839   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
02840     gen_rtx_UNSPEC (DImode,
02841   gen_rtvec (1,
02842     operand0),
02843   10),
02844     gen_rtx_SET (VOIDmode,
02845   gen_rtx_REG (DImode,
02846   7),
02847   gen_rtx_MINUS (DImode,
02848   gen_rtx_REG (DImode,
02849   7),
02850   operand0)),
02851     gen_rtx_CLOBBER (VOIDmode,
02852   operand0),
02853     gen_rtx_CLOBBER (VOIDmode,
02854   gen_rtx_REG (CCmode,
02855   17))));
02856 }
02857 
02858 /* ../../gcc/gcc/config/i386/i386.md:17883 */
02859 rtx
02860 gen_trap ()
02861 {
02862   return gen_rtx_TRAP_IF (VOIDmode,
02863   const1_rtx,
02864   GEN_INT (5LL));
02865 }
02866 
02867 /* ../../gcc/gcc/config/i386/i386.md:17935 */
02868 rtx
02869 gen_movv4sf_internal (operand0, operand1)
02870      rtx operand0;
02871      rtx operand1;
02872 {
02873   return gen_rtx_SET (VOIDmode,
02874   operand0,
02875   operand1);
02876 }
02877 
02878 /* ../../gcc/gcc/config/i386/i386.md:17947 */
02879 rtx
02880 gen_movv4si_internal (operand0, operand1)
02881      rtx operand0;
02882      rtx operand1;
02883 {
02884   return gen_rtx_SET (VOIDmode,
02885   operand0,
02886   operand1);
02887 }
02888 
02889 /* ../../gcc/gcc/config/i386/i386.md:17959 */
02890 rtx
02891 gen_movv2di_internal (operand0, operand1)
02892      rtx operand0;
02893      rtx operand1;
02894 {
02895   return gen_rtx_SET (VOIDmode,
02896   operand0,
02897   operand1);
02898 }
02899 
02900 /* ../../gcc/gcc/config/i386/i386.md:17971 */
02901 rtx
02902 gen_movv8qi_internal (operand0, operand1)
02903      rtx operand0;
02904      rtx operand1;
02905 {
02906   return gen_rtx_SET (VOIDmode,
02907   operand0,
02908   operand1);
02909 }
02910 
02911 /* ../../gcc/gcc/config/i386/i386.md:17983 */
02912 rtx
02913 gen_movv4hi_internal (operand0, operand1)
02914      rtx operand0;
02915      rtx operand1;
02916 {
02917   return gen_rtx_SET (VOIDmode,
02918   operand0,
02919   operand1);
02920 }
02921 
02922 /* ../../gcc/gcc/config/i386/i386.md:17995 */
02923 rtx
02924 gen_movv2si_internal (operand0, operand1)
02925      rtx operand0;
02926      rtx operand1;
02927 {
02928   return gen_rtx_SET (VOIDmode,
02929   operand0,
02930   operand1);
02931 }
02932 
02933 /* ../../gcc/gcc/config/i386/i386.md:18007 */
02934 rtx
02935 gen_movv2sf_internal (operand0, operand1)
02936      rtx operand0;
02937      rtx operand1;
02938 {
02939   return gen_rtx_SET (VOIDmode,
02940   operand0,
02941   operand1);
02942 }
02943 
02944 /* ../../gcc/gcc/config/i386/i386.md:18031 */
02945 rtx
02946 gen_movv2df_internal (operand0, operand1)
02947      rtx operand0;
02948      rtx operand1;
02949 {
02950   return gen_rtx_SET (VOIDmode,
02951   operand0,
02952   operand1);
02953 }
02954 
02955 /* ../../gcc/gcc/config/i386/i386.md:18043 */
02956 rtx
02957 gen_movv8hi_internal (operand0, operand1)
02958      rtx operand0;
02959      rtx operand1;
02960 {
02961   return gen_rtx_SET (VOIDmode,
02962   operand0,
02963   operand1);
02964 }
02965 
02966 /* ../../gcc/gcc/config/i386/i386.md:18055 */
02967 rtx
02968 gen_movv16qi_internal (operand0, operand1)
02969      rtx operand0;
02970      rtx operand1;
02971 {
02972   return gen_rtx_SET (VOIDmode,
02973   operand0,
02974   operand1);
02975 }
02976 
02977 /* ../../gcc/gcc/config/i386/i386.md:18361 */
02978 rtx
02979 gen_movti_internal (operand0, operand1)
02980      rtx operand0;
02981      rtx operand1;
02982 {
02983   return gen_rtx_SET (VOIDmode,
02984   operand0,
02985   operand1);
02986 }
02987 
02988 /* ../../gcc/gcc/config/i386/i386.md:18449 */
02989 rtx
02990 gen_sse_movmskps (operand0, operand1)
02991      rtx operand0;
02992      rtx operand1;
02993 {
02994   return gen_rtx_SET (VOIDmode,
02995   operand0,
02996   gen_rtx_UNSPEC (SImode,
02997   gen_rtvec (1,
02998     operand1),
02999   33));
03000 }
03001 
03002 /* ../../gcc/gcc/config/i386/i386.md:18458 */
03003 rtx
03004 gen_mmx_pmovmskb (operand0, operand1)
03005      rtx operand0;
03006      rtx operand1;
03007 {
03008   return gen_rtx_SET (VOIDmode,
03009   operand0,
03010   gen_rtx_UNSPEC (SImode,
03011   gen_rtvec (1,
03012     operand1),
03013   33));
03014 }
03015 
03016 /* ../../gcc/gcc/config/i386/i386.md:18468 */
03017 rtx
03018 gen_mmx_maskmovq (operand0, operand1, operand2)
03019      rtx operand0;
03020      rtx operand1;
03021      rtx operand2;
03022 {
03023   return gen_rtx_SET (VOIDmode,
03024   gen_rtx_MEM (V8QImode,
03025   operand0),
03026   gen_rtx_UNSPEC (V8QImode,
03027   gen_rtvec (2,
03028     operand1,
03029     operand2),
03030   32));
03031 }
03032 
03033 /* ../../gcc/gcc/config/i386/i386.md:18479 */
03034 rtx
03035 gen_mmx_maskmovq_rex (operand0, operand1, operand2)
03036      rtx operand0;
03037      rtx operand1;
03038      rtx operand2;
03039 {
03040   return gen_rtx_SET (VOIDmode,
03041   gen_rtx_MEM (V8QImode,
03042   operand0),
03043   gen_rtx_UNSPEC (V8QImode,
03044   gen_rtvec (2,
03045     operand1,
03046     operand2),
03047   32));
03048 }
03049 
03050 /* ../../gcc/gcc/config/i386/i386.md:18490 */
03051 rtx
03052 gen_sse_movntv4sf (operand0, operand1)
03053      rtx operand0;
03054      rtx operand1;
03055 {
03056   return gen_rtx_SET (VOIDmode,
03057   operand0,
03058   gen_rtx_UNSPEC (V4SFmode,
03059   gen_rtvec (1,
03060     operand1),
03061   34));
03062 }
03063 
03064 /* ../../gcc/gcc/config/i386/i386.md:18499 */
03065 rtx
03066 gen_sse_movntdi (operand0, operand1)
03067      rtx operand0;
03068      rtx operand1;
03069 {
03070   return gen_rtx_SET (VOIDmode,
03071   operand0,
03072   gen_rtx_UNSPEC (DImode,
03073   gen_rtvec (1,
03074     operand1),
03075   34));
03076 }
03077 
03078 /* ../../gcc/gcc/config/i386/i386.md:18508 */
03079 rtx
03080 gen_sse_movhlps (operand0, operand1, operand2)
03081      rtx operand0;
03082      rtx operand1;
03083      rtx operand2;
03084 {
03085   return gen_rtx_SET (VOIDmode,
03086   operand0,
03087   gen_rtx_VEC_MERGE (V4SFmode,
03088   operand1,
03089   gen_rtx_VEC_SELECT (V4SFmode,
03090   operand2,
03091   gen_rtx_PARALLEL (VOIDmode,
03092   gen_rtvec (4,
03093     GEN_INT (2LL),
03094     GEN_INT (3LL),
03095     const0_rtx,
03096     const1_rtx))),
03097   GEN_INT (3LL)));
03098 }
03099 
03100 /* ../../gcc/gcc/config/i386/i386.md:18523 */
03101 rtx
03102 gen_sse_movlhps (operand0, operand1, operand2)
03103      rtx operand0;
03104      rtx operand1;
03105      rtx operand2;
03106 {
03107   return gen_rtx_SET (VOIDmode,
03108   operand0,
03109   gen_rtx_VEC_MERGE (V4SFmode,
03110   operand1,
03111   gen_rtx_VEC_SELECT (V4SFmode,
03112   operand2,
03113   gen_rtx_PARALLEL (VOIDmode,
03114   gen_rtvec (4,
03115     GEN_INT (2LL),
03116     GEN_INT (3LL),
03117     const0_rtx,
03118     const1_rtx))),
03119   GEN_INT (12LL)));
03120 }
03121 
03122 /* ../../gcc/gcc/config/i386/i386.md:18538 */
03123 rtx
03124 gen_sse_movhps (operand0, operand1, operand2)
03125      rtx operand0;
03126      rtx operand1;
03127      rtx operand2;
03128 {
03129   return gen_rtx_SET (VOIDmode,
03130   operand0,
03131   gen_rtx_VEC_MERGE (V4SFmode,
03132   operand1,
03133   operand2,
03134   GEN_INT (12LL)));
03135 }
03136 
03137 /* ../../gcc/gcc/config/i386/i386.md:18550 */
03138 rtx
03139 gen_sse_movlps (operand0, operand1, operand2)
03140      rtx operand0;
03141      rtx operand1;
03142      rtx operand2;
03143 {
03144   return gen_rtx_SET (VOIDmode,
03145   operand0,
03146   gen_rtx_VEC_MERGE (V4SFmode,
03147   operand1,
03148   operand2,
03149   GEN_INT (3LL)));
03150 }
03151 
03152 /* ../../gcc/gcc/config/i386/i386.md:18572 */
03153 rtx
03154 gen_sse_loadss_1 (operand0, operand1, operand2)
03155      rtx operand0;
03156      rtx operand1;
03157      rtx operand2;
03158 {
03159   return gen_rtx_SET (VOIDmode,
03160   operand0,
03161   gen_rtx_VEC_MERGE (V4SFmode,
03162   gen_rtx_VEC_DUPLICATE (V4SFmode,
03163   operand1),
03164   operand2,
03165   const1_rtx));
03166 }
03167 
03168 /* ../../gcc/gcc/config/i386/i386.md:18583 */
03169 rtx
03170 gen_sse_movss (operand0, operand1, operand2)
03171      rtx operand0;
03172      rtx operand1;
03173      rtx operand2;
03174 {
03175   return gen_rtx_SET (VOIDmode,
03176   operand0,
03177   gen_rtx_VEC_MERGE (V4SFmode,
03178   operand1,
03179   operand2,
03180   const1_rtx));
03181 }
03182 
03183 /* ../../gcc/gcc/config/i386/i386.md:18594 */
03184 rtx
03185 gen_sse_storess (operand0, operand1)
03186      rtx operand0;
03187      rtx operand1;
03188 {
03189   return gen_rtx_SET (VOIDmode,
03190   operand0,
03191   gen_rtx_VEC_SELECT (SFmode,
03192   operand1,
03193   gen_rtx_PARALLEL (VOIDmode,
03194   gen_rtvec (1,
03195     const0_rtx))));
03196 }
03197 
03198 /* ../../gcc/gcc/config/i386/i386.md:18604 */
03199 rtx
03200 gen_sse_shufps (operand0, operand1, operand2, operand3)
03201      rtx operand0;
03202      rtx operand1;
03203      rtx operand2;
03204      rtx operand3;
03205 {
03206   return gen_rtx_SET (VOIDmode,
03207   operand0,
03208   gen_rtx_UNSPEC (V4SFmode,
03209   gen_rtvec (3,
03210     operand1,
03211     operand2,
03212     operand3),
03213   41));
03214 }
03215 
03216 /* ../../gcc/gcc/config/i386/i386.md:18619 */
03217 rtx
03218 gen_addv4sf3 (operand0, operand1, operand2)
03219      rtx operand0;
03220      rtx operand1;
03221      rtx operand2;
03222 {
03223   return gen_rtx_SET (VOIDmode,
03224   operand0,
03225   gen_rtx_PLUS (V4SFmode,
03226   operand1,
03227   operand2));
03228 }
03229 
03230 /* ../../gcc/gcc/config/i386/i386.md:18628 */
03231 rtx
03232 gen_vmaddv4sf3 (operand0, operand1, operand2)
03233      rtx operand0;
03234      rtx operand1;
03235      rtx operand2;
03236 {
03237   return gen_rtx_SET (VOIDmode,
03238   operand0,
03239   gen_rtx_VEC_MERGE (V4SFmode,
03240   gen_rtx_PLUS (V4SFmode,
03241   operand1,
03242   operand2),
03243   operand1,
03244   const1_rtx));
03245 }
03246 
03247 /* ../../gcc/gcc/config/i386/i386.md:18640 */
03248 rtx
03249 gen_subv4sf3 (operand0, operand1, operand2)
03250      rtx operand0;
03251      rtx operand1;
03252      rtx operand2;
03253 {
03254   return gen_rtx_SET (VOIDmode,
03255   operand0,
03256   gen_rtx_MINUS (V4SFmode,
03257   operand1,
03258   operand2));
03259 }
03260 
03261 /* ../../gcc/gcc/config/i386/i386.md:18649 */
03262 rtx
03263 gen_vmsubv4sf3 (operand0, operand1, operand2)
03264      rtx operand0;
03265      rtx operand1;
03266      rtx operand2;
03267 {
03268   return gen_rtx_SET (VOIDmode,
03269   operand0,
03270   gen_rtx_VEC_MERGE (V4SFmode,
03271   gen_rtx_MINUS (V4SFmode,
03272   operand1,
03273   operand2),
03274   operand1,
03275   const1_rtx));
03276 }
03277 
03278 /* ../../gcc/gcc/config/i386/i386.md:18661 */
03279 rtx
03280 gen_mulv4sf3 (operand0, operand1, operand2)
03281      rtx operand0;
03282      rtx operand1;
03283      rtx operand2;
03284 {
03285   return gen_rtx_SET (VOIDmode,
03286   operand0,
03287   gen_rtx_MULT (V4SFmode,
03288   operand1,
03289   operand2));
03290 }
03291 
03292 /* ../../gcc/gcc/config/i386/i386.md:18670 */
03293 rtx
03294 gen_vmmulv4sf3 (operand0, operand1, operand2)
03295      rtx operand0;
03296      rtx operand1;
03297      rtx operand2;
03298 {
03299   return gen_rtx_SET (VOIDmode,
03300   operand0,
03301   gen_rtx_VEC_MERGE (V4SFmode,
03302   gen_rtx_MULT (V4SFmode,
03303   operand1,
03304   operand2),
03305   operand1,
03306   const1_rtx));
03307 }
03308 
03309 /* ../../gcc/gcc/config/i386/i386.md:18682 */
03310 rtx
03311 gen_divv4sf3 (operand0, operand1, operand2)
03312      rtx operand0;
03313      rtx operand1;
03314      rtx operand2;
03315 {
03316   return gen_rtx_SET (VOIDmode,
03317   operand0,
03318   gen_rtx_DIV (V4SFmode,
03319   operand1,
03320   operand2));
03321 }
03322 
03323 /* ../../gcc/gcc/config/i386/i386.md:18691 */
03324 rtx
03325 gen_vmdivv4sf3 (operand0, operand1, operand2)
03326      rtx operand0;
03327      rtx operand1;
03328      rtx operand2;
03329 {
03330   return gen_rtx_SET (VOIDmode,
03331   operand0,
03332   gen_rtx_VEC_MERGE (V4SFmode,
03333   gen_rtx_DIV (V4SFmode,
03334   operand1,
03335   operand2),
03336   operand1,
03337   const1_rtx));
03338 }
03339 
03340 /* ../../gcc/gcc/config/i386/i386.md:18706 */
03341 rtx
03342 gen_rcpv4sf2 (operand0, operand1)
03343      rtx operand0;
03344      rtx operand1;
03345 {
03346   return gen_rtx_SET (VOIDmode,
03347   operand0,
03348   gen_rtx_UNSPEC (V4SFmode,
03349   gen_rtvec (1,
03350     operand1),
03351   42));
03352 }
03353 
03354 /* ../../gcc/gcc/config/i386/i386.md:18715 */
03355 rtx
03356 gen_vmrcpv4sf2 (operand0, operand1, operand2)
03357      rtx operand0;
03358      rtx operand1;
03359      rtx operand2;
03360 {
03361   return gen_rtx_SET (VOIDmode,
03362   operand0,
03363   gen_rtx_VEC_MERGE (V4SFmode,
03364   gen_rtx_UNSPEC (V4SFmode,
03365   gen_rtvec (1,
03366     operand1),
03367   42),
03368   operand2,
03369   const1_rtx));
03370 }
03371 
03372 /* ../../gcc/gcc/config/i386/i386.md:18727 */
03373 rtx
03374 gen_rsqrtv4sf2 (operand0, operand1)
03375      rtx operand0;
03376      rtx operand1;
03377 {
03378   return gen_rtx_SET (VOIDmode,
03379   operand0,
03380   gen_rtx_UNSPEC (V4SFmode,
03381   gen_rtvec (1,
03382     operand1),
03383   43));
03384 }
03385 
03386 /* ../../gcc/gcc/config/i386/i386.md:18736 */
03387 rtx
03388 gen_vmrsqrtv4sf2 (operand0, operand1, operand2)
03389      rtx operand0;
03390      rtx operand1;
03391      rtx operand2;
03392 {
03393   return gen_rtx_SET (VOIDmode,
03394   operand0,
03395   gen_rtx_VEC_MERGE (V4SFmode,
03396   gen_rtx_UNSPEC (V4SFmode,
03397   gen_rtvec (1,
03398     operand1),
03399   43),
03400   operand2,
03401   const1_rtx));
03402 }
03403 
03404 /* ../../gcc/gcc/config/i386/i386.md:18748 */
03405 rtx
03406 gen_sqrtv4sf2 (operand0, operand1)
03407      rtx operand0;
03408      rtx operand1;
03409 {
03410   return gen_rtx_SET (VOIDmode,
03411   operand0,
03412   gen_rtx_SQRT (V4SFmode,
03413   operand1));
03414 }
03415 
03416 /* ../../gcc/gcc/config/i386/i386.md:18756 */
03417 rtx
03418 gen_vmsqrtv4sf2 (operand0, operand1, operand2)
03419      rtx operand0;
03420      rtx operand1;
03421      rtx operand2;
03422 {
03423   return gen_rtx_SET (VOIDmode,
03424   operand0,
03425   gen_rtx_VEC_MERGE (V4SFmode,
03426   gen_rtx_SQRT (V4SFmode,
03427   operand1),
03428   operand2,
03429   const1_rtx));
03430 }
03431 
03432 /* ../../gcc/gcc/config/i386/i386.md:19026 */
03433 rtx
03434 gen_sse2_andv2di3 (operand0, operand1, operand2)
03435      rtx operand0;
03436      rtx operand1;
03437      rtx operand2;
03438 {
03439   return gen_rtx_SET (VOIDmode,
03440   operand0,
03441   gen_rtx_AND (V2DImode,
03442   operand1,
03443   operand2));
03444 }
03445 
03446 /* ../../gcc/gcc/config/i386/i386.md:19045 */
03447 rtx
03448 gen_sse2_nandv2di3 (operand0, operand1, operand2)
03449      rtx operand0;
03450      rtx operand1;
03451      rtx operand2;
03452 {
03453   return gen_rtx_SET (VOIDmode,
03454   operand0,
03455   gen_rtx_AND (V2DImode,
03456   gen_rtx_NOT (V2DImode,
03457   operand1),
03458   operand2));
03459 }
03460 
03461 /* ../../gcc/gcc/config/i386/i386.md:19065 */
03462 rtx
03463 gen_sse2_iorv2di3 (operand0, operand1, operand2)
03464      rtx operand0;
03465      rtx operand1;
03466      rtx operand2;
03467 {
03468   return gen_rtx_SET (VOIDmode,
03469   operand0,
03470   gen_rtx_IOR (V2DImode,
03471   operand1,
03472   operand2));
03473 }
03474 
03475 /* ../../gcc/gcc/config/i386/i386.md:19085 */
03476 rtx
03477 gen_sse2_xorv2di3 (operand0, operand1, operand2)
03478      rtx operand0;
03479      rtx operand1;
03480      rtx operand2;
03481 {
03482   return gen_rtx_SET (VOIDmode,
03483   operand0,
03484   gen_rtx_XOR (V2DImode,
03485   operand1,
03486   operand2));
03487 }
03488 
03489 /* ../../gcc/gcc/config/i386/i386.md:19097 */
03490 rtx
03491 gen_sse_clrv4sf (operand0)
03492      rtx operand0;
03493 {
03494   return gen_rtx_SET (VOIDmode,
03495   operand0,
03496   gen_rtx_UNSPEC (V4SFmode,
03497   gen_rtvec (1,
03498     const0_rtx),
03499   45));
03500 }
03501 
03502 /* ../../gcc/gcc/config/i386/i386.md:19108 */
03503 rtx
03504 gen_sse_clrv2df (operand0)
03505      rtx operand0;
03506 {
03507   return gen_rtx_SET (VOIDmode,
03508   operand0,
03509   gen_rtx_UNSPEC (V2DFmode,
03510   gen_rtvec (1,
03511     const0_rtx),
03512   45));
03513 }
03514 
03515 /* ../../gcc/gcc/config/i386/i386.md:19119 */
03516 rtx
03517 gen_maskcmpv4sf3 (operand0, operand1, operand2, operand3)
03518      rtx operand0;
03519      rtx operand1;
03520      rtx operand2;
03521      rtx operand3;
03522 {
03523   return gen_rtx_SET (VOIDmode,
03524   operand0,
03525   gen_rtx (GET_CODE (operand3), V4SImode,
03526     operand1,
03527     operand2));
03528 }
03529 
03530 /* ../../gcc/gcc/config/i386/i386.md:19129 */
03531 rtx
03532 gen_maskncmpv4sf3 (operand0, operand1, operand2, operand3)
03533      rtx operand0;
03534      rtx operand1;
03535      rtx operand2;
03536      rtx operand3;
03537 {
03538   return gen_rtx_SET (VOIDmode,
03539   operand0,
03540   gen_rtx_NOT (V4SImode,
03541   gen_rtx (GET_CODE (operand3), V4SImode,
03542     operand1,
03543     operand2)));
03544 }
03545 
03546 /* ../../gcc/gcc/config/i386/i386.md:19145 */
03547 rtx
03548 gen_vmmaskcmpv4sf3 (operand0, operand1, operand2, operand3)
03549      rtx operand0;
03550      rtx operand1;
03551      rtx operand2;
03552      rtx operand3;
03553 {
03554   return gen_rtx_SET (VOIDmode,
03555   operand0,
03556   gen_rtx_VEC_MERGE (V4SImode,
03557   gen_rtx (GET_CODE (operand3), V4SImode,
03558     operand1,
03559     operand2),
03560   gen_rtx_SUBREG (V4SImode,
03561   operand1,
03562   0),
03563   const1_rtx));
03564 }
03565 
03566 /* ../../gcc/gcc/config/i386/i386.md:19158 */
03567 rtx
03568 gen_vmmaskncmpv4sf3 (operand0, operand1, operand2, operand3)
03569      rtx operand0;
03570      rtx operand1;
03571      rtx operand2;
03572      rtx operand3;
03573 {
03574   return gen_rtx_SET (VOIDmode,
03575   operand0,
03576   gen_rtx_VEC_MERGE (V4SImode,
03577   gen_rtx_NOT (V4SImode,
03578   gen_rtx (GET_CODE (operand3), V4SImode,
03579     operand1,
03580     operand2)),
03581   gen_rtx_SUBREG (V4SImode,
03582   operand1,
03583   0),
03584   const1_rtx));
03585 }
03586 
03587 /* ../../gcc/gcc/config/i386/i386.md:19177 */
03588 rtx
03589 gen_sse_comi (operand0, operand1)
03590      rtx operand0;
03591      rtx operand1;
03592 {
03593   return gen_rtx_SET (VOIDmode,
03594   gen_rtx_REG (CCFPmode,
03595   17),
03596   gen_rtx_COMPARE (CCFPmode,
03597   gen_rtx_VEC_SELECT (SFmode,
03598   operand0,
03599   gen_rtx_PARALLEL (VOIDmode,
03600   gen_rtvec (1,
03601     const0_rtx))),
03602   gen_rtx_VEC_SELECT (SFmode,
03603   operand1,
03604   gen_rtx_PARALLEL (VOIDmode,
03605   gen_rtvec (1,
03606     const0_rtx)))));
03607 }
03608 
03609 /* ../../gcc/gcc/config/i386/i386.md:19190 */
03610 rtx
03611 gen_sse_ucomi (operand0, operand1)
03612      rtx operand0;
03613      rtx operand1;
03614 {
03615   return gen_rtx_SET (VOIDmode,
03616   gen_rtx_REG (CCFPUmode,
03617   17),
03618   gen_rtx_COMPARE (CCFPUmode,
03619   gen_rtx_VEC_SELECT (SFmode,
03620   operand0,
03621   gen_rtx_PARALLEL (VOIDmode,
03622   gen_rtvec (1,
03623     const0_rtx))),
03624   gen_rtx_VEC_SELECT (SFmode,
03625   operand1,
03626   gen_rtx_PARALLEL (VOIDmode,
03627   gen_rtvec (1,
03628     const0_rtx)))));
03629 }
03630 
03631 /* ../../gcc/gcc/config/i386/i386.md:19206 */
03632 rtx
03633 gen_sse_unpckhps (operand0, operand1, operand2)
03634      rtx operand0;
03635      rtx operand1;
03636      rtx operand2;
03637 {
03638   return gen_rtx_SET (VOIDmode,
03639   operand0,
03640   gen_rtx_VEC_MERGE (V4SFmode,
03641   gen_rtx_VEC_SELECT (V4SFmode,
03642   operand1,
03643   gen_rtx_PARALLEL (VOIDmode,
03644   gen_rtvec (4,
03645     GEN_INT (2LL),
03646     const0_rtx,
03647     GEN_INT (3LL),
03648     const1_rtx))),
03649   gen_rtx_VEC_SELECT (V4SFmode,
03650   operand2,
03651   gen_rtx_PARALLEL (VOIDmode,
03652   gen_rtvec (4,
03653     const0_rtx,
03654     GEN_INT (2LL),
03655     const1_rtx,
03656     GEN_INT (3LL)))),
03657   GEN_INT (5LL)));
03658 }
03659 
03660 /* ../../gcc/gcc/config/i386/i386.md:19225 */
03661 rtx
03662 gen_sse_unpcklps (operand0, operand1, operand2)
03663      rtx operand0;
03664      rtx operand1;
03665      rtx operand2;
03666 {
03667   return gen_rtx_SET (VOIDmode,
03668   operand0,
03669   gen_rtx_VEC_MERGE (V4SFmode,
03670   gen_rtx_VEC_SELECT (V4SFmode,
03671   operand1,
03672   gen_rtx_PARALLEL (VOIDmode,
03673   gen_rtvec (4,
03674     const0_rtx,
03675     GEN_INT (2LL),
03676     const1_rtx,
03677     GEN_INT (3LL)))),
03678   gen_rtx_VEC_SELECT (V4SFmode,
03679   operand2,
03680   gen_rtx_PARALLEL (VOIDmode,
03681   gen_rtvec (4,
03682     GEN_INT (2LL),
03683     const0_rtx,
03684     GEN_INT (3LL),
03685     const1_rtx))),
03686   GEN_INT (5LL)));
03687 }
03688 
03689 /* ../../gcc/gcc/config/i386/i386.md:19247 */
03690 rtx
03691 gen_smaxv4sf3 (operand0, operand1, operand2)
03692      rtx operand0;
03693      rtx operand1;
03694      rtx operand2;
03695 {
03696   return gen_rtx_SET (VOIDmode,
03697   operand0,
03698   gen_rtx_SMAX (V4SFmode,
03699   operand1,
03700   operand2));
03701 }
03702 
03703 /* ../../gcc/gcc/config/i386/i386.md:19256 */
03704 rtx
03705 gen_vmsmaxv4sf3 (operand0, operand1, operand2)
03706      rtx operand0;
03707      rtx operand1;
03708      rtx operand2;
03709 {
03710   return gen_rtx_SET (VOIDmode,
03711   operand0,
03712   gen_rtx_VEC_MERGE (V4SFmode,
03713   gen_rtx_SMAX (V4SFmode,
03714   operand1,
03715   operand2),
03716   operand1,
03717   const1_rtx));
03718 }
03719 
03720 /* ../../gcc/gcc/config/i386/i386.md:19268 */
03721 rtx
03722 gen_sminv4sf3 (operand0, operand1, operand2)
03723      rtx operand0;
03724      rtx operand1;
03725      rtx operand2;
03726 {
03727   return gen_rtx_SET (VOIDmode,
03728   operand0,
03729   gen_rtx_SMIN (V4SFmode,
03730   operand1,
03731   operand2));
03732 }
03733 
03734 /* ../../gcc/gcc/config/i386/i386.md:19277 */
03735 rtx
03736 gen_vmsminv4sf3 (operand0, operand1, operand2)
03737      rtx operand0;
03738      rtx operand1;
03739      rtx operand2;
03740 {
03741   return gen_rtx_SET (VOIDmode,
03742   operand0,
03743   gen_rtx_VEC_MERGE (V4SFmode,
03744   gen_rtx_SMIN (V4SFmode,
03745   operand1,
03746   operand2),
03747   operand1,
03748   const1_rtx));
03749 }
03750 
03751 /* ../../gcc/gcc/config/i386/i386.md:19291 */
03752 rtx
03753 gen_cvtpi2ps (operand0, operand1, operand2)
03754      rtx operand0;
03755      rtx operand1;
03756      rtx operand2;
03757 {
03758   return gen_rtx_SET (VOIDmode,
03759   operand0,
03760   gen_rtx_VEC_MERGE (V4SFmode,
03761   operand1,
03762   gen_rtx_VEC_DUPLICATE (V4SFmode,
03763   gen_rtx_FLOAT (V2SFmode,
03764   operand2)),
03765   GEN_INT (12LL)));
03766 }
03767 
03768 /* ../../gcc/gcc/config/i386/i386.md:19303 */
03769 rtx
03770 gen_cvtps2pi (operand0, operand1)
03771      rtx operand0;
03772      rtx operand1;
03773 {
03774   return gen_rtx_SET (VOIDmode,
03775   operand0,
03776   gen_rtx_VEC_SELECT (V2SImode,
03777   gen_rtx_FIX (V4SImode,
03778   operand1),
03779   gen_rtx_PARALLEL (VOIDmode,
03780   gen_rtvec (2,
03781     const0_rtx,
03782     const1_rtx))));
03783 }
03784 
03785 /* ../../gcc/gcc/config/i386/i386.md:19313 */
03786 rtx
03787 gen_cvttps2pi (operand0, operand1)
03788      rtx operand0;
03789      rtx operand1;
03790 {
03791   return gen_rtx_SET (VOIDmode,
03792   operand0,
03793   gen_rtx_VEC_SELECT (V2SImode,
03794   gen_rtx_UNSPEC (V4SImode,
03795   gen_rtvec (1,
03796     operand1),
03797   30),
03798   gen_rtx_PARALLEL (VOIDmode,
03799   gen_rtvec (2,
03800     const0_rtx,
03801     const1_rtx))));
03802 }
03803 
03804 /* ../../gcc/gcc/config/i386/i386.md:19324 */
03805 rtx
03806 gen_cvtsi2ss (operand0, operand1, operand2)
03807      rtx operand0;
03808      rtx operand1;
03809      rtx operand2;
03810 {
03811   return gen_rtx_SET (VOIDmode,
03812   operand0,
03813   gen_rtx_VEC_MERGE (V4SFmode,
03814   operand1,
03815   gen_rtx_VEC_DUPLICATE (V4SFmode,
03816   gen_rtx_FLOAT (SFmode,
03817   operand2)),
03818   GEN_INT (14LL)));
03819 }
03820 
03821 /* ../../gcc/gcc/config/i386/i386.md:19336 */
03822 rtx
03823 gen_cvtsi2ssq (operand0, operand1, operand2)
03824      rtx operand0;
03825      rtx operand1;
03826      rtx operand2;
03827 {
03828   return gen_rtx_SET (VOIDmode,
03829   operand0,
03830   gen_rtx_VEC_MERGE (V4SFmode,
03831   operand1,
03832   gen_rtx_VEC_DUPLICATE (V4SFmode,
03833   gen_rtx_FLOAT (SFmode,
03834   operand2)),
03835   GEN_INT (14LL)));
03836 }
03837 
03838 /* ../../gcc/gcc/config/i386/i386.md:19349 */
03839 rtx
03840 gen_cvtss2si (operand0, operand1)
03841      rtx operand0;
03842      rtx operand1;
03843 {
03844   return gen_rtx_SET (VOIDmode,
03845   operand0,
03846   gen_rtx_VEC_SELECT (SImode,
03847   gen_rtx_FIX (V4SImode,
03848   operand1),
03849   gen_rtx_PARALLEL (VOIDmode,
03850   gen_rtvec (1,
03851     const0_rtx))));
03852 }
03853 
03854 /* ../../gcc/gcc/config/i386/i386.md:19359 */
03855 rtx
03856 gen_cvtss2siq (operand0, operand1)
03857      rtx operand0;
03858      rtx operand1;
03859 {
03860   return gen_rtx_SET (VOIDmode,
03861   operand0,
03862   gen_rtx_VEC_SELECT (DImode,
03863   gen_rtx_FIX (V4DImode,
03864   operand1),
03865   gen_rtx_PARALLEL (VOIDmode,
03866   gen_rtvec (1,
03867     const0_rtx))));
03868 }
03869 
03870 /* ../../gcc/gcc/config/i386/i386.md:19370 */
03871 rtx
03872 gen_cvttss2si (operand0, operand1)
03873      rtx operand0;
03874      rtx operand1;
03875 {
03876   return gen_rtx_SET (VOIDmode,
03877   operand0,
03878   gen_rtx_VEC_SELECT (SImode,
03879   gen_rtx_UNSPEC (V4SImode,
03880   gen_rtvec (1,
03881     operand1),
03882   30),
03883   gen_rtx_PARALLEL (VOIDmode,
03884   gen_rtvec (1,
03885     const0_rtx))));
03886 }
03887 
03888 /* ../../gcc/gcc/config/i386/i386.md:19381 */
03889 rtx
03890 gen_cvttss2siq (operand0, operand1)
03891      rtx operand0;
03892      rtx operand1;
03893 {
03894   return gen_rtx_SET (VOIDmode,
03895   operand0,
03896   gen_rtx_VEC_SELECT (DImode,
03897   gen_rtx_UNSPEC (V4DImode,
03898   gen_rtvec (1,
03899     operand1),
03900   30),
03901   gen_rtx_PARALLEL (VOIDmode,
03902   gen_rtvec (1,
03903     const0_rtx))));
03904 }
03905 
03906 /* ../../gcc/gcc/config/i386/i386.md:19398 */
03907 rtx
03908 gen_addv8qi3 (operand0, operand1, operand2)
03909      rtx operand0;
03910      rtx operand1;
03911      rtx operand2;
03912 {
03913   return gen_rtx_SET (VOIDmode,
03914   operand0,
03915   gen_rtx_PLUS (V8QImode,
03916   operand1,
03917   operand2));
03918 }
03919 
03920 /* ../../gcc/gcc/config/i386/i386.md:19407 */
03921 rtx
03922 gen_addv4hi3 (operand0, operand1, operand2)
03923      rtx operand0;
03924      rtx operand1;
03925      rtx operand2;
03926 {
03927   return gen_rtx_SET (VOIDmode,
03928   operand0,
03929   gen_rtx_PLUS (V4HImode,
03930   operand1,
03931   operand2));
03932 }
03933 
03934 /* ../../gcc/gcc/config/i386/i386.md:19416 */
03935 rtx
03936 gen_addv2si3 (operand0, operand1, operand2)
03937      rtx operand0;
03938      rtx operand1;
03939      rtx operand2;
03940 {
03941   return gen_rtx_SET (VOIDmode,
03942   operand0,
03943   gen_rtx_PLUS (V2SImode,
03944   operand1,
03945   operand2));
03946 }
03947 
03948 /* ../../gcc/gcc/config/i386/i386.md:19425 */
03949 rtx
03950 gen_mmx_adddi3 (operand0, operand1, operand2)
03951      rtx operand0;
03952      rtx operand1;
03953      rtx operand2;
03954 {
03955   return gen_rtx_SET (VOIDmode,
03956   operand0,
03957   gen_rtx_UNSPEC (DImode,
03958   gen_rtvec (1,
03959     gen_rtx_PLUS (DImode,
03960   operand1,
03961   operand2)),
03962   45));
03963 }
03964 
03965 /* ../../gcc/gcc/config/i386/i386.md:19436 */
03966 rtx
03967 gen_ssaddv8qi3 (operand0, operand1, operand2)
03968      rtx operand0;
03969      rtx operand1;
03970      rtx operand2;
03971 {
03972   return gen_rtx_SET (VOIDmode,
03973   operand0,
03974   gen_rtx_SS_PLUS (V8QImode,
03975   operand1,
03976   operand2));
03977 }
03978 
03979 /* ../../gcc/gcc/config/i386/i386.md:19445 */
03980 rtx
03981 gen_ssaddv4hi3 (operand0, operand1, operand2)
03982      rtx operand0;
03983      rtx operand1;
03984      rtx operand2;
03985 {
03986   return gen_rtx_SET (VOIDmode,
03987   operand0,
03988   gen_rtx_SS_PLUS (V4HImode,
03989   operand1,
03990   operand2));
03991 }
03992 
03993 /* ../../gcc/gcc/config/i386/i386.md:19454 */
03994 rtx
03995 gen_usaddv8qi3 (operand0, operand1, operand2)
03996      rtx operand0;
03997      rtx operand1;
03998      rtx operand2;
03999 {
04000   return gen_rtx_SET (VOIDmode,
04001   operand0,
04002   gen_rtx_US_PLUS (V8QImode,
04003   operand1,
04004   operand2));
04005 }
04006 
04007 /* ../../gcc/gcc/config/i386/i386.md:19463 */
04008 rtx
04009 gen_usaddv4hi3 (operand0, operand1, operand2)
04010      rtx operand0;
04011      rtx operand1;
04012      rtx operand2;
04013 {
04014   return gen_rtx_SET (VOIDmode,
04015   operand0,
04016   gen_rtx_US_PLUS (V4HImode,
04017   operand1,
04018   operand2));
04019 }
04020 
04021 /* ../../gcc/gcc/config/i386/i386.md:19472 */
04022 rtx
04023 gen_subv8qi3 (operand0, operand1, operand2)
04024      rtx operand0;
04025      rtx operand1;
04026      rtx operand2;
04027 {
04028   return gen_rtx_SET (VOIDmode,
04029   operand0,
04030   gen_rtx_MINUS (V8QImode,
04031   operand1,
04032   operand2));
04033 }
04034 
04035 /* ../../gcc/gcc/config/i386/i386.md:19481 */
04036 rtx
04037 gen_subv4hi3 (operand0, operand1, operand2)
04038      rtx operand0;
04039      rtx operand1;
04040      rtx operand2;
04041 {
04042   return gen_rtx_SET (VOIDmode,
04043   operand0,
04044   gen_rtx_MINUS (V4HImode,
04045   operand1,
04046   operand2));
04047 }
04048 
04049 /* ../../gcc/gcc/config/i386/i386.md:19490 */
04050 rtx
04051 gen_subv2si3 (operand0, operand1, operand2)
04052      rtx operand0;
04053      rtx operand1;
04054      rtx operand2;
04055 {
04056   return gen_rtx_SET (VOIDmode,
04057   operand0,
04058   gen_rtx_MINUS (V2SImode,
04059   operand1,
04060   operand2));
04061 }
04062 
04063 /* ../../gcc/gcc/config/i386/i386.md:19499 */
04064 rtx
04065 gen_mmx_subdi3 (operand0, operand1, operand2)
04066      rtx operand0;
04067      rtx operand1;
04068      rtx operand2;
04069 {
04070   return gen_rtx_SET (VOIDmode,
04071   operand0,
04072   gen_rtx_UNSPEC (DImode,
04073   gen_rtvec (1,
04074     gen_rtx_MINUS (DImode,
04075   operand1,
04076   operand2)),
04077   45));
04078 }
04079 
04080 /* ../../gcc/gcc/config/i386/i386.md:19510 */
04081 rtx
04082 gen_sssubv8qi3 (operand0, operand1, operand2)
04083      rtx operand0;
04084      rtx operand1;
04085      rtx operand2;
04086 {
04087   return gen_rtx_SET (VOIDmode,
04088   operand0,
04089   gen_rtx_SS_MINUS (V8QImode,
04090   operand1,
04091   operand2));
04092 }
04093 
04094 /* ../../gcc/gcc/config/i386/i386.md:19519 */
04095 rtx
04096 gen_sssubv4hi3 (operand0, operand1, operand2)
04097      rtx operand0;
04098      rtx operand1;
04099      rtx operand2;
04100 {
04101   return gen_rtx_SET (VOIDmode,
04102   operand0,
04103   gen_rtx_SS_MINUS (V4HImode,
04104   operand1,
04105   operand2));
04106 }
04107 
04108 /* ../../gcc/gcc/config/i386/i386.md:19528 */
04109 rtx
04110 gen_ussubv8qi3 (operand0, operand1, operand2)
04111      rtx operand0;
04112      rtx operand1;
04113      rtx operand2;
04114 {
04115   return gen_rtx_SET (VOIDmode,
04116   operand0,
04117   gen_rtx_US_MINUS (V8QImode,
04118   operand1,
04119   operand2));
04120 }
04121 
04122 /* ../../gcc/gcc/config/i386/i386.md:19537 */
04123 rtx
04124 gen_ussubv4hi3 (operand0, operand1, operand2)
04125      rtx operand0;
04126      rtx operand1;
04127      rtx operand2;
04128 {
04129   return gen_rtx_SET (VOIDmode,
04130   operand0,
04131   gen_rtx_US_MINUS (V4HImode,
04132   operand1,
04133   operand2));
04134 }
04135 
04136 /* ../../gcc/gcc/config/i386/i386.md:19546 */
04137 rtx
04138 gen_mulv4hi3 (operand0, operand1, operand2)
04139      rtx operand0;
04140      rtx operand1;
04141      rtx operand2;
04142 {
04143   return gen_rtx_SET (VOIDmode,
04144   operand0,
04145   gen_rtx_MULT (V4HImode,
04146   operand1,
04147   operand2));
04148 }
04149 
04150 /* ../../gcc/gcc/config/i386/i386.md:19555 */
04151 rtx
04152 gen_smulv4hi3_highpart (operand0, operand1, operand2)
04153      rtx operand0;
04154      rtx operand1;
04155      rtx operand2;
04156 {
04157   return gen_rtx_SET (VOIDmode,
04158   operand0,
04159   gen_rtx_TRUNCATE (V4HImode,
04160   gen_rtx_LSHIFTRT (V4SImode,
04161   gen_rtx_MULT (V4SImode,
04162   gen_rtx_SIGN_EXTEND (V4SImode,
04163   operand1),
04164   gen_rtx_SIGN_EXTEND (V4SImode,
04165   operand2)),
04166   GEN_INT (16LL))));
04167 }
04168 
04169 /* ../../gcc/gcc/config/i386/i386.md:19569 */
04170 rtx
04171 gen_umulv4hi3_highpart (operand0, operand1, operand2)
04172      rtx operand0;
04173      rtx operand1;
04174      rtx operand2;
04175 {
04176   return gen_rtx_SET (VOIDmode,
04177   operand0,
04178   gen_rtx_TRUNCATE (V4HImode,
04179   gen_rtx_LSHIFTRT (V4SImode,
04180   gen_rtx_MULT (V4SImode,
04181   gen_rtx_ZERO_EXTEND (V4SImode,
04182   operand1),
04183   gen_rtx_ZERO_EXTEND (V4SImode,
04184   operand2)),
04185   GEN_INT (16LL))));
04186 }
04187 
04188 /* ../../gcc/gcc/config/i386/i386.md:19583 */
04189 rtx
04190 gen_mmx_pmaddwd (operand0, operand1, operand2)
04191      rtx operand0;
04192      rtx operand1;
04193      rtx operand2;
04194 {
04195   return gen_rtx_SET (VOIDmode,
04196   operand0,
04197   gen_rtx_PLUS (V2SImode,
04198   gen_rtx_MULT (V2SImode,
04199   gen_rtx_SIGN_EXTEND (V2SImode,
04200   gen_rtx_VEC_SELECT (V2HImode,
04201   operand1,
04202   gen_rtx_PARALLEL (VOIDmode,
04203   gen_rtvec (2,
04204     const0_rtx,
04205     GEN_INT (2LL))))),
04206   gen_rtx_SIGN_EXTEND (V2SImode,
04207   gen_rtx_VEC_SELECT (V2HImode,
04208   operand2,
04209   gen_rtx_PARALLEL (VOIDmode,
04210   gen_rtvec (2,
04211     const0_rtx,
04212     GEN_INT (2LL)))))),
04213   gen_rtx_MULT (V2SImode,
04214   gen_rtx_SIGN_EXTEND (V2SImode,
04215   gen_rtx_VEC_SELECT (V2HImode,
04216   operand1,
04217   gen_rtx_PARALLEL (VOIDmode,
04218   gen_rtvec (2,
04219     const1_rtx,
04220     GEN_INT (3LL))))),
04221   gen_rtx_SIGN_EXTEND (V2SImode,
04222   gen_rtx_VEC_SELECT (V2HImode,
04223   operand2,
04224   gen_rtx_PARALLEL (VOIDmode,
04225   gen_rtvec (2,
04226     const1_rtx,
04227     GEN_INT (3LL))))))));
04228 }
04229 
04230 /* ../../gcc/gcc/config/i386/i386.md:19610 */
04231 rtx
04232 gen_mmx_iordi3 (operand0, operand1, operand2)
04233      rtx operand0;
04234      rtx operand1;
04235      rtx operand2;
04236 {
04237   return gen_rtx_SET (VOIDmode,
04238   operand0,
04239   gen_rtx_UNSPEC (DImode,
04240   gen_rtvec (1,
04241     gen_rtx_IOR (DImode,
04242   operand1,
04243   operand2)),
04244   45));
04245 }
04246 
04247 /* ../../gcc/gcc/config/i386/i386.md:19621 */
04248 rtx
04249 gen_mmx_xordi3 (operand0, operand1, operand2)
04250      rtx operand0;
04251      rtx operand1;
04252      rtx operand2;
04253 {
04254   return gen_rtx_SET (VOIDmode,
04255   operand0,
04256   gen_rtx_UNSPEC (DImode,
04257   gen_rtvec (1,
04258     gen_rtx_XOR (DImode,
04259   operand1,
04260   operand2)),
04261   45));
04262 }
04263 
04264 /* ../../gcc/gcc/config/i386/i386.md:19635 */
04265 rtx
04266 gen_mmx_clrdi (operand0)
04267      rtx operand0;
04268 {
04269   return gen_rtx_SET (VOIDmode,
04270   operand0,
04271   gen_rtx_UNSPEC (DImode,
04272   gen_rtvec (1,
04273     const0_rtx),
04274   45));
04275 }
04276 
04277 /* ../../gcc/gcc/config/i386/i386.md:19644 */
04278 rtx
04279 gen_mmx_anddi3 (operand0, operand1, operand2)
04280      rtx operand0;
04281      rtx operand1;
04282      rtx operand2;
04283 {
04284   return gen_rtx_SET (VOIDmode,
04285   operand0,
04286   gen_rtx_UNSPEC (DImode,
04287   gen_rtvec (1,
04288     gen_rtx_AND (DImode,
04289   operand1,
04290   operand2)),
04291   45));
04292 }
04293 
04294 /* ../../gcc/gcc/config/i386/i386.md:19655 */
04295 rtx
04296 gen_mmx_nanddi3 (operand0, operand1, operand2)
04297      rtx operand0;
04298      rtx operand1;
04299      rtx operand2;
04300 {
04301   return gen_rtx_SET (VOIDmode,
04302   operand0,
04303   gen_rtx_UNSPEC (DImode,
04304   gen_rtvec (1,
04305     gen_rtx_AND (DImode,
04306   gen_rtx_NOT (DImode,
04307   operand1),
04308   operand2)),
04309   45));
04310 }
04311 
04312 /* ../../gcc/gcc/config/i386/i386.md:19669 */
04313 rtx
04314 gen_mmx_uavgv8qi3 (operand0, operand1, operand2)
04315      rtx operand0;
04316      rtx operand1;
04317      rtx operand2;
04318 {
04319   return gen_rtx_SET (VOIDmode,
04320   operand0,
04321   gen_rtx_ASHIFTRT (V8QImode,
04322   gen_rtx_PLUS (V8QImode,
04323   gen_rtx_PLUS (V8QImode,
04324   operand1,
04325   operand2),
04326   gen_rtx_CONST_VECTOR (V8QImode,
04327   gen_rtvec (8,
04328     const1_rtx,
04329     const1_rtx,
04330     const1_rtx,
04331     const1_rtx,
04332     const1_rtx,
04333     const1_rtx,
04334     const1_rtx,
04335     const1_rtx))),
04336   const1_rtx));
04337 }
04338 
04339 /* ../../gcc/gcc/config/i386/i386.md:19689 */
04340 rtx
04341 gen_mmx_uavgv4hi3 (operand0, operand1, operand2)
04342      rtx operand0;
04343      rtx operand1;
04344      rtx operand2;
04345 {
04346   return gen_rtx_SET (VOIDmode,
04347   operand0,
04348   gen_rtx_ASHIFTRT (V4HImode,
04349   gen_rtx_PLUS (V4HImode,
04350   gen_rtx_PLUS (V4HImode,
04351   operand1,
04352   operand2),
04353   gen_rtx_CONST_VECTOR (V4HImode,
04354   gen_rtvec (4,
04355     const1_rtx,
04356     const1_rtx,
04357     const1_rtx,
04358     const1_rtx))),
04359   const1_rtx));
04360 }
04361 
04362 /* ../../gcc/gcc/config/i386/i386.md:19705 */
04363 rtx
04364 gen_mmx_psadbw (operand0, operand1, operand2)
04365      rtx operand0;
04366      rtx operand1;
04367      rtx operand2;
04368 {
04369   return gen_rtx_SET (VOIDmode,
04370   operand0,
04371   gen_rtx_UNSPEC (DImode,
04372   gen_rtvec (2,
04373     operand1,
04374     operand2),
04375   61));
04376 }
04377 
04378 /* ../../gcc/gcc/config/i386/i386.md:19718 */
04379 rtx
04380 gen_mmx_pinsrw (operand0, operand1, operand2, operand3)
04381      rtx operand0;
04382      rtx operand1;
04383      rtx operand2;
04384      rtx operand3;
04385 {
04386   return gen_rtx_SET (VOIDmode,
04387   operand0,
04388   gen_rtx_VEC_MERGE (V4HImode,
04389   operand1,
04390   gen_rtx_VEC_DUPLICATE (V4HImode,
04391   gen_rtx_TRUNCATE (HImode,
04392   operand2)),
04393   operand3));
04394 }
04395 
04396 /* ../../gcc/gcc/config/i386/i386.md:19729 */
04397 rtx
04398 gen_mmx_pextrw (operand0, operand1, operand2)
04399      rtx operand0;
04400      rtx operand1;
04401      rtx operand2;
04402 {
04403   return gen_rtx_SET (VOIDmode,
04404   operand0,
04405   gen_rtx_ZERO_EXTEND (SImode,
04406   gen_rtx_VEC_SELECT (HImode,
04407   operand1,
04408   gen_rtx_PARALLEL (VOIDmode,
04409   gen_rtvec (1,
04410     operand2)))));
04411 }
04412 
04413 /* ../../gcc/gcc/config/i386/i386.md:19739 */
04414 rtx
04415 gen_mmx_pshufw (operand0, operand1, operand2)
04416      rtx operand0;
04417      rtx operand1;
04418      rtx operand2;
04419 {
04420   return gen_rtx_SET (VOIDmode,
04421   operand0,
04422   gen_rtx_UNSPEC (V4HImode,
04423   gen_rtvec (2,
04424     operand1,
04425     operand2),
04426   41));
04427 }
04428 
04429 /* ../../gcc/gcc/config/i386/i386.md:19752 */
04430 rtx
04431 gen_eqv8qi3 (operand0, operand1, operand2)
04432      rtx operand0;
04433      rtx operand1;
04434      rtx operand2;
04435 {
04436   return gen_rtx_SET (VOIDmode,
04437   operand0,
04438   gen_rtx_EQ (V8QImode,
04439   operand1,
04440   operand2));
04441 }
04442 
04443 /* ../../gcc/gcc/config/i386/i386.md:19761 */
04444 rtx
04445 gen_eqv4hi3 (operand0, operand1, operand2)
04446      rtx operand0;
04447      rtx operand1;
04448      rtx operand2;
04449 {
04450   return gen_rtx_SET (VOIDmode,
04451   operand0,
04452   gen_rtx_EQ (V4HImode,
04453   operand1,
04454   operand2));
04455 }
04456 
04457 /* ../../gcc/gcc/config/i386/i386.md:19770 */
04458 rtx
04459 gen_eqv2si3 (operand0, operand1, operand2)
04460      rtx operand0;
04461      rtx operand1;
04462      rtx operand2;
04463 {
04464   return gen_rtx_SET (VOIDmode,
04465   operand0,
04466   gen_rtx_EQ (V2SImode,
04467   operand1,
04468   operand2));
04469 }
04470 
04471 /* ../../gcc/gcc/config/i386/i386.md:19779 */
04472 rtx
04473 gen_gtv8qi3 (operand0, operand1, operand2)
04474      rtx operand0;
04475      rtx operand1;
04476      rtx operand2;
04477 {
04478   return gen_rtx_SET (VOIDmode,
04479   operand0,
04480   gen_rtx_GT (V8QImode,
04481   operand1,
04482   operand2));
04483 }
04484 
04485 /* ../../gcc/gcc/config/i386/i386.md:19788 */
04486 rtx
04487 gen_gtv4hi3 (operand0, operand1, operand2)
04488      rtx operand0;
04489      rtx operand1;
04490      rtx operand2;
04491 {
04492   return gen_rtx_SET (VOIDmode,
04493   operand0,
04494   gen_rtx_GT (V4HImode,
04495   operand1,
04496   operand2));
04497 }
04498 
04499 /* ../../gcc/gcc/config/i386/i386.md:19797 */
04500 rtx
04501 gen_gtv2si3 (operand0, operand1, operand2)
04502      rtx operand0;
04503      rtx operand1;
04504      rtx operand2;
04505 {
04506   return gen_rtx_SET (VOIDmode,
04507   operand0,
04508   gen_rtx_GT (V2SImode,
04509   operand1,
04510   operand2));
04511 }
04512 
04513 /* ../../gcc/gcc/config/i386/i386.md:19809 */
04514 rtx
04515 gen_umaxv8qi3 (operand0, operand1, operand2)
04516      rtx operand0;
04517      rtx operand1;
04518      rtx operand2;
04519 {
04520   return gen_rtx_SET (VOIDmode,
04521   operand0,
04522   gen_rtx_UMAX (V8QImode,
04523   operand1,
04524   operand2));
04525 }
04526 
04527 /* ../../gcc/gcc/config/i386/i386.md:19818 */
04528 rtx
04529 gen_smaxv4hi3 (operand0, operand1, operand2)
04530      rtx operand0;
04531      rtx operand1;
04532      rtx operand2;
04533 {
04534   return gen_rtx_SET (VOIDmode,
04535   operand0,
04536   gen_rtx_SMAX (V4HImode,
04537   operand1,
04538   operand2));
04539 }
04540 
04541 /* ../../gcc/gcc/config/i386/i386.md:19827 */
04542 rtx
04543 gen_uminv8qi3 (operand0, operand1, operand2)
04544      rtx operand0;
04545      rtx operand1;
04546      rtx operand2;
04547 {
04548   return gen_rtx_SET (VOIDmode,
04549   operand0,
04550   gen_rtx_UMIN (V8QImode,
04551   operand1,
04552   operand2));
04553 }
04554 
04555 /* ../../gcc/gcc/config/i386/i386.md:19836 */
04556 rtx
04557 gen_sminv4hi3 (operand0, operand1, operand2)
04558      rtx operand0;
04559      rtx operand1;
04560      rtx operand2;
04561 {
04562   return gen_rtx_SET (VOIDmode,
04563   operand0,
04564   gen_rtx_SMIN (V4HImode,
04565   operand1,
04566   operand2));
04567 }
04568 
04569 /* ../../gcc/gcc/config/i386/i386.md:19848 */
04570 rtx
04571 gen_ashrv4hi3 (operand0, operand1, operand2)
04572      rtx operand0;
04573      rtx operand1;
04574      rtx operand2;
04575 {
04576   return gen_rtx_SET (VOIDmode,
04577   operand0,
04578   gen_rtx_ASHIFTRT (V4HImode,
04579   operand1,
04580   operand2));
04581 }
04582 
04583 /* ../../gcc/gcc/config/i386/i386.md:19857 */
04584 rtx
04585 gen_ashrv2si3 (operand0, operand1, operand2)
04586      rtx operand0;
04587      rtx operand1;
04588      rtx operand2;
04589 {
04590   return gen_rtx_SET (VOIDmode,
04591   operand0,
04592   gen_rtx_ASHIFTRT (V2SImode,
04593   operand1,
04594   operand2));
04595 }
04596 
04597 /* ../../gcc/gcc/config/i386/i386.md:19866 */
04598 rtx
04599 gen_lshrv4hi3 (operand0, operand1, operand2)
04600      rtx operand0;
04601      rtx operand1;
04602      rtx operand2;
04603 {
04604   return gen_rtx_SET (VOIDmode,
04605   operand0,
04606   gen_rtx_LSHIFTRT (V4HImode,
04607   operand1,
04608   operand2));
04609 }
04610 
04611 /* ../../gcc/gcc/config/i386/i386.md:19875 */
04612 rtx
04613 gen_lshrv2si3 (operand0, operand1, operand2)
04614      rtx operand0;
04615      rtx operand1;
04616      rtx operand2;
04617 {
04618   return gen_rtx_SET (VOIDmode,
04619   operand0,
04620   gen_rtx_LSHIFTRT (V2SImode,
04621   operand1,
04622   operand2));
04623 }
04624 
04625 /* ../../gcc/gcc/config/i386/i386.md:19885 */
04626 rtx
04627 gen_mmx_lshrdi3 (operand0, operand1, operand2)
04628      rtx operand0;
04629      rtx operand1;
04630      rtx operand2;
04631 {
04632   return gen_rtx_SET (VOIDmode,
04633   operand0,
04634   gen_rtx_UNSPEC (DImode,
04635   gen_rtvec (1,
04636     gen_rtx_LSHIFTRT (DImode,
04637   operand1,
04638   operand2)),
04639   45));
04640 }
04641 
04642 /* ../../gcc/gcc/config/i386/i386.md:19896 */
04643 rtx
04644 gen_ashlv4hi3 (operand0, operand1, operand2)
04645      rtx operand0;
04646      rtx operand1;
04647      rtx operand2;
04648 {
04649   return gen_rtx_SET (VOIDmode,
04650   operand0,
04651   gen_rtx_ASHIFT (V4HImode,
04652   operand1,
04653   operand2));
04654 }
04655 
04656 /* ../../gcc/gcc/config/i386/i386.md:19905 */
04657 rtx
04658 gen_ashlv2si3 (operand0, operand1, operand2)
04659      rtx operand0;
04660      rtx operand1;
04661      rtx operand2;
04662 {
04663   return gen_rtx_SET (VOIDmode,
04664   operand0,
04665   gen_rtx_ASHIFT (V2SImode,
04666   operand1,
04667   operand2));
04668 }
04669 
04670 /* ../../gcc/gcc/config/i386/i386.md:19915 */
04671 rtx
04672 gen_mmx_ashldi3 (operand0, operand1, operand2)
04673      rtx operand0;
04674      rtx operand1;
04675      rtx operand2;
04676 {
04677   return gen_rtx_SET (VOIDmode,
04678   operand0,
04679   gen_rtx_UNSPEC (DImode,
04680   gen_rtvec (1,
04681     gen_rtx_ASHIFT (DImode,
04682   operand1,
04683   operand2)),
04684   45));
04685 }
04686 
04687 /* ../../gcc/gcc/config/i386/i386.md:19929 */
04688 rtx
04689 gen_mmx_packsswb (operand0, operand1, operand2)
04690      rtx operand0;
04691      rtx operand1;
04692      rtx operand2;
04693 {
04694   return gen_rtx_SET (VOIDmode,
04695   operand0,
04696   gen_rtx_VEC_CONCAT (V8QImode,
04697   gen_rtx_SS_TRUNCATE (V4QImode,
04698   operand1),
04699   gen_rtx_SS_TRUNCATE (V4QImode,
04700   operand2)));
04701 }
04702 
04703 /* ../../gcc/gcc/config/i386/i386.md:19939 */
04704 rtx
04705 gen_mmx_packssdw (operand0, operand1, operand2)
04706      rtx operand0;
04707      rtx operand1;
04708      rtx operand2;
04709 {
04710   return gen_rtx_SET (VOIDmode,
04711   operand0,
04712   gen_rtx_VEC_CONCAT (V4HImode,
04713   gen_rtx_SS_TRUNCATE (V2HImode,
04714   operand1),
04715   gen_rtx_SS_TRUNCATE (V2HImode,
04716   operand2)));
04717 }
04718 
04719 /* ../../gcc/gcc/config/i386/i386.md:19949 */
04720 rtx
04721 gen_mmx_packuswb (operand0, operand1, operand2)
04722      rtx operand0;
04723      rtx operand1;
04724      rtx operand2;
04725 {
04726   return gen_rtx_SET (VOIDmode,
04727   operand0,
04728   gen_rtx_VEC_CONCAT (V8QImode,
04729   gen_rtx_US_TRUNCATE (V4QImode,
04730   operand1),
04731   gen_rtx_US_TRUNCATE (V4QImode,
04732   operand2)));
04733 }
04734 
04735 /* ../../gcc/gcc/config/i386/i386.md:19959 */
04736 rtx
04737 gen_mmx_punpckhbw (operand0, operand1, operand2)
04738      rtx operand0;
04739      rtx operand1;
04740      rtx operand2;
04741 {
04742   return gen_rtx_SET (VOIDmode,
04743   operand0,
04744   gen_rtx_VEC_MERGE (V8QImode,
04745   gen_rtx_VEC_SELECT (V8QImode,
04746   operand1,
04747   gen_rtx_PARALLEL (VOIDmode,
04748   gen_rtvec (8,
04749     GEN_INT (4LL),
04750     const0_rtx,
04751     GEN_INT (5LL),
04752     const1_rtx,
04753     GEN_INT (6LL),
04754     GEN_INT (2LL),
04755     GEN_INT (7LL),
04756     GEN_INT (3LL)))),
04757   gen_rtx_VEC_SELECT (V8QImode,
04758   operand2,
04759   gen_rtx_PARALLEL (VOIDmode,
04760   gen_rtvec (8,
04761     const0_rtx,
04762     GEN_INT (4LL),
04763     const1_rtx,
04764     GEN_INT (5LL),
04765     GEN_INT (2LL),
04766     GEN_INT (6LL),
04767     GEN_INT (3LL),
04768     GEN_INT (7LL)))),
04769   GEN_INT (85LL)));
04770 }
04771 
04772 /* ../../gcc/gcc/config/i386/i386.md:19986 */
04773 rtx
04774 gen_mmx_punpckhwd (operand0, operand1, operand2)
04775      rtx operand0;
04776      rtx operand1;
04777      rtx operand2;
04778 {
04779   return gen_rtx_SET (VOIDmode,
04780   operand0,
04781   gen_rtx_VEC_MERGE (V4HImode,
04782   gen_rtx_VEC_SELECT (V4HImode,
04783   operand1,
04784   gen_rtx_PARALLEL (VOIDmode,
04785   gen_rtvec (4,
04786     const0_rtx,
04787     GEN_INT (2LL),
04788     const1_rtx,
04789     GEN_INT (3LL)))),
04790   gen_rtx_VEC_SELECT (V4HImode,
04791   operand2,
04792   gen_rtx_PARALLEL (VOIDmode,
04793   gen_rtvec (4,
04794     GEN_INT (2LL),
04795     const0_rtx,
04796     GEN_INT (3LL),
04797     const1_rtx))),
04798   GEN_INT (5LL)));
04799 }
04800 
04801 /* ../../gcc/gcc/config/i386/i386.md:20005 */
04802 rtx
04803 gen_mmx_punpckhdq (operand0, operand1, operand2)
04804      rtx operand0;
04805      rtx operand1;
04806      rtx operand2;
04807 {
04808   return gen_rtx_SET (VOIDmode,
04809   operand0,
04810   gen_rtx_VEC_MERGE (V2SImode,
04811   operand1,
04812   gen_rtx_VEC_SELECT (V2SImode,
04813   operand2,
04814   gen_rtx_PARALLEL (VOIDmode,
04815   gen_rtvec (2,
04816     const1_rtx,
04817     const0_rtx))),
04818   const1_rtx));
04819 }
04820 
04821 /* ../../gcc/gcc/config/i386/i386.md:20018 */
04822 rtx
04823 gen_mmx_punpcklbw (operand0, operand1, operand2)
04824      rtx operand0;
04825      rtx operand1;
04826      rtx operand2;
04827 {
04828   return gen_rtx_SET (VOIDmode,
04829   operand0,
04830   gen_rtx_VEC_MERGE (V8QImode,
04831   gen_rtx_VEC_SELECT (V8QImode,
04832   operand1,
04833   gen_rtx_PARALLEL (VOIDmode,
04834   gen_rtvec (8,
04835     const0_rtx,
04836     GEN_INT (4LL),
04837     const1_rtx,
04838     GEN_INT (5LL),
04839     GEN_INT (2LL),
04840     GEN_INT (6LL),
04841     GEN_INT (3LL),
04842     GEN_INT (7LL)))),
04843   gen_rtx_VEC_SELECT (V8QImode,
04844   operand2,
04845   gen_rtx_PARALLEL (VOIDmode,
04846   gen_rtvec (8,
04847     GEN_INT (4LL),
04848     const0_rtx,
04849     GEN_INT (5LL),
04850     const1_rtx,
04851     GEN_INT (6LL),
04852     GEN_INT (2LL),
04853     GEN_INT (7LL),
04854     GEN_INT (3LL)))),
04855   GEN_INT (85LL)));
04856 }
04857 
04858 /* ../../gcc/gcc/config/i386/i386.md:20045 */
04859 rtx
04860 gen_mmx_punpcklwd (operand0, operand1, operand2)
04861      rtx operand0;
04862      rtx operand1;
04863      rtx operand2;
04864 {
04865   return gen_rtx_SET (VOIDmode,
04866   operand0,
04867   gen_rtx_VEC_MERGE (V4HImode,
04868   gen_rtx_VEC_SELECT (V4HImode,
04869   operand1,
04870   gen_rtx_PARALLEL (VOIDmode,
04871   gen_rtvec (4,
04872     GEN_INT (2LL),
04873     const0_rtx,
04874     GEN_INT (3LL),
04875     const1_rtx))),
04876   gen_rtx_VEC_SELECT (V4HImode,
04877   operand2,
04878   gen_rtx_PARALLEL (VOIDmode,
04879   gen_rtvec (4,
04880     const0_rtx,
04881     GEN_INT (2LL),
04882     const1_rtx,
04883     GEN_INT (3LL)))),
04884   GEN_INT (5LL)));
04885 }
04886 
04887 /* ../../gcc/gcc/config/i386/i386.md:20064 */
04888 rtx
04889 gen_mmx_punpckldq (operand0, operand1, operand2)
04890      rtx operand0;
04891      rtx operand1;
04892      rtx operand2;
04893 {
04894   return gen_rtx_SET (VOIDmode,
04895   operand0,
04896   gen_rtx_VEC_MERGE (V2SImode,
04897   gen_rtx_VEC_SELECT (V2SImode,
04898   operand1,
04899   gen_rtx_PARALLEL (VOIDmode,
04900   gen_rtvec (2,
04901     const1_rtx,
04902     const0_rtx))),
04903   operand2,
04904   const1_rtx));
04905 }
04906 
04907 /* ../../gcc/gcc/config/i386/i386.md:20080 */
04908 rtx
04909 gen_emms ()
04910 {
04911   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (17,
04912     gen_rtx_UNSPEC_VOLATILE (VOIDmode,
04913   gen_rtvec (1,
04914     const0_rtx),
04915   31),
04916     gen_rtx_CLOBBER (VOIDmode,
04917   gen_rtx_REG (XFmode,
04918   8)),
04919     gen_rtx_CLOBBER (VOIDmode,
04920   gen_rtx_REG (XFmode,
04921   9)),
04922     gen_rtx_CLOBBER (VOIDmode,
04923   gen_rtx_REG (XFmode,
04924   10)),
04925     gen_rtx_CLOBBER (VOIDmode,
04926   gen_rtx_REG (XFmode,
04927   11)),
04928     gen_rtx_CLOBBER (VOIDmode,
04929   gen_rtx_REG (XFmode,
04930   12)),
04931     gen_rtx_CLOBBER (VOIDmode,
04932   gen_rtx_REG (XFmode,
04933   13)),
04934     gen_rtx_CLOBBER (VOIDmode,
04935   gen_rtx_REG (XFmode,
04936   14)),
04937     gen_rtx_CLOBBER (VOIDmode,
04938   gen_rtx_REG (XFmode,
04939   15)),
04940     gen_rtx_CLOBBER (VOIDmode,
04941   gen_rtx_REG (DImode,
04942   29)),
04943     gen_rtx_CLOBBER (VOIDmode,
04944   gen_rtx_REG (DImode,
04945   30)),
04946     gen_rtx_CLOBBER (VOIDmode,
04947   gen_rtx_REG (DImode,
04948   31)),
04949     gen_rtx_CLOBBER (VOIDmode,
04950   gen_rtx_REG (DImode,
04951   32)),
04952     gen_rtx_CLOBBER (VOIDmode,
04953   gen_rtx_REG (DImode,
04954   33)),
04955     gen_rtx_CLOBBER (VOIDmode,
04956   gen_rtx_REG (DImode,
04957   34)),
04958     gen_rtx_CLOBBER (VOIDmode,
04959   gen_rtx_REG (DImode,
04960   35)),
04961     gen_rtx_CLOBBER (VOIDmode,
04962   gen_rtx_REG (DImode,
04963   36))));
04964 }
04965 
04966 /* ../../gcc/gcc/config/i386/i386.md:20103 */
04967 rtx
04968 gen_ldmxcsr (operand0)
04969      rtx operand0;
04970 {
04971   return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
04972   gen_rtvec (1,
04973     operand0),
04974   37);
04975 }
04976 
04977 /* ../../gcc/gcc/config/i386/i386.md:20111 */
04978 rtx
04979 gen_stmxcsr (operand0)
04980      rtx operand0;
04981 {
04982   return gen_rtx_SET (VOIDmode,
04983   operand0,
04984   gen_rtx_UNSPEC_VOLATILE (SImode,
04985   gen_rtvec (1,
04986     const0_rtx),
04987   40));
04988 }
04989 
04990 /* ../../gcc/gcc/config/i386/i386.md:20199 */
04991 rtx
04992 gen_addv2sf3 (operand0, operand1, operand2)
04993      rtx operand0;
04994      rtx operand1;
04995      rtx operand2;
04996 {
04997   return gen_rtx_SET (VOIDmode,
04998   operand0,
04999   gen_rtx_PLUS (V2SFmode,
05000   operand1,
05001   operand2));
05002 }
05003 
05004 /* ../../gcc/gcc/config/i386/i386.md:20208 */
05005 rtx
05006 gen_subv2sf3 (operand0, operand1, operand2)
05007      rtx operand0;
05008      rtx operand1;
05009      rtx operand2;
05010 {
05011   return gen_rtx_SET (VOIDmode,
05012   operand0,
05013   gen_rtx_MINUS (V2SFmode,
05014   operand1,
05015   operand2));
05016 }
05017 
05018 /* ../../gcc/gcc/config/i386/i386.md:20217 */
05019 rtx
05020 gen_subrv2sf3 (operand0, operand1, operand2)
05021      rtx operand0;
05022      rtx operand1;
05023      rtx operand2;
05024 {
05025   return gen_rtx_SET (VOIDmode,
05026   operand0,
05027   gen_rtx_MINUS (V2SFmode,
05028   operand2,
05029   operand1));
05030 }
05031 
05032 /* ../../gcc/gcc/config/i386/i386.md:20226 */
05033 rtx
05034 gen_gtv2sf3 (operand0, operand1, operand2)
05035      rtx operand0;
05036      rtx operand1;
05037      rtx operand2;
05038 {
05039   return gen_rtx_SET (VOIDmode,
05040   operand0,
05041   gen_rtx_GT (V2SImode,
05042   operand1,
05043   operand2));
05044 }
05045 
05046 /* ../../gcc/gcc/config/i386/i386.md:20235 */
05047 rtx
05048 gen_gev2sf3 (operand0, operand1, operand2)
05049      rtx operand0;
05050      rtx operand1;
05051      rtx operand2;
05052 {
05053   return gen_rtx_SET (VOIDmode,
05054   operand0,
05055   gen_rtx_GE (V2SImode,
05056   operand1,
05057   operand2));
05058 }
05059 
05060 /* ../../gcc/gcc/config/i386/i386.md:20244 */
05061 rtx
05062 gen_eqv2sf3 (operand0, operand1, operand2)
05063      rtx operand0;
05064      rtx operand1;
05065      rtx operand2;
05066 {
05067   return gen_rtx_SET (VOIDmode,
05068   operand0,
05069   gen_rtx_EQ (V2SImode,
05070   operand1,
05071   operand2));
05072 }
05073 
05074 /* ../../gcc/gcc/config/i386/i386.md:20253 */
05075 rtx
05076 gen_pfmaxv2sf3 (operand0, operand1, operand2)
05077      rtx operand0;
05078      rtx operand1;
05079      rtx operand2;
05080 {
05081   return gen_rtx_SET (VOIDmode,
05082   operand0,
05083   gen_rtx_SMAX (V2SFmode,
05084   operand1,
05085   operand2));
05086 }
05087 
05088 /* ../../gcc/gcc/config/i386/i386.md:20262 */
05089 rtx
05090 gen_pfminv2sf3 (operand0, operand1, operand2)
05091      rtx operand0;
05092      rtx operand1;
05093      rtx operand2;
05094 {
05095   return gen_rtx_SET (VOIDmode,
05096   operand0,
05097   gen_rtx_SMIN (V2SFmode,
05098   operand1,
05099   operand2));
05100 }
05101 
05102 /* ../../gcc/gcc/config/i386/i386.md:20271 */
05103 rtx
05104 gen_mulv2sf3 (operand0, operand1, operand2)
05105      rtx operand0;
05106      rtx operand1;
05107      rtx operand2;
05108 {
05109   return gen_rtx_SET (VOIDmode,
05110   operand0,
05111   gen_rtx_MULT (V2SFmode,
05112   operand1,
05113   operand2));
05114 }
05115 
05116 /* ../../gcc/gcc/config/i386/i386.md:20280 */
05117 rtx
05118 gen_femms ()
05119 {
05120   return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (17,
05121     gen_rtx_UNSPEC_VOLATILE (VOIDmode,
05122   gen_rtvec (1,
05123     const0_rtx),
05124   46),
05125     gen_rtx_CLOBBER (VOIDmode,
05126   gen_rtx_REG (XFmode,
05127   8)),
05128     gen_rtx_CLOBBER (VOIDmode,
05129   gen_rtx_REG (XFmode,
05130   9)),
05131     gen_rtx_CLOBBER (VOIDmode,
05132   gen_rtx_REG (XFmode,
05133   10)),
05134     gen_rtx_CLOBBER (VOIDmode,
05135   gen_rtx_REG (XFmode,
05136   11)),
05137     gen_rtx_CLOBBER (VOIDmode,
05138   gen_rtx_REG (XFmode,
05139   12)),
05140     gen_rtx_CLOBBER (VOIDmode,
05141   gen_rtx_REG (XFmode,
05142   13)),
05143     gen_rtx_CLOBBER (VOIDmode,
05144   gen_rtx_REG (XFmode,
05145   14)),
05146     gen_rtx_CLOBBER (VOIDmode,
05147   gen_rtx_REG (XFmode,
05148   15)),
05149     gen_rtx_CLOBBER (VOIDmode,
05150   gen_rtx_REG (DImode,
05151   29)),
05152     gen_rtx_CLOBBER (VOIDmode,
05153   gen_rtx_REG (DImode,
05154   30)),
05155     gen_rtx_CLOBBER (VOIDmode,
05156   gen_rtx_REG (DImode,
05157   31)),
05158     gen_rtx_CLOBBER (VOIDmode,
05159   gen_rtx_REG (DImode,
05160   32)),
05161     gen_rtx_CLOBBER (VOIDmode,
05162   gen_rtx_REG (DImode,
05163   33)),
05164     gen_rtx_CLOBBER (VOIDmode,
05165   gen_rtx_REG (DImode,
05166   34)),
05167     gen_rtx_CLOBBER (VOIDmode,
05168   gen_rtx_REG (DImode,
05169   35)),
05170     gen_rtx_CLOBBER (VOIDmode,
05171   gen_rtx_REG (DImode,
05172   36))));
05173 }
05174 
05175 /* ../../gcc/gcc/config/i386/i386.md:20303 */
05176 rtx
05177 gen_pf2id (operand0, operand1)
05178      rtx operand0;
05179      rtx operand1;
05180 {
05181   return gen_rtx_SET (VOIDmode,
05182   operand0,
05183   gen_rtx_FIX (V2SImode,
05184   operand1));
05185 }
05186 
05187 /* ../../gcc/gcc/config/i386/i386.md:20311 */
05188 rtx
05189 gen_pf2iw (operand0, operand1)
05190      rtx operand0;
05191      rtx operand1;
05192 {
05193   return gen_rtx_SET (VOIDmode,
05194   operand0,
05195   gen_rtx_SIGN_EXTEND (V2SImode,
05196   gen_rtx_SS_TRUNCATE (V2HImode,
05197   gen_rtx_FIX (V2SImode,
05198   operand1))));
05199 }
05200 
05201 /* ../../gcc/gcc/config/i386/i386.md:20321 */
05202 rtx
05203 gen_pfacc (operand0, operand1, operand2)
05204      rtx operand0;
05205      rtx operand1;
05206      rtx operand2;
05207 {
05208   return gen_rtx_SET (VOIDmode,
05209   operand0,
05210   gen_rtx_VEC_CONCAT (V2SFmode,
05211   gen_rtx_PLUS (SFmode,
05212   gen_rtx_VEC_SELECT (SFmode,
05213   operand1,
05214   gen_rtx_PARALLEL (VOIDmode,
05215   gen_rtvec (1,
05216     const0_rtx))),
05217   gen_rtx_VEC_SELECT (SFmode,
05218   operand1,
05219   gen_rtx_PARALLEL (VOIDmode,
05220   gen_rtvec (1,
05221     const1_rtx)))),
05222   gen_rtx_PLUS (SFmode,
05223   gen_rtx_VEC_SELECT (SFmode,
05224   operand2,
05225   gen_rtx_PARALLEL (VOIDmode,
05226   gen_rtvec (1,
05227     const0_rtx))),
05228   gen_rtx_VEC_SELECT (SFmode,
05229   operand2,
05230   gen_rtx_PARALLEL (VOIDmode,
05231   gen_rtvec (1,
05232     const1_rtx))))));
05233 }
05234 
05235 /* ../../gcc/gcc/config/i386/i386.md:20339 */
05236 rtx
05237 gen_pfnacc (operand0, operand1, operand2)
05238      rtx operand0;
05239      rtx operand1;
05240      rtx operand2;
05241 {
05242   return gen_rtx_SET (VOIDmode,
05243   operand0,
05244   gen_rtx_VEC_CONCAT (V2SFmode,
05245   gen_rtx_MINUS (SFmode,
05246   gen_rtx_VEC_SELECT (SFmode,
05247   operand1,
05248   gen_rtx_PARALLEL (VOIDmode,
05249   gen_rtvec (1,
05250     const0_rtx))),
05251   gen_rtx_VEC_SELECT (SFmode,
05252   operand1,
05253   gen_rtx_PARALLEL (VOIDmode,
05254   gen_rtvec (1,
05255     const1_rtx)))),
05256   gen_rtx_MINUS (SFmode,
05257   gen_rtx_VEC_SELECT (SFmode,
05258   operand2,
05259   gen_rtx_PARALLEL (VOIDmode,
05260   gen_rtvec (1,
05261     const0_rtx))),
05262   gen_rtx_VEC_SELECT (SFmode,
05263   operand2,
05264   gen_rtx_PARALLEL (VOIDmode,
05265   gen_rtvec (1,
05266     const1_rtx))))));
05267 }
05268 
05269 /* ../../gcc/gcc/config/i386/i386.md:20357 */
05270 rtx
05271 gen_pfpnacc (operand0, operand1, operand2)
05272      rtx operand0;
05273      rtx operand1;
05274      rtx operand2;
05275 {
05276   return gen_rtx_SET (VOIDmode,
05277   operand0,
05278   gen_rtx_VEC_CONCAT (V2SFmode,
05279   gen_rtx_MINUS (SFmode,
05280   gen_rtx_VEC_SELECT (SFmode,
05281   operand1,
05282   gen_rtx_PARALLEL (VOIDmode,
05283   gen_rtvec (1,
05284     const0_rtx))),
05285   gen_rtx_VEC_SELECT (SFmode,
05286   operand1,
05287   gen_rtx_PARALLEL (VOIDmode,
05288   gen_rtvec (1,
05289     const1_rtx)))),
05290   gen_rtx_PLUS (SFmode,
05291   gen_rtx_VEC_SELECT (SFmode,
05292   operand2,
05293   gen_rtx_PARALLEL (VOIDmode,
05294   gen_rtvec (1,
05295     const0_rtx))),
05296   gen_rtx_VEC_SELECT (SFmode,
05297   operand2,
05298   gen_rtx_PARALLEL (VOIDmode,
05299   gen_rtvec (1,
05300     const1_rtx))))));
05301 }
05302 
05303 /* ../../gcc/gcc/config/i386/i386.md:20375 */
05304 rtx
05305 gen_pi2fw (operand0, operand1)
05306      rtx operand0;
05307      rtx operand1;
05308 {
05309   return gen_rtx_SET (VOIDmode,
05310   operand0,
05311   gen_rtx_FLOAT (V2SFmode,
05312   gen_rtx_VEC_CONCAT (V2SImode,
05313   gen_rtx_SIGN_EXTEND (SImode,
05314   gen_rtx_TRUNCATE (HImode,
05315   gen_rtx_VEC_SELECT (SImode,
05316   operand1,
05317   gen_rtx_PARALLEL (VOIDmode,
05318   gen_rtvec (1,
05319     const0_rtx))))),
05320   gen_rtx_SIGN_EXTEND (SImode,
05321   gen_rtx_TRUNCATE (HImode,
05322   gen_rtx_VEC_SELECT (SImode,
05323   operand1,
05324   gen_rtx_PARALLEL (VOIDmode,
05325   gen_rtvec (1,
05326     const1_rtx))))))));
05327 }
05328 
05329 /* ../../gcc/gcc/config/i386/i386.md:20392 */
05330 rtx
05331 gen_floatv2si2 (operand0, operand1)
05332      rtx operand0;
05333      rtx operand1;
05334 {
05335   return gen_rtx_SET (VOIDmode,
05336   operand0,
05337   gen_rtx_FLOAT (V2SFmode,
05338   operand1));
05339 }
05340 
05341 /* ../../gcc/gcc/config/i386/i386.md:20403 */
05342 rtx
05343 gen_pavgusb (operand0, operand1, operand2)
05344      rtx operand0;
05345      rtx operand1;
05346      rtx operand2;
05347 {
05348   return gen_rtx_SET (VOIDmode,
05349   operand0,
05350   gen_rtx_UNSPEC (V8QImode,
05351   gen_rtvec (2,
05352     operand1,
05353     operand2),
05354   49));
05355 }
05356 
05357 /* ../../gcc/gcc/config/i386/i386.md:20416 */
05358 rtx
05359 gen_pfrcpv2sf2 (operand0, operand1)
05360      rtx operand0;
05361      rtx operand1;
05362 {
05363   return gen_rtx_SET (VOIDmode,
05364   operand0,
05365   gen_rtx_UNSPEC (V2SFmode,
05366   gen_rtvec (1,
05367     operand1),
05368   50));
05369 }
05370 
05371 /* ../../gcc/gcc/config/i386/i386.md:20425 */
05372 rtx
05373 gen_pfrcpit1v2sf3 (operand0, operand1, operand2)
05374      rtx operand0;
05375      rtx operand1;
05376      rtx operand2;
05377 {
05378   return gen_rtx_SET (VOIDmode,
05379   operand0,
05380   gen_rtx_UNSPEC (V2SFmode,
05381   gen_rtvec (2,
05382     operand1,
05383     operand2),
05384   51));
05385 }
05386 
05387 /* ../../gcc/gcc/config/i386/i386.md:20435 */
05388 rtx
05389 gen_pfrcpit2v2sf3 (operand0, operand1, operand2)
05390      rtx operand0;
05391      rtx operand1;
05392      rtx operand2;
05393 {
05394   return gen_rtx_SET (VOIDmode,
05395   operand0,
05396   gen_rtx_UNSPEC (V2SFmode,
05397   gen_rtvec (2,
05398     operand1,
05399     operand2),
05400   52));
05401 }
05402 
05403 /* ../../gcc/gcc/config/i386/i386.md:20445 */
05404 rtx
05405 gen_pfrsqrtv2sf2 (operand0, operand1)
05406      rtx operand0;
05407      rtx operand1;
05408 {
05409   return gen_rtx_SET (VOIDmode,
05410   operand0,
05411   gen_rtx_UNSPEC (V2SFmode,
05412   gen_rtvec (1,
05413     operand1),
05414   53));
05415 }
05416 
05417 /* ../../gcc/gcc/config/i386/i386.md:20454 */
05418 rtx
05419 gen_pfrsqit1v2sf3 (operand0, operand1, operand2)
05420      rtx operand0;
05421      rtx operand1;
05422      rtx operand2;
05423 {
05424   return gen_rtx_SET (VOIDmode,
05425   operand0,
05426   gen_rtx_UNSPEC (V2SFmode,
05427   gen_rtvec (2,
05428     operand1,
05429     operand2),
05430   54));
05431 }
05432 
05433 /* ../../gcc/gcc/config/i386/i386.md:20464 */
05434 rtx
05435 gen_pmulhrwv4hi3 (operand0, operand1, operand2)
05436      rtx operand0;
05437      rtx operand1;
05438      rtx operand2;
05439 {
05440   return gen_rtx_SET (VOIDmode,
05441   operand0,
05442   gen_rtx_TRUNCATE (V4HImode,
05443   gen_rtx_LSHIFTRT (V4SImode,
05444   gen_rtx_PLUS (V4SImode,
05445   gen_rtx_MULT (V4SImode,
05446   gen_rtx_SIGN_EXTEND (V4SImode,
05447   operand1),
05448   gen_rtx_SIGN_EXTEND (V4SImode,
05449   operand2)),
05450   gen_rtx_CONST_VECTOR (V4SImode,
05451   gen_rtvec (4,
05452     GEN_INT (32768LL),
05453     GEN_INT (32768LL),
05454     GEN_INT (32768LL),
05455     GEN_INT (32768LL)))),
05456   GEN_INT (16LL))));
05457 }
05458 
05459 /* ../../gcc/gcc/config/i386/i386.md:20484 */
05460 rtx
05461 gen_pswapdv2si2 (operand0, operand1)
05462      rtx operand0;
05463      rtx operand1;
05464 {
05465   return gen_rtx_SET (VOIDmode,
05466   operand0,
05467   gen_rtx_VEC_SELECT (V2SImode,
05468   operand1,
05469   gen_rtx_PARALLEL (VOIDmode,
05470   gen_rtvec (2,
05471     const1_rtx,
05472     const0_rtx))));
05473 }
05474 
05475 /* ../../gcc/gcc/config/i386/i386.md:20493 */
05476 rtx
05477 gen_pswapdv2sf2 (operand0, operand1)
05478      rtx operand0;
05479      rtx operand1;
05480 {
05481   return gen_rtx_SET (VOIDmode,
05482   operand0,
05483   gen_rtx_VEC_SELECT (V2SFmode,
05484   operand1,
05485   gen_rtx_PARALLEL (VOIDmode,
05486   gen_rtvec (2,
05487     const1_rtx,
05488     const0_rtx))));
05489 }
05490 
05491 /* ../../gcc/gcc/config/i386/i386.md:20596 */
05492 rtx
05493 gen_addv2df3 (operand0, operand1, operand2)
05494      rtx operand0;
05495      rtx operand1;
05496      rtx operand2;
05497 {
05498   return gen_rtx_SET (VOIDmode,
05499   operand0,
05500   gen_rtx_PLUS (V2DFmode,
05501   operand1,
05502   operand2));
05503 }
05504 
05505 /* ../../gcc/gcc/config/i386/i386.md:20605 */
05506 rtx
05507 gen_vmaddv2df3 (operand0, operand1, operand2)
05508      rtx operand0;
05509      rtx operand1;
05510      rtx operand2;
05511 {
05512   return gen_rtx_SET (VOIDmode,
05513   operand0,
05514   gen_rtx_VEC_MERGE (V2DFmode,
05515   gen_rtx_PLUS (V2DFmode,
05516   operand1,
05517   operand2),
05518   operand1,
05519   const1_rtx));
05520 }
05521 
05522 /* ../../gcc/gcc/config/i386/i386.md:20616 */
05523 rtx
05524 gen_subv2df3 (operand0, operand1, operand2)
05525      rtx operand0;
05526      rtx operand1;
05527      rtx operand2;
05528 {
05529   return gen_rtx_SET (VOIDmode,
05530   operand0,
05531   gen_rtx_MINUS (V2DFmode,
05532   operand1,
05533   operand2));
05534 }
05535 
05536 /* ../../gcc/gcc/config/i386/i386.md:20625 */
05537 rtx
05538 gen_vmsubv2df3 (operand0, operand1, operand2)
05539      rtx operand0;
05540      rtx operand1;
05541      rtx operand2;
05542 {
05543   return gen_rtx_SET (VOIDmode,
05544   operand0,
05545   gen_rtx_VEC_MERGE (V2DFmode,
05546   gen_rtx_MINUS (V2DFmode,
05547   operand1,
05548   operand2),
05549   operand1,
05550   const1_rtx));
05551 }
05552 
05553 /* ../../gcc/gcc/config/i386/i386.md:20636 */
05554 rtx
05555 gen_mulv2df3 (operand0, operand1, operand2)
05556      rtx operand0;
05557      rtx operand1;
05558      rtx operand2;
05559 {
05560   return gen_rtx_SET (VOIDmode,
05561   operand0,
05562   gen_rtx_MULT (V2DFmode,
05563   operand1,
05564   operand2));
05565 }
05566 
05567 /* ../../gcc/gcc/config/i386/i386.md:20645 */
05568 rtx
05569 gen_vmmulv2df3 (operand0, operand1, operand2)
05570      rtx operand0;
05571      rtx operand1;
05572      rtx operand2;
05573 {
05574   return gen_rtx_SET (VOIDmode,
05575   operand0,
05576   gen_rtx_VEC_MERGE (V2DFmode,
05577   gen_rtx_MULT (V2DFmode,
05578   operand1,
05579   operand2),
05580   operand1,
05581   const1_rtx));
05582 }
05583 
05584 /* ../../gcc/gcc/config/i386/i386.md:20656 */
05585 rtx
05586 gen_divv2df3 (operand0, operand1, operand2)
05587      rtx operand0;
05588      rtx operand1;
05589      rtx operand2;
05590 {
05591   return gen_rtx_SET (VOIDmode,
05592   operand0,
05593   gen_rtx_DIV (V2DFmode,
05594   operand1,
05595   operand2));
05596 }
05597 
05598 /* ../../gcc/gcc/config/i386/i386.md:20665 */
05599 rtx
05600 gen_vmdivv2df3 (operand0, operand1, operand2)
05601      rtx operand0;
05602      rtx operand1;
05603      rtx operand2;
05604 {
05605   return gen_rtx_SET (VOIDmode,
05606   operand0,
05607   gen_rtx_VEC_MERGE (V2DFmode,
05608   gen_rtx_DIV (V2DFmode,
05609   operand1,
05610   operand2),
05611   operand1,
05612   const1_rtx));
05613 }
05614 
05615 /* ../../gcc/gcc/config/i386/i386.md:20678 */
05616 rtx
05617 gen_smaxv2df3 (operand0, operand1, operand2)
05618      rtx operand0;
05619      rtx operand1;
05620      rtx operand2;
05621 {
05622   return gen_rtx_SET (VOIDmode,
05623   operand0,
05624   gen_rtx_SMAX (V2DFmode,
05625   operand1,
05626   operand2));
05627 }
05628 
05629 /* ../../gcc/gcc/config/i386/i386.md:20687 */
05630 rtx
05631 gen_vmsmaxv2df3 (operand0, operand1, operand2)
05632      rtx operand0;
05633      rtx operand1;
05634      rtx operand2;
05635 {
05636   return gen_rtx_SET (VOIDmode,
05637   operand0,
05638   gen_rtx_VEC_MERGE (V2DFmode,
05639   gen_rtx_SMAX (V2DFmode,
05640   operand1,
05641   operand2),
05642   operand1,
05643   const1_rtx));
05644 }
05645 
05646 /* ../../gcc/gcc/config/i386/i386.md:20698 */
05647 rtx
05648 gen_sminv2df3 (operand0, operand1, operand2)
05649      rtx operand0;
05650      rtx operand1;
05651      rtx operand2;
05652 {
05653   return gen_rtx_SET (VOIDmode,
05654   operand0,
05655   gen_rtx_SMIN (V2DFmode,
05656   operand1,
05657   operand2));
05658 }
05659 
05660 /* ../../gcc/gcc/config/i386/i386.md:20707 */
05661 rtx
05662 gen_vmsminv2df3 (operand0, operand1, operand2)
05663      rtx operand0;
05664      rtx operand1;
05665      rtx operand2;
05666 {
05667   return gen_rtx_SET (VOIDmode,
05668   operand0,
05669   gen_rtx_VEC_MERGE (V2DFmode,
05670   gen_rtx_SMIN (V2DFmode,
05671   operand1,
05672   operand2),
05673   operand1,
05674   const1_rtx));
05675 }
05676 
05677 /* ../../gcc/gcc/config/i386/i386.md:20720 */
05678 rtx
05679 gen_sqrtv2df2 (operand0, operand1)
05680      rtx operand0;
05681      rtx operand1;
05682 {
05683   return gen_rtx_SET (VOIDmode,
05684   operand0,
05685   gen_rtx_SQRT (V2DFmode,
05686   operand1));
05687 }
05688 
05689 /* ../../gcc/gcc/config/i386/i386.md:20728 */
05690 rtx
05691 gen_vmsqrtv2df2 (operand0, operand1, operand2)
05692      rtx operand0;
05693      rtx operand1;
05694      rtx operand2;
05695 {
05696   return gen_rtx_SET (VOIDmode,
05697   operand0,
05698   gen_rtx_VEC_MERGE (V2DFmode,
05699   gen_rtx_SQRT (V2DFmode,
05700   operand1),
05701   operand2,
05702   const1_rtx));
05703 }
05704 
05705 /* ../../gcc/gcc/config/i386/i386.md:20740 */
05706 rtx
05707 gen_maskcmpv2df3 (operand0, operand1, operand2, operand3)
05708      rtx operand0;
05709      rtx operand1;
05710      rtx operand2;
05711      rtx operand3;
05712 {
05713   return gen_rtx_SET (VOIDmode,
05714   operand0,
05715   gen_rtx (GET_CODE (operand3), V2DImode,
05716     operand1,
05717     operand2));
05718 }
05719 
05720 /* ../../gcc/gcc/config/i386/i386.md:20750 */
05721 rtx
05722 gen_maskncmpv2df3 (operand0, operand1, operand2, operand3)
05723      rtx operand0;
05724      rtx operand1;
05725      rtx operand2;
05726      rtx operand3;
05727 {
05728   return gen_rtx_SET (VOIDmode,
05729   operand0,
05730   gen_rtx_NOT (V2DImode,
05731   gen_rtx (GET_CODE (operand3), V2DImode,
05732     operand1,
05733     operand2)));
05734 }
05735 
05736 /* ../../gcc/gcc/config/i386/i386.md:20766 */
05737 rtx
05738 gen_vmmaskcmpv2df3 (operand0, operand1, operand2, operand3)
05739      rtx operand0;
05740      rtx operand1;
05741      rtx operand2;
05742      rtx operand3;
05743 {
05744   return gen_rtx_SET (VOIDmode,
05745   operand0,
05746   gen_rtx_VEC_MERGE (V2DImode,
05747   gen_rtx (GET_CODE (operand3), V2DImode,
05748     operand1,
05749     operand2),
05750   gen_rtx_SUBREG (V2DImode,
05751   operand1,
05752   0),
05753   const1_rtx));
05754 }
05755 
05756 /* ../../gcc/gcc/config/i386/i386.md:20779 */
05757 rtx
05758 gen_vmmaskncmpv2df3 (operand0, operand1, operand2, operand3)
05759      rtx operand0;
05760      rtx operand1;
05761      rtx operand2;
05762      rtx operand3;
05763 {
05764   return gen_rtx_SET (VOIDmode,
05765   operand0,
05766   gen_rtx_VEC_MERGE (V2DImode,
05767   gen_rtx_NOT (V2DImode,
05768   gen_rtx (GET_CODE (operand3), V2DImode,
05769     operand1,
05770     operand2)),
05771   gen_rtx_SUBREG (V2DImode,
05772   operand1,
05773   0),
05774   const1_rtx));
05775 }
05776 
05777 /* ../../gcc/gcc/config/i386/i386.md:20798 */
05778 rtx
05779 gen_sse2_comi (operand0, operand1)
05780      rtx operand0;
05781      rtx operand1;
05782 {
05783   return gen_rtx_SET (VOIDmode,
05784   gen_rtx_REG (CCFPmode,
05785   17),
05786   gen_rtx_COMPARE (CCFPmode,
05787   gen_rtx_VEC_SELECT (DFmode,
05788   operand0,
05789   gen_rtx_PARALLEL (VOIDmode,
05790   gen_rtvec (1,
05791     const0_rtx))),
05792   gen_rtx_VEC_SELECT (DFmode,
05793   operand1,
05794   gen_rtx_PARALLEL (VOIDmode,
05795   gen_rtvec (1,
05796     const0_rtx)))));
05797 }
05798 
05799 /* ../../gcc/gcc/config/i386/i386.md:20811 */
05800 rtx
05801 gen_sse2_ucomi (operand0, operand1)
05802      rtx operand0;
05803      rtx operand1;
05804 {
05805   return gen_rtx_SET (VOIDmode,
05806   gen_rtx_REG (CCFPUmode,
05807   17),
05808   gen_rtx_COMPARE (CCFPUmode,
05809   gen_rtx_VEC_SELECT (DFmode,
05810   operand0,
05811   gen_rtx_PARALLEL (VOIDmode,
05812   gen_rtvec (1,
05813     const0_rtx))),
05814   gen_rtx_VEC_SELECT (DFmode,
05815   operand1,
05816   gen_rtx_PARALLEL (VOIDmode,
05817   gen_rtvec (1,
05818     const0_rtx)))));
05819 }
05820 
05821 /* ../../gcc/gcc/config/i386/i386.md:20826 */
05822 rtx
05823 gen_sse2_movmskpd (operand0, operand1)
05824      rtx operand0;
05825      rtx operand1;
05826 {
05827   return gen_rtx_SET (VOIDmode,
05828   operand0,
05829   gen_rtx_UNSPEC (SImode,
05830   gen_rtvec (1,
05831     operand1),
05832   33));
05833 }
05834 
05835 /* ../../gcc/gcc/config/i386/i386.md:20835 */
05836 rtx
05837 gen_sse2_pmovmskb (operand0, operand1)
05838      rtx operand0;
05839      rtx operand1;
05840 {
05841   return gen_rtx_SET (VOIDmode,
05842   operand0,
05843   gen_rtx_UNSPEC (SImode,
05844   gen_rtvec (1,
05845     operand1),
05846   33));
05847 }
05848 
05849 /* ../../gcc/gcc/config/i386/i386.md:20844 */
05850 rtx
05851 gen_sse2_maskmovdqu (operand0, operand1, operand2)
05852      rtx operand0;
05853      rtx operand1;
05854      rtx operand2;
05855 {
05856   return gen_rtx_SET (VOIDmode,
05857   gen_rtx_MEM (V16QImode,
05858   operand0),
05859   gen_rtx_UNSPEC (V16QImode,
05860   gen_rtvec (2,
05861     operand1,
05862     operand2),
05863   32));
05864 }
05865 
05866 /* ../../gcc/gcc/config/i386/i386.md:20855 */
05867 rtx
05868 gen_sse2_maskmovdqu_rex64 (operand0, operand1, operand2)
05869      rtx operand0;
05870      rtx operand1;
05871      rtx operand2;
05872 {
05873   return gen_rtx_SET (VOIDmode,
05874   gen_rtx_MEM (V16QImode,
05875   operand0),
05876   gen_rtx_UNSPEC (V16QImode,
05877   gen_rtvec (2,
05878     operand1,
05879     operand2),
05880   32));
05881 }
05882 
05883 /* ../../gcc/gcc/config/i386/i386.md:20866 */
05884 rtx
05885 gen_sse2_movntv2df (operand0, operand1)
05886      rtx operand0;
05887      rtx operand1;
05888 {
05889   return gen_rtx_SET (VOIDmode,
05890   operand0,
05891   gen_rtx_UNSPEC (V2DFmode,
05892   gen_rtvec (1,
05893     operand1),
05894   34));
05895 }
05896 
05897 /* ../../gcc/gcc/config/i386/i386.md:20875 */
05898 rtx
05899 gen_sse2_movntv2di (operand0, operand1)
05900      rtx operand0;
05901      rtx operand1;
05902 {
05903   return gen_rtx_SET (VOIDmode,
05904   operand0,
05905   gen_rtx_UNSPEC (V2DImode,
05906   gen_rtvec (1,
05907     operand1),
05908   34));
05909 }
05910 
05911 /* ../../gcc/gcc/config/i386/i386.md:20884 */
05912 rtx
05913 gen_sse2_movntsi (operand0, operand1)
05914      rtx operand0;
05915      rtx operand1;
05916 {
05917   return gen_rtx_SET (VOIDmode,
05918   operand0,
05919   gen_rtx_UNSPEC (SImode,
05920   gen_rtvec (1,
05921     operand1),
05922   34));
05923 }
05924 
05925 /* ../../gcc/gcc/config/i386/i386.md:20897 */
05926 rtx
05927 gen_cvtdq2ps (operand0, operand1)
05928      rtx operand0;
05929      rtx operand1;
05930 {
05931   return gen_rtx_SET (VOIDmode,
05932   operand0,
05933   gen_rtx_FLOAT (V4SFmode,
05934   operand1));
05935 }
05936 
05937 /* ../../gcc/gcc/config/i386/i386.md:20905 */
05938 rtx
05939 gen_cvtps2dq (operand0, operand1)
05940      rtx operand0;
05941      rtx operand1;
05942 {
05943   return gen_rtx_SET (VOIDmode,
05944   operand0,
05945   gen_rtx_FIX (V4SImode,
05946   operand1));
05947 }
05948 
05949 /* ../../gcc/gcc/config/i386/i386.md:20913 */
05950 rtx
05951 gen_cvttps2dq (operand0, operand1)
05952      rtx operand0;
05953      rtx operand1;
05954 {
05955   return gen_rtx_SET (VOIDmode,
05956   operand0,
05957   gen_rtx_UNSPEC (V4SImode,
05958   gen_rtvec (1,
05959     operand1),
05960   30));
05961 }
05962 
05963 /* ../../gcc/gcc/config/i386/i386.md:20924 */
05964 rtx
05965 gen_cvtdq2pd (operand0, operand1)
05966      rtx operand0;
05967      rtx operand1;
05968 {
05969   return gen_rtx_SET (VOIDmode,
05970   operand0,
05971   gen_rtx_FLOAT (V2DFmode,
05972   gen_rtx_VEC_SELECT (V2SImode,
05973   operand1,
05974   gen_rtx_PARALLEL (VOIDmode,
05975   gen_rtvec (2,
05976     const0_rtx,
05977     const1_rtx)))));
05978 }
05979 
05980 /* ../../gcc/gcc/config/i386/i386.md:20936 */
05981 rtx
05982 gen_cvtpd2dq (operand0, operand1)
05983      rtx operand0;
05984      rtx operand1;
05985 {
05986   return gen_rtx_SET (VOIDmode,
05987   operand0,
05988   gen_rtx_VEC_CONCAT (V4SImode,
05989   gen_rtx_FIX (V2SImode,
05990   operand1),
05991   gen_rtx_CONST_VECTOR (V2SImode,
05992   gen_rtvec (2,
05993     const0_rtx,
05994     const0_rtx))));
05995 }
05996 
05997 /* ../../gcc/gcc/config/i386/i386.md:20946 */
05998 rtx
05999 gen_cvttpd2dq (operand0, operand1)
06000      rtx operand0;
06001      rtx operand1;
06002 {
06003   return gen_rtx_SET (VOIDmode,
06004   operand0,
06005   gen_rtx_VEC_CONCAT (V4SImode,
06006   gen_rtx_UNSPEC (V2SImode,
06007   gen_rtvec (1,
06008     operand1),
06009   30),
06010   gen_rtx_CONST_VECTOR (V2SImode,
06011   gen_rtvec (2,
06012     const0_rtx,
06013     const0_rtx))));
06014 }
06015 
06016 /* ../../gcc/gcc/config/i386/i386.md:20957 */
06017 rtx
06018 gen_cvtpd2pi (operand0, operand1)
06019      rtx operand0;
06020      rtx operand1;
06021 {
06022   return gen_rtx_SET (VOIDmode,
06023   operand0,
06024   gen_rtx_FIX (V2SImode,
06025   operand1));
06026 }
06027 
06028 /* ../../gcc/gcc/config/i386/i386.md:20965 */
06029 rtx
06030 gen_cvttpd2pi (operand0, operand1)
06031      rtx operand0;
06032      rtx operand1;
06033 {
06034   return gen_rtx_SET (VOIDmode,
06035   operand0,
06036   gen_rtx_UNSPEC (V2SImode,
06037   gen_rtvec (1,
06038     operand1),
06039   30));
06040 }
06041 
06042 /* ../../gcc/gcc/config/i386/i386.md:20974 */
06043 rtx
06044 gen_cvtpi2pd (operand0, operand1)
06045      rtx operand0;
06046      rtx operand1;
06047 {
06048   return gen_rtx_SET (VOIDmode,
06049   operand0,
06050   gen_rtx_FLOAT (V2DFmode,
06051   operand1));
06052 }
06053 
06054 /* ../../gcc/gcc/config/i386/i386.md:20984 */
06055 rtx
06056 gen_cvtsd2si (operand0, operand1)
06057      rtx operand0;
06058      rtx operand1;
06059 {
06060   return gen_rtx_SET (VOIDmode,
06061   operand0,
06062   gen_rtx_FIX (SImode,
06063   gen_rtx_VEC_SELECT (DFmode,
06064   operand1,
06065   gen_rtx_PARALLEL (VOIDmode,
06066   gen_rtvec (1,
06067     const0_rtx)))));
06068 }
06069 
06070 /* ../../gcc/gcc/config/i386/i386.md:20993 */
06071 rtx
06072 gen_cvtsd2siq (operand0, operand1)
06073      rtx operand0;
06074      rtx operand1;
06075 {
06076   return gen_rtx_SET (VOIDmode,
06077   operand0,
06078   gen_rtx_FIX (DImode,
06079   gen_rtx_VEC_SELECT (DFmode,
06080   operand1,
06081   gen_rtx_PARALLEL (VOIDmode,
06082   gen_rtvec (1,
06083     const0_rtx)))));
06084 }
06085 
06086 /* ../../gcc/gcc/config/i386/i386.md:21002 */
06087 rtx
06088 gen_cvttsd2si (operand0, operand1)
06089      rtx operand0;
06090      rtx operand1;
06091 {
06092   return gen_rtx_SET (VOIDmode,
06093   operand0,
06094   gen_rtx_UNSPEC (SImode,
06095   gen_rtvec (1,
06096     gen_rtx_VEC_SELECT (DFmode,
06097   operand1,
06098   gen_rtx_PARALLEL (VOIDmode,
06099   gen_rtvec (1,
06100     const0_rtx)))),
06101   30));
06102 }
06103 
06104 /* ../../gcc/gcc/config/i386/i386.md:21011 */
06105 rtx
06106 gen_cvttsd2siq (operand0, operand1)
06107      rtx operand0;
06108      rtx operand1;
06109 {
06110   return gen_rtx_SET (VOIDmode,
06111   operand0,
06112   gen_rtx_UNSPEC (DImode,
06113   gen_rtvec (1,
06114     gen_rtx_VEC_SELECT (DFmode,
06115   operand1,
06116   gen_rtx_PARALLEL (VOIDmode,
06117   gen_rtvec (1,
06118     const0_rtx)))),
06119   30));
06120 }
06121 
06122 /* ../../gcc/gcc/config/i386/i386.md:21021 */
06123 rtx
06124 gen_cvtsi2sd (operand0, operand1, operand2)
06125      rtx operand0;
06126      rtx operand1;
06127      rtx operand2;
06128 {
06129   return gen_rtx_SET (VOIDmode,
06130   operand0,
06131   gen_rtx_VEC_MERGE (V2DFmode,
06132   operand1,
06133   gen_rtx_VEC_DUPLICATE (V2DFmode,
06134   gen_rtx_FLOAT (DFmode,
06135   operand2)),
06136   GEN_INT (2LL)));
06137 }
06138 
06139 /* ../../gcc/gcc/config/i386/i386.md:21033 */
06140 rtx
06141 gen_cvtsi2sdq (operand0, operand1, operand2)
06142      rtx operand0;
06143      rtx operand1;
06144      rtx operand2;
06145 {
06146   return gen_rtx_SET (VOIDmode,
06147   operand0,
06148   gen_rtx_VEC_MERGE (V2DFmode,
06149   operand1,
06150   gen_rtx_VEC_DUPLICATE (V2DFmode,
06151   gen_rtx_FLOAT (DFmode,
06152   operand2)),
06153   GEN_INT (2LL)));
06154 }
06155 
06156 /* ../../gcc/gcc/config/i386/i386.md:21048 */
06157 rtx
06158 gen_cvtsd2ss (operand0, operand1, operand2)
06159      rtx operand0;
06160      rtx operand1;
06161      rtx operand2;
06162 {
06163   return gen_rtx_SET (VOIDmode,
06164   operand0,
06165   gen_rtx_VEC_MERGE (V4SFmode,
06166   operand1,
06167   gen_rtx_VEC_DUPLICATE (V4SFmode,
06168   gen_rtx_FLOAT_TRUNCATE (V2SFmode,
06169   operand2)),
06170   GEN_INT (14LL)));
06171 }
06172 
06173 /* ../../gcc/gcc/config/i386/i386.md:21060 */
06174 rtx
06175 gen_cvtss2sd (operand0, operand1, operand2)
06176      rtx operand0;
06177      rtx operand1;
06178      rtx operand2;
06179 {
06180   return gen_rtx_SET (VOIDmode,
06181   operand0,
06182   gen_rtx_VEC_MERGE (V2DFmode,
06183   operand1,
06184   gen_rtx_FLOAT_EXTEND (V2DFmode,
06185   gen_rtx_VEC_SELECT (V2SFmode,
06186   operand2,
06187   gen_rtx_PARALLEL (VOIDmode,
06188   gen_rtvec (2,
06189     const0_rtx,
06190     const1_rtx)))),
06191   GEN_INT (2LL)));
06192 }
06193 
06194 /* ../../gcc/gcc/config/i386/i386.md:21074 */
06195 rtx
06196 gen_cvtpd2ps (operand0, operand1)
06197      rtx operand0;
06198      rtx operand1;
06199 {
06200   return gen_rtx_SET (VOIDmode,
06201   operand0,
06202   gen_rtx_SUBREG (V4SFmode,
06203   gen_rtx_VEC_CONCAT (V4SImode,
06204   gen_rtx_SUBREG (V2SImode,
06205   gen_rtx_FLOAT_TRUNCATE (V2SFmode,
06206   operand1),
06207   0),
06208   gen_rtx_CONST_VECTOR (V2SImode,
06209   gen_rtvec (2,
06210     const0_rtx,
06211     const0_rtx))),
06212   0));
06213 }
06214 
06215 /* ../../gcc/gcc/config/i386/i386.md:21086 */
06216 rtx
06217 gen_cvtps2pd (operand0, operand1)
06218      rtx operand0;
06219      rtx operand1;
06220 {
06221   return gen_rtx_SET (VOIDmode,
06222   operand0,
06223   gen_rtx_FLOAT_EXTEND (V2DFmode,
06224   gen_rtx_VEC_SELECT (V2SFmode,
06225   operand1,
06226   gen_rtx_PARALLEL (VOIDmode,
06227   gen_rtvec (2,
06228     const0_rtx,
06229     const1_rtx)))));
06230 }
06231 
06232 /* ../../gcc/gcc/config/i386/i386.md:21101 */
06233 rtx
06234 gen_addv16qi3 (operand0, operand1, operand2)
06235      rtx operand0;
06236      rtx operand1;
06237      rtx operand2;
06238 {
06239   return gen_rtx_SET (VOIDmode,
06240   operand0,
06241   gen_rtx_PLUS (V16QImode,
06242   operand1,
06243   operand2));
06244 }
06245 
06246 /* ../../gcc/gcc/config/i386/i386.md:21110 */
06247 rtx
06248 gen_addv8hi3 (operand0, operand1, operand2)
06249      rtx operand0;
06250      rtx operand1;
06251      rtx operand2;
06252 {
06253   return gen_rtx_SET (VOIDmode,
06254   operand0,
06255   gen_rtx_PLUS (V8HImode,
06256   operand1,
06257   operand2));
06258 }
06259 
06260 /* ../../gcc/gcc/config/i386/i386.md:21119 */
06261 rtx
06262 gen_addv4si3 (operand0, operand1, operand2)
06263      rtx operand0;
06264      rtx operand1;
06265      rtx operand2;
06266 {
06267   return gen_rtx_SET (VOIDmode,
06268   operand0,
06269   gen_rtx_PLUS (V4SImode,
06270   operand1,
06271   operand2));
06272 }
06273 
06274 /* ../../gcc/gcc/config/i386/i386.md:21128 */
06275 rtx
06276 gen_addv2di3 (operand0, operand1, operand2)
06277      rtx operand0;
06278      rtx operand1;
06279      rtx operand2;
06280 {
06281   return gen_rtx_SET (VOIDmode,
06282   operand0,
06283   gen_rtx_PLUS (V2DImode,
06284   operand1,
06285   operand2));
06286 }
06287 
06288 /* ../../gcc/gcc/config/i386/i386.md:21137 */
06289 rtx
06290 gen_ssaddv16qi3 (operand0, operand1, operand2)
06291      rtx operand0;
06292      rtx operand1;
06293      rtx operand2;
06294 {
06295   return gen_rtx_SET (VOIDmode,
06296   operand0,
06297   gen_rtx_SS_PLUS (V16QImode,
06298   operand1,
06299   operand2));
06300 }
06301 
06302 /* ../../gcc/gcc/config/i386/i386.md:21146 */
06303 rtx
06304 gen_ssaddv8hi3 (operand0, operand1, operand2)
06305      rtx operand0;
06306      rtx operand1;
06307      rtx operand2;
06308 {
06309   return gen_rtx_SET (VOIDmode,
06310   operand0,
06311   gen_rtx_SS_PLUS (V8HImode,
06312   operand1,
06313   operand2));
06314 }
06315 
06316 /* ../../gcc/gcc/config/i386/i386.md:21155 */
06317 rtx
06318 gen_usaddv16qi3 (operand0, operand1, operand2)
06319      rtx operand0;
06320      rtx operand1;
06321      rtx operand2;
06322 {
06323   return gen_rtx_SET (VOIDmode,
06324   operand0,
06325   gen_rtx_US_PLUS (V16QImode,
06326   operand1,
06327   operand2));
06328 }
06329 
06330 /* ../../gcc/gcc/config/i386/i386.md:21164 */
06331 rtx
06332 gen_usaddv8hi3 (operand0, operand1, operand2)
06333      rtx operand0;
06334      rtx operand1;
06335      rtx operand2;
06336 {
06337   return gen_rtx_SET (VOIDmode,
06338   operand0,
06339   gen_rtx_US_PLUS (V8HImode,
06340   operand1,
06341   operand2));
06342 }
06343 
06344 /* ../../gcc/gcc/config/i386/i386.md:21173 */
06345 rtx
06346 gen_subv16qi3 (operand0, operand1, operand2)
06347      rtx operand0;
06348      rtx operand1;
06349      rtx operand2;
06350 {
06351   return gen_rtx_SET (VOIDmode,
06352   operand0,
06353   gen_rtx_MINUS (V16QImode,
06354   operand1,
06355   operand2));
06356 }
06357 
06358 /* ../../gcc/gcc/config/i386/i386.md:21182 */
06359 rtx
06360 gen_subv8hi3 (operand0, operand1, operand2)
06361      rtx operand0;
06362      rtx operand1;
06363      rtx operand2;
06364 {
06365   return gen_rtx_SET (VOIDmode,
06366   operand0,
06367   gen_rtx_MINUS (V8HImode,
06368   operand1,
06369   operand2));
06370 }
06371 
06372 /* ../../gcc/gcc/config/i386/i386.md:21191 */
06373 rtx
06374 gen_subv4si3 (operand0, operand1, operand2)
06375      rtx operand0;
06376      rtx operand1;
06377      rtx operand2;
06378 {
06379   return gen_rtx_SET (VOIDmode,
06380   operand0,
06381   gen_rtx_MINUS (V4SImode,
06382   operand1,
06383   operand2));
06384 }
06385 
06386 /* ../../gcc/gcc/config/i386/i386.md:21200 */
06387 rtx
06388 gen_subv2di3 (operand0, operand1, operand2)
06389      rtx operand0;
06390      rtx operand1;
06391      rtx operand2;
06392 {
06393   return gen_rtx_SET (VOIDmode,
06394   operand0,
06395   gen_rtx_MINUS (V2DImode,
06396   operand1,
06397   operand2));
06398 }
06399 
06400 /* ../../gcc/gcc/config/i386/i386.md:21209 */
06401 rtx
06402 gen_sssubv16qi3 (operand0, operand1, operand2)
06403      rtx operand0;
06404      rtx operand1;
06405      rtx operand2;
06406 {
06407   return gen_rtx_SET (VOIDmode,
06408   operand0,
06409   gen_rtx_SS_MINUS (V16QImode,
06410   operand1,
06411   operand2));
06412 }
06413 
06414 /* ../../gcc/gcc/config/i386/i386.md:21218 */
06415 rtx
06416 gen_sssubv8hi3 (operand0, operand1, operand2)
06417      rtx operand0;
06418      rtx operand1;
06419      rtx operand2;
06420 {
06421   return gen_rtx_SET (VOIDmode,
06422   operand0,
06423   gen_rtx_SS_MINUS (V8HImode,
06424   operand1,
06425   operand2));
06426 }
06427 
06428 /* ../../gcc/gcc/config/i386/i386.md:21227 */
06429 rtx
06430 gen_ussubv16qi3 (operand0, operand1, operand2)
06431      rtx operand0;
06432      rtx operand1;
06433      rtx operand2;
06434 {
06435   return gen_rtx_SET (VOIDmode,
06436   operand0,
06437   gen_rtx_US_MINUS (V16QImode,
06438   operand1,
06439   operand2));
06440 }
06441 
06442 /* ../../gcc/gcc/config/i386/i386.md:21236 */
06443 rtx
06444 gen_ussubv8hi3 (operand0, operand1, operand2)
06445      rtx operand0;
06446      rtx operand1;
06447      rtx operand2;
06448 {
06449   return gen_rtx_SET (VOIDmode,
06450   operand0,
06451   gen_rtx_US_MINUS (V8HImode,
06452   operand1,
06453   operand2));
06454 }
06455 
06456 /* ../../gcc/gcc/config/i386/i386.md:21245 */
06457 rtx
06458 gen_mulv8hi3 (operand0, operand1, operand2)
06459      rtx operand0;
06460      rtx operand1;
06461      rtx operand2;
06462 {
06463   return gen_rtx_SET (VOIDmode,
06464   operand0,
06465   gen_rtx_MULT (V8HImode,
06466   operand1,
06467   operand2));
06468 }
06469 
06470 /* ../../gcc/gcc/config/i386/i386.md:21254 */
06471 rtx
06472 gen_smulv8hi3_highpart (operand0, operand1, operand2)
06473      rtx operand0;
06474      rtx operand1;
06475      rtx operand2;
06476 {
06477   return gen_rtx_SET (VOIDmode,
06478   operand0,
06479   gen_rtx_TRUNCATE (V8HImode,
06480   gen_rtx_LSHIFTRT (V8SImode,
06481   gen_rtx_MULT (V8SImode,
06482   gen_rtx_SIGN_EXTEND (V8SImode,
06483   operand1),
06484   gen_rtx_SIGN_EXTEND (V8SImode,
06485   operand2)),
06486   GEN_INT (16LL))));
06487 }
06488 
06489 /* ../../gcc/gcc/config/i386/i386.md:21266 */
06490 rtx
06491 gen_umulv8hi3_highpart (operand0, operand1, operand2)
06492      rtx operand0;
06493      rtx operand1;
06494      rtx operand2;
06495 {
06496   return gen_rtx_SET (VOIDmode,
06497   operand0,
06498   gen_rtx_TRUNCATE (V8HImode,
06499   gen_rtx_LSHIFTRT (V8SImode,
06500   gen_rtx_MULT (V8SImode,
06501   gen_rtx_ZERO_EXTEND (V8SImode,
06502   operand1),
06503   gen_rtx_ZERO_EXTEND (V8SImode,
06504   operand2)),
06505   GEN_INT (16LL))));
06506 }
06507 
06508 /* ../../gcc/gcc/config/i386/i386.md:21278 */
06509 rtx
06510 gen_sse2_umulsidi3 (operand0, operand1, operand2)
06511      rtx operand0;
06512      rtx operand1;
06513      rtx operand2;
06514 {
06515   return gen_rtx_SET (VOIDmode,
06516   operand0,
06517   gen_rtx_MULT (DImode,
06518   gen_rtx_ZERO_EXTEND (DImode,
06519   gen_rtx_VEC_SELECT (SImode,
06520   operand1,
06521   gen_rtx_PARALLEL (VOIDmode,
06522   gen_rtvec (1,
06523     const0_rtx)))),
06524   gen_rtx_ZERO_EXTEND (DImode,
06525   gen_rtx_VEC_SELECT (SImode,
06526   operand2,
06527   gen_rtx_PARALLEL (VOIDmode,
06528   gen_rtvec (1,
06529     const0_rtx))))));
06530 }
06531 
06532 /* ../../gcc/gcc/config/i386/i386.md:21291 */
06533 rtx
06534 gen_sse2_umulv2siv2di3 (operand0, operand1, operand2)
06535      rtx operand0;
06536      rtx operand1;
06537      rtx operand2;
06538 {
06539   return gen_rtx_SET (VOIDmode,
06540   operand0,
06541   gen_rtx_MULT (V2DImode,
06542   gen_rtx_ZERO_EXTEND (V2DImode,
06543   gen_rtx_VEC_SELECT (V2SImode,
06544   operand1,
06545   gen_rtx_PARALLEL (VOIDmode,
06546   gen_rtvec (2,
06547     const0_rtx,
06548     GEN_INT (2LL))))),
06549   gen_rtx_ZERO_EXTEND (V2DImode,
06550   gen_rtx_VEC_SELECT (V2SImode,
06551   operand2,
06552   gen_rtx_PARALLEL (VOIDmode,
06553   gen_rtvec (2,
06554     const0_rtx,
06555     GEN_INT (2LL)))))));
06556 }
06557 
06558 /* ../../gcc/gcc/config/i386/i386.md:21306 */
06559 rtx
06560 gen_sse2_pmaddwd (operand0, operand1, operand2)
06561      rtx operand0;
06562      rtx operand1;
06563      rtx operand2;
06564 {
06565   return gen_rtx_SET (VOIDmode,
06566   operand0,
06567   gen_rtx_PLUS (V4SImode,
06568   gen_rtx_MULT (V4SImode,
06569   gen_rtx_SIGN_EXTEND (V4SImode,
06570   gen_rtx_VEC_SELECT (V4HImode,
06571   operand1,
06572   gen_rtx_PARALLEL (VOIDmode,
06573   gen_rtvec (4,
06574     const0_rtx,
06575     GEN_INT (2LL),
06576     GEN_INT (4LL),
06577     GEN_INT (6LL))))),
06578   gen_rtx_SIGN_EXTEND (V4SImode,
06579   gen_rtx_VEC_SELECT (V4HImode,
06580   operand2,
06581   gen_rtx_PARALLEL (VOIDmode,
06582   gen_rtvec (4,
06583     const0_rtx,
06584     GEN_INT (2LL),
06585     GEN_INT (4LL),
06586     GEN_INT (6LL)))))),
06587   gen_rtx_MULT (V4SImode,
06588   gen_rtx_SIGN_EXTEND (V4SImode,
06589   gen_rtx_VEC_SELECT (V4HImode,
06590   operand1,
06591   gen_rtx_PARALLEL (VOIDmode,
06592   gen_rtvec (4,
06593     const1_rtx,
06594     GEN_INT (3LL),
06595     GEN_INT (5LL),
06596     GEN_INT (7LL))))),
06597   gen_rtx_SIGN_EXTEND (V4SImode,
06598   gen_rtx_VEC_SELECT (V4HImode,
06599   operand2,
06600   gen_rtx_PARALLEL (VOIDmode,
06601   gen_rtvec (4,
06602     const1_rtx,
06603     GEN_INT (3LL),
06604     GEN_INT (5LL),
06605     GEN_INT (7LL))))))));
06606 }
06607 
06608 /* ../../gcc/gcc/config/i386/i386.md:21338 */
06609 rtx
06610 gen_sse2_clrti (operand0)
06611      rtx operand0;
06612 {
06613   return gen_rtx_SET (VOIDmode,
06614   operand0,
06615   const0_rtx);
06616 }
06617 
06618 /* ../../gcc/gcc/config/i386/i386.md:21348 */
06619 rtx
06620 gen_sse2_uavgv16qi3 (operand0, operand1, operand2)
06621      rtx operand0;
06622      rtx operand1;
06623      rtx operand2;
06624 {
06625   return gen_rtx_SET (VOIDmode,
06626   operand0,
06627   gen_rtx_ASHIFTRT (V16QImode,
06628   gen_rtx_PLUS (V16QImode,
06629   gen_rtx_PLUS (V16QImode,
06630   operand1,
06631   operand2),
06632   gen_rtx_CONST_VECTOR (V16QImode,
06633   gen_rtvec (16,
06634     const1_rtx,
06635     const1_rtx,
06636     const1_rtx,
06637     const1_rtx,
06638     const1_rtx,
06639     const1_rtx,
06640     const1_rtx,
06641     const1_rtx,
06642     const1_rtx,
06643     const1_rtx,
06644     const1_rtx,
06645     const1_rtx,
06646     const1_rtx,
06647     const1_rtx,
06648     const1_rtx,
06649     const1_rtx))),
06650   const1_rtx));
06651 }
06652 
06653 /* ../../gcc/gcc/config/i386/i386.md:21368 */
06654 rtx
06655 gen_sse2_uavgv8hi3 (operand0, operand1, operand2)
06656      rtx operand0;
06657      rtx operand1;
06658      rtx operand2;
06659 {
06660   return gen_rtx_SET (VOIDmode,
06661   operand0,
06662   gen_rtx_ASHIFTRT (V8HImode,
06663   gen_rtx_PLUS (V8HImode,
06664   gen_rtx_PLUS (V8HImode,
06665   operand1,
06666   operand2),
06667   gen_rtx_CONST_VECTOR (V8HImode,
06668   gen_rtvec (8,
06669     const1_rtx,
06670     const1_rtx,
06671     const1_rtx,
06672     const1_rtx,
06673     const1_rtx,
06674     const1_rtx,
06675     const1_rtx,
06676     const1_rtx))),
06677   const1_rtx));
06678 }
06679 
06680 /* ../../gcc/gcc/config/i386/i386.md:21385 */
06681 rtx
06682 gen_sse2_psadbw (operand0, operand1, operand2)
06683      rtx operand0;
06684      rtx operand1;
06685      rtx operand2;
06686 {
06687   return gen_rtx_SET (VOIDmode,
06688   operand0,
06689   gen_rtx_UNSPEC (V2DImode,
06690   gen_rtvec (2,
06691     operand1,
06692     operand2),
06693   61));
06694 }
06695 
06696 /* ../../gcc/gcc/config/i386/i386.md:21398 */
06697 rtx
06698 gen_sse2_pinsrw (operand0, operand1, operand2, operand3)
06699      rtx operand0;
06700      rtx operand1;
06701      rtx operand2;
06702      rtx operand3;
06703 {
06704   return gen_rtx_SET (VOIDmode,
06705   operand0,
06706   gen_rtx_VEC_MERGE (V8HImode,
06707   operand1,
06708   gen_rtx_VEC_DUPLICATE (V8HImode,
06709   gen_rtx_TRUNCATE (HImode,
06710   operand2)),
06711   operand3));
06712 }
06713 
06714 /* ../../gcc/gcc/config/i386/i386.md:21410 */
06715 rtx
06716 gen_sse2_pextrw (operand0, operand1, operand2)
06717      rtx operand0;
06718      rtx operand1;
06719      rtx operand2;
06720 {
06721   return gen_rtx_SET (VOIDmode,
06722   operand0,
06723   gen_rtx_ZERO_EXTEND (SImode,
06724   gen_rtx_VEC_SELECT (HImode,
06725   operand1,
06726   gen_rtx_PARALLEL (VOIDmode,
06727   gen_rtvec (1,
06728     operand2)))));
06729 }
06730 
06731 /* ../../gcc/gcc/config/i386/i386.md:21421 */
06732 rtx
06733 gen_sse2_pshufd (operand0, operand1, operand2)
06734      rtx operand0;
06735      rtx operand1;
06736      rtx operand2;
06737 {
06738   return gen_rtx_SET (VOIDmode,
06739   operand0,
06740   gen_rtx_UNSPEC (V4SImode,
06741   gen_rtvec (2,
06742     operand1,
06743     operand2),
06744   41));
06745 }
06746 
06747 /* ../../gcc/gcc/config/i386/i386.md:21431 */
06748 rtx
06749 gen_sse2_pshuflw (operand0, operand1, operand2)
06750      rtx operand0;
06751      rtx operand1;
06752      rtx operand2;
06753 {
06754   return gen_rtx_SET (VOIDmode,
06755   operand0,
06756   gen_rtx_UNSPEC (V8HImode,
06757   gen_rtvec (2,
06758     operand1,
06759     operand2),
06760   55));
06761 }
06762 
06763 /* ../../gcc/gcc/config/i386/i386.md:21441 */
06764 rtx
06765 gen_sse2_pshufhw (operand0, operand1, operand2)
06766      rtx operand0;
06767      rtx operand1;
06768      rtx operand2;
06769 {
06770   return gen_rtx_SET (VOIDmode,
06771   operand0,
06772   gen_rtx_UNSPEC (V8HImode,
06773   gen_rtvec (2,
06774     operand1,
06775     operand2),
06776   56));
06777 }
06778 
06779 /* ../../gcc/gcc/config/i386/i386.md:21453 */
06780 rtx
06781 gen_eqv16qi3 (operand0, operand1, operand2)
06782      rtx operand0;
06783      rtx operand1;
06784      rtx operand2;
06785 {
06786   return gen_rtx_SET (VOIDmode,
06787   operand0,
06788   gen_rtx_EQ (V16QImode,
06789   operand1,
06790   operand2));
06791 }
06792 
06793 /* ../../gcc/gcc/config/i386/i386.md:21462 */
06794 rtx
06795 gen_eqv8hi3 (operand0, operand1, operand2)
06796      rtx operand0;
06797      rtx operand1;
06798      rtx operand2;
06799 {
06800   return gen_rtx_SET (VOIDmode,
06801   operand0,
06802   gen_rtx_EQ (V8HImode,
06803   operand1,
06804   operand2));
06805 }
06806 
06807 /* ../../gcc/gcc/config/i386/i386.md:21471 */
06808 rtx
06809 gen_eqv4si3 (operand0, operand1, operand2)
06810      rtx operand0;
06811      rtx operand1;
06812      rtx operand2;
06813 {
06814   return gen_rtx_SET (VOIDmode,
06815   operand0,
06816   gen_rtx_EQ (V4SImode,
06817   operand1,
06818   operand2));
06819 }
06820 
06821 /* ../../gcc/gcc/config/i386/i386.md:21480 */
06822 rtx
06823 gen_gtv16qi3 (operand0, operand1, operand2)
06824      rtx operand0;
06825      rtx operand1;
06826      rtx operand2;
06827 {
06828   return gen_rtx_SET (VOIDmode,
06829   operand0,
06830   gen_rtx_GT (V16QImode,
06831   operand1,
06832   operand2));
06833 }
06834 
06835 /* ../../gcc/gcc/config/i386/i386.md:21489 */
06836 rtx
06837 gen_gtv8hi3 (operand0, operand1, operand2)
06838      rtx operand0;
06839      rtx operand1;
06840      rtx operand2;
06841 {
06842   return gen_rtx_SET (VOIDmode,
06843   operand0,
06844   gen_rtx_GT (V8HImode,
06845   operand1,
06846   operand2));
06847 }
06848 
06849 /* ../../gcc/gcc/config/i386/i386.md:21498 */
06850 rtx
06851 gen_gtv4si3 (operand0, operand1, operand2)
06852      rtx operand0;
06853      rtx operand1;
06854      rtx operand2;
06855 {
06856   return gen_rtx_SET (VOIDmode,
06857   operand0,
06858   gen_rtx_GT (V4SImode,
06859   operand1,
06860   operand2));
06861 }
06862 
06863 /* ../../gcc/gcc/config/i386/i386.md:21510 */
06864 rtx
06865 gen_umaxv16qi3 (operand0, operand1, operand2)
06866      rtx operand0;
06867      rtx operand1;
06868      rtx operand2;
06869 {
06870   return gen_rtx_SET (VOIDmode,
06871   operand0,
06872   gen_rtx_UMAX (V16QImode,
06873   operand1,
06874   operand2));
06875 }
06876 
06877 /* ../../gcc/gcc/config/i386/i386.md:21519 */
06878 rtx
06879 gen_smaxv8hi3 (operand0, operand1, operand2)
06880      rtx operand0;
06881      rtx operand1;
06882      rtx operand2;
06883 {
06884   return gen_rtx_SET (VOIDmode,
06885   operand0,
06886   gen_rtx_SMAX (V8HImode,
06887   operand1,
06888   operand2));
06889 }
06890 
06891 /* ../../gcc/gcc/config/i386/i386.md:21528 */
06892 rtx
06893 gen_uminv16qi3 (operand0, operand1, operand2)
06894      rtx operand0;
06895      rtx operand1;
06896      rtx operand2;
06897 {
06898   return gen_rtx_SET (VOIDmode,
06899   operand0,
06900   gen_rtx_UMIN (V16QImode,
06901   operand1,
06902   operand2));
06903 }
06904 
06905 /* ../../gcc/gcc/config/i386/i386.md:21537 */
06906 rtx
06907 gen_sminv8hi3 (operand0, operand1, operand2)
06908      rtx operand0;
06909      rtx operand1;
06910      rtx operand2;
06911 {
06912   return gen_rtx_SET (VOIDmode,
06913   operand0,
06914   gen_rtx_SMIN (V8HImode,
06915   operand1,
06916   operand2));
06917 }
06918 
06919 /* ../../gcc/gcc/config/i386/i386.md:21549 */
06920 rtx
06921 gen_ashrv8hi3 (operand0, operand1, operand2)
06922      rtx operand0;
06923      rtx operand1;
06924      rtx operand2;
06925 {
06926   return gen_rtx_SET (VOIDmode,
06927   operand0,
06928   gen_rtx_ASHIFTRT (V8HImode,
06929   operand1,
06930   operand2));
06931 }
06932 
06933 /* ../../gcc/gcc/config/i386/i386.md:21558 */
06934 rtx
06935 gen_ashrv4si3 (operand0, operand1, operand2)
06936      rtx operand0;
06937      rtx operand1;
06938      rtx operand2;
06939 {
06940   return gen_rtx_SET (VOIDmode,
06941   operand0,
06942   gen_rtx_ASHIFTRT (V4SImode,
06943   operand1,
06944   operand2));
06945 }
06946 
06947 /* ../../gcc/gcc/config/i386/i386.md:21567 */
06948 rtx
06949 gen_lshrv8hi3 (operand0, operand1, operand2)
06950      rtx operand0;
06951      rtx operand1;
06952      rtx operand2;
06953 {
06954   return gen_rtx_SET (VOIDmode,
06955   operand0,
06956   gen_rtx_LSHIFTRT (V8HImode,
06957   operand1,
06958   operand2));
06959 }
06960 
06961 /* ../../gcc/gcc/config/i386/i386.md:21576 */
06962 rtx
06963 gen_lshrv4si3 (operand0, operand1, operand2)
06964      rtx operand0;
06965      rtx operand1;
06966      rtx operand2;
06967 {
06968   return gen_rtx_SET (VOIDmode,
06969   operand0,
06970   gen_rtx_LSHIFTRT (V4SImode,
06971   operand1,
06972   operand2));
06973 }
06974 
06975 /* ../../gcc/gcc/config/i386/i386.md:21585 */
06976 rtx
06977 gen_lshrv2di3 (operand0, operand1, operand2)
06978      rtx operand0;
06979      rtx operand1;
06980      rtx operand2;
06981 {
06982   return gen_rtx_SET (VOIDmode,
06983   operand0,
06984   gen_rtx_LSHIFTRT (V2DImode,
06985   operand1,
06986   operand2));
06987 }
06988 
06989 /* ../../gcc/gcc/config/i386/i386.md:21594 */
06990 rtx
06991 gen_ashlv8hi3 (operand0, operand1, operand2)
06992      rtx operand0;
06993      rtx operand1;
06994      rtx operand2;
06995 {
06996   return gen_rtx_SET (VOIDmode,
06997   operand0,
06998   gen_rtx_ASHIFT (V8HImode,
06999   operand1,
07000   operand2));
07001 }
07002 
07003 /* ../../gcc/gcc/config/i386/i386.md:21603 */
07004 rtx
07005 gen_ashlv4si3 (operand0, operand1, operand2)
07006      rtx operand0;
07007      rtx operand1;
07008      rtx operand2;
07009 {
07010   return gen_rtx_SET (VOIDmode,
07011   operand0,
07012   gen_rtx_ASHIFT (V4SImode,
07013   operand1,
07014   operand2));
07015 }
07016 
07017 /* ../../gcc/gcc/config/i386/i386.md:21612 */
07018 rtx
07019 gen_ashlv2di3 (operand0, operand1, operand2)
07020      rtx operand0;
07021      rtx operand1;
07022      rtx operand2;
07023 {
07024   return gen_rtx_SET (VOIDmode,
07025   operand0,
07026   gen_rtx_ASHIFT (V2DImode,
07027   operand1,
07028   operand2));
07029 }
07030 
07031 /* ../../gcc/gcc/config/i386/i386.md:21621 */
07032 rtx
07033 gen_ashrv8hi3_ti (operand0, operand1, operand2)
07034      rtx operand0;
07035      rtx operand1;
07036      rtx operand2;
07037 {
07038   return gen_rtx_SET (VOIDmode,
07039   operand0,
07040   gen_rtx_ASHIFTRT (V8HImode,
07041   operand1,
07042   gen_rtx_SUBREG (TImode,
07043   operand2,
07044   0)));
07045 }
07046 
07047 /* ../../gcc/gcc/config/i386/i386.md:21630 */
07048 rtx
07049 gen_ashrv4si3_ti (operand0, operand1, operand2)
07050      rtx operand0;
07051      rtx operand1;
07052      rtx operand2;
07053 {
07054   return gen_rtx_SET (VOIDmode,
07055   operand0,
07056   gen_rtx_ASHIFTRT (V4SImode,
07057   operand1,
07058   gen_rtx_SUBREG (TImode,
07059   operand2,
07060   0)));
07061 }
07062 
07063 /* ../../gcc/gcc/config/i386/i386.md:21639 */
07064 rtx
07065 gen_lshrv8hi3_ti (operand0, operand1, operand2)
07066      rtx operand0;
07067      rtx operand1;
07068      rtx operand2;
07069 {
07070   return gen_rtx_SET (VOIDmode,
07071   operand0,
07072   gen_rtx_LSHIFTRT (V8HImode,
07073   operand1,
07074   gen_rtx_SUBREG (TImode,
07075   operand2,
07076   0)));
07077 }
07078 
07079 /* ../../gcc/gcc/config/i386/i386.md:21648 */
07080 rtx
07081 gen_lshrv4si3_ti (operand0, operand1, operand2)
07082      rtx operand0;
07083      rtx operand1;
07084      rtx operand2;
07085 {
07086   return gen_rtx_SET (VOIDmode,
07087   operand0,
07088   gen_rtx_LSHIFTRT (V4SImode,
07089   operand1,
07090   gen_rtx_SUBREG (TImode,
07091   operand2,
07092   0)));
07093 }
07094 
07095 /* ../../gcc/gcc/config/i386/i386.md:21657 */
07096 rtx
07097 gen_lshrv2di3_ti (operand0, operand1, operand2)
07098      rtx operand0;
07099      rtx operand1;
07100      rtx operand2;
07101 {
07102   return gen_rtx_SET (VOIDmode,
07103   operand0,
07104   gen_rtx_LSHIFTRT (V2DImode,
07105   operand1,
07106   gen_rtx_SUBREG (TImode,
07107   operand2,
07108   0)));
07109 }
07110 
07111 /* ../../gcc/gcc/config/i386/i386.md:21666 */
07112 rtx
07113 gen_ashlv8hi3_ti (operand0, operand1, operand2)
07114      rtx operand0;
07115      rtx operand1;
07116      rtx operand2;
07117 {
07118   return gen_rtx_SET (VOIDmode,
07119   operand0,
07120   gen_rtx_ASHIFT (V8HImode,
07121   operand1,
07122   gen_rtx_SUBREG (TImode,
07123   operand2,
07124   0)));
07125 }
07126 
07127 /* ../../gcc/gcc/config/i386/i386.md:21675 */
07128 rtx
07129 gen_ashlv4si3_ti (operand0, operand1, operand2)
07130      rtx operand0;
07131      rtx operand1;
07132      rtx operand2;
07133 {
07134   return gen_rtx_SET (VOIDmode,
07135   operand0,
07136   gen_rtx_ASHIFT (V4SImode,
07137   operand1,
07138   gen_rtx_SUBREG (TImode,
07139   operand2,
07140   0)));
07141 }
07142 
07143 /* ../../gcc/gcc/config/i386/i386.md:21684 */
07144 rtx
07145 gen_ashlv2di3_ti (operand0, operand1, operand2)
07146      rtx operand0;
07147      rtx operand1;
07148      rtx operand2;
07149 {
07150   return gen_rtx_SET (VOIDmode,
07151   operand0,
07152   gen_rtx_ASHIFT (V2DImode,
07153   operand1,
07154   gen_rtx_SUBREG (TImode,
07155   operand2,
07156   0)));
07157 }
07158 
07159 /* ../../gcc/gcc/config/i386/i386.md:21697 */
07160 rtx
07161 gen_sse2_ashlti3 (operand0, operand1, operand2)
07162      rtx operand0;
07163      rtx operand1;
07164      rtx operand2;
07165 {
07166   return gen_rtx_SET (VOIDmode,
07167   operand0,
07168   gen_rtx_UNSPEC (TImode,
07169   gen_rtvec (1,
07170     gen_rtx_ASHIFT (TImode,
07171   operand1,
07172   gen_rtx_MULT (SImode,
07173   operand2,
07174   GEN_INT (8LL)))),
07175   45));
07176 }
07177 
07178 /* ../../gcc/gcc/config/i386/i386.md:21708 */
07179 rtx
07180 gen_sse2_lshrti3 (operand0, operand1, operand2)
07181      rtx operand0;
07182      rtx operand1;
07183      rtx operand2;
07184 {
07185   return gen_rtx_SET (VOIDmode,
07186   operand0,
07187   gen_rtx_UNSPEC (TImode,
07188   gen_rtvec (1,
07189     gen_rtx_LSHIFTRT (TImode,
07190   operand1,
07191   gen_rtx_MULT (SImode,
07192   operand2,
07193   GEN_INT (8LL)))),
07194   45));
07195 }
07196 
07197 /* ../../gcc/gcc/config/i386/i386.md:21721 */
07198 rtx
07199 gen_sse2_unpckhpd (operand0, operand1, operand2)
07200      rtx operand0;
07201      rtx operand1;
07202      rtx operand2;
07203 {
07204   return gen_rtx_SET (VOIDmode,
07205   operand0,
07206   gen_rtx_VEC_CONCAT (V2DFmode,
07207   gen_rtx_VEC_SELECT (V2DFmode,
07208   operand1,
07209   gen_rtx_PARALLEL (VOIDmode,
07210   gen_rtvec (1,
07211     const1_rtx))),
07212   gen_rtx_VEC_SELECT (V2DFmode,
07213   operand2,
07214   gen_rtx_PARALLEL (VOIDmode,
07215   gen_rtvec (1,
07216     const0_rtx)))));
07217 }
07218 
07219 /* ../../gcc/gcc/config/i386/i386.md:21733 */
07220 rtx
07221 gen_sse2_unpcklpd (operand0, operand1, operand2)
07222      rtx operand0;
07223      rtx operand1;
07224      rtx operand2;
07225 {
07226   return gen_rtx_SET (VOIDmode,
07227   operand0,
07228   gen_rtx_VEC_CONCAT (V2DFmode,
07229   gen_rtx_VEC_SELECT (V2DFmode,
07230   operand1,
07231   gen_rtx_PARALLEL (VOIDmode,
07232   gen_rtvec (1,
07233     const0_rtx))),
07234   gen_rtx_VEC_SELECT (V2DFmode,
07235   operand2,
07236   gen_rtx_PARALLEL (VOIDmode,
07237   gen_rtvec (1,
07238     const1_rtx)))));
07239 }
07240 
07241 /* ../../gcc/gcc/config/i386/i386.md:21747 */
07242 rtx
07243 gen_sse2_packsswb (operand0, operand1, operand2)
07244      rtx operand0;
07245      rtx operand1;
07246      rtx operand2;
07247 {
07248   return gen_rtx_SET (VOIDmode,
07249   operand0,
07250   gen_rtx_VEC_CONCAT (V16QImode,
07251   gen_rtx_SS_TRUNCATE (V8QImode,
07252   operand1),
07253   gen_rtx_SS_TRUNCATE (V8QImode,
07254   operand2)));
07255 }
07256 
07257 /* ../../gcc/gcc/config/i386/i386.md:21757 */
07258 rtx
07259 gen_sse2_packssdw (operand0, operand1, operand2)
07260      rtx operand0;
07261      rtx operand1;
07262      rtx operand2;
07263 {
07264   return gen_rtx_SET (VOIDmode,
07265   operand0,
07266   gen_rtx_VEC_CONCAT (V8HImode,
07267   gen_rtx_SS_TRUNCATE (V4HImode,
07268   operand1),
07269   gen_rtx_SS_TRUNCATE (V4HImode,
07270   operand2)));
07271 }
07272 
07273 /* ../../gcc/gcc/config/i386/i386.md:21767 */
07274 rtx
07275 gen_sse2_packuswb (operand0, operand1, operand2)
07276      rtx operand0;
07277      rtx operand1;
07278      rtx operand2;
07279 {
07280   return gen_rtx_SET (VOIDmode,
07281   operand0,
07282   gen_rtx_VEC_CONCAT (V16QImode,
07283   gen_rtx_US_TRUNCATE (V8QImode,
07284   operand1),
07285   gen_rtx_US_TRUNCATE (V8QImode,
07286   operand2)));
07287 }
07288 
07289 /* ../../gcc/gcc/config/i386/i386.md:21777 */
07290 rtx
07291 gen_sse2_punpckhbw (operand0, operand1, operand2)
07292      rtx operand0;
07293      rtx operand1;
07294      rtx operand2;
07295 {
07296   return gen_rtx_SET (VOIDmode,
07297   operand0,
07298   gen_rtx_VEC_MERGE (V16QImode,
07299   gen_rtx_VEC_SELECT (V16QImode,
07300   operand1,
07301   gen_rtx_PARALLEL (VOIDmode,
07302   gen_rtvec (16,
07303     GEN_INT (8LL),
07304     const0_rtx,
07305     GEN_INT (9LL),
07306     const1_rtx,
07307     GEN_INT (10LL),
07308     GEN_INT (2LL),
07309     GEN_INT (11LL),
07310     GEN_INT (3LL),
07311     GEN_INT (12LL),
07312     GEN_INT (4LL),
07313     GEN_INT (13LL),
07314     GEN_INT (5LL),
07315     GEN_INT (14LL),
07316     GEN_INT (6LL),
07317     GEN_INT (15LL),
07318     GEN_INT (7LL)))),
07319   gen_rtx_VEC_SELECT (V16QImode,
07320   operand2,
07321   gen_rtx_PARALLEL (VOIDmode,
07322   gen_rtvec (16,
07323     const0_rtx,
07324     GEN_INT (8LL),
07325     const1_rtx,
07326     GEN_INT (9LL),
07327     GEN_INT (2LL),
07328     GEN_INT (10LL),
07329     GEN_INT (3LL),
07330     GEN_INT (11LL),
07331     GEN_INT (4LL),
07332     GEN_INT (12LL),
07333     GEN_INT (5LL),
07334     GEN_INT (13LL),
07335     GEN_INT (6LL),
07336     GEN_INT (14LL),
07337     GEN_INT (7LL),
07338     GEN_INT (15LL)))),
07339   GEN_INT (21845LL)));
07340 }
07341 
07342 /* ../../gcc/gcc/config/i386/i386.md:21804 */
07343 rtx
07344 gen_sse2_punpckhwd (operand0, operand1, operand2)
07345      rtx operand0;
07346      rtx operand1;
07347      rtx operand2;
07348 {
07349   return gen_rtx_SET (VOIDmode,
07350   operand0,
07351   gen_rtx_VEC_MERGE (V8HImode,
07352   gen_rtx_VEC_SELECT (V8HImode,
07353   operand1,
07354   gen_rtx_PARALLEL (VOIDmode,
07355   gen_rtvec (8,
07356     GEN_INT (4LL),
07357     const0_rtx,
07358     GEN_INT (5LL),
07359     const1_rtx,
07360     GEN_INT (6LL),
07361     GEN_INT (2LL),
07362     GEN_INT (7LL),
07363     GEN_INT (3LL)))),
07364   gen_rtx_VEC_SELECT (V8HImode,
07365   operand2,
07366   gen_rtx_PARALLEL (VOIDmode,
07367   gen_rtvec (8,
07368     const0_rtx,
07369     GEN_INT (4LL),
07370     const1_rtx,
07371     GEN_INT (5LL),
07372     GEN_INT (2LL),
07373     GEN_INT (6LL),
07374     GEN_INT (3LL),
07375     GEN_INT (7LL)))),
07376   GEN_INT (85LL)));
07377 }
07378 
07379 /* ../../gcc/gcc/config/i386/i386.md:21823 */
07380 rtx
07381 gen_sse2_punpckhdq (operand0, operand1, operand2)
07382      rtx operand0;
07383      rtx operand1;
07384      rtx operand2;
07385 {
07386   return gen_rtx_SET (VOIDmode,
07387   operand0,
07388   gen_rtx_VEC_MERGE (V4SImode,
07389   gen_rtx_VEC_SELECT (V4SImode,
07390   operand1,
07391   gen_rtx_PARALLEL (VOIDmode,
07392   gen_rtvec (4,
07393     GEN_INT (2LL),
07394     const0_rtx,
07395     GEN_INT (3LL),
07396     const1_rtx))),
07397   gen_rtx_VEC_SELECT (V4SImode,
07398   operand2,
07399   gen_rtx_PARALLEL (VOIDmode,
07400   gen_rtvec (4,
07401     const0_rtx,
07402     GEN_INT (2LL),
07403     const1_rtx,
07404     GEN_INT (3LL)))),
07405   GEN_INT (5LL)));
07406 }
07407 
07408 /* ../../gcc/gcc/config/i386/i386.md:21838 */
07409 rtx
07410 gen_sse2_punpcklbw (operand0, operand1, operand2)
07411      rtx operand0;
07412      rtx operand1;
07413      rtx operand2;
07414 {
07415   return gen_rtx_SET (VOIDmode,
07416   operand0,
07417   gen_rtx_VEC_MERGE (V16QImode,
07418   gen_rtx_VEC_SELECT (V16QImode,
07419   operand1,
07420   gen_rtx_PARALLEL (VOIDmode,
07421   gen_rtvec (16,
07422     const0_rtx,
07423     GEN_INT (8LL),
07424     const1_rtx,
07425     GEN_INT (9LL),
07426     GEN_INT (2LL),
07427     GEN_INT (10LL),
07428     GEN_INT (3LL),
07429     GEN_INT (11LL),
07430     GEN_INT (4LL),
07431     GEN_INT (12LL),
07432     GEN_INT (5LL),
07433     GEN_INT (13LL),
07434     GEN_INT (6LL),
07435     GEN_INT (14LL),
07436     GEN_INT (7LL),
07437     GEN_INT (15LL)))),
07438   gen_rtx_VEC_SELECT (V16QImode,
07439   operand2,
07440   gen_rtx_PARALLEL (VOIDmode,
07441   gen_rtvec (16,
07442     GEN_INT (8LL),
07443     const0_rtx,
07444     GEN_INT (9LL),
07445     const1_rtx,
07446     GEN_INT (10LL),
07447     GEN_INT (2LL),
07448     GEN_INT (11LL),
07449     GEN_INT (3LL),
07450     GEN_INT (12LL),
07451     GEN_INT (4LL),
07452     GEN_INT (13LL),
07453     GEN_INT (5LL),
07454     GEN_INT (14LL),
07455     GEN_INT (6LL),
07456     GEN_INT (15LL),
07457     GEN_INT (7LL)))),
07458   GEN_INT (21845LL)));
07459 }
07460 
07461 /* ../../gcc/gcc/config/i386/i386.md:21865 */
07462 rtx
07463 gen_sse2_punpcklwd (operand0, operand1, operand2)
07464      rtx operand0;
07465      rtx operand1;
07466      rtx operand2;
07467 {
07468   return gen_rtx_SET (VOIDmode,
07469   operand0,
07470   gen_rtx_VEC_MERGE (V8HImode,
07471   gen_rtx_VEC_SELECT (V8HImode,
07472   operand1,
07473   gen_rtx_PARALLEL (VOIDmode,
07474   gen_rtvec (8,
07475     const0_rtx,
07476     GEN_INT (4LL),
07477     const1_rtx,
07478     GEN_INT (5LL),
07479     GEN_INT (2LL),
07480     GEN_INT (6LL),
07481     GEN_INT (3LL),
07482     GEN_INT (7LL)))),
07483   gen_rtx_VEC_SELECT (V8HImode,
07484   operand2,
07485   gen_rtx_PARALLEL (VOIDmode,
07486   gen_rtvec (8,
07487     GEN_INT (4LL),
07488     const0_rtx,
07489     GEN_INT (5LL),
07490     const1_rtx,
07491     GEN_INT (6LL),
07492     GEN_INT (2LL),
07493     GEN_INT (7LL),
07494     GEN_INT (3LL)))),
07495   GEN_INT (85LL)));
07496 }
07497 
07498 /* ../../gcc/gcc/config/i386/i386.md:21884 */
07499 rtx
07500 gen_sse2_punpckldq (operand0, operand1, operand2)
07501      rtx operand0;
07502      rtx operand1;
07503      rtx operand2;
07504 {
07505   return gen_rtx_SET (VOIDmode,
07506   operand0,
07507   gen_rtx_VEC_MERGE (V4SImode,
07508   gen_rtx_VEC_SELECT (V4SImode,
07509   operand1,
07510   gen_rtx_PARALLEL (VOIDmode,
07511   gen_rtvec (4,
07512     const0_rtx,
07513     GEN_INT (2LL),
07514     const1_rtx,
07515     GEN_INT (3LL)))),
07516   gen_rtx_VEC_SELECT (V4SImode,
07517   operand2,
07518   gen_rtx_PARALLEL (VOIDmode,
07519   gen_rtvec (4,
07520     GEN_INT (2LL),
07521     const0_rtx,
07522     GEN_INT (3LL),
07523     const1_rtx))),
07524   GEN_INT (5LL)));
07525 }
07526 
07527 /* ../../gcc/gcc/config/i386/i386.md:21899 */
07528 rtx
07529 gen_sse2_punpcklqdq (operand0, operand1, operand2)
07530      rtx operand0;
07531      rtx operand1;
07532      rtx operand2;
07533 {
07534   return gen_rtx_SET (VOIDmode,
07535   operand0,
07536   gen_rtx_VEC_MERGE (V2DImode,
07537   gen_rtx_VEC_SELECT (V2DImode,
07538   operand2,
07539   gen_rtx_PARALLEL (VOIDmode,
07540   gen_rtvec (2,
07541     const1_rtx,
07542     const0_rtx))),
07543   operand1,
07544   const1_rtx));
07545 }
07546 
07547 /* ../../gcc/gcc/config/i386/i386.md:21912 */
07548 rtx
07549 gen_sse2_punpckhqdq (operand0, operand1, operand2)
07550      rtx operand0;
07551      rtx operand1;
07552      rtx operand2;
07553 {
07554   return gen_rtx_SET (VOIDmode,
07555   operand0,
07556   gen_rtx_VEC_MERGE (V2DImode,
07557   operand1,
07558   gen_rtx_VEC_SELECT (V2DImode,
07559   operand2,
07560   gen_rtx_PARALLEL (VOIDmode,
07561   gen_rtvec (2,
07562     const1_rtx,
07563     const0_rtx))),
07564   const1_rtx));
07565 }
07566 
07567 /* ../../gcc/gcc/config/i386/i386.md:21927 */
07568 rtx
07569 gen_sse2_movapd (operand0, operand1)
07570      rtx operand0;
07571      rtx operand1;
07572 {
07573   return gen_rtx_SET (VOIDmode,
07574   operand0,
07575   gen_rtx_UNSPEC (V2DFmode,
07576   gen_rtvec (1,
07577     operand1),
07578   38));
07579 }
07580 
07581 /* ../../gcc/gcc/config/i386/i386.md:21937 */
07582 rtx
07583 gen_sse2_movupd (operand0, operand1)
07584      rtx operand0;
07585      rtx operand1;
07586 {
07587   return gen_rtx_SET (VOIDmode,
07588   operand0,
07589   gen_rtx_UNSPEC (V2DFmode,
07590   gen_rtvec (1,
07591     operand1),
07592   39));
07593 }
07594 
07595 /* ../../gcc/gcc/config/i386/i386.md:21947 */
07596 rtx
07597 gen_sse2_movdqa (operand0, operand1)
07598      rtx operand0;
07599      rtx operand1;
07600 {
07601   return gen_rtx_SET (VOIDmode,
07602   operand0,
07603   gen_rtx_UNSPEC (V16QImode,
07604   gen_rtvec (1,
07605     operand1),
07606   38));
07607 }
07608 
07609 /* ../../gcc/gcc/config/i386/i386.md:21957 */
07610 rtx
07611 gen_sse2_movdqu (operand0, operand1)
07612      rtx operand0;
07613      rtx operand1;
07614 {
07615   return gen_rtx_SET (VOIDmode,
07616   operand0,
07617   gen_rtx_UNSPEC (V16QImode,
07618   gen_rtvec (1,
07619     operand1),
07620   39));
07621 }
07622 
07623 /* ../../gcc/gcc/config/i386/i386.md:21967 */
07624 rtx
07625 gen_sse2_movdq2q (operand0, operand1)
07626      rtx operand0;
07627      rtx operand1;
07628 {
07629   return gen_rtx_SET (VOIDmode,
07630   operand0,
07631   gen_rtx_VEC_SELECT (DImode,
07632   operand1,
07633   gen_rtx_PARALLEL (VOIDmode,
07634   gen_rtvec (1,
07635     const0_rtx))));
07636 }
07637 
07638 /* ../../gcc/gcc/config/i386/i386.md:21978 */
07639 rtx
07640 gen_sse2_movdq2q_rex64 (operand0, operand1)
07641      rtx operand0;
07642      rtx operand1;
07643 {
07644   return gen_rtx_SET (VOIDmode,
07645   operand0,
07646   gen_rtx_VEC_SELECT (DImode,
07647   operand1,
07648   gen_rtx_PARALLEL (VOIDmode,
07649   gen_rtvec (1,
07650     const0_rtx))));
07651 }
07652 
07653 /* ../../gcc/gcc/config/i386/i386.md:21990 */
07654 rtx
07655 gen_sse2_movq2dq (operand0, operand1)
07656      rtx operand0;
07657      rtx operand1;
07658 {
07659   return gen_rtx_SET (VOIDmode,
07660   operand0,
07661   gen_rtx_VEC_CONCAT (V2DImode,
07662   operand1,
07663   const0_rtx));
07664 }
07665 
07666 /* ../../gcc/gcc/config/i386/i386.md:22001 */
07667 rtx
07668 gen_sse2_movq2dq_rex64 (operand0, operand1)
07669      rtx operand0;
07670      rtx operand1;
07671 {
07672   return gen_rtx_SET (VOIDmode,
07673   operand0,
07674   gen_rtx_VEC_CONCAT (V2DImode,
07675   operand1,
07676   const0_rtx));
07677 }
07678 
07679 /* ../../gcc/gcc/config/i386/i386.md:22013 */
07680 rtx
07681 gen_sse2_movq (operand0, operand1)
07682      rtx operand0;
07683      rtx operand1;
07684 {
07685   return gen_rtx_SET (VOIDmode,
07686   operand0,
07687   gen_rtx_VEC_CONCAT (V2DImode,
07688   gen_rtx_VEC_SELECT (DImode,
07689   operand1,
07690   gen_rtx_PARALLEL (VOIDmode,
07691   gen_rtvec (1,
07692     const0_rtx))),
07693   const0_rtx));
07694 }
07695 
07696 /* ../../gcc/gcc/config/i386/i386.md:22024 */
07697 rtx
07698 gen_sse2_loadd (operand0, operand1)
07699      rtx operand0;
07700      rtx operand1;
07701 {
07702   return gen_rtx_SET (VOIDmode,
07703   operand0,
07704   gen_rtx_VEC_MERGE (V4SImode,
07705   gen_rtx_VEC_DUPLICATE (V4SImode,
07706   operand1),
07707   gen_rtx_CONST_VECTOR (V4SImode,
07708   gen_rtvec (4,
07709     const0_rtx,
07710     const0_rtx,
07711     const0_rtx,
07712     const0_rtx)),
07713   const1_rtx));
07714 }
07715 
07716 /* ../../gcc/gcc/config/i386/i386.md:22038 */
07717 rtx
07718 gen_sse2_stored (operand0, operand1)
07719      rtx operand0;
07720      rtx operand1;
07721 {
07722   return gen_rtx_SET (VOIDmode,
07723   operand0,
07724   gen_rtx_VEC_SELECT (SImode,
07725   operand1,
07726   gen_rtx_PARALLEL (VOIDmode,
07727   gen_rtvec (1,
07728     const0_rtx))));
07729 }
07730 
07731 /* ../../gcc/gcc/config/i386/i386.md:22048 */
07732 rtx
07733 gen_sse2_movhpd (operand0, operand1, operand2)
07734      rtx operand0;
07735      rtx operand1;
07736      rtx operand2;
07737 {
07738   return gen_rtx_SET (VOIDmode,
07739   operand0,
07740   gen_rtx_VEC_MERGE (V2DFmode,
07741   operand1,
07742   operand2,
07743   GEN_INT (2LL)));
07744 }
07745 
07746 /* ../../gcc/gcc/config/i386/i386.md:22059 */
07747 rtx
07748 gen_sse2_movlpd (operand0, operand1, operand2)
07749      rtx operand0;
07750      rtx operand1;
07751      rtx operand2;
07752 {
07753   return gen_rtx_SET (VOIDmode,
07754   operand0,
07755   gen_rtx_VEC_MERGE (V2DFmode,
07756   operand1,
07757   operand2,
07758   const1_rtx));
07759 }
07760 
07761 /* ../../gcc/gcc/config/i386/i386.md:22080 */
07762 rtx
07763 gen_sse2_loadsd_1 (operand0, operand1, operand2)
07764      rtx operand0;
07765      rtx operand1;
07766      rtx operand2;
07767 {
07768   return gen_rtx_SET (VOIDmode,
07769   operand0,
07770   gen_rtx_VEC_MERGE (V2DFmode,
07771   gen_rtx_VEC_DUPLICATE (V2DFmode,
07772   operand1),
07773   operand2,
07774   const1_rtx));
07775 }
07776 
07777 /* ../../gcc/gcc/config/i386/i386.md:22091 */
07778 rtx
07779 gen_sse2_movsd (operand0, operand1, operand2)
07780      rtx operand0;
07781      rtx operand1;
07782      rtx operand2;
07783 {
07784   return gen_rtx_SET (VOIDmode,
07785   operand0,
07786   gen_rtx_VEC_MERGE (V2DFmode,
07787   operand1,
07788   operand2,
07789   const1_rtx));
07790 }
07791 
07792 /* ../../gcc/gcc/config/i386/i386.md:22102 */
07793 rtx
07794 gen_sse2_storesd (operand0, operand1)
07795      rtx operand0;
07796      rtx operand1;
07797 {
07798   return gen_rtx_SET (VOIDmode,
07799   operand0,
07800   gen_rtx_VEC_SELECT (DFmode,
07801   operand1,
07802   gen_rtx_PARALLEL (VOIDmode,
07803   gen_rtvec (1,
07804     const0_rtx))));
07805 }
07806 
07807 /* ../../gcc/gcc/config/i386/i386.md:22112 */
07808 rtx
07809 gen_sse2_shufpd (operand0, operand1, operand2, operand3)
07810      rtx operand0;
07811      rtx operand1;
07812      rtx operand2;
07813      rtx operand3;
07814 {
07815   return gen_rtx_SET (VOIDmode,
07816   operand0,
07817   gen_rtx_UNSPEC (V2DFmode,
07818   gen_rtvec (3,
07819     operand1,
07820     operand2,
07821     operand3),
07822   41));
07823 }
07824 
07825 /* ../../gcc/gcc/config/i386/i386.md:22124 */
07826 rtx
07827 gen_sse2_clflush (operand0)
07828      rtx operand0;
07829 {
07830   return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
07831   gen_rtvec (1,
07832     operand0),
07833   57);
07834 }
07835 
07836 /* ../../gcc/gcc/config/i386/i386.md:22168 */
07837 rtx
07838 gen_mwait (operand0, operand1)
07839      rtx operand0;
07840      rtx operand1;
07841 {
07842   return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
07843   gen_rtvec (2,
07844     operand0,
07845     operand1),
07846   70);
07847 }
07848 
07849 /* ../../gcc/gcc/config/i386/i386.md:22176 */
07850 rtx
07851 gen_monitor (operand0, operand1, operand2)
07852      rtx operand0;
07853      rtx operand1;
07854      rtx operand2;
07855 {
07856   return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
07857   gen_rtvec (3,
07858     operand0,
07859     operand1,
07860     operand2),
07861   69);
07862 }
07863 
07864 /* ../../gcc/gcc/config/i386/i386.md:22187 */
07865 rtx
07866 gen_addsubv4sf3 (operand0, operand1, operand2)
07867      rtx operand0;
07868      rtx operand1;
07869      rtx operand2;
07870 {
07871   return gen_rtx_SET (VOIDmode,
07872   operand0,
07873   gen_rtx_UNSPEC (V4SFmode,
07874   gen_rtvec (2,
07875     operand1,
07876     operand2),
07877   71));
07878 }
07879 
07880 /* ../../gcc/gcc/config/i386/i386.md:22197 */
07881 rtx
07882 gen_addsubv2df3 (operand0, operand1, operand2)
07883      rtx operand0;
07884      rtx operand1;
07885      rtx operand2;
07886 {
07887   return gen_rtx_SET (VOIDmode,
07888   operand0,
07889   gen_rtx_UNSPEC (V2DFmode,
07890   gen_rtvec (2,
07891     operand1,
07892     operand2),
07893   71));
07894 }
07895 
07896 /* ../../gcc/gcc/config/i386/i386.md:22207 */
07897 rtx
07898 gen_haddv4sf3 (operand0, operand1, operand2)
07899      rtx operand0;
07900      rtx operand1;
07901      rtx operand2;
07902 {
07903   return gen_rtx_SET (VOIDmode,
07904   operand0,
07905   gen_rtx_UNSPEC (V4SFmode,
07906   gen_rtvec (2,
07907     operand1,
07908     operand2),
07909   72));
07910 }
07911 
07912 /* ../../gcc/gcc/config/i386/i386.md:22217 */
07913 rtx
07914 gen_haddv2df3 (operand0, operand1, operand2)
07915      rtx operand0;
07916      rtx operand1;
07917      rtx operand2;
07918 {
07919   return gen_rtx_SET (VOIDmode,
07920   operand0,
07921   gen_rtx_UNSPEC (V2DFmode,
07922   gen_rtvec (2,
07923     operand1,
07924     operand2),
07925   72));
07926 }
07927 
07928 /* ../../gcc/gcc/config/i386/i386.md:22227 */
07929 rtx
07930 gen_hsubv4sf3 (operand0, operand1, operand2)
07931      rtx operand0;
07932      rtx operand1;
07933      rtx operand2;
07934 {
07935   return gen_rtx_SET (VOIDmode,
07936   operand0,
07937   gen_rtx_UNSPEC (V4SFmode,
07938   gen_rtvec (2,
07939     operand1,
07940     operand2),
07941   73));
07942 }
07943 
07944 /* ../../gcc/gcc/config/i386/i386.md:22237 */
07945 rtx
07946 gen_hsubv2df3 (operand0, operand1, operand2)
07947      rtx operand0;
07948      rtx operand1;
07949      rtx operand2;
07950 {
07951   return gen_rtx_SET (VOIDmode,
07952   operand0,
07953   gen_rtx_UNSPEC (V2DFmode,
07954   gen_rtvec (2,
07955     operand1,
07956     operand2),
07957   73));
07958 }
07959 
07960 /* ../../gcc/gcc/config/i386/i386.md:22247 */
07961 rtx
07962 gen_movshdup (operand0, operand1)
07963      rtx operand0;
07964      rtx operand1;
07965 {
07966   return gen_rtx_SET (VOIDmode,
07967   operand0,
07968   gen_rtx_UNSPEC (V4SFmode,
07969   gen_rtvec (1,
07970     operand1),
07971   74));
07972 }
07973 
07974 /* ../../gcc/gcc/config/i386/i386.md:22256 */
07975 rtx
07976 gen_movsldup (operand0, operand1)
07977      rtx operand0;
07978      rtx operand1;
07979 {
07980   return gen_rtx_SET (VOIDmode,
07981   operand0,
07982   gen_rtx_UNSPEC (V4SFmode,
07983   gen_rtvec (1,
07984     operand1),
07985   75));
07986 }
07987 
07988 /* ../../gcc/gcc/config/i386/i386.md:22265 */
07989 rtx
07990 gen_lddqu (operand0, operand1)
07991      rtx operand0;
07992      rtx operand1;
07993 {
07994   return gen_rtx_SET (VOIDmode,
07995   operand0,
07996   gen_rtx_UNSPEC (V16QImode,
07997   gen_rtvec (1,
07998     operand1),
07999   76));
08000 }
08001 
08002 /* ../../gcc/gcc/config/i386/i386.md:22274 */
08003 rtx
08004 gen_loadddup (operand0, operand1)
08005      rtx operand0;
08006      rtx operand1;
08007 {
08008   return gen_rtx_SET (VOIDmode,
08009   operand0,
08010   gen_rtx_VEC_DUPLICATE (V2DFmode,
08011   operand1));
08012 }
08013 
08014 /* ../../gcc/gcc/config/i386/i386.md:22282 */
08015 rtx
08016 gen_movddup (operand0, operand1)
08017      rtx operand0;
08018      rtx operand1;
08019 {
08020   return gen_rtx_SET (VOIDmode,
08021   operand0,
08022   gen_rtx_VEC_DUPLICATE (V2DFmode,
08023   gen_rtx_VEC_SELECT (DFmode,
08024   operand1,
08025   gen_rtx_PARALLEL (VOIDmode,
08026   gen_rtvec (1,
08027     const0_rtx)))));
08028 }
08029 
08030 /* ../../gcc/gcc/config/i386/i386.md:392 */
08031 rtx
08032 gen_cmpdi (operand0, operand1)
08033      rtx operand0;
08034      rtx operand1;
08035 {
08036   rtx _val = 0;
08037   start_sequence ();
08038   {
08039     rtx operands[2];
08040     operands[0] = operand0;
08041     operands[1] = operand1;
08042 {
08043   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
08044     operands[0] = force_reg (DImode, operands[0]);
08045   ix86_compare_op0 = operands[0];
08046   ix86_compare_op1 = operands[1];
08047   DONE;
08048 }
08049     operand0 = operands[0];
08050     operand1 = operands[1];
08051   }
08052   emit_insn (gen_rtx_SET (VOIDmode,
08053   gen_rtx_REG (CCmode,
08054   17),
08055   gen_rtx_COMPARE (CCmode,
08056   operand0,
08057   operand1)));
08058   _val = get_insns ();
08059   end_sequence ();
08060   return _val;
08061 }
08062 
08063 /* ../../gcc/gcc/config/i386/i386.md:405 */
08064 rtx
08065 gen_cmpsi (operand0, operand1)
08066      rtx operand0;
08067      rtx operand1;
08068 {
08069   rtx _val = 0;
08070   start_sequence ();
08071   {
08072     rtx operands[2];
08073     operands[0] = operand0;
08074     operands[1] = operand1;
08075 {
08076   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
08077     operands[0] = force_reg (SImode, operands[0]);
08078   ix86_compare_op0 = operands[0];
08079   ix86_compare_op1 = operands[1];
08080   DONE;
08081 }
08082     operand0 = operands[0];
08083     operand1 = operands[1];
08084   }
08085   emit_insn (gen_rtx_SET (VOIDmode,
08086   gen_rtx_REG (CCmode,
08087   17),
08088   gen_rtx_COMPARE (CCmode,
08089   operand0,
08090   operand1)));
08091   _val = get_insns ();
08092   end_sequence ();
08093   return _val;
08094 }
08095 
08096 /* ../../gcc/gcc/config/i386/i386.md:418 */
08097 rtx
08098 gen_cmphi (operand0, operand1)
08099      rtx operand0;
08100      rtx operand1;
08101 {
08102   rtx _val = 0;
08103   start_sequence ();
08104   {
08105     rtx operands[2];
08106     operands[0] = operand0;
08107     operands[1] = operand1;
08108 {
08109   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
08110     operands[0] = force_reg (HImode, operands[0]);
08111   ix86_compare_op0 = operands[0];
08112   ix86_compare_op1 = operands[1];
08113   DONE;
08114 }
08115     operand0 = operands[0];
08116     operand1 = operands[1];
08117   }
08118   emit_insn (gen_rtx_SET (VOIDmode,
08119   gen_rtx_REG (CCmode,
08120   17),
08121   gen_rtx_COMPARE (CCmode,
08122   operand0,
08123   operand1)));
08124   _val = get_insns ();
08125   end_sequence ();
08126   return _val;
08127 }
08128 
08129 /* ../../gcc/gcc/config/i386/i386.md:431 */
08130 rtx
08131 gen_cmpqi (operand0, operand1)
08132      rtx operand0;
08133      rtx operand1;
08134 {
08135   rtx _val = 0;
08136   start_sequence ();
08137   {
08138     rtx operands[2];
08139     operands[0] = operand0;
08140     operands[1] = operand1;
08141 {
08142   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
08143     operands[0] = force_reg (QImode, operands[0]);
08144   ix86_compare_op0 = operands[0];
08145   ix86_compare_op1 = operands[1];
08146   DONE;
08147 }
08148     operand0 = operands[0];
08149     operand1 = operands[1];
08150   }
08151   emit_insn (gen_rtx_SET (VOIDmode,
08152   gen_rtx_REG (CCmode,
08153   17),
08154   gen_rtx_COMPARE (CCmode,
08155   operand0,
08156   operand1)));
08157   _val = get_insns ();
08158   end_sequence ();
08159   return _val;
08160 }
08161 
08162 /* ../../gcc/gcc/config/i386/i386.md:466 */
08163 rtx
08164 gen_cmpdi_1_rex64 (operand0, operand1)
08165      rtx operand0;
08166      rtx operand1;
08167 {
08168   return gen_rtx_SET (VOIDmode,
08169   gen_rtx_REG (CCmode,
08170   17),
08171   gen_rtx_COMPARE (CCmode,
08172   operand0,
08173   operand1));
08174 }
08175 
08176 /* ../../gcc/gcc/config/i386/i386.md:505 */
08177 rtx
08178 gen_cmpsi_1 (operand0, operand1)
08179      rtx operand0;
08180      rtx operand1;
08181 {
08182   return gen_rtx_SET (VOIDmode,
08183   gen_rtx_REG (CCmode,
08184   17),
08185   gen_rtx_COMPARE (CCmode,
08186   operand0,
08187   operand1));
08188 }
08189 
08190 /* ../../gcc/gcc/config/i386/i386.md:629 */
08191 rtx
08192 gen_cmpqi_ext_3 (operand0, operand1)
08193      rtx operand0;
08194      rtx operand1;
08195 {
08196   return gen_rtx_SET (VOIDmode,
08197   gen_rtx_REG (CCmode,
08198   17),
08199   gen_rtx_COMPARE (CCmode,
08200   gen_rtx_SUBREG (QImode,
08201   gen_rtx_ZERO_EXTRACT (SImode,
08202   operand0,
08203   GEN_INT (8LL),
08204   GEN_INT (8LL)),
08205   0),
08206   operand1));
08207 }
08208 
08209 /* ../../gcc/gcc/config/i386/i386.md:692 */
08210 rtx
08211 gen_cmpxf (operand0, operand1)
08212      rtx operand0;
08213      rtx operand1;
08214 {
08215   rtx _val = 0;
08216   start_sequence ();
08217   {
08218     rtx operands[2];
08219     operands[0] = operand0;
08220     operands[1] = operand1;
08221 {
08222   ix86_compare_op0 = operands[0];
08223   ix86_compare_op1 = operands[1];
08224   DONE;
08225 }
08226     operand0 = operands[0];
08227     operand1 = operands[1];
08228   }
08229   emit_insn (gen_rtx_SET (VOIDmode,
08230   gen_rtx_REG (CCmode,
08231   17),
08232   gen_rtx_COMPARE (CCmode,
08233   operand0,
08234   operand1)));
08235   _val = get_insns ();
08236   end_sequence ();
08237   return _val;
08238 }
08239 
08240 /* ../../gcc/gcc/config/i386/i386.md:703 */
08241 rtx
08242 gen_cmptf (operand0, operand1)
08243      rtx operand0;
08244      rtx operand1;
08245 {
08246   rtx _val = 0;
08247   start_sequence ();
08248   {
08249     rtx operands[2];
08250     operands[0] = operand0;
08251     operands[1] = operand1;
08252 {
08253   ix86_compare_op0 = operands[0];
08254   ix86_compare_op1 = operands[1];
08255   DONE;
08256 }
08257     operand0 = operands[0];
08258     operand1 = operands[1];
08259   }
08260   emit_insn (gen_rtx_SET (VOIDmode,
08261   gen_rtx_REG (CCmode,
08262   17),
08263   gen_rtx_COMPARE (CCmode,
08264   operand0,
08265   operand1)));
08266   _val = get_insns ();
08267   end_sequence ();
08268   return _val;
08269 }
08270 
08271 /* ../../gcc/gcc/config/i386/i386.md:714 */
08272 rtx
08273 gen_cmpdf (operand0, operand1)
08274      rtx operand0;
08275      rtx operand1;
08276 {
08277   rtx _val = 0;
08278   start_sequence ();
08279   {
08280     rtx operands[2];
08281     operands[0] = operand0;
08282     operands[1] = operand1;
08283 {
08284   ix86_compare_op0 = operands[0];
08285   ix86_compare_op1 = operands[1];
08286   DONE;
08287 }
08288     operand0 = operands[0];
08289     operand1 = operands[1];
08290   }
08291   emit_insn (gen_rtx_SET (VOIDmode,
08292   gen_rtx_REG (CCmode,
08293   17),
08294   gen_rtx_COMPARE (CCmode,
08295   operand0,
08296   operand1)));
08297   _val = get_insns ();
08298   end_sequence ();
08299   return _val;
08300 }
08301 
08302 /* ../../gcc/gcc/config/i386/i386.md:725 */
08303 rtx
08304 gen_cmpsf (operand0, operand1)
08305      rtx operand0;
08306      rtx operand1;
08307 {
08308   rtx _val = 0;
08309   start_sequence ();
08310   {
08311     rtx operands[2];
08312     operands[0] = operand0;
08313     operands[1] = operand1;
08314 {
08315   ix86_compare_op0 = operands[0];
08316   ix86_compare_op1 = operands[1];
08317   DONE;
08318 }
08319     operand0 = operands[0];
08320     operand1 = operands[1];
08321   }
08322   emit_insn (gen_rtx_SET (VOIDmode,
08323   gen_rtx_REG (CCmode,
08324   17),
08325   gen_rtx_COMPARE (CCmode,
08326   operand0,
08327   operand1)));
08328   _val = get_insns ();
08329   end_sequence ();
08330   return _val;
08331 }
08332 
08333 /* ../../gcc/gcc/config/i386/i386.md:1028 */
08334 rtx
08335 gen_movsi (operand0, operand1)
08336      rtx operand0;
08337      rtx operand1;
08338 {
08339   rtx _val = 0;
08340   start_sequence ();
08341   {
08342     rtx operands[2];
08343     operands[0] = operand0;
08344     operands[1] = operand1;
08345 ix86_expand_move (SImode, operands); DONE;
08346     operand0 = operands[0];
08347     operand1 = operands[1];
08348   }
08349   emit_insn (gen_rtx_SET (VOIDmode,
08350   operand0,
08351   operand1));
08352   _val = get_insns ();
08353   end_sequence ();
08354   return _val;
08355 }
08356 
08357 /* ../../gcc/gcc/config/i386/i386.md:1198 */
08358 rtx
08359 gen_movhi (operand0, operand1)
08360      rtx operand0;
08361      rtx operand1;
08362 {
08363   rtx _val = 0;
08364   start_sequence ();
08365   {
08366     rtx operands[2];
08367     operands[0] = operand0;
08368     operands[1] = operand1;
08369 ix86_expand_move (HImode, operands); DONE;
08370     operand0 = operands[0];
08371     operand1 = operands[1];
08372   }
08373   emit_insn (gen_rtx_SET (VOIDmode,
08374   operand0,
08375   operand1));
08376   _val = get_insns ();
08377   end_sequence ();
08378   return _val;
08379 }
08380 
08381 /* ../../gcc/gcc/config/i386/i386.md:1329 */
08382 rtx
08383 gen_movstricthi (operand0, operand1)
08384      rtx operand0;
08385      rtx operand1;
08386 {
08387   rtx _val = 0;
08388   start_sequence ();
08389   {
08390     rtx operands[2];
08391     operands[0] = operand0;
08392     operands[1] = operand1;
08393 {
08394   /* Don't generate memory->memory moves, go through a register */
08395   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
08396     operands[1] = force_reg (HImode, operands[1]);
08397 }
08398     operand0 = operands[0];
08399     operand1 = operands[1];
08400   }
08401   emit_insn (gen_rtx_SET (VOIDmode,
08402   gen_rtx_STRICT_LOW_PART (VOIDmode,
08403   operand0),
08404   operand1));
08405   _val = get_insns ();
08406   end_sequence ();
08407   return _val;
08408 }
08409 
08410 /* ../../gcc/gcc/config/i386/i386.md:1359 */
08411 rtx
08412 gen_movqi (operand0, operand1)
08413      rtx operand0;
08414      rtx operand1;
08415 {
08416   rtx _val = 0;
08417   start_sequence ();
08418   {
08419     rtx operands[2];
08420     operands[0] = operand0;
08421     operands[1] = operand1;
08422 ix86_expand_move (QImode, operands); DONE;
08423     operand0 = operands[0];
08424     operand1 = operands[1];
08425   }
08426   emit_insn (gen_rtx_SET (VOIDmode,
08427   operand0,
08428   operand1));
08429   _val = get_insns ();
08430   end_sequence ();
08431   return _val;
08432 }
08433 
08434 /* ../../gcc/gcc/config/i386/i386.md:1454 */
08435 rtx
08436 gen_reload_outqi (operand0, operand1, operand2)
08437      rtx operand0;
08438      rtx operand1;
08439      rtx operand2;
08440 {
08441   rtx _val = 0;
08442   start_sequence ();
08443   {
08444     rtx operands[3];
08445     operands[0] = operand0;
08446     operands[1] = operand1;
08447     operands[2] = operand2;
08448 {
08449   rtx op0, op1, op2;
08450   op0 = operands[0]; op1 = operands[1]; op2 = operands[2];
08451 
08452   if (reg_overlap_mentioned_p (op2, op0))
08453     abort ();
08454   if (! q_regs_operand (op1, QImode))
08455     {
08456       emit_insn (gen_movqi (op2, op1));
08457       op1 = op2;
08458     }
08459   emit_insn (gen_movqi (op0, op1));
08460   DONE;
08461 }
08462     operand0 = operands[0];
08463     operand1 = operands[1];
08464     operand2 = operands[2];
08465   }
08466   emit (gen_rtx_PARALLEL (VOIDmode,
08467   gen_rtvec (3,
08468     operand0,
08469     operand1,
08470     operand2)));
08471   _val = get_insns ();
08472   end_sequence ();
08473   return _val;
08474 }
08475 
08476 /* ../../gcc/gcc/config/i386/i386.md:1487 */
08477 rtx
08478 gen_movstrictqi (operand0, operand1)
08479      rtx operand0;
08480      rtx operand1;
08481 {
08482   rtx _val = 0;
08483   start_sequence ();
08484   {
08485     rtx operands[2];
08486     operands[0] = operand0;
08487     operands[1] = operand1;
08488 {
08489   /* Don't generate memory->memory moves, go through a register.  */
08490   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
08491     operands[1] = force_reg (QImode, operands[1]);
08492 }
08493     operand0 = operands[0];
08494     operand1 = operands[1];
08495   }
08496   emit_insn (gen_rtx_SET (VOIDmode,
08497   gen_rtx_STRICT_LOW_PART (VOIDmode,
08498   operand0),
08499   operand1));
08500   _val = get_insns ();
08501   end_sequence ();
08502   return _val;
08503 }
08504 
08505 /* ../../gcc/gcc/config/i386/i386.md:1716 */
08506 rtx
08507 gen_movdi (operand0, operand1)
08508      rtx operand0;
08509      rtx operand1;
08510 {
08511   rtx _val = 0;
08512   start_sequence ();
08513   {
08514     rtx operands[2];
08515     operands[0] = operand0;
08516     operands[1] = operand1;
08517 ix86_expand_move (DImode, operands); DONE;
08518     operand0 = operands[0];
08519     operand1 = operands[1];
08520   }
08521   emit_insn (gen_rtx_SET (VOIDmode,
08522   operand0,
08523   operand1));
08524   _val = get_insns ();
08525   end_sequence ();
08526   return _val;
08527 }
08528 
08529 /* ../../gcc/gcc/config/i386/i386.md:1742 */
08530 extern rtx gen_peephole2_1054 PARAMS ((rtx, rtx *));
08531 rtx
08532 gen_peephole2_1054 (curr_insn, operands)
08533      rtx curr_insn ATTRIBUTE_UNUSED;
08534      rtx *operands;
08535 {
08536   rtx operand0;
08537   rtx operand1;
08538   rtx operand2;
08539   rtx _val = 0;
08540   HARD_REG_SET _regs_allocated;
08541   CLEAR_HARD_REG_SET (_regs_allocated);
08542   if ((operands[2] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
08543     return NULL;
08544   start_sequence ();
08545 
08546   operand0 = operands[0];
08547   operand1 = operands[1];
08548   operand2 = operands[2];
08549   emit_insn (gen_rtx_SET (VOIDmode,
08550   operand2,
08551   operand1));
08552   emit_insn (gen_rtx_SET (VOIDmode,
08553   operand0,
08554   copy_rtx (operand2)));
08555   _val = get_insns ();
08556   end_sequence ();
08557   return _val;
08558 }
08559 
08560 /* ../../gcc/gcc/config/i386/i386.md:1754 */
08561 extern rtx gen_peephole2_1055 PARAMS ((rtx, rtx *));
08562 rtx
08563 gen_peephole2_1055 (curr_insn, operands)
08564      rtx curr_insn ATTRIBUTE_UNUSED;
08565      rtx *operands;
08566 {
08567   rtx operand0;
08568   rtx operand1;
08569   rtx operand2;
08570   rtx operand3;
08571   rtx _val = 0;
08572   HARD_REG_SET _regs_allocated;
08573   CLEAR_HARD_REG_SET (_regs_allocated);
08574   start_sequence ();
08575 split_di (operands + 1, 1, operands + 2, operands + 3);
08576    operands[1] = gen_lowpart (DImode, operands[2]);
08577    operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
08578                 GEN_INT (4)));
08579   
08580   operand0 = operands[0];
08581   operand1 = operands[1];
08582   operand2 = operands[2];
08583   operand3 = operands[3];
08584   emit_insn (gen_rtx_SET (VOIDmode,
08585   operand0,
08586   operand1));
08587   emit_insn (gen_rtx_SET (VOIDmode,
08588   operand2,
08589   operand3));
08590   _val = get_insns ();
08591   end_sequence ();
08592   return _val;
08593 }
08594 
08595 /* ../../gcc/gcc/config/i386/i386.md:1767 */
08596 extern rtx gen_split_1056 PARAMS ((rtx *));
08597 rtx
08598 gen_split_1056 (operands)
08599       rtx *operands;
08600 {
08601   rtx operand0;
08602   rtx operand1;
08603   rtx operand2;
08604   rtx operand3;
08605   rtx _val = 0;
08606   start_sequence ();
08607 split_di (operands + 1, 1, operands + 2, operands + 3);
08608    operands[1] = gen_lowpart (DImode, operands[2]);
08609    operands[2] = gen_rtx_MEM (SImode, gen_rtx_PLUS (DImode, stack_pointer_rtx,
08610                 GEN_INT (4)));
08611   
08612   operand0 = operands[0];
08613   operand1 = operands[1];
08614   operand2 = operands[2];
08615   operand3 = operands[3];
08616   emit_insn (gen_rtx_SET (VOIDmode,
08617   operand0,
08618   operand1));
08619   emit_insn (gen_rtx_SET (VOIDmode,
08620   operand2,
08621   operand3));
08622   _val = get_insns ();
08623   end_sequence ();
08624   return _val;
08625 }
08626 
08627 /* ../../gcc/gcc/config/i386/i386.md:1854 */
08628 extern rtx gen_split_1057 PARAMS ((rtx *));
08629 rtx
08630 gen_split_1057 (operands)
08631       rtx *operands ATTRIBUTE_UNUSED;
08632 {
08633   rtx _val = 0;
08634   start_sequence ();
08635 ix86_split_long_move (operands); DONE;
08636   emit_insn (const0_rtx);
08637   _val = get_insns ();
08638   end_sequence ();
08639   return _val;
08640 }
08641 
08642 /* ../../gcc/gcc/config/i386/i386.md:1863 */
08643 extern rtx gen_split_1058 PARAMS ((rtx *));
08644 rtx
08645 gen_split_1058 (operands)
08646       rtx *operands ATTRIBUTE_UNUSED;
08647 {
08648   rtx _val = 0;
08649   start_sequence ();
08650 ix86_split_long_move (operands); DONE;
08651   emit_insn (const0_rtx);
08652   _val = get_insns ();
08653   end_sequence ();
08654   return _val;
08655 }
08656 
08657 /* ../../gcc/gcc/config/i386/i386.md:1952 */
08658 extern rtx gen_peephole2_1059 PARAMS ((rtx, rtx *));
08659 rtx
08660 gen_peephole2_1059 (curr_insn, operands)
08661      rtx curr_insn ATTRIBUTE_UNUSED;
08662      rtx *operands;
08663 {
08664   rtx operand0;
08665   rtx operand1;
08666   rtx operand2;
08667   rtx _val = 0;
08668   HARD_REG_SET _regs_allocated;
08669   CLEAR_HARD_REG_SET (_regs_allocated);
08670   if ((operands[2] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
08671     return NULL;
08672   start_sequence ();
08673 
08674   operand0 = operands[0];
08675   operand1 = operands[1];
08676   operand2 = operands[2];
08677   emit_insn (gen_rtx_SET (VOIDmode,
08678   operand2,
08679   operand1));
08680   emit_insn (gen_rtx_SET (VOIDmode,
08681   operand0,
08682   copy_rtx (operand2)));
08683   _val = get_insns ();
08684   end_sequence ();
08685   return _val;
08686 }
08687 
08688 /* ../../gcc/gcc/config/i386/i386.md:1964 */
08689 extern rtx gen_peephole2_1060 PARAMS ((rtx, rtx *));
08690 rtx
08691 gen_peephole2_1060 (curr_insn, operands)
08692      rtx curr_insn ATTRIBUTE_UNUSED;
08693      rtx *operands;
08694 {
08695   rtx operand0;
08696   rtx operand1;
08697   rtx operand2;
08698   rtx operand3;
08699   rtx operand4;
08700   rtx operand5;
08701   rtx _val = 0;
08702   HARD_REG_SET _regs_allocated;
08703   CLEAR_HARD_REG_SET (_regs_allocated);
08704   start_sequence ();
08705 split_di (operands, 2, operands + 2, operands + 4);
08706   operand0 = operands[0];
08707   operand1 = operands[1];
08708   operand2 = operands[2];
08709   operand3 = operands[3];
08710   operand4 = operands[4];
08711   operand5 = operands[5];
08712   emit_insn (gen_rtx_SET (VOIDmode,
08713   operand2,
08714   operand3));
08715   emit_insn (gen_rtx_SET (VOIDmode,
08716   operand4,
08717   operand5));
08718   _val = get_insns ();
08719   end_sequence ();
08720   return _val;
08721 }
08722 
08723 /* ../../gcc/gcc/config/i386/i386.md:1973 */
08724 extern rtx gen_split_1061 PARAMS ((rtx *));
08725 rtx
08726 gen_split_1061 (operands)
08727       rtx *operands;
08728 {
08729   rtx operand0;
08730   rtx operand1;
08731   rtx operand2;
08732   rtx operand3;
08733   rtx operand4;
08734   rtx operand5;
08735   rtx _val = 0;
08736   start_sequence ();
08737 split_di (operands, 2, operands + 2, operands + 4);
08738   operand0 = operands[0];
08739   operand1 = operands[1];
08740   operand2 = operands[2];
08741   operand3 = operands[3];
08742   operand4 = operands[4];
08743   operand5 = operands[5];
08744   emit_insn (gen_rtx_SET (VOIDmode,
08745   operand2,
08746   operand3));
08747   emit_insn (gen_rtx_SET (VOIDmode,
08748   operand4,
08749   operand5));
08750   _val = get_insns ();
08751   end_sequence ();
08752   return _val;
08753 }
08754 
08755 /* ../../gcc/gcc/config/i386/i386.md:1998 */
08756 rtx
08757 gen_movsf (operand0, operand1)
08758      rtx operand0;
08759      rtx operand1;
08760 {
08761   rtx _val = 0;
08762   start_sequence ();
08763   {
08764     rtx operands[2];
08765     operands[0] = operand0;
08766     operands[1] = operand1;
08767 ix86_expand_move (SFmode, operands); DONE;
08768     operand0 = operands[0];
08769     operand1 = operands[1];
08770   }
08771   emit_insn (gen_rtx_SET (VOIDmode,
08772   operand0,
08773   operand1));
08774   _val = get_insns ();
08775   end_sequence ();
08776   return _val;
08777 }
08778 
08779 /* ../../gcc/gcc/config/i386/i386.md:2063 */
08780 extern rtx gen_split_1063 PARAMS ((rtx *));
08781 rtx
08782 gen_split_1063 (operands)
08783       rtx *operands;
08784 {
08785   rtx operand0;
08786   rtx operand1;
08787   rtx _val = 0;
08788   start_sequence ();
08789 operands[1] = get_pool_constant (XEXP (operands[1], 0));
08790   operand0 = operands[0];
08791   operand1 = operands[1];
08792   emit_insn (gen_rtx_SET (VOIDmode,
08793   operand0,
08794   operand1));
08795   _val = get_insns ();
08796   end_sequence ();
08797   return _val;
08798 }
08799 
08800 /* ../../gcc/gcc/config/i386/i386.md:2076 */
08801 extern rtx gen_split_1064 PARAMS ((rtx *));
08802 rtx
08803 gen_split_1064 (operands)
08804       rtx *operands;
08805 {
08806   rtx operand0;
08807   rtx operand1;
08808   rtx _val = 0;
08809   start_sequence ();
08810   operand0 = operands[0];
08811   operand1 = operands[1];
08812   emit_insn (gen_rtx_SET (VOIDmode,
08813   gen_rtx_REG (SImode,
08814   7),
08815   gen_rtx_PLUS (SImode,
08816   gen_rtx_REG (SImode,
08817   7),
08818   GEN_INT (-4LL))));
08819   emit_insn (gen_rtx_SET (VOIDmode,
08820   gen_rtx_MEM (SFmode,
08821   gen_rtx_REG (SImode,
08822   7)),
08823   operand1));
08824   _val = get_insns ();
08825   end_sequence ();
08826   return _val;
08827 }
08828 
08829 /* ../../gcc/gcc/config/i386/i386.md:2083 */
08830 extern rtx gen_split_1065 PARAMS ((rtx *));
08831 rtx
08832 gen_split_1065 (operands)
08833       rtx *operands;
08834 {
08835   rtx operand0;
08836   rtx operand1;
08837   rtx _val = 0;
08838   start_sequence ();
08839   operand0 = operands[0];
08840   operand1 = operands[1];
08841   emit_insn (gen_rtx_SET (VOIDmode,
08842   gen_rtx_REG (DImode,
08843   7),
08844   gen_rtx_PLUS (DImode,
08845   gen_rtx_REG (DImode,
08846   7),
08847   GEN_INT (-8LL))));
08848   emit_insn (gen_rtx_SET (VOIDmode,
08849   gen_rtx_MEM (SFmode,
08850   gen_rtx_REG (DImode,
08851   7)),
08852   operand1));
08853   _val = get_insns ();
08854   end_sequence ();
08855   return _val;
08856 }
08857 
08858 /* ../../gcc/gcc/config/i386/i386.md:2172 */
08859 rtx
08860 gen_movdf (operand0, operand1)
08861      rtx operand0;
08862      rtx operand1;
08863 {
08864   rtx _val = 0;
08865   start_sequence ();
08866   {
08867     rtx operands[2];
08868     operands[0] = operand0;
08869     operands[1] = operand1;
08870 ix86_expand_move (DFmode, operands); DONE;
08871     operand0 = operands[0];
08872     operand1 = operands[1];
08873   }
08874   emit_insn (gen_rtx_SET (VOIDmode,
08875   operand0,
08876   operand1));
08877   _val = get_insns ();
08878   end_sequence ();
08879   return _val;
08880 }
08881 
08882 /* ../../gcc/gcc/config/i386/i386.md:2248 */
08883 extern rtx gen_split_1067 PARAMS ((rtx *));
08884 rtx
08885 gen_split_1067 (operands)
08886       rtx *operands;
08887 {
08888   rtx operand0;
08889   rtx operand1;
08890   rtx _val = 0;
08891   start_sequence ();
08892 
08893   operand0 = operands[0];
08894   operand1 = operands[1];
08895   emit_insn (gen_rtx_SET (VOIDmode,
08896   gen_rtx_REG (SImode,
08897   7),
08898   gen_rtx_PLUS (SImode,
08899   gen_rtx_REG (SImode,
08900   7),
08901   GEN_INT (-8LL))));
08902   emit_insn (gen_rtx_SET (VOIDmode,
08903   gen_rtx_MEM (DFmode,
08904   gen_rtx_REG (SImode,
08905   7)),
08906   operand1));
08907   _val = get_insns ();
08908   end_sequence ();
08909   return _val;
08910 }
08911 
08912 /* ../../gcc/gcc/config/i386/i386.md:2256 */
08913 extern rtx gen_split_1068 PARAMS ((rtx *));
08914 rtx
08915 gen_split_1068 (operands)
08916       rtx *operands;
08917 {
08918   rtx operand0;
08919   rtx operand1;
08920   rtx _val = 0;
08921   start_sequence ();
08922 
08923   operand0 = operands[0];
08924   operand1 = operands[1];
08925   emit_insn (gen_rtx_SET (VOIDmode,
08926   gen_rtx_REG (DImode,
08927   7),
08928   gen_rtx_PLUS (DImode,
08929   gen_rtx_REG (DImode,
08930   7),
08931   GEN_INT (-8LL))));
08932   emit_insn (gen_rtx_SET (VOIDmode,
08933   gen_rtx_MEM (DFmode,
08934   gen_rtx_REG (DImode,
08935   7)),
08936   operand1));
08937   _val = get_insns ();
08938   end_sequence ();
08939   return _val;
08940 }
08941 
08942 /* ../../gcc/gcc/config/i386/i386.md:2264 */
08943 extern rtx gen_split_1069 PARAMS ((rtx *));
08944 rtx
08945 gen_split_1069 (operands)
08946       rtx *operands ATTRIBUTE_UNUSED;
08947 {
08948   rtx _val = 0;
08949   start_sequence ();
08950 ix86_split_long_move (operands); DONE;
08951   emit_insn (const0_rtx);
08952   _val = get_insns ();
08953   end_sequence ();
08954   return _val;
08955 }
08956 
08957 /* ../../gcc/gcc/config/i386/i386.md:2398 */
08958 extern rtx gen_split_1070 PARAMS ((rtx *));
08959 rtx
08960 gen_split_1070 (operands)
08961       rtx *operands ATTRIBUTE_UNUSED;
08962 {
08963   rtx _val = 0;
08964   start_sequence ();
08965 ix86_split_long_move (operands); DONE;
08966   emit_insn (const0_rtx);
08967   _val = get_insns ();
08968   end_sequence ();
08969   return _val;
08970 }
08971 
08972 /* ../../gcc/gcc/config/i386/i386.md:2427 */
08973 rtx
08974 gen_movxf (operand0, operand1)
08975      rtx operand0;
08976      rtx operand1;
08977 {
08978   rtx _val = 0;
08979   start_sequence ();
08980   {
08981     rtx operands[2];
08982     operands[0] = operand0;
08983     operands[1] = operand1;
08984 ix86_expand_move (XFmode, operands); DONE;
08985     operand0 = operands[0];
08986     operand1 = operands[1];
08987   }
08988   emit_insn (gen_rtx_SET (VOIDmode,
08989   operand0,
08990   operand1));
08991   _val = get_insns ();
08992   end_sequence ();
08993   return _val;
08994 }
08995 
08996 /* ../../gcc/gcc/config/i386/i386.md:2433 */
08997 rtx
08998 gen_movtf (operand0, operand1)
08999      rtx operand0;
09000      rtx operand1;
09001 {
09002   rtx _val = 0;
09003   start_sequence ();
09004   {
09005     rtx operands[2];
09006     operands[0] = operand0;
09007     operands[1] = operand1;
09008 ix86_expand_move (TFmode, operands); DONE;
09009     operand0 = operands[0];
09010     operand1 = operands[1];
09011   }
09012   emit_insn (gen_rtx_SET (VOIDmode,
09013   operand0,
09014   operand1));
09015   _val = get_insns ();
09016   end_sequence ();
09017   return _val;
09018 }
09019 
09020 /* ../../gcc/gcc/config/i386/i386.md:2562 */
09021 extern rtx gen_split_1073 PARAMS ((rtx *));
09022 rtx
09023 gen_split_1073 (operands)
09024       rtx *operands ATTRIBUTE_UNUSED;
09025 {
09026   rtx _val = 0;
09027   start_sequence ();
09028 ix86_split_long_move (operands); DONE;
09029   emit_insn (const0_rtx);
09030   _val = get_insns ();
09031   end_sequence ();
09032   return _val;
09033 }
09034 
09035 /* ../../gcc/gcc/config/i386/i386.md:2573 */
09036 extern rtx gen_split_1074 PARAMS ((rtx *));
09037 rtx
09038 gen_split_1074 (operands)
09039       rtx *operands;
09040 {
09041   rtx operand0;
09042   rtx operand1;
09043   rtx _val = 0;
09044   start_sequence ();
09045   operand0 = operands[0];
09046   operand1 = operands[1];
09047   emit_insn (gen_rtx_SET (VOIDmode,
09048   gen_rtx_REG (SImode,
09049   7),
09050   gen_rtx_PLUS (SImode,
09051   gen_rtx_REG (SImode,
09052   7),
09053   GEN_INT (-12LL))));
09054   emit_insn (gen_rtx_SET (VOIDmode,
09055   gen_rtx_MEM (XFmode,
09056   gen_rtx_REG (SImode,
09057   7)),
09058   operand1));
09059   _val = get_insns ();
09060   end_sequence ();
09061   return _val;
09062 }
09063 
09064 /* ../../gcc/gcc/config/i386/i386.md:2580 */
09065 extern rtx gen_split_1075 PARAMS ((rtx *));
09066 rtx
09067 gen_split_1075 (operands)
09068       rtx *operands;
09069 {
09070   rtx operand0;
09071   rtx operand1;
09072   rtx _val = 0;
09073   start_sequence ();
09074   operand0 = operands[0];
09075   operand1 = operands[1];
09076   emit_insn (gen_rtx_SET (VOIDmode,
09077   gen_rtx_REG (SImode,
09078   7),
09079   gen_rtx_PLUS (SImode,
09080   gen_rtx_REG (SImode,
09081   7),
09082   GEN_INT (-16LL))));
09083   emit_insn (gen_rtx_SET (VOIDmode,
09084   gen_rtx_MEM (TFmode,
09085   gen_rtx_REG (SImode,
09086   7)),
09087   operand1));
09088   _val = get_insns ();
09089   end_sequence ();
09090   return _val;
09091 }
09092 
09093 /* ../../gcc/gcc/config/i386/i386.md:2587 */
09094 extern rtx gen_split_1076 PARAMS ((rtx *));
09095 rtx
09096 gen_split_1076 (operands)
09097       rtx *operands;
09098 {
09099   rtx operand0;
09100   rtx operand1;
09101   rtx _val = 0;
09102   start_sequence ();
09103   operand0 = operands[0];
09104   operand1 = operands[1];
09105   emit_insn (gen_rtx_SET (VOIDmode,
09106   gen_rtx_REG (DImode,
09107   7),
09108   gen_rtx_PLUS (DImode,
09109   gen_rtx_REG (DImode,
09110   7),
09111   GEN_INT (-16LL))));
09112   emit_insn (gen_rtx_SET (VOIDmode,
09113   gen_rtx_MEM (TFmode,
09114   gen_rtx_REG (DImode,
09115   7)),
09116   operand1));
09117   _val = get_insns ();
09118   end_sequence ();
09119   return _val;
09120 }
09121 
09122 /* ../../gcc/gcc/config/i386/i386.md:2783 */
09123 extern rtx gen_split_1077 PARAMS ((rtx *));
09124 rtx
09125 gen_split_1077 (operands)
09126       rtx *operands ATTRIBUTE_UNUSED;
09127 {
09128   rtx _val = 0;
09129   start_sequence ();
09130 ix86_split_long_move (operands); DONE;
09131   emit_insn (const0_rtx);
09132   _val = get_insns ();
09133   end_sequence ();
09134   return _val;
09135 }
09136 
09137 /* ../../gcc/gcc/config/i386/i386.md:2798 */
09138 extern rtx gen_split_1078 PARAMS ((rtx *));
09139 rtx
09140 gen_split_1078 (operands)
09141       rtx *operands;
09142 {
09143   rtx operand0;
09144   rtx operand1;
09145   rtx _val = 0;
09146   start_sequence ();
09147 operands[1] = get_pool_constant (XEXP (operands[1], 0));
09148   operand0 = operands[0];
09149   operand1 = operands[1];
09150   emit_insn (gen_rtx_SET (VOIDmode,
09151   operand0,
09152   operand1));
09153   _val = get_insns ();
09154   end_sequence ();
09155   return _val;
09156 }
09157 
09158 /* ../../gcc/gcc/config/i386/i386.md:2851 */
09159 rtx
09160 gen_zero_extendhisi2 (operand0, operand1)
09161      rtx operand0;
09162      rtx operand1;
09163 {
09164   rtx _val = 0;
09165   start_sequence ();
09166   {
09167     rtx operands[2];
09168     operands[0] = operand0;
09169     operands[1] = operand1;
09170 {
09171   if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
09172     {
09173       operands[1] = force_reg (HImode, operands[1]);
09174       emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
09175       DONE;
09176     }
09177 }
09178     operand0 = operands[0];
09179     operand1 = operands[1];
09180   }
09181   emit_insn (gen_rtx_SET (VOIDmode,
09182   operand0,
09183   gen_rtx_ZERO_EXTEND (SImode,
09184   operand1)));
09185   _val = get_insns ();
09186   end_sequence ();
09187   return _val;
09188 }
09189 
09190 /* ../../gcc/gcc/config/i386/i386.md:2873 */
09191 extern rtx gen_split_1080 PARAMS ((rtx *));
09192 rtx
09193 gen_split_1080 (operands)
09194       rtx *operands;
09195 {
09196   rtx operand0;
09197   rtx _val = 0;
09198   start_sequence ();
09199 
09200   operand0 = operands[0];
09201   emit (gen_rtx_PARALLEL (VOIDmode,
09202   gen_rtvec (2,
09203     gen_rtx_SET (VOIDmode,
09204   operand0,
09205   gen_rtx_AND (SImode,
09206   copy_rtx (operand0),
09207   GEN_INT (65535LL))),
09208     gen_rtx_CLOBBER (VOIDmode,
09209   gen_rtx_REG (CCmode,
09210   17)))));
09211   _val = get_insns ();
09212   end_sequence ();
09213   return _val;
09214 }
09215 
09216 /* ../../gcc/gcc/config/i386/i386.md:2890 */
09217 rtx
09218 gen_zero_extendqihi2 (operand0, operand1)
09219      rtx operand0;
09220      rtx operand1;
09221 {
09222   return gen_rtx_PARALLEL (VOIDmode,
09223   gen_rtvec (2,
09224     gen_rtx_SET (VOIDmode,
09225   operand0,
09226   gen_rtx_ZERO_EXTEND (HImode,
09227   operand1)),
09228     gen_rtx_CLOBBER (VOIDmode,
09229   gen_rtx_REG (CCmode,
09230   17))));
09231 }
09232 
09233 /* ../../gcc/gcc/config/i386/i386.md:2925 */
09234 extern rtx gen_split_1082 PARAMS ((rtx *));
09235 rtx
09236 gen_split_1082 (operands)
09237       rtx *operands;
09238 {
09239   rtx operand0;
09240   rtx operand1;
09241   rtx _val = 0;
09242   start_sequence ();
09243   operand0 = operands[0];
09244   operand1 = operands[1];
09245   emit_insn (gen_rtx_SET (VOIDmode,
09246   operand0,
09247   gen_rtx_ZERO_EXTEND (HImode,
09248   operand1)));
09249   _val = get_insns ();
09250   end_sequence ();
09251   return _val;
09252 }
09253 
09254 /* ../../gcc/gcc/config/i386/i386.md:2937 */
09255 extern rtx gen_split_1083 PARAMS ((rtx *));
09256 rtx
09257 gen_split_1083 (operands)
09258       rtx *operands;
09259 {
09260   rtx operand0;
09261   rtx operand1;
09262   rtx operand2;
09263   rtx _val = 0;
09264   start_sequence ();
09265 operands[2] = gen_lowpart (QImode, operands[0]);
09266   operand0 = operands[0];
09267   operand1 = operands[1];
09268   operand2 = operands[2];
09269   emit_insn (gen_rtx_SET (VOIDmode,
09270   operand0,
09271   const0_rtx));
09272   emit_insn (gen_rtx_SET (VOIDmode,
09273   gen_rtx_STRICT_LOW_PART (VOIDmode,
09274   operand2),
09275   operand1));
09276   _val = get_insns ();
09277   end_sequence ();
09278   return _val;
09279 }
09280 
09281 /* ../../gcc/gcc/config/i386/i386.md:2950 */
09282 extern rtx gen_split_1084 PARAMS ((rtx *));
09283 rtx
09284 gen_split_1084 (operands)
09285       rtx *operands;
09286 {
09287   rtx operand0;
09288   rtx _val = 0;
09289   start_sequence ();
09290 
09291   operand0 = operands[0];
09292   emit (gen_rtx_PARALLEL (VOIDmode,
09293   gen_rtvec (2,
09294     gen_rtx_SET (VOIDmode,
09295   operand0,
09296   gen_rtx_AND (HImode,
09297   copy_rtx (operand0),
09298   GEN_INT (255LL))),
09299     gen_rtx_CLOBBER (VOIDmode,
09300   gen_rtx_REG (CCmode,
09301   17)))));
09302   _val = get_insns ();
09303   end_sequence ();
09304   return _val;
09305 }
09306 
09307 /* ../../gcc/gcc/config/i386/i386.md:2960 */
09308 rtx
09309 gen_zero_extendqisi2 (operand0, operand1)
09310      rtx operand0;
09311      rtx operand1;
09312 {
09313   return gen_rtx_PARALLEL (VOIDmode,
09314   gen_rtvec (2,
09315     gen_rtx_SET (VOIDmode,
09316   operand0,
09317   gen_rtx_ZERO_EXTEND (SImode,
09318   operand1)),
09319     gen_rtx_CLOBBER (VOIDmode,
09320   gen_rtx_REG (CCmode,
09321   17))));
09322 }
09323 
09324 /* ../../gcc/gcc/config/i386/i386.md:2995 */
09325 extern rtx gen_split_1086 PARAMS ((rtx *));
09326 rtx
09327 gen_split_1086 (operands)
09328       rtx *operands;
09329 {
09330   rtx operand0;
09331   rtx operand1;
09332   rtx _val = 0;
09333   start_sequence ();
09334   operand0 = operands[0];
09335   operand1 = operands[1];
09336   emit_insn (gen_rtx_SET (VOIDmode,
09337   operand0,
09338   gen_rtx_ZERO_EXTEND (SImode,
09339   operand1)));
09340   _val = get_insns ();
09341   end_sequence ();
09342   return _val;
09343 }
09344 
09345 /* ../../gcc/gcc/config/i386/i386.md:3007 */
09346 extern rtx gen_split_1087 PARAMS ((rtx *));
09347 rtx
09348 gen_split_1087 (operands)
09349       rtx *operands;
09350 {
09351   rtx operand0;
09352   rtx operand1;
09353   rtx operand2;
09354   rtx _val = 0;
09355   start_sequence ();
09356 operands[2] = gen_lowpart (QImode, operands[0]);
09357   operand0 = operands[0];
09358   operand1 = operands[1];
09359   operand2 = operands[2];
09360   emit_insn (gen_rtx_SET (VOIDmode,
09361   operand0,
09362   const0_rtx));
09363   emit_insn (gen_rtx_SET (VOIDmode,
09364   gen_rtx_STRICT_LOW_PART (VOIDmode,
09365   operand2),
09366   operand1));
09367   _val = get_insns ();
09368   end_sequence ();
09369   return _val;
09370 }
09371 
09372 /* ../../gcc/gcc/config/i386/i386.md:3021 */
09373 extern rtx gen_split_1088 PARAMS ((rtx *));
09374 rtx
09375 gen_split_1088 (operands)
09376       rtx *operands;
09377 {
09378   rtx operand0;
09379   rtx _val = 0;
09380   start_sequence ();
09381 
09382   operand0 = operands[0];
09383   emit (gen_rtx_PARALLEL (VOIDmode,
09384   gen_rtvec (2,
09385     gen_rtx_SET (VOIDmode,
09386   operand0,
09387   gen_rtx_AND (SImode,
09388   copy_rtx (operand0),
09389   GEN_INT (255LL))),
09390     gen_rtx_CLOBBER (VOIDmode,
09391   gen_rtx_REG (CCmode,
09392   17)))));
09393   _val = get_insns ();
09394   end_sequence ();
09395   return _val;
09396 }
09397 
09398 /* ../../gcc/gcc/config/i386/i386.md:3032 */
09399 rtx
09400 gen_zero_extendsidi2 (operand0, operand1)
09401      rtx operand0;
09402      rtx operand1;
09403 {
09404   rtx _val = 0;
09405   start_sequence ();
09406   {
09407     rtx operands[2];
09408     operands[0] = operand0;
09409     operands[1] = operand1;
09410 if (!TARGET_64BIT)
09411      {
09412        emit_insn (gen_zero_extendsidi2_32 (operands[0], operands[1]));
09413        DONE;
09414      }
09415   
09416     operand0 = operands[0];
09417     operand1 = operands[1];
09418   }
09419   emit_insn (gen_rtx_SET (VOIDmode,
09420   operand0,
09421   gen_rtx_ZERO_EXTEND (DImode,
09422   operand1)));
09423   _val = get_insns ();
09424   end_sequence ();
09425   return _val;
09426 }
09427 
09428 /* ../../gcc/gcc/config/i386/i386.md:3061 */
09429 extern rtx gen_split_1090 PARAMS ((rtx *));
09430 rtx
09431 gen_split_1090 (operands)
09432       rtx *operands;
09433 {
09434   rtx operand0;
09435   rtx operand1;
09436   rtx operand2;
09437   rtx operand3;
09438   rtx operand4;
09439   rtx _val = 0;
09440   start_sequence ();
09441 split_di (&operands[0], 1, &operands[3], &operands[4]);
09442   operand0 = operands[0];
09443   operand1 = operands[1];
09444   operand2 = operands[2];
09445   operand3 = operands[3];
09446   operand4 = operands[4];
09447   emit_insn (gen_rtx_SET (VOIDmode,
09448   operand4,
09449   const0_rtx));
09450   _val = get_insns ();
09451   end_sequence ();
09452   return _val;
09453 }
09454 
09455 /* ../../gcc/gcc/config/i386/i386.md:3068 */
09456 extern rtx gen_split_1091 PARAMS ((rtx *));
09457 rtx
09458 gen_split_1091 (operands)
09459       rtx *operands;
09460 {
09461   rtx operand0;
09462   rtx operand1;
09463   rtx operand2;
09464   rtx operand3;
09465   rtx operand4;
09466   rtx _val = 0;
09467   start_sequence ();
09468 split_di (&operands[0], 1, &operands[3], &operands[4]);
09469   operand0 = operands[0];
09470   operand1 = operands[1];
09471   operand2 = operands[2];
09472   operand3 = operands[3];
09473   operand4 = operands[4];
09474   emit_insn (gen_rtx_SET (VOIDmode,
09475   operand4,
09476   const0_rtx));
09477   _val = get_insns ();
09478   end_sequence ();
09479   return _val;
09480 }
09481 
09482 /* ../../gcc/gcc/config/i386/i386.md:3077 */
09483 extern rtx gen_split_1092 PARAMS ((rtx *));
09484 rtx
09485 gen_split_1092 (operands)
09486       rtx *operands;
09487 {
09488   rtx operand0;
09489   rtx operand1;
09490   rtx operand2;
09491   rtx operand3;
09492   rtx operand4;
09493   rtx _val = 0;
09494   start_sequence ();
09495 split_di (&operands[0], 1, &operands[3], &operands[4]);
09496   operand0 = operands[0];
09497   operand1 = operands[1];
09498   operand2 = operands[2];
09499   operand3 = operands[3];
09500   operand4 = operands[4];
09501   emit_insn (gen_rtx_SET (VOIDmode,
09502   operand3,
09503   operand1));
09504   emit_insn (gen_rtx_SET (VOIDmode,
09505   operand4,
09506   const0_rtx));
09507   _val = get_insns ();
09508   end_sequence ();
09509   return _val;
09510 }
09511 
09512 /* ../../gcc/gcc/config/i386/i386.md:3108 */
09513 rtx
09514 gen_extendsidi2 (operand0, operand1)
09515      rtx operand0;
09516      rtx operand1;
09517 {
09518   rtx operand2 ATTRIBUTE_UNUSED;
09519   rtx _val = 0;
09520   start_sequence ();
09521   {
09522     rtx operands[3];
09523     operands[0] = operand0;
09524     operands[1] = operand1;
09525 {
09526   if (TARGET_64BIT)
09527     {
09528       emit_insn (gen_extendsidi2_rex64 (operands[0], operands[1]));
09529       DONE;
09530     }
09531 }
09532     operand0 = operands[0];
09533     operand1 = operands[1];
09534     operand2 = operands[2];
09535   }
09536   emit (gen_rtx_PARALLEL (VOIDmode,
09537   gen_rtvec (3,
09538     gen_rtx_SET (VOIDmode,
09539   operand0,
09540   gen_rtx_SIGN_EXTEND (DImode,
09541   operand1)),
09542     gen_rtx_CLOBBER (VOIDmode,
09543   gen_rtx_REG (CCmode,
09544   17)),
09545     gen_rtx_CLOBBER (VOIDmode,
09546   gen_rtx_SCRATCH (SImode)))));
09547   _val = get_insns ();
09548   end_sequence ();
09549   return _val;
09550 }
09551 
09552 /* ../../gcc/gcc/config/i386/i386.md:3159 */
09553 extern rtx gen_split_1094 PARAMS ((rtx *));
09554 rtx
09555 gen_split_1094 (operands)
09556       rtx *operands;
09557 {
09558   rtx operand0;
09559   rtx operand1;
09560   rtx operand2;
09561   rtx operand3;
09562   rtx operand4;
09563   rtx _val = 0;
09564   start_sequence ();
09565 split_di (&operands[0], 1, &operands[3], &operands[4]);
09566   operand0 = operands[0];
09567   operand1 = operands[1];
09568   operand2 = operands[2];
09569   operand3 = operands[3];
09570   operand4 = operands[4];
09571   emit_insn (gen_rtx_SET (VOIDmode,
09572   operand3,
09573   operand1));
09574   emit (gen_rtx_PARALLEL (VOIDmode,
09575   gen_rtvec (2,
09576     gen_rtx_SET (VOIDmode,
09577   copy_rtx (operand1),
09578   gen_rtx_ASHIFTRT (SImode,
09579   copy_rtx (operand1),
09580   GEN_INT (31LL))),
09581     gen_rtx_CLOBBER (VOIDmode,
09582   gen_rtx_REG (CCmode,
09583   17)))));
09584   emit_insn (gen_rtx_SET (VOIDmode,
09585   operand4,
09586   copy_rtx (operand1)));
09587   _val = get_insns ();
09588   end_sequence ();
09589   return _val;
09590 }
09591 
09592 /* ../../gcc/gcc/config/i386/i386.md:3174 */
09593 extern rtx gen_split_1095 PARAMS ((rtx *));
09594 rtx
09595 gen_split_1095 (operands)
09596       rtx *operands ATTRIBUTE_UNUSED;
09597 {
09598   rtx _val = 0;
09599   start_sequence ();
09600 {
09601   split_di (&operands[0], 1, &operands[3], &operands[4]);
09602 
09603   emit_move_insn (operands[3], operands[1]);
09604 
09605   /* Generate a cltd if possible and doing so it profitable.  */
09606   if (true_regnum (operands[1]) == 0
09607       && true_regnum (operands[2]) == 1
09608       && (optimize_size || TARGET_USE_CLTD))
09609     {
09610       emit_insn (gen_ashrsi3_31 (operands[2], operands[1], GEN_INT (31)));
09611     }
09612   else
09613     {
09614       emit_move_insn (operands[2], operands[1]);
09615       emit_insn (gen_ashrsi3_31 (operands[2], operands[2], GEN_INT (31)));
09616     }
09617   emit_move_insn (operands[4], operands[2]);
09618   DONE;
09619 }
09620   emit_insn (const0_rtx);
09621   _val = get_insns ();
09622   end_sequence ();
09623   return _val;
09624 }
09625 
09626 /* ../../gcc/gcc/config/i386/i386.md:3204 */
09627 extern rtx gen_split_1096 PARAMS ((rtx *));
09628 rtx
09629 gen_split_1096 (operands)
09630       rtx *operands ATTRIBUTE_UNUSED;
09631 {
09632   rtx _val = 0;
09633   start_sequence ();
09634 {
09635   split_di (&operands[0], 1, &operands[3], &operands[4]);
09636 
09637   if (true_regnum (operands[3]) != true_regnum (operands[1]))
09638     emit_move_insn (operands[3], operands[1]);
09639 
09640   /* Generate a cltd if possible and doing so it profitable.  */
09641   if (true_regnum (operands[3]) == 0
09642       && (optimize_size || TARGET_USE_CLTD))
09643     {
09644       emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
09645       DONE;
09646     }
09647 
09648   if (true_regnum (operands[4]) != true_regnum (operands[1]))
09649     emit_move_insn (operands[4], operands[1]);
09650 
09651   emit_insn (gen_ashrsi3_31 (operands[4], operands[4], GEN_INT (31)));
09652   DONE;
09653 }
09654   emit_insn (const0_rtx);
09655   _val = get_insns ();
09656   end_sequence ();
09657   return _val;
09658 }
09659 
09660 /* ../../gcc/gcc/config/i386/i386.md:3340 */
09661 extern rtx gen_split_1097 PARAMS ((rtx *));
09662 rtx
09663 gen_split_1097 (operands)
09664       rtx *operands;
09665 {
09666   rtx operand0;
09667   rtx operand1;
09668   rtx _val = 0;
09669   start_sequence ();
09670   operand0 = operands[0];
09671   operand1 = operands[1];
09672   emit_insn (gen_rtx_SET (VOIDmode,
09673   gen_rtx_REG (SImode,
09674   7),
09675   gen_rtx_PLUS (SImode,
09676   gen_rtx_REG (SImode,
09677   7),
09678   GEN_INT (-8LL))));
09679   emit_insn (gen_rtx_SET (VOIDmode,
09680   gen_rtx_MEM (DFmode,
09681   gen_rtx_REG (SImode,
09682   7)),
09683   gen_rtx_FLOAT_EXTEND (DFmode,
09684   operand1)));
09685   _val = get_insns ();
09686   end_sequence ();
09687   return _val;
09688 }
09689 
09690 /* ../../gcc/gcc/config/i386/i386.md:3347 */
09691 extern rtx gen_split_1098 PARAMS ((rtx *));
09692 rtx
09693 gen_split_1098 (operands)
09694       rtx *operands;
09695 {
09696   rtx operand0;
09697   rtx operand1;
09698   rtx _val = 0;
09699   start_sequence ();
09700   operand0 = operands[0];
09701   operand1 = operands[1];
09702   emit_insn (gen_rtx_SET (VOIDmode,
09703   gen_rtx_REG (DImode,
09704   7),
09705   gen_rtx_PLUS (DImode,
09706   gen_rtx_REG (DImode,
09707   7),
09708   GEN_INT (-8LL))));
09709   emit_insn (gen_rtx_SET (VOIDmode,
09710   gen_rtx_MEM (DFmode,
09711   gen_rtx_REG (DImode,
09712   7)),
09713   gen_rtx_FLOAT_EXTEND (DFmode,
09714   operand1)));
09715   _val = get_insns ();
09716   end_sequence ();
09717   return _val;
09718 }
09719 
09720 /* ../../gcc/gcc/config/i386/i386.md:3360 */
09721 extern rtx gen_split_1099 PARAMS ((rtx *));
09722 rtx
09723 gen_split_1099 (operands)
09724       rtx *operands;
09725 {
09726   rtx operand0;
09727   rtx operand1;
09728   rtx _val = 0;
09729   start_sequence ();
09730   operand0 = operands[0];
09731   operand1 = operands[1];
09732   emit_insn (gen_rtx_SET (VOIDmode,
09733   gen_rtx_REG (SImode,
09734   7),
09735   gen_rtx_PLUS (SImode,
09736   gen_rtx_REG (SImode,
09737   7),
09738   GEN_INT (-12LL))));
09739   emit_insn (gen_rtx_SET (VOIDmode,
09740   gen_rtx_MEM (XFmode,
09741   gen_rtx_REG (SImode,
09742   7)),
09743   gen_rtx_FLOAT_EXTEND (XFmode,
09744   operand1)));
09745   _val = get_insns ();
09746   end_sequence ();
09747   return _val;
09748 }
09749 
09750 /* ../../gcc/gcc/config/i386/i386.md:3373 */
09751 extern rtx gen_split_1100 PARAMS ((rtx *));
09752 rtx
09753 gen_split_1100 (operands)
09754       rtx *operands;
09755 {
09756   rtx operand0;
09757   rtx operand1;
09758   rtx _val = 0;
09759   start_sequence ();
09760   operand0 = operands[0];
09761   operand1 = operands[1];
09762   emit_insn (gen_rtx_SET (VOIDmode,
09763   gen_rtx_REG (SImode,
09764   7),
09765   gen_rtx_PLUS (SImode,
09766   gen_rtx_REG (SImode,
09767   7),
09768   GEN_INT (-16LL))));
09769   emit_insn (gen_rtx_SET (VOIDmode,
09770   gen_rtx_MEM (TFmode,
09771   gen_rtx_REG (SImode,
09772   7)),
09773   gen_rtx_FLOAT_EXTEND (TFmode,
09774   operand1)));
09775   _val = get_insns ();
09776   end_sequence ();
09777   return _val;
09778 }
09779 
09780 /* ../../gcc/gcc/config/i386/i386.md:3380 */
09781 extern rtx gen_split_1101 PARAMS ((rtx *));
09782 rtx
09783 gen_split_1101 (operands)
09784       rtx *operands;
09785 {
09786   rtx operand0;
09787   rtx operand1;
09788   rtx _val = 0;
09789   start_sequence ();
09790   operand0 = operands[0];
09791   operand1 = operands[1];
09792   emit_insn (gen_rtx_SET (VOIDmode,
09793   gen_rtx_REG (DImode,
09794   7),
09795   gen_rtx_PLUS (DImode,
09796   gen_rtx_REG (DImode,
09797   7),
09798   GEN_INT (-16LL))));
09799   emit_insn (gen_rtx_SET (VOIDmode,
09800   gen_rtx_MEM (DFmode,
09801   gen_rtx_REG (DImode,
09802   7)),
09803   gen_rtx_FLOAT_EXTEND (TFmode,
09804   operand1)));
09805   _val = get_insns ();
09806   end_sequence ();
09807   return _val;
09808 }
09809 
09810 /* ../../gcc/gcc/config/i386/i386.md:3393 */
09811 extern rtx gen_split_1102 PARAMS ((rtx *));
09812 rtx
09813 gen_split_1102 (operands)
09814       rtx *operands;
09815 {
09816   rtx operand0;
09817   rtx operand1;
09818   rtx _val = 0;
09819   start_sequence ();
09820   operand0 = operands[0];
09821   operand1 = operands[1];
09822   emit_insn (gen_rtx_SET (VOIDmode,
09823   gen_rtx_REG (SImode,
09824   7),
09825   gen_rtx_PLUS (SImode,
09826   gen_rtx_REG (SImode,
09827   7),
09828   GEN_INT (-12LL))));
09829   emit_insn (gen_rtx_SET (VOIDmode,
09830   gen_rtx_MEM (DFmode,
09831   gen_rtx_REG (SImode,
09832   7)),
09833   gen_rtx_FLOAT_EXTEND (XFmode,
09834   operand1)));
09835   _val = get_insns ();
09836   end_sequence ();
09837   return _val;
09838 }
09839 
09840 /* ../../gcc/gcc/config/i386/i386.md:3406 */
09841 extern rtx gen_split_1103 PARAMS ((rtx *));
09842 rtx
09843 gen_split_1103 (operands)
09844       rtx *operands;
09845 {
09846   rtx operand0;
09847   rtx operand1;
09848   rtx _val = 0;
09849   start_sequence ();
09850   operand0 = operands[0];
09851   operand1 = operands[1];
09852   emit_insn (gen_rtx_SET (VOIDmode,
09853   gen_rtx_REG (SImode,
09854   7),
09855   gen_rtx_PLUS (SImode,
09856   gen_rtx_REG (SImode,
09857   7),
09858   GEN_INT (-16LL))));
09859   emit_insn (gen_rtx_SET (VOIDmode,
09860   gen_rtx_MEM (TFmode,
09861   gen_rtx_REG (SImode,
09862   7)),
09863   gen_rtx_FLOAT_EXTEND (XFmode,
09864   operand1)));
09865   _val = get_insns ();
09866   end_sequence ();
09867   return _val;
09868 }
09869 
09870 /* ../../gcc/gcc/config/i386/i386.md:3413 */
09871 extern rtx gen_split_1104 PARAMS ((rtx *));
09872 rtx
09873 gen_split_1104 (operands)
09874       rtx *operands;
09875 {
09876   rtx operand0;
09877   rtx operand1;
09878   rtx _val = 0;
09879   start_sequence ();
09880   operand0 = operands[0];
09881   operand1 = operands[1];
09882   emit_insn (gen_rtx_SET (VOIDmode,
09883   gen_rtx_REG (DImode,
09884   7),
09885   gen_rtx_PLUS (DImode,
09886   gen_rtx_REG (DImode,
09887   7),
09888   GEN_INT (-16LL))));
09889   emit_insn (gen_rtx_SET (VOIDmode,
09890   gen_rtx_MEM (TFmode,
09891   gen_rtx_REG (DImode,
09892   7)),
09893   gen_rtx_FLOAT_EXTEND (TFmode,
09894   operand1)));
09895   _val = get_insns ();
09896   end_sequence ();
09897   return _val;
09898 }
09899 
09900 /* ../../gcc/gcc/config/i386/i386.md:3420 */
09901 rtx
09902 gen_extendsfdf2 (operand0, operand1)
09903      rtx operand0;
09904      rtx operand1;
09905 {
09906   rtx _val = 0;
09907   start_sequence ();
09908   {
09909     rtx operands[2];
09910     operands[0] = operand0;
09911     operands[1] = operand1;
09912 {
09913   /* ??? Needed for compress_float_constant since all fp constants
09914      are LEGITIMATE_CONSTANT_P.  */
09915   if (GET_CODE (operands[1]) == CONST_DOUBLE)
09916     operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
09917   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
09918     operands[1] = force_reg (SFmode, operands[1]);
09919 }
09920     operand0 = operands[0];
09921     operand1 = operands[1];
09922   }
09923   emit_insn (gen_rtx_SET (VOIDmode,
09924   operand0,
09925   gen_rtx_FLOAT_EXTEND (DFmode,
09926   operand1)));
09927   _val = get_insns ();
09928   end_sequence ();
09929   return _val;
09930 }
09931 
09932 /* ../../gcc/gcc/config/i386/i386.md:3475 */
09933 rtx
09934 gen_extendsfxf2 (operand0, operand1)
09935      rtx operand0;
09936      rtx operand1;
09937 {
09938   rtx _val = 0;
09939   start_sequence ();
09940   {
09941     rtx operands[2];
09942     operands[0] = operand0;
09943     operands[1] = operand1;
09944 {
09945   /* ??? Needed for compress_float_constant since all fp constants
09946      are LEGITIMATE_CONSTANT_P.  */
09947   if (GET_CODE (operands[1]) == CONST_DOUBLE)
09948     operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
09949   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
09950     operands[1] = force_reg (SFmode, operands[1]);
09951 }
09952     operand0 = operands[0];
09953     operand1 = operands[1];
09954   }
09955   emit_insn (gen_rtx_SET (VOIDmode,
09956   operand0,
09957   gen_rtx_FLOAT_EXTEND (XFmode,
09958   operand1)));
09959   _val = get_insns ();
09960   end_sequence ();
09961   return _val;
09962 }
09963 
09964 /* ../../gcc/gcc/config/i386/i386.md:3520 */
09965 rtx
09966 gen_extendsftf2 (operand0, operand1)
09967      rtx operand0;
09968      rtx operand1;
09969 {
09970   rtx _val = 0;
09971   start_sequence ();
09972   {
09973     rtx operands[2];
09974     operands[0] = operand0;
09975     operands[1] = operand1;
09976 {
09977   /* ??? Needed for compress_float_constant since all fp constants
09978      are LEGITIMATE_CONSTANT_P.  */
09979   if (GET_CODE (operands[1]) == CONST_DOUBLE)
09980     operands[1] = validize_mem (force_const_mem (SFmode, operands[1]));
09981   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
09982     operands[1] = force_reg (SFmode, operands[1]);
09983 }
09984     operand0 = operands[0];
09985     operand1 = operands[1];
09986   }
09987   emit_insn (gen_rtx_SET (VOIDmode,
09988   operand0,
09989   gen_rtx_FLOAT_EXTEND (TFmode,
09990   operand1)));
09991   _val = get_insns ();
09992   end_sequence ();
09993   return _val;
09994 }
09995 
09996 /* ../../gcc/gcc/config/i386/i386.md:3565 */
09997 rtx
09998 gen_extenddfxf2 (operand0, operand1)
09999      rtx operand0;
10000      rtx operand1;
10001 {
10002   rtx _val = 0;
10003   start_sequence ();
10004   {
10005     rtx operands[2];
10006     operands[0] = operand0;
10007     operands[1] = operand1;
10008 {
10009   /* ??? Needed for compress_float_constant since all fp constants
10010      are LEGITIMATE_CONSTANT_P.  */
10011   if (GET_CODE (operands[1]) == CONST_DOUBLE)
10012     operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
10013   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
10014     operands[1] = force_reg (DFmode, operands[1]);
10015 }
10016     operand0 = operands[0];
10017     operand1 = operands[1];
10018   }
10019   emit_insn (gen_rtx_SET (VOIDmode,
10020   operand0,
10021   gen_rtx_FLOAT_EXTEND (XFmode,
10022   operand1)));
10023   _val = get_insns ();
10024   end_sequence ();
10025   return _val;
10026 }
10027 
10028 /* ../../gcc/gcc/config/i386/i386.md:3610 */
10029 rtx
10030 gen_extenddftf2 (operand0, operand1)
10031      rtx operand0;
10032      rtx operand1;
10033 {
10034   rtx _val = 0;
10035   start_sequence ();
10036   {
10037     rtx operands[2];
10038     operands[0] = operand0;
10039     operands[1] = operand1;
10040 {
10041   /* ??? Needed for compress_float_constant since all fp constants
10042      are LEGITIMATE_CONSTANT_P.  */
10043   if (GET_CODE (operands[1]) == CONST_DOUBLE)
10044     operands[1] = validize_mem (force_const_mem (DFmode, operands[1]));
10045   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
10046     operands[1] = force_reg (DFmode, operands[1]);
10047 }
10048     operand0 = operands[0];
10049     operand1 = operands[1];
10050   }
10051   emit_insn (gen_rtx_SET (VOIDmode,
10052   operand0,
10053   gen_rtx_FLOAT_EXTEND (TFmode,
10054   operand1)));
10055   _val = get_insns ();
10056   end_sequence ();
10057   return _val;
10058 }
10059 
10060 /* ../../gcc/gcc/config/i386/i386.md:3661 */
10061 rtx
10062 gen_truncdfsf2 (operand0, operand1)
10063      rtx operand0;
10064      rtx operand1;
10065 {
10066   rtx operand2;
10067   rtx _val = 0;
10068   start_sequence ();
10069   {
10070     rtx operands[3];
10071     operands[0] = operand0;
10072     operands[1] = operand1;
10073 
10074    if (TARGET_80387)
10075      operands[2] = assign_386_stack_local (SFmode, 0);
10076    else
10077      {
10078   emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
10079   DONE;
10080      }
10081 
10082     operand0 = operands[0];
10083     operand1 = operands[1];
10084     operand2 = operands[2];
10085   }
10086   emit (gen_rtx_PARALLEL (VOIDmode,
10087   gen_rtvec (2,
10088     gen_rtx_SET (VOIDmode,
10089   operand0,
10090   gen_rtx_FLOAT_TRUNCATE (SFmode,
10091   operand1)),
10092     gen_rtx_CLOBBER (VOIDmode,
10093   operand2))));
10094   _val = get_insns ();
10095   end_sequence ();
10096   return _val;
10097 }
10098 
10099 /* ../../gcc/gcc/config/i386/i386.md:3767 */
10100 extern rtx gen_split_1111 PARAMS ((rtx *));
10101 rtx
10102 gen_split_1111 (operands)
10103       rtx *operands;
10104 {
10105   rtx operand0;
10106   rtx operand1;
10107   rtx _val = 0;
10108   start_sequence ();
10109 
10110   operand0 = operands[0];
10111   operand1 = operands[1];
10112   emit_insn (gen_rtx_SET (VOIDmode,
10113   operand0,
10114   gen_rtx_FLOAT_TRUNCATE (SFmode,
10115   operand1)));
10116   _val = get_insns ();
10117   end_sequence ();
10118   return _val;
10119 }
10120 
10121 /* ../../gcc/gcc/config/i386/i386.md:3776 */
10122 extern rtx gen_split_1112 PARAMS ((rtx *));
10123 rtx
10124 gen_split_1112 (operands)
10125       rtx *operands;
10126 {
10127   rtx operand0;
10128   rtx operand1;
10129   rtx _val = 0;
10130   start_sequence ();
10131 
10132   operand0 = operands[0];
10133   operand1 = operands[1];
10134   emit_insn (gen_rtx_SET (VOIDmode,
10135   operand0,
10136   gen_rtx_FLOAT_TRUNCATE (SFmode,
10137   operand1)));
10138   _val = get_insns ();
10139   end_sequence ();
10140   return _val;
10141 }
10142 
10143 /* ../../gcc/gcc/config/i386/i386.md:3786 */
10144 extern rtx gen_split_1113 PARAMS ((rtx *));
10145 rtx
10146 gen_split_1113 (operands)
10147       rtx *operands;
10148 {
10149   rtx operand0;
10150   rtx operand1;
10151   rtx operand2;
10152   rtx _val = 0;
10153   start_sequence ();
10154 
10155   operand0 = operands[0];
10156   operand1 = operands[1];
10157   operand2 = operands[2];
10158   emit_insn (gen_rtx_SET (VOIDmode,
10159   operand2,
10160   gen_rtx_FLOAT_TRUNCATE (SFmode,
10161   operand1)));
10162   emit_insn (gen_rtx_SET (VOIDmode,
10163   operand0,
10164   copy_rtx (operand2)));
10165   _val = get_insns ();
10166   end_sequence ();
10167   return _val;
10168 }
10169 
10170 /* ../../gcc/gcc/config/i386/i386.md:3796 */
10171 rtx
10172 gen_truncxfsf2 (operand0, operand1)
10173      rtx operand0;
10174      rtx operand1;
10175 {
10176   rtx operand2;
10177   rtx _val = 0;
10178   start_sequence ();
10179   {
10180     rtx operands[3];
10181     operands[0] = operand0;
10182     operands[1] = operand1;
10183 operands[2] = assign_386_stack_local (SFmode, 0);
10184     operand0 = operands[0];
10185     operand1 = operands[1];
10186     operand2 = operands[2];
10187   }
10188   emit (gen_rtx_PARALLEL (VOIDmode,
10189   gen_rtvec (2,
10190     gen_rtx_SET (VOIDmode,
10191   operand0,
10192   gen_rtx_FLOAT_TRUNCATE (SFmode,
10193   operand1)),
10194     gen_rtx_CLOBBER (VOIDmode,
10195   operand2))));
10196   _val = get_insns ();
10197   end_sequence ();
10198   return _val;
10199 }
10200 
10201 /* ../../gcc/gcc/config/i386/i386.md:3839 */
10202 extern rtx gen_split_1115 PARAMS ((rtx *));
10203 rtx
10204 gen_split_1115 (operands)
10205       rtx *operands;
10206 {
10207   rtx operand0;
10208   rtx operand1;
10209   rtx _val = 0;
10210   start_sequence ();
10211 
10212   operand0 = operands[0];
10213   operand1 = operands[1];
10214   emit_insn (gen_rtx_SET (VOIDmode,
10215   operand0,
10216   gen_rtx_FLOAT_TRUNCATE (SFmode,
10217   operand1)));
10218   _val = get_insns ();
10219   end_sequence ();
10220   return _val;
10221 }
10222 
10223 /* ../../gcc/gcc/config/i386/i386.md:3848 */
10224 extern rtx gen_split_1116 PARAMS ((rtx *));
10225 rtx
10226 gen_split_1116 (operands)
10227       rtx *operands;
10228 {
10229   rtx operand0;
10230   rtx operand1;
10231   rtx operand2;
10232   rtx _val = 0;
10233   start_sequence ();
10234 
10235   operand0 = operands[0];
10236   operand1 = operands[1];
10237   operand2 = operands[2];
10238   emit_insn (gen_rtx_SET (VOIDmode,
10239   operand2,
10240   gen_rtx_FLOAT_TRUNCATE (SFmode,
10241   operand1)));
10242   emit_insn (gen_rtx_SET (VOIDmode,
10243   operand0,
10244   copy_rtx (operand2)));
10245   _val = get_insns ();
10246   end_sequence ();
10247   return _val;
10248 }
10249 
10250 /* ../../gcc/gcc/config/i386/i386.md:3858 */
10251 rtx
10252 gen_trunctfsf2 (operand0, operand1)
10253      rtx operand0;
10254      rtx operand1;
10255 {
10256   rtx operand2;
10257   rtx _val = 0;
10258   start_sequence ();
10259   {
10260     rtx operands[3];
10261     operands[0] = operand0;
10262     operands[1] = operand1;
10263 operands[2] = assign_386_stack_local (SFmode, 0);
10264     operand0 = operands[0];
10265     operand1 = operands[1];
10266     operand2 = operands[2];
10267   }
10268   emit (gen_rtx_PARALLEL (VOIDmode,
10269   gen_rtvec (2,
10270     gen_rtx_SET (VOIDmode,
10271   operand0,
10272   gen_rtx_FLOAT_TRUNCATE (SFmode,
10273   operand1)),
10274     gen_rtx_CLOBBER (VOIDmode,
10275   operand2))));
10276   _val = get_insns ();
10277   end_sequence ();
10278   return _val;
10279 }
10280 
10281 /* ../../gcc/gcc/config/i386/i386.md:3901 */
10282 extern rtx gen_split_1118 PARAMS ((rtx *));
10283 rtx
10284 gen_split_1118 (operands)
10285       rtx *operands;
10286 {
10287   rtx operand0;
10288   rtx operand1;
10289   rtx _val = 0;
10290   start_sequence ();
10291 
10292   operand0 = operands[0];
10293   operand1 = operands[1];
10294   emit_insn (gen_rtx_SET (VOIDmode,
10295   operand0,
10296   gen_rtx_FLOAT_TRUNCATE (SFmode,
10297   operand1)));
10298   _val = get_insns ();
10299   end_sequence ();
10300   return _val;
10301 }
10302 
10303 /* ../../gcc/gcc/config/i386/i386.md:3910 */
10304 extern rtx gen_split_1119 PARAMS ((rtx *));
10305 rtx
10306 gen_split_1119 (operands)
10307       rtx *operands;
10308 {
10309   rtx operand0;
10310   rtx operand1;
10311   rtx operand2;
10312   rtx _val = 0;
10313   start_sequence ();
10314 
10315   operand0 = operands[0];
10316   operand1 = operands[1];
10317   operand2 = operands[2];
10318   emit_insn (gen_rtx_SET (VOIDmode,
10319   operand2,
10320   gen_rtx_FLOAT_TRUNCATE (SFmode,
10321   operand1)));
10322   emit_insn (gen_rtx_SET (VOIDmode,
10323   operand0,
10324   copy_rtx (operand2)));
10325   _val = get_insns ();
10326   end_sequence ();
10327   return _val;
10328 }
10329 
10330 /* ../../gcc/gcc/config/i386/i386.md:3921 */
10331 rtx
10332 gen_truncxfdf2 (operand0, operand1)
10333      rtx operand0;
10334      rtx operand1;
10335 {
10336   rtx operand2;
10337   rtx _val = 0;
10338   start_sequence ();
10339   {
10340     rtx operands[3];
10341     operands[0] = operand0;
10342     operands[1] = operand1;
10343 operands[2] = assign_386_stack_local (DFmode, 0);
10344     operand0 = operands[0];
10345     operand1 = operands[1];
10346     operand2 = operands[2];
10347   }
10348   emit (gen_rtx_PARALLEL (VOIDmode,
10349   gen_rtvec (2,
10350     gen_rtx_SET (VOIDmode,
10351   operand0,
10352   gen_rtx_FLOAT_TRUNCATE (DFmode,
10353   operand1)),
10354     gen_rtx_CLOBBER (VOIDmode,
10355   operand2))));
10356   _val = get_insns ();
10357   end_sequence ();
10358   return _val;
10359 }
10360 
10361 /* ../../gcc/gcc/config/i386/i386.md:3965 */
10362 extern rtx gen_split_1121 PARAMS ((rtx *));
10363 rtx
10364 gen_split_1121 (operands)
10365       rtx *operands;
10366 {
10367   rtx operand0;
10368   rtx operand1;
10369   rtx _val = 0;
10370   start_sequence ();
10371 
10372   operand0 = operands[0];
10373   operand1 = operands[1];
10374   emit_insn (gen_rtx_SET (VOIDmode,
10375   operand0,
10376   gen_rtx_FLOAT_TRUNCATE (DFmode,
10377   operand1)));
10378   _val = get_insns ();
10379   end_sequence ();
10380   return _val;
10381 }
10382 
10383 /* ../../gcc/gcc/config/i386/i386.md:3974 */
10384 extern rtx gen_split_1122 PARAMS ((rtx *));
10385 rtx
10386 gen_split_1122 (operands)
10387       rtx *operands;
10388 {
10389   rtx operand0;
10390   rtx operand1;
10391   rtx operand2;
10392   rtx _val = 0;
10393   start_sequence ();
10394 
10395   operand0 = operands[0];
10396   operand1 = operands[1];
10397   operand2 = operands[2];
10398   emit_insn (gen_rtx_SET (VOIDmode,
10399   operand2,
10400   gen_rtx_FLOAT_TRUNCATE (DFmode,
10401   operand1)));
10402   emit_insn (gen_rtx_SET (VOIDmode,
10403   operand0,
10404   copy_rtx (operand2)));
10405   _val = get_insns ();
10406   end_sequence ();
10407   return _val;
10408 }
10409 
10410 /* ../../gcc/gcc/config/i386/i386.md:3984 */
10411 rtx
10412 gen_trunctfdf2 (operand0, operand1)
10413      rtx operand0;
10414      rtx operand1;
10415 {
10416   rtx operand2;
10417   rtx _val = 0;
10418   start_sequence ();
10419   {
10420     rtx operands[3];
10421     operands[0] = operand0;
10422     operands[1] = operand1;
10423 operands[2] = assign_386_stack_local (DFmode, 0);
10424     operand0 = operands[0];
10425     operand1 = operands[1];
10426     operand2 = operands[2];
10427   }
10428   emit (gen_rtx_PARALLEL (VOIDmode,
10429   gen_rtvec (2,
10430     gen_rtx_SET (VOIDmode,
10431   operand0,
10432   gen_rtx_FLOAT_TRUNCATE (DFmode,
10433   operand1)),
10434     gen_rtx_CLOBBER (VOIDmode,
10435   operand2))));
10436   _val = get_insns ();
10437   end_sequence ();
10438   return _val;
10439 }
10440 
10441 /* ../../gcc/gcc/config/i386/i386.md:4028 */
10442 extern rtx gen_split_1124 PARAMS ((rtx *));
10443 rtx
10444 gen_split_1124 (operands)
10445       rtx *operands;
10446 {
10447   rtx operand0;
10448   rtx operand1;
10449   rtx _val = 0;
10450   start_sequence ();
10451 
10452   operand0 = operands[0];
10453   operand1 = operands[1];
10454   emit_insn (gen_rtx_SET (VOIDmode,
10455   operand0,
10456   gen_rtx_FLOAT_TRUNCATE (DFmode,
10457   operand1)));
10458   _val = get_insns ();
10459   end_sequence ();
10460   return _val;
10461 }
10462 
10463 /* ../../gcc/gcc/config/i386/i386.md:4037 */
10464 extern rtx gen_split_1125 PARAMS ((rtx *));
10465 rtx
10466 gen_split_1125 (operands)
10467       rtx *operands;
10468 {
10469   rtx operand0;
10470   rtx operand1;
10471   rtx operand2;
10472   rtx _val = 0;
10473   start_sequence ();
10474 
10475   operand0 = operands[0];
10476   operand1 = operands[1];
10477   operand2 = operands[2];
10478   emit_insn (gen_rtx_SET (VOIDmode,
10479   operand2,
10480   gen_rtx_FLOAT_TRUNCATE (DFmode,
10481   operand1)));
10482   emit_insn (gen_rtx_SET (VOIDmode,
10483   operand0,
10484   copy_rtx (operand2)));
10485   _val = get_insns ();
10486   end_sequence ();
10487   return _val;
10488 }
10489 
10490 /* ../../gcc/gcc/config/i386/i386.md:4052 */
10491 rtx
10492 gen_fix_truncxfdi2 (operand0, operand1)
10493      rtx operand0;
10494      rtx operand1;
10495 {
10496   return gen_rtx_SET (VOIDmode,
10497   operand0,
10498   gen_rtx_FIX (DImode,
10499   operand1));
10500 }
10501 
10502 /* ../../gcc/gcc/config/i386/i386.md:4058 */
10503 rtx
10504 gen_fix_trunctfdi2 (operand0, operand1)
10505      rtx operand0;
10506      rtx operand1;
10507 {
10508   return gen_rtx_SET (VOIDmode,
10509   operand0,
10510   gen_rtx_FIX (DImode,
10511   operand1));
10512 }
10513 
10514 /* ../../gcc/gcc/config/i386/i386.md:4064 */
10515 rtx
10516 gen_fix_truncdfdi2 (operand0, operand1)
10517      rtx operand0;
10518      rtx operand1;
10519 {
10520   rtx _val = 0;
10521   start_sequence ();
10522   {
10523     rtx operands[2];
10524     operands[0] = operand0;
10525     operands[1] = operand1;
10526 {
10527   if (TARGET_64BIT && TARGET_SSE2)
10528    {
10529      rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
10530      emit_insn (gen_fix_truncdfdi_sse (out, operands[1]));
10531      if (out != operands[0])
10532   emit_move_insn (operands[0], out);
10533      DONE;
10534    }
10535 }
10536     operand0 = operands[0];
10537     operand1 = operands[1];
10538   }
10539   emit_insn (gen_rtx_SET (VOIDmode,
10540   operand0,
10541   gen_rtx_FIX (DImode,
10542   operand1)));
10543   _val = get_insns ();
10544   end_sequence ();
10545   return _val;
10546 }
10547 
10548 /* ../../gcc/gcc/config/i386/i386.md:4079 */
10549 rtx
10550 gen_fix_truncsfdi2 (operand0, operand1)
10551      rtx operand0;
10552      rtx operand1;
10553 {
10554   rtx _val = 0;
10555   start_sequence ();
10556   {
10557     rtx operands[2];
10558     operands[0] = operand0;
10559     operands[1] = operand1;
10560 {
10561   if (TARGET_SSE && TARGET_64BIT)
10562    {
10563      rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (DImode);
10564      emit_insn (gen_fix_truncsfdi_sse (out, operands[1]));
10565      if (out != operands[0])
10566   emit_move_insn (operands[0], out);
10567      DONE;
10568    }
10569 }
10570     operand0 = operands[0];
10571     operand1 = operands[1];
10572   }
10573   emit_insn (gen_rtx_SET (VOIDmode,
10574   operand0,
10575   gen_rtx_FIX (DImode,
10576   operand1)));
10577   _val = get_insns ();
10578   end_sequence ();
10579   return _val;
10580 }
10581 
10582 /* ../../gcc/gcc/config/i386/i386.md:4096 */
10583 extern rtx gen_split_1130 PARAMS ((rtx *));
10584 rtx
10585 gen_split_1130 (operands)
10586       rtx *operands ATTRIBUTE_UNUSED;
10587 {
10588   rtx _val = 0;
10589   start_sequence ();
10590 {
10591   operands[2] = assign_386_stack_local (HImode, 1);
10592   operands[3] = assign_386_stack_local (HImode, 2);
10593   if (memory_operand (operands[0], VOIDmode))
10594     emit_insn (gen_fix_truncdi_memory (operands[0], operands[1],
10595                operands[2], operands[3]));
10596   else
10597     {
10598       operands[4] = assign_386_stack_local (DImode, 0);
10599       emit_insn (gen_fix_truncdi_nomemory (operands[0], operands[1],
10600              operands[2], operands[3],
10601              operands[4]));
10602     }
10603   DONE;
10604 }
10605   emit_insn (const0_rtx);
10606   _val = get_insns ();
10607   end_sequence ();
10608   return _val;
10609 }
10610 
10611 /* ../../gcc/gcc/config/i386/i386.md:4145 */
10612 extern rtx gen_split_1131 PARAMS ((rtx *));
10613 rtx
10614 gen_split_1131 (operands)
10615       rtx *operands;
10616 {
10617   rtx operand0;
10618   rtx operand1;
10619   rtx operand2;
10620   rtx operand3;
10621   rtx operand4;
10622   rtx operand5;
10623   rtx _val = 0;
10624   start_sequence ();
10625 
10626   operand0 = operands[0];
10627   operand1 = operands[1];
10628   operand2 = operands[2];
10629   operand3 = operands[3];
10630   operand4 = operands[4];
10631   operand5 = operands[5];
10632   emit (gen_rtx_PARALLEL (VOIDmode,
10633   gen_rtvec (4,
10634     gen_rtx_SET (VOIDmode,
10635   operand4,
10636   gen_rtx_FIX (DImode,
10637   operand1)),
10638     gen_rtx_USE (VOIDmode,
10639   operand2),
10640     gen_rtx_USE (VOIDmode,
10641   operand3),
10642     gen_rtx_CLOBBER (VOIDmode,
10643   operand5))));
10644   emit_insn (gen_rtx_SET (VOIDmode,
10645   operand0,
10646   copy_rtx (operand4)));
10647   _val = get_insns ();
10648   end_sequence ();
10649   return _val;
10650 }
10651 
10652 /* ../../gcc/gcc/config/i386/i386.md:4160 */
10653 extern rtx gen_split_1132 PARAMS ((rtx *));
10654 rtx
10655 gen_split_1132 (operands)
10656       rtx *operands;
10657 {
10658   rtx operand0;
10659   rtx operand1;
10660   rtx operand2;
10661   rtx operand3;
10662   rtx operand4;
10663   rtx operand5;
10664   rtx _val = 0;
10665   start_sequence ();
10666 
10667   operand0 = operands[0];
10668   operand1 = operands[1];
10669   operand2 = operands[2];
10670   operand3 = operands[3];
10671   operand4 = operands[4];
10672   operand5 = operands[5];
10673   emit (gen_rtx_PARALLEL (VOIDmode,
10674   gen_rtvec (4,
10675     gen_rtx_SET (VOIDmode,
10676   operand0,
10677   gen_rtx_FIX (DImode,
10678   operand1)),
10679     gen_rtx_USE (VOIDmode,
10680   operand2),
10681     gen_rtx_USE (VOIDmode,
10682   operand3),
10683     gen_rtx_CLOBBER (VOIDmode,
10684   operand5))));
10685   _val = get_insns ();
10686   end_sequence ();
10687   return _val;
10688 }
10689 
10690 /* ../../gcc/gcc/config/i386/i386.md:4191 */
10691 rtx
10692 gen_fix_truncxfsi2 (operand0, operand1)
10693      rtx operand0;
10694      rtx operand1;
10695 {
10696   return gen_rtx_SET (VOIDmode,
10697   operand0,
10698   gen_rtx_FIX (SImode,
10699   operand1));
10700 }
10701 
10702 /* ../../gcc/gcc/config/i386/i386.md:4197 */
10703 rtx
10704 gen_fix_trunctfsi2 (operand0, operand1)
10705      rtx operand0;
10706      rtx operand1;
10707 {
10708   return gen_rtx_SET (VOIDmode,
10709   operand0,
10710   gen_rtx_FIX (SImode,
10711   operand1));
10712 }
10713 
10714 /* ../../gcc/gcc/config/i386/i386.md:4203 */
10715 rtx
10716 gen_fix_truncdfsi2 (operand0, operand1)
10717      rtx operand0;
10718      rtx operand1;
10719 {
10720   rtx _val = 0;
10721   start_sequence ();
10722   {
10723     rtx operands[2];
10724     operands[0] = operand0;
10725     operands[1] = operand1;
10726 {
10727   if (TARGET_SSE2)
10728    {
10729      rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
10730      emit_insn (gen_fix_truncdfsi_sse (out, operands[1]));
10731      if (out != operands[0])
10732   emit_move_insn (operands[0], out);
10733      DONE;
10734    }
10735 }
10736     operand0 = operands[0];
10737     operand1 = operands[1];
10738   }
10739   emit_insn (gen_rtx_SET (VOIDmode,
10740   operand0,
10741   gen_rtx_FIX (SImode,
10742   operand1)));
10743   _val = get_insns ();
10744   end_sequence ();
10745   return _val;
10746 }
10747 
10748 /* ../../gcc/gcc/config/i386/i386.md:4218 */
10749 rtx
10750 gen_fix_truncsfsi2 (operand0, operand1)
10751      rtx operand0;
10752      rtx operand1;
10753 {
10754   rtx _val = 0;
10755   start_sequence ();
10756   {
10757     rtx operands[2];
10758     operands[0] = operand0;
10759     operands[1] = operand1;
10760 {
10761   if (TARGET_SSE)
10762    {
10763      rtx out = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
10764      emit_insn (gen_fix_truncsfsi_sse (out, operands[1]));
10765      if (out != operands[0])
10766   emit_move_insn (operands[0], out);
10767      DONE;
10768    }
10769 }
10770     operand0 = operands[0];
10771     operand1 = operands[1];
10772   }
10773   emit_insn (gen_rtx_SET (VOIDmode,
10774   operand0,
10775   gen_rtx_FIX (SImode,
10776   operand1)));
10777   _val = get_insns ();
10778   end_sequence ();
10779   return _val;
10780 }
10781 
10782 /* ../../gcc/gcc/config/i386/i386.md:4235 */
10783 extern rtx gen_split_1137 PARAMS ((rtx *));
10784 rtx
10785 gen_split_1137 (operands)
10786       rtx *operands ATTRIBUTE_UNUSED;
10787 {
10788   rtx _val = 0;
10789   start_sequence ();
10790 {
10791   operands[2] = assign_386_stack_local (HImode, 1);
10792   operands[3] = assign_386_stack_local (HImode, 2);
10793   if (memory_operand (operands[0], VOIDmode))
10794     emit_insn (gen_fix_truncsi_memory (operands[0], operands[1],
10795                operands[2], operands[3]));
10796   else
10797     {
10798       operands[4] = assign_386_stack_local (SImode, 0);
10799       emit_insn (gen_fix_truncsi_nomemory (operands[0], operands[1],
10800              operands[2], operands[3],
10801              operands[4]));
10802     }
10803   DONE;
10804 }
10805   emit_insn (const0_rtx);
10806   _val = get_insns ();
10807   end_sequence ();
10808   return _val;
10809 }
10810 
10811 /* ../../gcc/gcc/config/i386/i386.md:4297 */
10812 extern rtx gen_split_1138 PARAMS ((rtx *));
10813 rtx
10814 gen_split_1138 (operands)
10815       rtx *operands;
10816 {
10817   rtx operand0;
10818   rtx operand1;
10819   rtx operand2;
10820   rtx operand3;
10821   rtx operand4;
10822   rtx _val = 0;
10823   start_sequence ();
10824 
10825   operand0 = operands[0];
10826   operand1 = operands[1];
10827   operand2 = operands[2];
10828   operand3 = operands[3];
10829   operand4 = operands[4];
10830   emit (gen_rtx_PARALLEL (VOIDmode,
10831   gen_rtvec (3,
10832     gen_rtx_SET (VOIDmode,
10833   operand4,
10834   gen_rtx_FIX (SImode,
10835   operand1)),
10836     gen_rtx_USE (VOIDmode,
10837   operand2),
10838     gen_rtx_USE (VOIDmode,
10839   operand3))));
10840   emit_insn (gen_rtx_SET (VOIDmode,
10841   operand0,
10842   copy_rtx (operand4)));
10843   _val = get_insns ();
10844   end_sequence ();
10845   return _val;
10846 }
10847 
10848 /* ../../gcc/gcc/config/i386/i386.md:4310 */
10849 extern rtx gen_split_1139 PARAMS ((rtx *));
10850 rtx
10851 gen_split_1139 (operands)
10852       rtx *operands;
10853 {
10854   rtx operand0;
10855   rtx operand1;
10856   rtx operand2;
10857   rtx operand3;
10858   rtx _val = 0;
10859   start_sequence ();
10860 
10861   operand0 = operands[0];
10862   operand1 = operands[1];
10863   operand2 = operands[2];
10864   operand3 = operands[3];
10865   emit (gen_rtx_PARALLEL (VOIDmode,
10866   gen_rtvec (3,
10867     gen_rtx_SET (VOIDmode,
10868   operand0,
10869   gen_rtx_FIX (SImode,
10870   operand1)),
10871     gen_rtx_USE (VOIDmode,
10872   operand2),
10873     gen_rtx_USE (VOIDmode,
10874   operand3))));
10875   _val = get_insns ();
10876   end_sequence ();
10877   return _val;
10878 }
10879 
10880 /* ../../gcc/gcc/config/i386/i386.md:4324 */
10881 rtx
10882 gen_fix_truncxfhi2 (operand0, operand1)
10883      rtx operand0;
10884      rtx operand1;
10885 {
10886   return gen_rtx_SET (VOIDmode,
10887   operand0,
10888   gen_rtx_FIX (HImode,
10889   operand1));
10890 }
10891 
10892 /* ../../gcc/gcc/config/i386/i386.md:4330 */
10893 rtx
10894 gen_fix_trunctfhi2 (operand0, operand1)
10895      rtx operand0;
10896      rtx operand1;
10897 {
10898   return gen_rtx_SET (VOIDmode,
10899   operand0,
10900   gen_rtx_FIX (HImode,
10901   operand1));
10902 }
10903 
10904 /* ../../gcc/gcc/config/i386/i386.md:4336 */
10905 rtx
10906 gen_fix_truncdfhi2 (operand0, operand1)
10907      rtx operand0;
10908      rtx operand1;
10909 {
10910   return gen_rtx_SET (VOIDmode,
10911   operand0,
10912   gen_rtx_FIX (HImode,
10913   operand1));
10914 }
10915 
10916 /* ../../gcc/gcc/config/i386/i386.md:4342 */
10917 rtx
10918 gen_fix_truncsfhi2 (operand0, operand1)
10919      rtx operand0;
10920      rtx operand1;
10921 {
10922   return gen_rtx_SET (VOIDmode,
10923   operand0,
10924   gen_rtx_FIX (HImode,
10925   operand1));
10926 }
10927 
10928 /* ../../gcc/gcc/config/i386/i386.md:4350 */
10929 extern rtx gen_split_1144 PARAMS ((rtx *));
10930 rtx
10931 gen_split_1144 (operands)
10932       rtx *operands ATTRIBUTE_UNUSED;
10933 {
10934   rtx _val = 0;
10935   start_sequence ();
10936 {
10937   operands[2] = assign_386_stack_local (HImode, 1);
10938   operands[3] = assign_386_stack_local (HImode, 2);
10939   if (memory_operand (operands[0], VOIDmode))
10940     emit_insn (gen_fix_trunchi_memory (operands[0], operands[1],
10941                operands[2], operands[3]));
10942   else
10943     {
10944       operands[4] = assign_386_stack_local (HImode, 0);
10945       emit_insn (gen_fix_trunchi_nomemory (operands[0], operands[1],
10946              operands[2], operands[3],
10947              operands[4]));
10948     }
10949   DONE;
10950 }
10951   emit_insn (const0_rtx);
10952   _val = get_insns ();
10953   end_sequence ();
10954   return _val;
10955 }
10956 
10957 /* ../../gcc/gcc/config/i386/i386.md:4397 */
10958 extern rtx gen_split_1145 PARAMS ((rtx *));
10959 rtx
10960 gen_split_1145 (operands)
10961       rtx *operands;
10962 {
10963   rtx operand0;
10964   rtx operand1;
10965   rtx operand2;
10966   rtx operand3;
10967   rtx _val = 0;
10968   start_sequence ();
10969 
10970   operand0 = operands[0];
10971   operand1 = operands[1];
10972   operand2 = operands[2];
10973   operand3 = operands[3];
10974   emit (gen_rtx_PARALLEL (VOIDmode,
10975   gen_rtvec (3,
10976     gen_rtx_SET (VOIDmode,
10977   operand0,
10978   gen_rtx_FIX (HImode,
10979   operand1)),
10980     gen_rtx_USE (VOIDmode,
10981   operand2),
10982     gen_rtx_USE (VOIDmode,
10983   operand3))));
10984   _val = get_insns ();
10985   end_sequence ();
10986   return _val;
10987 }
10988 
10989 /* ../../gcc/gcc/config/i386/i386.md:4409 */
10990 extern rtx gen_split_1146 PARAMS ((rtx *));
10991 rtx
10992 gen_split_1146 (operands)
10993       rtx *operands;
10994 {
10995   rtx operand0;
10996   rtx operand1;
10997   rtx operand2;
10998   rtx operand3;
10999   rtx operand4;
11000   rtx _val = 0;
11001   start_sequence ();
11002 
11003   operand0 = operands[0];
11004   operand1 = operands[1];
11005   operand2 = operands[2];
11006   operand3 = operands[3];
11007   operand4 = operands[4];
11008   emit (gen_rtx_PARALLEL (VOIDmode,
11009   gen_rtvec (4,
11010     gen_rtx_SET (VOIDmode,
11011   operand4,
11012   gen_rtx_FIX (HImode,
11013   operand1)),
11014     gen_rtx_USE (VOIDmode,
11015   operand2),
11016     gen_rtx_USE (VOIDmode,
11017   operand3),
11018     gen_rtx_CLOBBER (VOIDmode,
11019   copy_rtx (operand4)))));
11020   emit_insn (gen_rtx_SET (VOIDmode,
11021   operand0,
11022   copy_rtx (operand4)));
11023   _val = get_insns ();
11024   end_sequence ();
11025   return _val;
11026 }
11027 
11028 /* ../../gcc/gcc/config/i386/i386.md:4461 */
11029 rtx
11030 gen_floatsisf2 (operand0, operand1)
11031      rtx operand0;
11032      rtx operand1;
11033 {
11034   return gen_rtx_SET (VOIDmode,
11035   operand0,
11036   gen_rtx_FLOAT (SFmode,
11037   operand1));
11038 }
11039 
11040 /* ../../gcc/gcc/config/i386/i386.md:4488 */
11041 rtx
11042 gen_floatdisf2 (operand0, operand1)
11043      rtx operand0;
11044      rtx operand1;
11045 {
11046   return gen_rtx_SET (VOIDmode,
11047   operand0,
11048   gen_rtx_FLOAT (SFmode,
11049   operand1));
11050 }
11051 
11052 /* ../../gcc/gcc/config/i386/i386.md:4537 */
11053 rtx
11054 gen_floatsidf2 (operand0, operand1)
11055      rtx operand0;
11056      rtx operand1;
11057 {
11058   return gen_rtx_SET (VOIDmode,
11059   operand0,
11060   gen_rtx_FLOAT (DFmode,
11061   operand1));
11062 }
11063 
11064 /* ../../gcc/gcc/config/i386/i386.md:4564 */
11065 rtx
11066 gen_floatdidf2 (operand0, operand1)
11067      rtx operand0;
11068      rtx operand1;
11069 {
11070   return gen_rtx_SET (VOIDmode,
11071   operand0,
11072   gen_rtx_FLOAT (DFmode,
11073   operand1));
11074 }
11075 
11076 /* ../../gcc/gcc/config/i386/i386.md:4669 */
11077 extern rtx gen_split_1151 PARAMS ((rtx *));
11078 rtx
11079 gen_split_1151 (operands)
11080       rtx *operands ATTRIBUTE_UNUSED;
11081 {
11082   rtx _val = 0;
11083   start_sequence ();
11084 {
11085   operands[2] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
11086   operands[2] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[2]);
11087   emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[2]));
11088   ix86_free_from_memory (GET_MODE (operands[1]));
11089   DONE;
11090 }
11091   emit_insn (const0_rtx);
11092   _val = get_insns ();
11093   end_sequence ();
11094   return _val;
11095 }
11096 
11097 /* ../../gcc/gcc/config/i386/i386.md:4689 */
11098 rtx
11099 gen_adddi3 (operand0, operand1, operand2)
11100      rtx operand0;
11101      rtx operand1;
11102      rtx operand2;
11103 {
11104   rtx _val = 0;
11105   start_sequence ();
11106   {
11107     rtx operands[3];
11108     operands[0] = operand0;
11109     operands[1] = operand1;
11110     operands[2] = operand2;
11111 ix86_expand_binary_operator (PLUS, DImode, operands); DONE;
11112     operand0 = operands[0];
11113     operand1 = operands[1];
11114     operand2 = operands[2];
11115   }
11116   emit_insn (gen_rtx_SET (VOIDmode,
11117   operand0,
11118   gen_rtx_PLUS (DImode,
11119   operand1,
11120   operand2)));
11121   emit_insn (gen_rtx_CLOBBER (VOIDmode,
11122   gen_rtx_REG (CCmode,
11123   17)));
11124   _val = get_insns ();
11125   end_sequence ();
11126   return _val;
11127 }
11128 
11129 /* ../../gcc/gcc/config/i386/i386.md:4705 */
11130 extern rtx gen_split_1153 PARAMS ((rtx *));
11131 rtx
11132 gen_split_1153 (operands)
11133       rtx *operands;
11134 {
11135   rtx operand0;
11136   rtx operand1;
11137   rtx operand2;
11138   rtx operand3;
11139   rtx operand4;
11140   rtx operand5;
11141   rtx _val = 0;
11142   start_sequence ();
11143 split_di (operands+0, 1, operands+0, operands+3);
11144    split_di (operands+1, 1, operands+1, operands+4);
11145    split_di (operands+2, 1, operands+2, operands+5);
11146   operand0 = operands[0];
11147   operand1 = operands[1];
11148   operand2 = operands[2];
11149   operand3 = operands[3];
11150   operand4 = operands[4];
11151   operand5 = operands[5];
11152   emit (gen_rtx_PARALLEL (VOIDmode,
11153   gen_rtvec (2,
11154     gen_rtx_SET (VOIDmode,
11155   gen_rtx_REG (CCmode,
11156   17),
11157   gen_rtx_UNSPEC (CCmode,
11158   gen_rtvec (2,
11159     operand1,
11160     operand2),
11161   27)),
11162     gen_rtx_SET (VOIDmode,
11163   operand0,
11164   gen_rtx_PLUS (SImode,
11165   copy_rtx (operand1),
11166   copy_rtx (operand2))))));
11167   emit (gen_rtx_PARALLEL (VOIDmode,
11168   gen_rtvec (2,
11169     gen_rtx_SET (VOIDmode,
11170   operand3,
11171   gen_rtx_PLUS (SImode,
11172   gen_rtx_PLUS (SImode,
11173   gen_rtx_LTU (SImode,
11174   gen_rtx_REG (CCmode,
11175   17),
11176   const0_rtx),
11177   operand4),
11178   operand5)),
11179     gen_rtx_CLOBBER (VOIDmode,
11180   gen_rtx_REG (CCmode,
11181   17)))));
11182   _val = get_insns ();
11183   end_sequence ();
11184   return _val;
11185 }
11186 
11187 /* ../../gcc/gcc/config/i386/i386.md:4799 */
11188 rtx
11189 gen_addsi3 (operand0, operand1, operand2)
11190      rtx operand0;
11191      rtx operand1;
11192      rtx operand2;
11193 {
11194   rtx _val = 0;
11195   start_sequence ();
11196   {
11197     rtx operands[3];
11198     operands[0] = operand0;
11199     operands[1] = operand1;
11200     operands[2] = operand2;
11201 ix86_expand_binary_operator (PLUS, SImode, operands); DONE;
11202     operand0 = operands[0];
11203     operand1 = operands[1];
11204     operand2 = operands[2];
11205   }
11206   emit (gen_rtx_PARALLEL (VOIDmode,
11207   gen_rtvec (2,
11208     gen_rtx_SET (VOIDmode,
11209   operand0,
11210   gen_rtx_PLUS (SImode,
11211   operand1,
11212   operand2)),
11213     gen_rtx_CLOBBER (VOIDmode,
11214   gen_rtx_REG (CCmode,
11215   17)))));
11216   _val = get_insns ();
11217   end_sequence ();
11218   return _val;
11219 }
11220 
11221 /* ../../gcc/gcc/config/i386/i386.md:4843 */
11222 extern rtx gen_split_1155 PARAMS ((rtx *));
11223 rtx
11224 gen_split_1155 (operands)
11225       rtx *operands ATTRIBUTE_UNUSED;
11226 {
11227   rtx _val = 0;
11228   start_sequence ();
11229 {
11230   rtx pat;
11231   operands[0] = gen_lowpart (SImode, operands[0]);
11232   operands[1] = gen_lowpart (Pmode, operands[1]);
11233   operands[2] = gen_lowpart (Pmode, operands[2]);
11234   operands[3] = gen_lowpart (Pmode, operands[3]);
11235   pat = gen_rtx_PLUS (Pmode, gen_rtx_PLUS (Pmode, operands[1], operands[2]),
11236             operands[3]);
11237   if (Pmode != SImode)
11238     pat = gen_rtx_SUBREG (SImode, pat, 0);
11239   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11240   DONE;
11241 }
11242   emit_insn (const0_rtx);
11243   _val = get_insns ();
11244   end_sequence ();
11245   return _val;
11246 }
11247 
11248 /* ../../gcc/gcc/config/i386/i386.md:4874 */
11249 extern rtx gen_split_1156 PARAMS ((rtx *));
11250 rtx
11251 gen_split_1156 (operands)
11252       rtx *operands;
11253 {
11254   rtx operand0;
11255   rtx operand1;
11256   rtx operand2;
11257   rtx operand3;
11258   rtx _val = 0;
11259   start_sequence ();
11260 {
11261   operands[1] = gen_lowpart (Pmode, operands[1]);
11262   operands[2] = gen_lowpart (Pmode, operands[2]);
11263   operands[3] = gen_lowpart (Pmode, operands[3]);
11264 }
11265   operand0 = operands[0];
11266   operand1 = operands[1];
11267   operand2 = operands[2];
11268   operand3 = operands[3];
11269   emit_insn (gen_rtx_SET (VOIDmode,
11270   operand0,
11271   gen_rtx_ZERO_EXTEND (DImode,
11272   gen_rtx_SUBREG (SImode,
11273   gen_rtx_PLUS (DImode,
11274   gen_rtx_PLUS (DImode,
11275   operand1,
11276   operand2),
11277   operand3),
11278   0))));
11279   _val = get_insns ();
11280   end_sequence ();
11281   return _val;
11282 }
11283 
11284 /* ../../gcc/gcc/config/i386/i386.md:4895 */
11285 extern rtx gen_split_1157 PARAMS ((rtx *));
11286 rtx
11287 gen_split_1157 (operands)
11288       rtx *operands ATTRIBUTE_UNUSED;
11289 {
11290   rtx _val = 0;
11291   start_sequence ();
11292 {
11293   rtx pat;
11294   operands[0] = gen_lowpart (SImode, operands[0]);
11295   operands[1] = gen_lowpart (Pmode, operands[1]);
11296   operands[3] = gen_lowpart (Pmode, operands[3]);
11297   pat = gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1], operands[2]),
11298             operands[3]);
11299   if (Pmode != SImode)
11300     pat = gen_rtx_SUBREG (SImode, pat, 0);
11301   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11302   DONE;
11303 }
11304   emit_insn (const0_rtx);
11305   _val = get_insns ();
11306   end_sequence ();
11307   return _val;
11308 }
11309 
11310 /* ../../gcc/gcc/config/i386/i386.md:4924 */
11311 extern rtx gen_split_1158 PARAMS ((rtx *));
11312 rtx
11313 gen_split_1158 (operands)
11314       rtx *operands;
11315 {
11316   rtx operand0;
11317   rtx operand1;
11318   rtx operand2;
11319   rtx operand3;
11320   rtx _val = 0;
11321   start_sequence ();
11322 {
11323   operands[1] = gen_lowpart (Pmode, operands[1]);
11324   operands[3] = gen_lowpart (Pmode, operands[3]);
11325 }
11326   operand0 = operands[0];
11327   operand1 = operands[1];
11328   operand2 = operands[2];
11329   operand3 = operands[3];
11330   emit_insn (gen_rtx_SET (VOIDmode,
11331   operand0,
11332   gen_rtx_ZERO_EXTEND (DImode,
11333   gen_rtx_SUBREG (SImode,
11334   gen_rtx_PLUS (DImode,
11335   gen_rtx_MULT (DImode,
11336   operand1,
11337   operand2),
11338   operand3),
11339   0))));
11340   _val = get_insns ();
11341   end_sequence ();
11342   return _val;
11343 }
11344 
11345 /* ../../gcc/gcc/config/i386/i386.md:4944 */
11346 extern rtx gen_split_1159 PARAMS ((rtx *));
11347 rtx
11348 gen_split_1159 (operands)
11349       rtx *operands ATTRIBUTE_UNUSED;
11350 {
11351   rtx _val = 0;
11352   start_sequence ();
11353 {
11354   rtx pat;
11355   operands[0] = gen_lowpart (SImode, operands[0]);
11356   operands[1] = gen_lowpart (Pmode, operands[1]);
11357   operands[3] = gen_lowpart (Pmode, operands[3]);
11358   operands[4] = gen_lowpart (Pmode, operands[4]);
11359   pat = gen_rtx_PLUS (Pmode,
11360             gen_rtx_PLUS (Pmode, gen_rtx_MULT (Pmode, operands[1],
11361                      operands[2]),
11362             operands[3]),
11363             operands[4]);
11364   if (Pmode != SImode)
11365     pat = gen_rtx_SUBREG (SImode, pat, 0);
11366   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11367   DONE;
11368 }
11369   emit_insn (const0_rtx);
11370   _val = get_insns ();
11371   end_sequence ();
11372   return _val;
11373 }
11374 
11375 /* ../../gcc/gcc/config/i386/i386.md:4977 */
11376 extern rtx gen_split_1160 PARAMS ((rtx *));
11377 rtx
11378 gen_split_1160 (operands)
11379       rtx *operands;
11380 {
11381   rtx operand0;
11382   rtx operand1;
11383   rtx operand2;
11384   rtx operand3;
11385   rtx operand4;
11386   rtx _val = 0;
11387   start_sequence ();
11388 {
11389   operands[1] = gen_lowpart (Pmode, operands[1]);
11390   operands[3] = gen_lowpart (Pmode, operands[3]);
11391   operands[4] = gen_lowpart (Pmode, operands[4]);
11392 }
11393   operand0 = operands[0];
11394   operand1 = operands[1];
11395   operand2 = operands[2];
11396   operand3 = operands[3];
11397   operand4 = operands[4];
11398   emit_insn (gen_rtx_SET (VOIDmode,
11399   operand0,
11400   gen_rtx_ZERO_EXTEND (DImode,
11401   gen_rtx_SUBREG (SImode,
11402   gen_rtx_PLUS (DImode,
11403   gen_rtx_PLUS (DImode,
11404   gen_rtx_MULT (DImode,
11405   operand1,
11406   operand2),
11407   operand3),
11408   operand4),
11409   0))));
11410   _val = get_insns ();
11411   end_sequence ();
11412   return _val;
11413 }
11414 
11415 /* ../../gcc/gcc/config/i386/i386.md:5056 */
11416 extern rtx gen_split_1161 PARAMS ((rtx *));
11417 rtx
11418 gen_split_1161 (operands)
11419       rtx *operands;
11420 {
11421   rtx operand0;
11422   rtx operand1;
11423   rtx operand2;
11424   rtx _val = 0;
11425   start_sequence ();
11426 
11427   operand0 = operands[0];
11428   operand1 = operands[1];
11429   operand2 = operands[2];
11430   emit_insn (gen_rtx_SET (VOIDmode,
11431   operand0,
11432   gen_rtx_PLUS (DImode,
11433   operand1,
11434   operand2)));
11435   _val = get_insns ();
11436   end_sequence ();
11437   return _val;
11438 }
11439 
11440 /* ../../gcc/gcc/config/i386/i386.md:5322 */
11441 extern rtx gen_split_1162 PARAMS ((rtx *));
11442 rtx
11443 gen_split_1162 (operands)
11444       rtx *operands ATTRIBUTE_UNUSED;
11445 {
11446   rtx _val = 0;
11447   start_sequence ();
11448 {
11449   rtx pat;
11450   /* In -fPIC mode the constructs like (const (unspec [symbol_ref]))
11451      may confuse gen_lowpart.  */
11452   if (GET_MODE (operands[0]) != Pmode)
11453     {
11454       operands[1] = gen_lowpart (Pmode, operands[1]);
11455       operands[2] = gen_lowpart (Pmode, operands[2]);
11456     }
11457   operands[0] = gen_lowpart (SImode, operands[0]);
11458   pat = gen_rtx_PLUS (Pmode, operands[1], operands[2]);
11459   if (Pmode != SImode)
11460     pat = gen_rtx_SUBREG (SImode, pat, 0);
11461   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
11462   DONE;
11463 }
11464   emit_insn (const0_rtx);
11465   _val = get_insns ();
11466   end_sequence ();
11467   return _val;
11468 }
11469 
11470 /* ../../gcc/gcc/config/i386/i386.md:5402 */
11471 extern rtx gen_split_1163 PARAMS ((rtx *));
11472 rtx
11473 gen_split_1163 (operands)
11474       rtx *operands;
11475 {
11476   rtx operand0;
11477   rtx operand1;
11478   rtx operand2;
11479   rtx _val = 0;
11480   start_sequence ();
11481 {
11482   operands[1] = gen_lowpart (Pmode, operands[1]);
11483   operands[2] = gen_lowpart (Pmode, operands[2]);
11484 }
11485   operand0 = operands[0];
11486   operand1 = operands[1];
11487   operand2 = operands[2];
11488   emit_insn (gen_rtx_SET (VOIDmode,
11489   operand0,
11490   gen_rtx_ZERO_EXTEND (DImode,
11491   gen_rtx_SUBREG (SImode,
11492   gen_rtx_PLUS (DImode,
11493   operand1,
11494   operand2),
11495   0))));
11496   _val = get_insns ();
11497   end_sequence ();
11498   return _val;
11499 }
11500 
11501 /* ../../gcc/gcc/config/i386/i386.md:5690 */
11502 rtx
11503 gen_addhi3 (operand0, operand1, operand2)
11504      rtx operand0;
11505      rtx operand1;
11506      rtx operand2;
11507 {
11508   rtx _val = 0;
11509   start_sequence ();
11510   {
11511     rtx operands[3];
11512     operands[0] = operand0;
11513     operands[1] = operand1;
11514     operands[2] = operand2;
11515 ix86_expand_binary_operator (PLUS, HImode, operands); DONE;
11516     operand0 = operands[0];
11517     operand1 = operands[1];
11518     operand2 = operands[2];
11519   }
11520   emit (gen_rtx_PARALLEL (VOIDmode,
11521   gen_rtvec (2,
11522     gen_rtx_SET (VOIDmode,
11523   operand0,
11524   gen_rtx_PLUS (HImode,
11525   operand1,
11526   operand2)),
11527     gen_rtx_CLOBBER (VOIDmode,
11528   gen_rtx_REG (CCmode,
11529   17)))));
11530   _val = get_insns ();
11531   end_sequence ();
11532   return _val;
11533 }
11534 
11535 /* ../../gcc/gcc/config/i386/i386.md:5935 */
11536 rtx
11537 gen_addqi3 (operand0, operand1, operand2)
11538      rtx operand0;
11539      rtx operand1;
11540      rtx operand2;
11541 {
11542   rtx _val = 0;
11543   start_sequence ();
11544   {
11545     rtx operands[3];
11546     operands[0] = operand0;
11547     operands[1] = operand1;
11548     operands[2] = operand2;
11549 ix86_expand_binary_operator (PLUS, QImode, operands); DONE;
11550     operand0 = operands[0];
11551     operand1 = operands[1];
11552     operand2 = operands[2];
11553   }
11554   emit (gen_rtx_PARALLEL (VOIDmode,
11555   gen_rtvec (2,
11556     gen_rtx_SET (VOIDmode,
11557   operand0,
11558   gen_rtx_PLUS (QImode,
11559   operand1,
11560   operand2)),
11561     gen_rtx_CLOBBER (VOIDmode,
11562   gen_rtx_REG (CCmode,
11563   17)))));
11564   _val = get_insns ();
11565   end_sequence ();
11566   return _val;
11567 }
11568 
11569 /* ../../gcc/gcc/config/i386/i386.md:6312 */
11570 rtx
11571 gen_addxf3 (operand0, operand1, operand2)
11572      rtx operand0;
11573      rtx operand1;
11574      rtx operand2;
11575 {
11576   return gen_rtx_SET (VOIDmode,
11577   operand0,
11578   gen_rtx_PLUS (XFmode,
11579   operand1,
11580   operand2));
11581 }
11582 
11583 /* ../../gcc/gcc/config/i386/i386.md:6319 */
11584 rtx
11585 gen_addtf3 (operand0, operand1, operand2)
11586      rtx operand0;
11587      rtx operand1;
11588      rtx operand2;
11589 {
11590   return gen_rtx_SET (VOIDmode,
11591   operand0,
11592   gen_rtx_PLUS (TFmode,
11593   operand1,
11594   operand2));
11595 }
11596 
11597 /* ../../gcc/gcc/config/i386/i386.md:6326 */
11598 rtx
11599 gen_adddf3 (operand0, operand1, operand2)
11600      rtx operand0;
11601      rtx operand1;
11602      rtx operand2;
11603 {
11604   return gen_rtx_SET (VOIDmode,
11605   operand0,
11606   gen_rtx_PLUS (DFmode,
11607   operand1,
11608   operand2));
11609 }
11610 
11611 /* ../../gcc/gcc/config/i386/i386.md:6333 */
11612 rtx
11613 gen_addsf3 (operand0, operand1, operand2)
11614      rtx operand0;
11615      rtx operand1;
11616      rtx operand2;
11617 {
11618   return gen_rtx_SET (VOIDmode,
11619   operand0,
11620   gen_rtx_PLUS (SFmode,
11621   operand1,
11622   operand2));
11623 }
11624 
11625 /* ../../gcc/gcc/config/i386/i386.md:6344 */
11626 rtx
11627 gen_subdi3 (operand0, operand1, operand2)
11628      rtx operand0;
11629      rtx operand1;
11630      rtx operand2;
11631 {
11632   rtx _val = 0;
11633   start_sequence ();
11634   {
11635     rtx operands[3];
11636     operands[0] = operand0;
11637     operands[1] = operand1;
11638     operands[2] = operand2;
11639 ix86_expand_binary_operator (MINUS, DImode, operands); DONE;
11640     operand0 = operands[0];
11641     operand1 = operands[1];
11642     operand2 = operands[2];
11643   }
11644   emit (gen_rtx_PARALLEL (VOIDmode,
11645   gen_rtvec (2,
11646     gen_rtx_SET (VOIDmode,
11647   operand0,
11648   gen_rtx_MINUS (DImode,
11649   operand1,
11650   operand2)),
11651     gen_rtx_CLOBBER (VOIDmode,
11652   gen_rtx_REG (CCmode,
11653   17)))));
11654   _val = get_insns ();
11655   end_sequence ();
11656   return _val;
11657 }
11658 
11659 /* ../../gcc/gcc/config/i386/i386.md:6360 */
11660 extern rtx gen_split_1171 PARAMS ((rtx *));
11661 rtx
11662 gen_split_1171 (operands)
11663       rtx *operands;
11664 {
11665   rtx operand0;
11666   rtx operand1;
11667   rtx operand2;
11668   rtx operand3;
11669   rtx operand4;
11670   rtx operand5;
11671   rtx _val = 0;
11672   start_sequence ();
11673 split_di (operands+0, 1, operands+0, operands+3);
11674    split_di (operands+1, 1, operands+1, operands+4);
11675    split_di (operands+2, 1, operands+2, operands+5);
11676   operand0 = operands[0];
11677   operand1 = operands[1];
11678   operand2 = operands[2];
11679   operand3 = operands[3];
11680   operand4 = operands[4];
11681   operand5 = operands[5];
11682   emit (gen_rtx_PARALLEL (VOIDmode,
11683   gen_rtvec (2,
11684     gen_rtx_SET (VOIDmode,
11685   gen_rtx_REG (CCmode,
11686   17),
11687   gen_rtx_COMPARE (CCmode,
11688   operand1,
11689   operand2)),
11690     gen_rtx_SET (VOIDmode,
11691   operand0,
11692   gen_rtx_MINUS (SImode,
11693   copy_rtx (operand1),
11694   copy_rtx (operand2))))));
11695   emit (gen_rtx_PARALLEL (VOIDmode,
11696   gen_rtvec (2,
11697     gen_rtx_SET (VOIDmode,
11698   operand3,
11699   gen_rtx_MINUS (SImode,
11700   operand4,
11701   gen_rtx_PLUS (SImode,
11702   gen_rtx_LTU (SImode,
11703   gen_rtx_REG (CCmode,
11704   17),
11705   const0_rtx),
11706   operand5))),
11707     gen_rtx_CLOBBER (VOIDmode,
11708   gen_rtx_REG (CCmode,
11709   17)))));
11710   _val = get_insns ();
11711   end_sequence ();
11712   return _val;
11713 }
11714 
11715 /* ../../gcc/gcc/config/i386/i386.md:6454 */
11716 rtx
11717 gen_subsi3 (operand0, operand1, operand2)
11718      rtx operand0;
11719      rtx operand1;
11720      rtx operand2;
11721 {
11722   rtx _val = 0;
11723   start_sequence ();
11724   {
11725     rtx operands[3];
11726     operands[0] = operand0;
11727     operands[1] = operand1;
11728     operands[2] = operand2;
11729 ix86_expand_binary_operator (MINUS, SImode, operands); DONE;
11730     operand0 = operands[0];
11731     operand1 = operands[1];
11732     operand2 = operands[2];
11733   }
11734   emit (gen_rtx_PARALLEL (VOIDmode,
11735   gen_rtvec (2,
11736     gen_rtx_SET (VOIDmode,
11737   operand0,
11738   gen_rtx_MINUS (SImode,
11739   operand1,
11740   operand2)),
11741     gen_rtx_CLOBBER (VOIDmode,
11742   gen_rtx_REG (CCmode,
11743   17)))));
11744   _val = get_insns ();
11745   end_sequence ();
11746   return _val;
11747 }
11748 
11749 /* ../../gcc/gcc/config/i386/i386.md:6539 */
11750 rtx
11751 gen_subhi3 (operand0, operand1, operand2)
11752      rtx operand0;
11753      rtx operand1;
11754      rtx operand2;
11755 {
11756   rtx _val = 0;
11757   start_sequence ();
11758   {
11759     rtx operands[3];
11760     operands[0] = operand0;
11761     operands[1] = operand1;
11762     operands[2] = operand2;
11763 ix86_expand_binary_operator (MINUS, HImode, operands); DONE;
11764     operand0 = operands[0];
11765     operand1 = operands[1];
11766     operand2 = operands[2];
11767   }
11768   emit (gen_rtx_PARALLEL (VOIDmode,
11769   gen_rtvec (2,
11770     gen_rtx_SET (VOIDmode,
11771   operand0,
11772   gen_rtx_MINUS (HImode,
11773   operand1,
11774   operand2)),
11775     gen_rtx_CLOBBER (VOIDmode,
11776   gen_rtx_REG (CCmode,
11777   17)))));
11778   _val = get_insns ();
11779   end_sequence ();
11780   return _val;
11781 }
11782 
11783 /* ../../gcc/gcc/config/i386/i386.md:6583 */
11784 rtx
11785 gen_subqi3 (operand0, operand1, operand2)
11786      rtx operand0;
11787      rtx operand1;
11788      rtx operand2;
11789 {
11790   rtx _val = 0;
11791   start_sequence ();
11792   {
11793     rtx operands[3];
11794     operands[0] = operand0;
11795     operands[1] = operand1;
11796     operands[2] = operand2;
11797 ix86_expand_binary_operator (MINUS, QImode, operands); DONE;
11798     operand0 = operands[0];
11799     operand1 = operands[1];
11800     operand2 = operands[2];
11801   }
11802   emit (gen_rtx_PARALLEL (VOIDmode,
11803   gen_rtvec (2,
11804     gen_rtx_SET (VOIDmode,
11805   operand0,
11806   gen_rtx_MINUS (QImode,
11807   operand1,
11808   operand2)),
11809     gen_rtx_CLOBBER (VOIDmode,
11810   gen_rtx_REG (CCmode,
11811   17)))));
11812   _val = get_insns ();
11813   end_sequence ();
11814   return _val;
11815 }
11816 
11817 /* ../../gcc/gcc/config/i386/i386.md:6640 */
11818 rtx
11819 gen_subxf3 (operand0, operand1, operand2)
11820      rtx operand0;
11821      rtx operand1;
11822      rtx operand2;
11823 {
11824   return gen_rtx_SET (VOIDmode,
11825   operand0,
11826   gen_rtx_MINUS (XFmode,
11827   operand1,
11828   operand2));
11829 }
11830 
11831 /* ../../gcc/gcc/config/i386/i386.md:6647 */
11832 rtx
11833 gen_subtf3 (operand0, operand1, operand2)
11834      rtx operand0;
11835      rtx operand1;
11836      rtx operand2;
11837 {
11838   return gen_rtx_SET (VOIDmode,
11839   operand0,
11840   gen_rtx_MINUS (TFmode,
11841   operand1,
11842   operand2));
11843 }
11844 
11845 /* ../../gcc/gcc/config/i386/i386.md:6654 */
11846 rtx
11847 gen_subdf3 (operand0, operand1, operand2)
11848      rtx operand0;
11849      rtx operand1;
11850      rtx operand2;
11851 {
11852   return gen_rtx_SET (VOIDmode,
11853   operand0,
11854   gen_rtx_MINUS (DFmode,
11855   operand1,
11856   operand2));
11857 }
11858 
11859 /* ../../gcc/gcc/config/i386/i386.md:6661 */
11860 rtx
11861 gen_subsf3 (operand0, operand1, operand2)
11862      rtx operand0;
11863      rtx operand1;
11864      rtx operand2;
11865 {
11866   return gen_rtx_SET (VOIDmode,
11867   operand0,
11868   gen_rtx_MINUS (SFmode,
11869   operand1,
11870   operand2));
11871 }
11872 
11873 /* ../../gcc/gcc/config/i386/i386.md:6670 */
11874 rtx
11875 gen_muldi3 (operand0, operand1, operand2)
11876      rtx operand0;
11877      rtx operand1;
11878      rtx operand2;
11879 {
11880   return gen_rtx_PARALLEL (VOIDmode,
11881   gen_rtvec (2,
11882     gen_rtx_SET (VOIDmode,
11883   operand0,
11884   gen_rtx_MULT (DImode,
11885   operand1,
11886   operand2)),
11887     gen_rtx_CLOBBER (VOIDmode,
11888   gen_rtx_REG (CCmode,
11889   17))));
11890 }
11891 
11892 /* ../../gcc/gcc/config/i386/i386.md:6693 */
11893 rtx
11894 gen_mulsi3 (operand0, operand1, operand2)
11895      rtx operand0;
11896      rtx operand1;
11897      rtx operand2;
11898 {
11899   return gen_rtx_PARALLEL (VOIDmode,
11900   gen_rtvec (2,
11901     gen_rtx_SET (VOIDmode,
11902   operand0,
11903   gen_rtx_MULT (SImode,
11904   operand1,
11905   operand2)),
11906     gen_rtx_CLOBBER (VOIDmode,
11907   gen_rtx_REG (CCmode,
11908   17))));
11909 }
11910 
11911 /* ../../gcc/gcc/config/i386/i386.md:6755 */
11912 rtx
11913 gen_mulhi3 (operand0, operand1, operand2)
11914      rtx operand0;
11915      rtx operand1;
11916      rtx operand2;
11917 {
11918   return gen_rtx_PARALLEL (VOIDmode,
11919   gen_rtvec (2,
11920     gen_rtx_SET (VOIDmode,
11921   operand0,
11922   gen_rtx_MULT (HImode,
11923   operand1,
11924   operand2)),
11925     gen_rtx_CLOBBER (VOIDmode,
11926   gen_rtx_REG (CCmode,
11927   17))));
11928 }
11929 
11930 /* ../../gcc/gcc/config/i386/i386.md:6779 */
11931 rtx
11932 gen_mulqi3 (operand0, operand1, operand2)
11933      rtx operand0;
11934      rtx operand1;
11935      rtx operand2;
11936 {
11937   return gen_rtx_PARALLEL (VOIDmode,
11938   gen_rtvec (2,
11939     gen_rtx_SET (VOIDmode,
11940   operand0,
11941   gen_rtx_MULT (QImode,
11942   operand1,
11943   operand2)),
11944     gen_rtx_CLOBBER (VOIDmode,
11945   gen_rtx_REG (CCmode,
11946   17))));
11947 }
11948 
11949 /* ../../gcc/gcc/config/i386/i386.md:6799 */
11950 rtx
11951 gen_umulqihi3 (operand0, operand1, operand2)
11952      rtx operand0;
11953      rtx operand1;
11954      rtx operand2;
11955 {
11956   return gen_rtx_PARALLEL (VOIDmode,
11957   gen_rtvec (2,
11958     gen_rtx_SET (VOIDmode,
11959   operand0,
11960   gen_rtx_MULT (HImode,
11961   gen_rtx_ZERO_EXTEND (HImode,
11962   operand1),
11963   gen_rtx_ZERO_EXTEND (HImode,
11964   operand2))),
11965     gen_rtx_CLOBBER (VOIDmode,
11966   gen_rtx_REG (CCmode,
11967   17))));
11968 }
11969 
11970 /* ../../gcc/gcc/config/i386/i386.md:6821 */
11971 rtx
11972 gen_mulqihi3 (operand0, operand1, operand2)
11973      rtx operand0;
11974      rtx operand1;
11975      rtx operand2;
11976 {
11977   return gen_rtx_PARALLEL (VOIDmode,
11978   gen_rtvec (2,
11979     gen_rtx_SET (VOIDmode,
11980   operand0,
11981   gen_rtx_MULT (HImode,
11982   gen_rtx_SIGN_EXTEND (HImode,
11983   operand1),
11984   gen_rtx_SIGN_EXTEND (HImode,
11985   operand2))),
11986     gen_rtx_CLOBBER (VOIDmode,
11987   gen_rtx_REG (CCmode,
11988   17))));
11989 }
11990 
11991 /* ../../gcc/gcc/config/i386/i386.md:6841 */
11992 rtx
11993 gen_umulditi3 (operand0, operand1, operand2)
11994      rtx operand0;
11995      rtx operand1;
11996      rtx operand2;
11997 {
11998   return gen_rtx_PARALLEL (VOIDmode,
11999   gen_rtvec (2,
12000     gen_rtx_SET (VOIDmode,
12001   operand0,
12002   gen_rtx_MULT (TImode,
12003   gen_rtx_ZERO_EXTEND (TImode,
12004   operand1),
12005   gen_rtx_ZERO_EXTEND (TImode,
12006   operand2))),
12007     gen_rtx_CLOBBER (VOIDmode,
12008   gen_rtx_REG (CCmode,
12009   17))));
12010 }
12011 
12012 /* ../../gcc/gcc/config/i386/i386.md:6865 */
12013 rtx
12014 gen_umulsidi3 (operand0, operand1, operand2)
12015      rtx operand0;
12016      rtx operand1;
12017      rtx operand2;
12018 {
12019   return gen_rtx_PARALLEL (VOIDmode,
12020   gen_rtvec (2,
12021     gen_rtx_SET (VOIDmode,
12022   operand0,
12023   gen_rtx_MULT (DImode,
12024   gen_rtx_ZERO_EXTEND (DImode,
12025   operand1),
12026   gen_rtx_ZERO_EXTEND (DImode,
12027   operand2))),
12028     gen_rtx_CLOBBER (VOIDmode,
12029   gen_rtx_REG (CCmode,
12030   17))));
12031 }
12032 
12033 /* ../../gcc/gcc/config/i386/i386.md:6888 */
12034 rtx
12035 gen_mulditi3 (operand0, operand1, operand2)
12036      rtx operand0;
12037      rtx operand1;
12038      rtx operand2;
12039 {
12040   return gen_rtx_PARALLEL (VOIDmode,
12041   gen_rtvec (2,
12042     gen_rtx_SET (VOIDmode,
12043   operand0,
12044   gen_rtx_MULT (TImode,
12045   gen_rtx_SIGN_EXTEND (TImode,
12046   operand1),
12047   gen_rtx_SIGN_EXTEND (TImode,
12048   operand2))),
12049     gen_rtx_CLOBBER (VOIDmode,
12050   gen_rtx_REG (CCmode,
12051   17))));
12052 }
12053 
12054 /* ../../gcc/gcc/config/i386/i386.md:6910 */
12055 rtx
12056 gen_mulsidi3 (operand0, operand1, operand2)
12057      rtx operand0;
12058      rtx operand1;
12059      rtx operand2;
12060 {
12061   return gen_rtx_PARALLEL (VOIDmode,
12062   gen_rtvec (2,
12063     gen_rtx_SET (VOIDmode,
12064   operand0,
12065   gen_rtx_MULT (DImode,
12066   gen_rtx_SIGN_EXTEND (DImode,
12067   operand1),
12068   gen_rtx_SIGN_EXTEND (DImode,
12069   operand2))),
12070     gen_rtx_CLOBBER (VOIDmode,
12071   gen_rtx_REG (CCmode,
12072   17))));
12073 }
12074 
12075 /* ../../gcc/gcc/config/i386/i386.md:6932 */
12076 rtx
12077 gen_umuldi3_highpart (operand0, operand1, operand2)
12078      rtx operand0;
12079      rtx operand1;
12080      rtx operand2;
12081 {
12082   return gen_rtx_PARALLEL (VOIDmode,
12083   gen_rtvec (3,
12084     gen_rtx_SET (VOIDmode,
12085   operand0,
12086   gen_rtx_TRUNCATE (DImode,
12087   gen_rtx_LSHIFTRT (TImode,
12088   gen_rtx_MULT (TImode,
12089   gen_rtx_ZERO_EXTEND (TImode,
12090   operand1),
12091   gen_rtx_ZERO_EXTEND (TImode,
12092   operand2)),
12093   GEN_INT (64LL)))),
12094     gen_rtx_CLOBBER (VOIDmode,
12095   gen_rtx_SCRATCH (DImode)),
12096     gen_rtx_CLOBBER (VOIDmode,
12097   gen_rtx_REG (CCmode,
12098   17))));
12099 }
12100 
12101 /* ../../gcc/gcc/config/i386/i386.md:6965 */
12102 rtx
12103 gen_umulsi3_highpart (operand0, operand1, operand2)
12104      rtx operand0;
12105      rtx operand1;
12106      rtx operand2;
12107 {
12108   return gen_rtx_PARALLEL (VOIDmode,
12109   gen_rtvec (3,
12110     gen_rtx_SET (VOIDmode,
12111   operand0,
12112   gen_rtx_TRUNCATE (SImode,
12113   gen_rtx_LSHIFTRT (DImode,
12114   gen_rtx_MULT (DImode,
12115   gen_rtx_ZERO_EXTEND (DImode,
12116   operand1),
12117   gen_rtx_ZERO_EXTEND (DImode,
12118   operand2)),
12119   GEN_INT (32LL)))),
12120     gen_rtx_CLOBBER (VOIDmode,
12121   gen_rtx_SCRATCH (SImode)),
12122     gen_rtx_CLOBBER (VOIDmode,
12123   gen_rtx_REG (CCmode,
12124   17))));
12125 }
12126 
12127 /* ../../gcc/gcc/config/i386/i386.md:7016 */
12128 rtx
12129 gen_smuldi3_highpart (operand0, operand1, operand2)
12130      rtx operand0;
12131      rtx operand1;
12132      rtx operand2;
12133 {
12134   return gen_rtx_PARALLEL (VOIDmode,
12135   gen_rtvec (3,
12136     gen_rtx_SET (VOIDmode,
12137   operand0,
12138   gen_rtx_TRUNCATE (DImode,
12139   gen_rtx_LSHIFTRT (TImode,
12140   gen_rtx_MULT (TImode,
12141   gen_rtx_SIGN_EXTEND (TImode,
12142   operand1),
12143   gen_rtx_SIGN_EXTEND (TImode,
12144   operand2)),
12145   GEN_INT (64LL)))),
12146     gen_rtx_CLOBBER (VOIDmode,
12147   gen_rtx_SCRATCH (DImode)),
12148     gen_rtx_CLOBBER (VOIDmode,
12149   gen_rtx_REG (CCmode,
12150   17))));
12151 }
12152 
12153 /* ../../gcc/gcc/config/i386/i386.md:7048 */
12154 rtx
12155 gen_smulsi3_highpart (operand0, operand1, operand2)
12156      rtx operand0;
12157      rtx operand1;
12158      rtx operand2;
12159 {
12160   return gen_rtx_PARALLEL (VOIDmode,
12161   gen_rtvec (3,
12162     gen_rtx_SET (VOIDmode,
12163   operand0,
12164   gen_rtx_TRUNCATE (SImode,
12165   gen_rtx_LSHIFTRT (DImode,
12166   gen_rtx_MULT (DImode,
12167   gen_rtx_SIGN_EXTEND (DImode,
12168   operand1),
12169   gen_rtx_SIGN_EXTEND (DImode,
12170   operand2)),
12171   GEN_INT (32LL)))),
12172     gen_rtx_CLOBBER (VOIDmode,
12173   gen_rtx_SCRATCH (SImode)),
12174     gen_rtx_CLOBBER (VOIDmode,
12175   gen_rtx_REG (CCmode,
12176   17))));
12177 }
12178 
12179 /* ../../gcc/gcc/config/i386/i386.md:7099 */
12180 rtx
12181 gen_mulxf3 (operand0, operand1, operand2)
12182      rtx operand0;
12183      rtx operand1;
12184      rtx operand2;
12185 {
12186   return gen_rtx_SET (VOIDmode,
12187   operand0,
12188   gen_rtx_MULT (XFmode,
12189   operand1,
12190   operand2));
12191 }
12192 
12193 /* ../../gcc/gcc/config/i386/i386.md:7106 */
12194 rtx
12195 gen_multf3 (operand0, operand1, operand2)
12196      rtx operand0;
12197      rtx operand1;
12198      rtx operand2;
12199 {
12200   return gen_rtx_SET (VOIDmode,
12201   operand0,
12202   gen_rtx_MULT (TFmode,
12203   operand1,
12204   operand2));
12205 }
12206 
12207 /* ../../gcc/gcc/config/i386/i386.md:7113 */
12208 rtx
12209 gen_muldf3 (operand0, operand1, operand2)
12210      rtx operand0;
12211      rtx operand1;
12212      rtx operand2;
12213 {
12214   return gen_rtx_SET (VOIDmode,
12215   operand0,
12216   gen_rtx_MULT (DFmode,
12217   operand1,
12218   operand2));
12219 }
12220 
12221 /* ../../gcc/gcc/config/i386/i386.md:7120 */
12222 rtx
12223 gen_mulsf3 (operand0, operand1, operand2)
12224      rtx operand0;
12225      rtx operand1;
12226      rtx operand2;
12227 {
12228   return gen_rtx_SET (VOIDmode,
12229   operand0,
12230   gen_rtx_MULT (SFmode,
12231   operand1,
12232   operand2));
12233 }
12234 
12235 /* ../../gcc/gcc/config/i386/i386.md:7153 */
12236 rtx
12237 gen_divxf3 (operand0, operand1, operand2)
12238      rtx operand0;
12239      rtx operand1;
12240      rtx operand2;
12241 {
12242   return gen_rtx_SET (VOIDmode,
12243   operand0,
12244   gen_rtx_DIV (XFmode,
12245   operand1,
12246   operand2));
12247 }
12248 
12249 /* ../../gcc/gcc/config/i386/i386.md:7160 */
12250 rtx
12251 gen_divtf3 (operand0, operand1, operand2)
12252      rtx operand0;
12253      rtx operand1;
12254      rtx operand2;
12255 {
12256   return gen_rtx_SET (VOIDmode,
12257   operand0,
12258   gen_rtx_DIV (TFmode,
12259   operand1,
12260   operand2));
12261 }
12262 
12263 /* ../../gcc/gcc/config/i386/i386.md:7167 */
12264 rtx
12265 gen_divdf3 (operand0, operand1, operand2)
12266      rtx operand0;
12267      rtx operand1;
12268      rtx operand2;
12269 {
12270   return gen_rtx_SET (VOIDmode,
12271   operand0,
12272   gen_rtx_DIV (DFmode,
12273   operand1,
12274   operand2));
12275 }
12276 
12277 /* ../../gcc/gcc/config/i386/i386.md:7174 */
12278 rtx
12279 gen_divsf3 (operand0, operand1, operand2)
12280      rtx operand0;
12281      rtx operand1;
12282      rtx operand2;
12283 {
12284   return gen_rtx_SET (VOIDmode,
12285   operand0,
12286   gen_rtx_DIV (SFmode,
12287   operand1,
12288   operand2));
12289 }
12290 
12291 /* ../../gcc/gcc/config/i386/i386.md:7183 */
12292 rtx
12293 gen_divmoddi4 (operand0, operand1, operand2, operand3)
12294      rtx operand0;
12295      rtx operand1;
12296      rtx operand2;
12297      rtx operand3;
12298 {
12299   return gen_rtx_PARALLEL (VOIDmode,
12300   gen_rtvec (3,
12301     gen_rtx_SET (VOIDmode,
12302   operand0,
12303   gen_rtx_DIV (DImode,
12304   operand1,
12305   operand2)),
12306     gen_rtx_SET (VOIDmode,
12307   operand3,
12308   gen_rtx_MOD (DImode,
12309   operand1,
12310   operand2)),
12311     gen_rtx_CLOBBER (VOIDmode,
12312   gen_rtx_REG (CCmode,
12313   17))));
12314 }
12315 
12316 /* ../../gcc/gcc/config/i386/i386.md:7232 */
12317 extern rtx gen_split_1202 PARAMS ((rtx *));
12318 rtx
12319 gen_split_1202 (operands)
12320       rtx *operands;
12321 {
12322   rtx operand0;
12323   rtx operand1;
12324   rtx operand2;
12325   rtx operand3;
12326   rtx operand4;
12327   rtx _val = 0;
12328   start_sequence ();
12329 {
12330   /* Avoid use of cltd in favor of a mov+shift.  */
12331   if (!TARGET_USE_CLTD && !optimize_size)
12332     {
12333       if (true_regnum (operands[1]))
12334         emit_move_insn (operands[0], operands[1]);
12335       else
12336   emit_move_insn (operands[3], operands[1]);
12337       operands[4] = operands[3];
12338     }
12339   else
12340     {
12341       if (true_regnum (operands[1]))
12342   abort();
12343       operands[4] = operands[1];
12344     }
12345 }
12346   operand0 = operands[0];
12347   operand1 = operands[1];
12348   operand2 = operands[2];
12349   operand3 = operands[3];
12350   operand4 = operands[4];
12351   emit (gen_rtx_PARALLEL (VOIDmode,
12352   gen_rtvec (2,
12353     gen_rtx_SET (VOIDmode,
12354   operand3,
12355   gen_rtx_ASHIFTRT (DImode,
12356   operand4,
12357   GEN_INT (63LL))),
12358     gen_rtx_CLOBBER (VOIDmode,
12359   gen_rtx_REG (CCmode,
12360   17)))));
12361   emit (gen_rtx_PARALLEL (VOIDmode,
12362   gen_rtvec (4,
12363     gen_rtx_SET (VOIDmode,
12364   operand0,
12365   gen_rtx_DIV (DImode,
12366   gen_rtx_REG (DImode,
12367   0),
12368   operand2)),
12369     gen_rtx_SET (VOIDmode,
12370   copy_rtx (operand3),
12371   gen_rtx_MOD (DImode,
12372   gen_rtx_REG (DImode,
12373   0),
12374   copy_rtx (operand2))),
12375     gen_rtx_USE (VOIDmode,
12376   copy_rtx (operand3)),
12377     gen_rtx_CLOBBER (VOIDmode,
12378   gen_rtx_REG (CCmode,
12379   17)))));
12380   _val = get_insns ();
12381   end_sequence ();
12382   return _val;
12383 }
12384 
12385 /* ../../gcc/gcc/config/i386/i386.md:7268 */
12386 rtx
12387 gen_divmodsi4 (operand0, operand1, operand2, operand3)
12388      rtx operand0;
12389      rtx operand1;
12390      rtx operand2;
12391      rtx operand3;
12392 {
12393   return gen_rtx_PARALLEL (VOIDmode,
12394   gen_rtvec (3,
12395     gen_rtx_SET (VOIDmode,
12396   operand0,
12397   gen_rtx_DIV (SImode,
12398   operand1,
12399   operand2)),
12400     gen_rtx_SET (VOIDmode,
12401   operand3,
12402   gen_rtx_MOD (SImode,
12403   operand1,
12404   operand2)),
12405     gen_rtx_CLOBBER (VOIDmode,
12406   gen_rtx_REG (CCmode,
12407   17))));
12408 }
12409 
12410 /* ../../gcc/gcc/config/i386/i386.md:7317 */
12411 extern rtx gen_split_1204 PARAMS ((rtx *));
12412 rtx
12413 gen_split_1204 (operands)
12414       rtx *operands;
12415 {
12416   rtx operand0;
12417   rtx operand1;
12418   rtx operand2;
12419   rtx operand3;
12420   rtx operand4;
12421   rtx _val = 0;
12422   start_sequence ();
12423 {
12424   /* Avoid use of cltd in favor of a mov+shift.  */
12425   if (!TARGET_USE_CLTD && !optimize_size)
12426     {
12427       if (true_regnum (operands[1]))
12428         emit_move_insn (operands[0], operands[1]);
12429       else
12430   emit_move_insn (operands[3], operands[1]);
12431       operands[4] = operands[3];
12432     }
12433   else
12434     {
12435       if (true_regnum (operands[1]))
12436   abort();
12437       operands[4] = operands[1];
12438     }
12439 }
12440   operand0 = operands[0];
12441   operand1 = operands[1];
12442   operand2 = operands[2];
12443   operand3 = operands[3];
12444   operand4 = operands[4];
12445   emit (gen_rtx_PARALLEL (VOIDmode,
12446   gen_rtvec (2,
12447     gen_rtx_SET (VOIDmode,
12448   operand3,
12449   gen_rtx_ASHIFTRT (SImode,
12450   operand4,
12451   GEN_INT (31LL))),
12452     gen_rtx_CLOBBER (VOIDmode,
12453   gen_rtx_REG (CCmode,
12454   17)))));
12455   emit (gen_rtx_PARALLEL (VOIDmode,
12456   gen_rtvec (4,
12457     gen_rtx_SET (VOIDmode,
12458   operand0,
12459   gen_rtx_DIV (SImode,
12460   gen_rtx_REG (SImode,
12461   0),
12462   operand2)),
12463     gen_rtx_SET (VOIDmode,
12464   copy_rtx (operand3),
12465   gen_rtx_MOD (SImode,
12466   gen_rtx_REG (SImode,
12467   0),
12468   copy_rtx (operand2))),
12469     gen_rtx_USE (VOIDmode,
12470   copy_rtx (operand3)),
12471     gen_rtx_CLOBBER (VOIDmode,
12472   gen_rtx_REG (CCmode,
12473   17)))));
12474   _val = get_insns ();
12475   end_sequence ();
12476   return _val;
12477 }
12478 
12479 /* ../../gcc/gcc/config/i386/i386.md:7392 */
12480 extern rtx gen_split_1205 PARAMS ((rtx *));
12481 rtx
12482 gen_split_1205 (operands)
12483       rtx *operands;
12484 {
12485   rtx operand0;
12486   rtx operand1;
12487   rtx operand2;
12488   rtx operand3;
12489   rtx _val = 0;
12490   start_sequence ();
12491 
12492   operand0 = operands[0];
12493   operand1 = operands[1];
12494   operand2 = operands[2];
12495   operand3 = operands[3];
12496   emit_insn (gen_rtx_SET (VOIDmode,
12497   operand3,
12498   const0_rtx));
12499   emit (gen_rtx_PARALLEL (VOIDmode,
12500   gen_rtvec (4,
12501     gen_rtx_SET (VOIDmode,
12502   operand0,
12503   gen_rtx_UDIV (DImode,
12504   operand1,
12505   operand2)),
12506     gen_rtx_SET (VOIDmode,
12507   copy_rtx (operand3),
12508   gen_rtx_UMOD (DImode,
12509   copy_rtx (operand1),
12510   copy_rtx (operand2))),
12511     gen_rtx_USE (VOIDmode,
12512   copy_rtx (operand3)),
12513     gen_rtx_CLOBBER (VOIDmode,
12514   gen_rtx_REG (CCmode,
12515   17)))));
12516   _val = get_insns ();
12517   end_sequence ();
12518   return _val;
12519 }
12520 
12521 /* ../../gcc/gcc/config/i386/i386.md:7436 */
12522 extern rtx gen_split_1206 PARAMS ((rtx *));
12523 rtx
12524 gen_split_1206 (operands)
12525       rtx *operands;
12526 {
12527   rtx operand0;
12528   rtx operand1;
12529   rtx operand2;
12530   rtx operand3;
12531   rtx _val = 0;
12532   start_sequence ();
12533 
12534   operand0 = operands[0];
12535   operand1 = operands[1];
12536   operand2 = operands[2];
12537   operand3 = operands[3];
12538   emit_insn (gen_rtx_SET (VOIDmode,
12539   operand3,
12540   const0_rtx));
12541   emit (gen_rtx_PARALLEL (VOIDmode,
12542   gen_rtvec (4,
12543     gen_rtx_SET (VOIDmode,
12544   operand0,
12545   gen_rtx_UDIV (SImode,
12546   operand1,
12547   operand2)),
12548     gen_rtx_SET (VOIDmode,
12549   copy_rtx (operand3),
12550   gen_rtx_UMOD (SImode,
12551   copy_rtx (operand1),
12552   copy_rtx (operand2))),
12553     gen_rtx_USE (VOIDmode,
12554   copy_rtx (operand3)),
12555     gen_rtx_CLOBBER (VOIDmode,
12556   gen_rtx_REG (CCmode,
12557   17)))));
12558   _val = get_insns ();
12559   end_sequence ();
12560   return _val;
12561 }
12562 
12563 /* ../../gcc/gcc/config/i386/i386.md:7453 */
12564 rtx
12565 gen_udivmodhi4 (operand0, operand1, operand2, operand3)
12566      rtx operand0;
12567      rtx operand1;
12568      rtx operand2;
12569      rtx operand3;
12570 {
12571   rtx operand4;
12572   rtx _val = 0;
12573   start_sequence ();
12574   {
12575     rtx operands[5];
12576     operands[0] = operand0;
12577     operands[1] = operand1;
12578     operands[2] = operand2;
12579     operands[3] = operand3;
12580 operands[4] = gen_reg_rtx (HImode);
12581     operand0 = operands[0];
12582     operand1 = operands[1];
12583     operand2 = operands[2];
12584     operand3 = operands[3];
12585     operand4 = operands[4];
12586   }
12587   emit_insn (gen_rtx_SET (VOIDmode,
12588   operand4,
12589   const0_rtx));
12590   emit (gen_rtx_PARALLEL (VOIDmode,
12591   gen_rtvec (4,
12592     gen_rtx_SET (VOIDmode,
12593   operand0,
12594   gen_rtx_UDIV (HImode,
12595   operand1,
12596   operand2)),
12597     gen_rtx_SET (VOIDmode,
12598   operand3,
12599   gen_rtx_UMOD (HImode,
12600   operand1,
12601   operand2)),
12602     gen_rtx_USE (VOIDmode,
12603   operand4),
12604     gen_rtx_CLOBBER (VOIDmode,
12605   gen_rtx_REG (CCmode,
12606   17)))));
12607   _val = get_insns ();
12608   end_sequence ();
12609   return _val;
12610 }
12611 
12612 /* ../../gcc/gcc/config/i386/i386.md:7535 */
12613 rtx
12614 gen_testsi_ccno_1 (operand0, operand1)
12615      rtx operand0;
12616      rtx operand1;
12617 {
12618   return gen_rtx_SET (VOIDmode,
12619   gen_rtx_REG (CCNOmode,
12620   17),
12621   gen_rtx_COMPARE (CCNOmode,
12622   gen_rtx_AND (SImode,
12623   operand0,
12624   operand1),
12625   const0_rtx));
12626 }
12627 
12628 /* ../../gcc/gcc/config/i386/i386.md:7556 */
12629 rtx
12630 gen_testqi_ccz_1 (operand0, operand1)
12631      rtx operand0;
12632      rtx operand1;
12633 {
12634   return gen_rtx_SET (VOIDmode,
12635   gen_rtx_REG (CCZmode,
12636   17),
12637   gen_rtx_COMPARE (CCZmode,
12638   gen_rtx_AND (QImode,
12639   operand0,
12640   operand1),
12641   const0_rtx));
12642 }
12643 
12644 /* ../../gcc/gcc/config/i386/i386.md:7585 */
12645 rtx
12646 gen_testqi_ext_ccno_0 (operand0, operand1)
12647      rtx operand0;
12648      rtx operand1;
12649 {
12650   return gen_rtx_SET (VOIDmode,
12651   gen_rtx_REG (CCNOmode,
12652   17),
12653   gen_rtx_COMPARE (CCNOmode,
12654   gen_rtx_AND (SImode,
12655   gen_rtx_ZERO_EXTRACT (SImode,
12656   operand0,
12657   GEN_INT (8LL),
12658   GEN_INT (8LL)),
12659   operand1),
12660   const0_rtx));
12661 }
12662 
12663 /* ../../gcc/gcc/config/i386/i386.md:7701 */
12664 extern rtx gen_split_1211 PARAMS ((rtx *));
12665 rtx
12666 gen_split_1211 (operands)
12667       rtx *operands;
12668 {
12669   rtx operand0;
12670   rtx operand1;
12671   rtx operand2;
12672   rtx operand3;
12673   rtx _val = 0;
12674   start_sequence ();
12675 {
12676   HOST_WIDE_INT len = INTVAL (operands[1]);
12677   HOST_WIDE_INT pos = INTVAL (operands[2]);
12678   HOST_WIDE_INT mask;
12679   enum machine_mode mode, submode;
12680 
12681   mode = GET_MODE (operands[0]);
12682   if (GET_CODE (operands[0]) == MEM)
12683     {
12684       /* ??? Combine likes to put non-volatile mem extractions in QImode
12685    no matter the size of the test.  So find a mode that works.  */
12686       if (! MEM_VOLATILE_P (operands[0]))
12687   {
12688     mode = smallest_mode_for_size (pos + len, MODE_INT);
12689     operands[0] = adjust_address (operands[0], mode, 0);
12690   }
12691     }
12692   else if (GET_CODE (operands[0]) == SUBREG
12693      && (submode = GET_MODE (SUBREG_REG (operands[0])),
12694          GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode))
12695      && pos + len <= GET_MODE_BITSIZE (submode))
12696     {
12697       /* Narrow a paradoxical subreg to prevent partial register stalls.  */
12698       mode = submode;
12699       operands[0] = SUBREG_REG (operands[0]);
12700     }
12701   else if (mode == HImode && pos + len <= 8)
12702     {
12703       /* Small HImode tests can be converted to QImode.  */
12704       mode = QImode;
12705       operands[0] = gen_lowpart (QImode, operands[0]);
12706     }
12707 
12708   mask  = ((HOST_WIDE_INT)1 << (pos + len)) - 1;
12709   mask &= ~(((HOST_WIDE_INT)1 << pos) - 1);
12710 
12711   operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode));
12712 }
12713   operand0 = operands[0];
12714   operand1 = operands[1];
12715   operand2 = operands[2];
12716   operand3 = operands[3];
12717   emit_insn (gen_rtx_SET (VOIDmode,
12718   gen_rtx_REG (CCNOmode,
12719   17),
12720   gen_rtx_COMPARE (CCNOmode,
12721   operand3,
12722   const0_rtx)));
12723   _val = get_insns ();
12724   end_sequence ();
12725   return _val;
12726 }
12727 
12728 /* ../../gcc/gcc/config/i386/i386.md:7754 */
12729 extern rtx gen_split_1212 PARAMS ((rtx *));
12730 rtx
12731 gen_split_1212 (operands)
12732       rtx *operands;
12733 {
12734   rtx operand0;
12735   rtx operand1;
12736   rtx _val = 0;
12737   start_sequence ();
12738 operands[0] = gen_lowpart (SImode, operands[0]);
12739    operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);
12740   operand0 = operands[0];
12741   operand1 = operands[1];
12742   emit_insn (gen_rtx_SET (VOIDmode,
12743   gen_rtx_REG (CCNOmode,
12744   17),
12745   gen_rtx_COMPARE (CCNOmode,
12746   gen_rtx_AND (SImode,
12747   gen_rtx_ZERO_EXTRACT (SImode,
12748   operand0,
12749   GEN_INT (8LL),
12750   GEN_INT (8LL)),
12751   operand1),
12752   const0_rtx)));
12753   _val = get_insns ();
12754   end_sequence ();
12755   return _val;
12756 }
12757 
12758 /* ../../gcc/gcc/config/i386/i386.md:7775 */
12759 extern rtx gen_split_1213 PARAMS ((rtx *));
12760 rtx
12761 gen_split_1213 (operands)
12762       rtx *operands;
12763 {
12764   rtx operand0;
12765   rtx operand1;
12766   rtx _val = 0;
12767   start_sequence ();
12768 operands[0] = gen_lowpart (QImode, operands[0]);
12769    operands[1] = gen_lowpart (QImode, operands[1]);
12770   operand0 = operands[0];
12771   operand1 = operands[1];
12772   emit_insn (gen_rtx_SET (VOIDmode,
12773   gen_rtx_REG (CCNOmode,
12774   17),
12775   gen_rtx_COMPARE (CCNOmode,
12776   gen_rtx_AND (QImode,
12777   operand0,
12778   operand1),
12779   const0_rtx)));
12780   _val = get_insns ();
12781   end_sequence ();
12782   return _val;
12783 }
12784 
12785 /* ../../gcc/gcc/config/i386/i386.md:7801 */
12786 rtx
12787 gen_anddi3 (operand0, operand1, operand2)
12788      rtx operand0;
12789      rtx operand1;
12790      rtx operand2;
12791 {
12792   rtx _val = 0;
12793   start_sequence ();
12794   {
12795     rtx operands[3];
12796     operands[0] = operand0;
12797     operands[1] = operand1;
12798     operands[2] = operand2;
12799 ix86_expand_binary_operator (AND, DImode, operands); DONE;
12800     operand0 = operands[0];
12801     operand1 = operands[1];
12802     operand2 = operands[2];
12803   }
12804   emit_insn (gen_rtx_SET (VOIDmode,
12805   operand0,
12806   gen_rtx_AND (DImode,
12807   operand1,
12808   operand2)));
12809   emit_insn (gen_rtx_CLOBBER (VOIDmode,
12810   gen_rtx_REG (CCmode,
12811   17)));
12812   _val = get_insns ();
12813   end_sequence ();
12814   return _val;
12815 }
12816 
12817 /* ../../gcc/gcc/config/i386/i386.md:7867 */
12818 rtx
12819 gen_andsi3 (operand0, operand1, operand2)
12820      rtx operand0;
12821      rtx operand1;
12822      rtx operand2;
12823 {
12824   rtx _val = 0;
12825   start_sequence ();
12826   {
12827     rtx operands[3];
12828     operands[0] = operand0;
12829     operands[1] = operand1;
12830     operands[2] = operand2;
12831 ix86_expand_binary_operator (AND, SImode, operands); DONE;
12832     operand0 = operands[0];
12833     operand1 = operands[1];
12834     operand2 = operands[2];
12835   }
12836   emit_insn (gen_rtx_SET (VOIDmode,
12837   operand0,
12838   gen_rtx_AND (SImode,
12839   operand1,
12840   operand2)));
12841   emit_insn (gen_rtx_CLOBBER (VOIDmode,
12842   gen_rtx_REG (CCmode,
12843   17)));
12844   _val = get_insns ();
12845   end_sequence ();
12846   return _val;
12847 }
12848 
12849 /* ../../gcc/gcc/config/i386/i386.md:7914 */
12850 extern rtx gen_split_1216 PARAMS ((rtx *));
12851 rtx
12852 gen_split_1216 (operands)
12853       rtx *operands;
12854 {
12855   rtx operand0;
12856   rtx operand1;
12857   rtx _val = 0;
12858   start_sequence ();
12859 operands[1] = gen_lowpart (HImode, operands[0]);
12860   operand0 = operands[0];
12861   operand1 = operands[1];
12862   emit_insn (gen_rtx_SET (VOIDmode,
12863   gen_rtx_STRICT_LOW_PART (VOIDmode,
12864   operand1),
12865   const0_rtx));
12866   _val = get_insns ();
12867   end_sequence ();
12868   return _val;
12869 }
12870 
12871 /* ../../gcc/gcc/config/i386/i386.md:7923 */
12872 extern rtx gen_split_1217 PARAMS ((rtx *));
12873 rtx
12874 gen_split_1217 (operands)
12875       rtx *operands;
12876 {
12877   rtx operand0;
12878   rtx operand1;
12879   rtx _val = 0;
12880   start_sequence ();
12881 operands[1] = gen_lowpart (QImode, operands[0]);
12882   operand0 = operands[0];
12883   operand1 = operands[1];
12884   emit_insn (gen_rtx_SET (VOIDmode,
12885   gen_rtx_STRICT_LOW_PART (VOIDmode,
12886   operand1),
12887   const0_rtx));
12888   _val = get_insns ();
12889   end_sequence ();
12890   return _val;
12891 }
12892 
12893 /* ../../gcc/gcc/config/i386/i386.md:7932 */
12894 extern rtx gen_split_1218 PARAMS ((rtx *));
12895 rtx
12896 gen_split_1218 (operands)
12897       rtx *operands;
12898 {
12899   rtx operand0;
12900   rtx _val = 0;
12901   start_sequence ();
12902 operands[0] = gen_lowpart (SImode, operands[0]);
12903   operand0 = operands[0];
12904   emit (gen_rtx_PARALLEL (VOIDmode,
12905   gen_rtvec (2,
12906     gen_rtx_SET (VOIDmode,
12907   gen_rtx_ZERO_EXTRACT (SImode,
12908   operand0,
12909   GEN_INT (8LL),
12910   GEN_INT (8LL)),
12911   gen_rtx_XOR (SImode,
12912   gen_rtx_ZERO_EXTRACT (SImode,
12913   copy_rtx (operand0),
12914   GEN_INT (8LL),
12915   GEN_INT (8LL)),
12916   gen_rtx_ZERO_EXTRACT (SImode,
12917   copy_rtx (operand0),
12918   GEN_INT (8LL),
12919   GEN_INT (8LL)))),
12920     gen_rtx_CLOBBER (VOIDmode,
12921   gen_rtx_REG (CCmode,
12922   17)))));
12923   _val = get_insns ();
12924   end_sequence ();
12925   return _val;
12926 }
12927 
12928 /* ../../gcc/gcc/config/i386/i386.md:7990 */
12929 rtx
12930 gen_andhi3 (operand0, operand1, operand2)
12931      rtx operand0;
12932      rtx operand1;
12933      rtx operand2;
12934 {
12935   rtx _val = 0;
12936   start_sequence ();
12937   {
12938     rtx operands[3];
12939     operands[0] = operand0;
12940     operands[1] = operand1;
12941     operands[2] = operand2;
12942 ix86_expand_binary_operator (AND, HImode, operands); DONE;
12943     operand0 = operands[0];
12944     operand1 = operands[1];
12945     operand2 = operands[2];
12946   }
12947   emit_insn (gen_rtx_SET (VOIDmode,
12948   operand0,
12949   gen_rtx_AND (HImode,
12950   operand1,
12951   operand2)));
12952   emit_insn (gen_rtx_CLOBBER (VOIDmode,
12953   gen_rtx_REG (CCmode,
12954   17)));
12955   _val = get_insns ();
12956   end_sequence ();
12957   return _val;
12958 }
12959 
12960 /* ../../gcc/gcc/config/i386/i386.md:8038 */
12961 rtx
12962 gen_andqi3 (operand0, operand1, operand2)
12963      rtx operand0;
12964      rtx operand1;
12965      rtx operand2;
12966 {
12967   rtx _val = 0;
12968   start_sequence ();
12969   {
12970     rtx operands[3];
12971     operands[0] = operand0;
12972     operands[1] = operand1;
12973     operands[2] = operand2;
12974 ix86_expand_binary_operator (AND, QImode, operands); DONE;
12975     operand0 = operands[0];
12976     operand1 = operands[1];
12977     operand2 = operands[2];
12978   }
12979   emit_insn (gen_rtx_SET (VOIDmode,
12980   operand0,
12981   gen_rtx_AND (QImode,
12982   operand1,
12983   operand2)));
12984   emit_insn (gen_rtx_CLOBBER (VOIDmode,
12985   gen_rtx_REG (CCmode,
12986   17)));
12987   _val = get_insns ();
12988   end_sequence ();
12989   return _val;
12990 }
12991 
12992 /* ../../gcc/gcc/config/i386/i386.md:8219 */
12993 extern rtx gen_split_1221 PARAMS ((rtx *));
12994 rtx
12995 gen_split_1221 (operands)
12996       rtx *operands;
12997 {
12998   rtx operand0;
12999   rtx operand1;
13000   rtx operand2;
13001   rtx _val = 0;
13002   start_sequence ();
13003 operands[0] = gen_lowpart (SImode, operands[0]);
13004    operands[1] = gen_lowpart (SImode, operands[1]);
13005    operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
13006   operand0 = operands[0];
13007   operand1 = operands[1];
13008   operand2 = operands[2];
13009   emit (gen_rtx_PARALLEL (VOIDmode,
13010   gen_rtvec (2,
13011     gen_rtx_SET (VOIDmode,
13012   gen_rtx_ZERO_EXTRACT (SImode,
13013   operand0,
13014   GEN_INT (8LL),
13015   GEN_INT (8LL)),
13016   gen_rtx_AND (SImode,
13017   gen_rtx_ZERO_EXTRACT (SImode,
13018   operand1,
13019   GEN_INT (8LL),
13020   GEN_INT (8LL)),
13021   operand2)),
13022     gen_rtx_CLOBBER (VOIDmode,
13023   gen_rtx_REG (CCmode,
13024   17)))));
13025   _val = get_insns ();
13026   end_sequence ();
13027   return _val;
13028 }
13029 
13030 /* ../../gcc/gcc/config/i386/i386.md:8240 */
13031 extern rtx gen_split_1222 PARAMS ((rtx *));
13032 rtx
13033 gen_split_1222 (operands)
13034       rtx *operands;
13035 {
13036   rtx operand0;
13037   rtx operand1;
13038   rtx operand2;
13039   rtx _val = 0;
13040   start_sequence ();
13041 operands[0] = gen_lowpart (QImode, operands[0]);
13042    operands[1] = gen_lowpart (QImode, operands[1]);
13043    operands[2] = gen_lowpart (QImode, operands[2]);
13044   operand0 = operands[0];
13045   operand1 = operands[1];
13046   operand2 = operands[2];
13047   emit (gen_rtx_PARALLEL (VOIDmode,
13048   gen_rtvec (2,
13049     gen_rtx_SET (VOIDmode,
13050   gen_rtx_STRICT_LOW_PART (VOIDmode,
13051   operand0),
13052   gen_rtx_AND (QImode,
13053   operand1,
13054   operand2)),
13055     gen_rtx_CLOBBER (VOIDmode,
13056   gen_rtx_REG (CCmode,
13057   17)))));
13058   _val = get_insns ();
13059   end_sequence ();
13060   return _val;
13061 }
13062 
13063 /* ../../gcc/gcc/config/i386/i386.md:8264 */
13064 rtx
13065 gen_iordi3 (operand0, operand1, operand2)
13066      rtx operand0;
13067      rtx operand1;
13068      rtx operand2;
13069 {
13070   rtx _val = 0;
13071   start_sequence ();
13072   {
13073     rtx operands[3];
13074     operands[0] = operand0;
13075     operands[1] = operand1;
13076     operands[2] = operand2;
13077 ix86_expand_binary_operator (IOR, DImode, operands); DONE;
13078     operand0 = operands[0];
13079     operand1 = operands[1];
13080     operand2 = operands[2];
13081   }
13082   emit_insn (gen_rtx_SET (VOIDmode,
13083   operand0,
13084   gen_rtx_IOR (DImode,
13085   operand1,
13086   operand2)));
13087   emit_insn (gen_rtx_CLOBBER (VOIDmode,
13088   gen_rtx_REG (CCmode,
13089   17)));
13090   _val = get_insns ();
13091   end_sequence ();
13092   return _val;
13093 }
13094 
13095 /* ../../gcc/gcc/config/i386/i386.md:8311 */
13096 rtx
13097 gen_iorsi3 (operand0, operand1, operand2)
13098      rtx operand0;
13099      rtx operand1;
13100      rtx operand2;
13101 {
13102   rtx _val = 0;
13103   start_sequence ();
13104   {
13105     rtx operands[3];
13106     operands[0] = operand0;
13107     operands[1] = operand1;
13108     operands[2] = operand2;
13109 ix86_expand_binary_operator (IOR, SImode, operands); DONE;
13110     operand0 = operands[0];
13111     operand1 = operands[1];
13112     operand2 = operands[2];
13113   }
13114   emit_insn (gen_rtx_SET (VOIDmode,
13115   operand0,
13116   gen_rtx_IOR (SImode,
13117   operand1,
13118   operand2)));
13119   emit_insn (gen_rtx_CLOBBER (VOIDmode,
13120   gen_rtx_REG (CCmode,
13121   17)));
13122   _val = get_insns ();
13123   end_sequence ();
13124   return _val;
13125 }
13126 
13127 /* ../../gcc/gcc/config/i386/i386.md:8404 */
13128 rtx
13129 gen_iorhi3 (operand0, operand1, operand2)
13130      rtx operand0;
13131      rtx operand1;
13132      rtx operand2;
13133 {
13134   rtx _val = 0;
13135   start_sequence ();
13136   {
13137     rtx operands[3];
13138     operands[0] = operand0;
13139     operands[1] = operand1;
13140     operands[2] = operand2;
13141 ix86_expand_binary_operator (IOR, HImode, operands); DONE;
13142     operand0 = operands[0];
13143     operand1 = operands[1];
13144     operand2 = operands[2];
13145   }
13146   emit_insn (gen_rtx_SET (VOIDmode,
13147   operand0,
13148   gen_rtx_IOR (HImode,
13149   operand1,
13150   operand2)));
13151   emit_insn (gen_rtx_CLOBBER (VOIDmode,
13152   gen_rtx_REG (CCmode,
13153   17)));
13154   _val = get_insns ();
13155   end_sequence ();
13156   return _val;
13157 }
13158 
13159 /* ../../gcc/gcc/config/i386/i386.md:8447 */
13160 rtx
13161 gen_iorqi3 (operand0, operand1, operand2)
13162      rtx operand0;
13163      rtx operand1;
13164      rtx operand2;
13165 {
13166   rtx _val = 0;
13167   start_sequence ();
13168   {
13169     rtx operands[3];
13170     operands[0] = operand0;
13171     operands[1] = operand1;
13172     operands[2] = operand2;
13173 ix86_expand_binary_operator (IOR, QImode, operands); DONE;
13174     operand0 = operands[0];
13175     operand1 = operands[1];
13176     operand2 = operands[2];
13177   }
13178   emit_insn (gen_rtx_SET (VOIDmode,
13179   operand0,
13180   gen_rtx_IOR (QImode,
13181   operand1,
13182   operand2)));
13183   emit_insn (gen_rtx_CLOBBER (VOIDmode,
13184   gen_rtx_REG (CCmode,
13185   17)));
13186   _val = get_insns ();
13187   end_sequence ();
13188   return _val;
13189 }
13190 
13191 /* ../../gcc/gcc/config/i386/i386.md:8592 */
13192 extern rtx gen_split_1227 PARAMS ((rtx *));
13193 rtx
13194 gen_split_1227 (operands)
13195       rtx *operands;
13196 {
13197   rtx operand0;
13198   rtx operand1;
13199   rtx operand2;
13200   rtx _val = 0;
13201   start_sequence ();
13202 operands[0] = gen_lowpart (SImode, operands[0]);
13203    operands[1] = gen_lowpart (SImode, operands[1]);
13204    operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
13205   operand0 = operands[0];
13206   operand1 = operands[1];
13207   operand2 = operands[2];
13208   emit (gen_rtx_PARALLEL (VOIDmode,
13209   gen_rtvec (2,
13210     gen_rtx_SET (VOIDmode,
13211   gen_rtx_ZERO_EXTRACT (SImode,
13212   operand0,
13213   GEN_INT (8LL),
13214   GEN_INT (8LL)),
13215   gen_rtx_IOR (SImode,
13216   gen_rtx_ZERO_EXTRACT (SImode,
13217   operand1,
13218   GEN_INT (8LL),
13219   GEN_INT (8LL)),
13220   operand2)),
13221     gen_rtx_CLOBBER (VOIDmode,
13222   gen_rtx_REG (CCmode,
13223   17)))));
13224   _val = get_insns ();
13225   end_sequence ();
13226   return _val;
13227 }
13228 
13229 /* ../../gcc/gcc/config/i386/i386.md:8613 */
13230 extern rtx gen_split_1228 PARAMS ((rtx *));
13231 rtx
13232 gen_split_1228 (operands)
13233       rtx *operands;
13234 {
13235   rtx operand0;
13236   rtx operand1;
13237   rtx operand2;
13238   rtx _val = 0;
13239   start_sequence ();
13240 operands[0] = gen_lowpart (QImode, operands[0]);
13241    operands[1] = gen_lowpart (QImode, operands[1]);
13242    operands[2] = gen_lowpart (QImode, operands[2]);
13243   operand0 = operands[0];
13244   operand1 = operands[1];
13245   operand2 = operands[2];
13246   emit (gen_rtx_PARALLEL (VOIDmode,
13247   gen_rtvec (2,
13248     gen_rtx_SET (VOIDmode,
13249   gen_rtx_STRICT_LOW_PART (VOIDmode,
13250   operand0),
13251   gen_rtx_IOR (QImode,
13252   operand1,
13253   operand2)),
13254     gen_rtx_CLOBBER (VOIDmode,
13255   gen_rtx_REG (CCmode,
13256   17)))));
13257   _val = get_insns ();
13258   end_sequence ();
13259   return _val;
13260 }
13261 
13262 /* ../../gcc/gcc/config/i386/i386.md:8637 */
13263 rtx
13264 gen_xordi3 (operand0, operand1, operand2)
13265      rtx operand0;
13266      rtx operand1;
13267      rtx operand2;
13268 {
13269   rtx _val = 0;
13270   start_sequence ();
13271   {
13272     rtx operands[3];
13273     operands[0] = operand0;
13274     operands[1] = operand1;
13275     operands[2] = operand2;
13276 ix86_expand_binary_operator (XOR, DImode, operands); DONE;
13277     operand0 = operands[0];
13278     operand1 = operands[1];
13279     operand2 = operands[2];
13280   }
13281   emit_insn (gen_rtx_SET (VOIDmode,
13282   operand0,
13283   gen_rtx_XOR (DImode,
13284   operand1,
13285   operand2)));
13286   emit_insn (gen_rtx_CLOBBER (VOIDmode,
13287   gen_rtx_REG (CCmode,
13288   17)));
13289   _val = get_insns ();
13290   end_sequence ();
13291   return _val;
13292 }
13293 
13294 /* ../../gcc/gcc/config/i386/i386.md:8687 */
13295 rtx
13296 gen_xorsi3 (operand0, operand1, operand2)
13297      rtx operand0;
13298      rtx operand1;
13299      rtx operand2;
13300 {
13301   rtx _val = 0;
13302   start_sequence ();
13303   {
13304     rtx operands[3];
13305     operands[0] = operand0;
13306     operands[1] = operand1;
13307     operands[2] = operand2;
13308 ix86_expand_binary_operator (XOR, SImode, operands); DONE;
13309     operand0 = operands[0];
13310     operand1 = operands[1];
13311     operand2 = operands[2];
13312   }
13313   emit_insn (gen_rtx_SET (VOIDmode,
13314   operand0,
13315   gen_rtx_XOR (SImode,
13316   operand1,
13317   operand2)));
13318   emit_insn (gen_rtx_CLOBBER (VOIDmode,
13319   gen_rtx_REG (CCmode,
13320   17)));
13321   _val = get_insns ();
13322   end_sequence ();
13323   return _val;
13324 }
13325 
13326 /* ../../gcc/gcc/config/i386/i386.md:8781 */
13327 rtx
13328 gen_xorhi3 (operand0, operand1, operand2)
13329      rtx operand0;
13330      rtx operand1;
13331      rtx operand2;
13332 {
13333   rtx _val = 0;
13334   start_sequence ();
13335   {
13336     rtx operands[3];
13337     operands[0] = operand0;
13338     operands[1] = operand1;
13339     operands[2] = operand2;
13340 ix86_expand_binary_operator (XOR, HImode, operands); DONE;
13341     operand0 = operands[0];
13342     operand1 = operands[1];
13343     operand2 = operands[2];
13344   }
13345   emit_insn (gen_rtx_SET (VOIDmode,
13346   operand0,
13347   gen_rtx_XOR (HImode,
13348   operand1,
13349   operand2)));
13350   emit_insn (gen_rtx_CLOBBER (VOIDmode,
13351   gen_rtx_REG (CCmode,
13352   17)));
13353   _val = get_insns ();
13354   end_sequence ();
13355   return _val;
13356 }
13357 
13358 /* ../../gcc/gcc/config/i386/i386.md:8824 */
13359 rtx
13360 gen_xorqi3 (operand0, operand1, operand2)
13361      rtx operand0;
13362      rtx operand1;
13363      rtx operand2;
13364 {
13365   rtx _val = 0;
13366   start_sequence ();
13367   {
13368     rtx operands[3];
13369     operands[0] = operand0;
13370     operands[1] = operand1;
13371     operands[2] = operand2;
13372 ix86_expand_binary_operator (XOR, QImode, operands); DONE;
13373     operand0 = operands[0];
13374     operand1 = operands[1];
13375     operand2 = operands[2];
13376   }
13377   emit_insn (gen_rtx_SET (VOIDmode,
13378   operand0,
13379   gen_rtx_XOR (QImode,
13380   operand1,
13381   operand2)));
13382   emit_insn (gen_rtx_CLOBBER (VOIDmode,
13383   gen_rtx_REG (CCmode,
13384   17)));
13385   _val = get_insns ();
13386   end_sequence ();
13387   return _val;
13388 }
13389 
13390 /* ../../gcc/gcc/config/i386/i386.md:9013 */
13391 rtx
13392 gen_xorqi_cc_ext_1 (operand0, operand1, operand2)
13393      rtx operand0;
13394      rtx operand1;
13395      rtx operand2;
13396 {
13397   return gen_rtx_PARALLEL (VOIDmode,
13398   gen_rtvec (2,
13399     gen_rtx_SET (VOIDmode,
13400   gen_rtx_REG (CCNOmode,
13401   17),
13402   gen_rtx_COMPARE (CCNOmode,
13403   gen_rtx_XOR (SImode,
13404   gen_rtx_ZERO_EXTRACT (SImode,
13405   operand1,
13406   GEN_INT (8LL),
13407   GEN_INT (8LL)),
13408   operand2),
13409   const0_rtx)),
13410     gen_rtx_SET (VOIDmode,
13411   gen_rtx_ZERO_EXTRACT (SImode,
13412   operand0,
13413   GEN_INT (8LL),
13414   GEN_INT (8LL)),
13415   gen_rtx_XOR (SImode,
13416   gen_rtx_ZERO_EXTRACT (SImode,
13417   operand1,
13418   GEN_INT (8LL),
13419   GEN_INT (8LL)),
13420   operand2))));
13421 }
13422 
13423 /* ../../gcc/gcc/config/i386/i386.md:9033 */
13424 extern rtx gen_split_1234 PARAMS ((rtx *));
13425 rtx
13426 gen_split_1234 (operands)
13427       rtx *operands;
13428 {
13429   rtx operand0;
13430   rtx operand1;
13431   rtx operand2;
13432   rtx _val = 0;
13433   start_sequence ();
13434 operands[0] = gen_lowpart (SImode, operands[0]);
13435    operands[1] = gen_lowpart (SImode, operands[1]);
13436    operands[2] = gen_int_mode ((INTVAL (operands[2]) >> 8) & 0xff, SImode);
13437   operand0 = operands[0];
13438   operand1 = operands[1];
13439   operand2 = operands[2];
13440   emit (gen_rtx_PARALLEL (VOIDmode,
13441   gen_rtvec (2,
13442     gen_rtx_SET (VOIDmode,
13443   gen_rtx_ZERO_EXTRACT (SImode,
13444   operand0,
13445   GEN_INT (8LL),
13446   GEN_INT (8LL)),
13447   gen_rtx_XOR (SImode,
13448   gen_rtx_ZERO_EXTRACT (SImode,
13449   operand1,
13450   GEN_INT (8LL),
13451   GEN_INT (8LL)),
13452   operand2)),
13453     gen_rtx_CLOBBER (VOIDmode,
13454   gen_rtx_REG (CCmode,
13455   17)))));
13456   _val = get_insns ();
13457   end_sequence ();
13458   return _val;
13459 }
13460 
13461 /* ../../gcc/gcc/config/i386/i386.md:9054 */
13462 extern rtx gen_split_1235 PARAMS ((rtx *));
13463 rtx
13464 gen_split_1235 (operands)
13465       rtx *operands;
13466 {
13467   rtx operand0;
13468   rtx operand1;
13469   rtx operand2;
13470   rtx _val = 0;
13471   start_sequence ();
13472 operands[0] = gen_lowpart (QImode, operands[0]);
13473    operands[1] = gen_lowpart (QImode, operands[1]);
13474    operands[2] = gen_lowpart (QImode, operands[2]);
13475   operand0 = operands[0];
13476   operand1 = operands[1];
13477   operand2 = operands[2];
13478   emit (gen_rtx_PARALLEL (VOIDmode,
13479   gen_rtvec (2,
13480     gen_rtx_SET (VOIDmode,
13481   gen_rtx_STRICT_LOW_PART (VOIDmode,
13482   operand0),
13483   gen_rtx_XOR (QImode,
13484   operand1,
13485   operand2)),
13486     gen_rtx_CLOBBER (VOIDmode,
13487   gen_rtx_REG (CCmode,
13488   17)))));
13489   _val = get_insns ();
13490   end_sequence ();
13491   return _val;
13492 }
13493 
13494 /* ../../gcc/gcc/config/i386/i386.md:9075 */
13495 rtx
13496 gen_negdi2 (operand0, operand1)
13497      rtx operand0;
13498      rtx operand1;
13499 {
13500   rtx _val = 0;
13501   start_sequence ();
13502   {
13503     rtx operands[2];
13504     operands[0] = operand0;
13505     operands[1] = operand1;
13506 ix86_expand_unary_operator (NEG, DImode, operands); DONE;
13507     operand0 = operands[0];
13508     operand1 = operands[1];
13509   }
13510   emit (gen_rtx_PARALLEL (VOIDmode,
13511   gen_rtvec (2,
13512     gen_rtx_SET (VOIDmode,
13513   operand0,
13514   gen_rtx_NEG (DImode,
13515   operand1)),
13516     gen_rtx_CLOBBER (VOIDmode,
13517   gen_rtx_REG (CCmode,
13518   17)))));
13519   _val = get_insns ();
13520   end_sequence ();
13521   return _val;
13522 }
13523 
13524 /* ../../gcc/gcc/config/i386/i386.md:9090 */
13525 extern rtx gen_split_1237 PARAMS ((rtx *));
13526 rtx
13527 gen_split_1237 (operands)
13528       rtx *operands;
13529 {
13530   rtx operand0;
13531   rtx operand1;
13532   rtx operand2;
13533   rtx operand3;
13534   rtx _val = 0;
13535   start_sequence ();
13536 split_di (operands+1, 1, operands+2, operands+3);
13537    split_di (operands+0, 1, operands+0, operands+1);
13538   operand0 = operands[0];
13539   operand1 = operands[1];
13540   operand2 = operands[2];
13541   operand3 = operands[3];
13542   emit (gen_rtx_PARALLEL (VOIDmode,
13543   gen_rtvec (2,
13544     gen_rtx_SET (VOIDmode,
13545   gen_rtx_REG (CCZmode,
13546   17),
13547   gen_rtx_COMPARE (CCZmode,
13548   gen_rtx_NEG (SImode,
13549   operand2),
13550   const0_rtx)),
13551     gen_rtx_SET (VOIDmode,
13552   operand0,
13553   gen_rtx_NEG (SImode,
13554   copy_rtx (operand2))))));
13555   emit (gen_rtx_PARALLEL (VOIDmode,
13556   gen_rtvec (2,
13557     gen_rtx_SET (VOIDmode,
13558   operand1,
13559   gen_rtx_PLUS (SImode,
13560   gen_rtx_PLUS (SImode,
13561   gen_rtx_LTU (SImode,
13562   gen_rtx_REG (CCmode,
13563   17),
13564   const0_rtx),
13565   operand3),
13566   const0_rtx)),
13567     gen_rtx_CLOBBER (VOIDmode,
13568   gen_rtx_REG (CCmode,
13569   17)))));
13570   emit (gen_rtx_PARALLEL (VOIDmode,
13571   gen_rtvec (2,
13572     gen_rtx_SET (VOIDmode,
13573   copy_rtx (operand1),
13574   gen_rtx_NEG (SImode,
13575   copy_rtx (operand1))),
13576     gen_rtx_CLOBBER (VOIDmode,
13577   gen_rtx_REG (CCmode,
13578   17)))));
13579   _val = get_insns ();
13580   end_sequence ();
13581   return _val;
13582 }
13583 
13584 /* ../../gcc/gcc/config/i386/i386.md:9137 */
13585 rtx
13586 gen_negsi2 (operand0, operand1)
13587      rtx operand0;
13588      rtx operand1;
13589 {
13590   rtx _val = 0;
13591   start_sequence ();
13592   {
13593     rtx operands[2];
13594     operands[0] = operand0;
13595     operands[1] = operand1;
13596 ix86_expand_unary_operator (NEG, SImode, operands); DONE;
13597     operand0 = operands[0];
13598     operand1 = operands[1];
13599   }
13600   emit (gen_rtx_PARALLEL (VOIDmode,
13601   gen_rtvec (2,
13602     gen_rtx_SET (VOIDmode,
13603   operand0,
13604   gen_rtx_NEG (SImode,
13605   operand1)),
13606     gen_rtx_CLOBBER (VOIDmode,
13607   gen_rtx_REG (CCmode,
13608   17)))));
13609   _val = get_insns ();
13610   end_sequence ();
13611   return _val;
13612 }
13613 
13614 /* ../../gcc/gcc/config/i386/i386.md:9197 */
13615 rtx
13616 gen_neghi2 (operand0, operand1)
13617      rtx operand0;
13618      rtx operand1;
13619 {
13620   rtx _val = 0;
13621   start_sequence ();
13622   {
13623     rtx operands[2];
13624     operands[0] = operand0;
13625     operands[1] = operand1;
13626 ix86_expand_unary_operator (NEG, HImode, operands); DONE;
13627     operand0 = operands[0];
13628     operand1 = operands[1];
13629   }
13630   emit (gen_rtx_PARALLEL (VOIDmode,
13631   gen_rtvec (2,
13632     gen_rtx_SET (VOIDmode,
13633   operand0,
13634   gen_rtx_NEG (HImode,
13635   operand1)),
13636     gen_rtx_CLOBBER (VOIDmode,
13637   gen_rtx_REG (CCmode,
13638   17)))));
13639   _val = get_insns ();
13640   end_sequence ();
13641   return _val;
13642 }
13643 
13644 /* ../../gcc/gcc/config/i386/i386.md:9224 */
13645 rtx
13646 gen_negqi2 (operand0, operand1)
13647      rtx operand0;
13648      rtx operand1;
13649 {
13650   rtx _val = 0;
13651   start_sequence ();
13652   {
13653     rtx operands[2];
13654     operands[0] = operand0;
13655     operands[1] = operand1;
13656 ix86_expand_unary_operator (NEG, QImode, operands); DONE;
13657     operand0 = operands[0];
13658     operand1 = operands[1];
13659   }
13660   emit (gen_rtx_PARALLEL (VOIDmode,
13661   gen_rtvec (2,
13662     gen_rtx_SET (VOIDmode,
13663   operand0,
13664   gen_rtx_NEG (QImode,
13665   operand1)),
13666     gen_rtx_CLOBBER (VOIDmode,
13667   gen_rtx_REG (CCmode,
13668   17)))));
13669   _val = get_insns ();
13670   end_sequence ();
13671   return _val;
13672 }
13673 
13674 /* ../../gcc/gcc/config/i386/i386.md:9253 */
13675 rtx
13676 gen_negsf2 (operand0, operand1)
13677      rtx operand0;
13678      rtx operand1;
13679 {
13680   rtx _val = 0;
13681   start_sequence ();
13682   {
13683     rtx operands[2];
13684     operands[0] = operand0;
13685     operands[1] = operand1;
13686 if (TARGET_SSE)
13687      {
13688        /* In case operand is in memory,  we will not use SSE.  */
13689        if (memory_operand (operands[0], VOIDmode)
13690      && rtx_equal_p (operands[0], operands[1]))
13691    emit_insn (gen_negsf2_memory (operands[0], operands[1]));
13692        else
13693   {
13694     /* Using SSE is tricky, since we need bitwise negation of -0
13695        in register.  */
13696     rtx reg = gen_reg_rtx (SFmode);
13697     rtx dest = operands[0];
13698 
13699     operands[1] = force_reg (SFmode, operands[1]);
13700     operands[0] = force_reg (SFmode, operands[0]);
13701     emit_move_insn (reg,
13702         gen_lowpart (SFmode,
13703                gen_int_mode (0x80000000, SImode)));
13704     emit_insn (gen_negsf2_ifs (operands[0], operands[1], reg));
13705     if (dest != operands[0])
13706       emit_move_insn (dest, operands[0]);
13707   }
13708        DONE;
13709      }
13710    ix86_expand_unary_operator (NEG, SFmode, operands); DONE;
13711     operand0 = operands[0];
13712     operand1 = operands[1];
13713   }
13714   emit (gen_rtx_PARALLEL (VOIDmode,
13715   gen_rtvec (2,
13716     gen_rtx_SET (VOIDmode,
13717   operand0,
13718   gen_rtx_NEG (SFmode,
13719   operand1)),
13720     gen_rtx_CLOBBER (VOIDmode,
13721   gen_rtx_REG (CCmode,
13722   17)))));
13723   _val = get_insns ();
13724   end_sequence ();
13725   return _val;
13726 }
13727 
13728 /* ../../gcc/gcc/config/i386/i386.md:9302 */
13729 extern rtx gen_split_1242 PARAMS ((rtx *));
13730 rtx
13731 gen_split_1242 (operands)
13732       rtx *operands;
13733 {
13734   rtx operand0;
13735   rtx operand1;
13736   rtx _val = 0;
13737   start_sequence ();
13738   operand0 = operands[0];
13739   operand1 = operands[1];
13740   emit (gen_rtx_PARALLEL (VOIDmode,
13741   gen_rtvec (2,
13742     gen_rtx_SET (VOIDmode,
13743   operand0,
13744   gen_rtx_NEG (SFmode,
13745   operand1)),
13746     gen_rtx_CLOBBER (VOIDmode,
13747   gen_rtx_REG (CCmode,
13748   17)))));
13749   _val = get_insns ();
13750   end_sequence ();
13751   return _val;
13752 }
13753 
13754 /* ../../gcc/gcc/config/i386/i386.md:9312 */
13755 extern rtx gen_split_1243 PARAMS ((rtx *));
13756 rtx
13757 gen_split_1243 (operands)
13758       rtx *operands;
13759 {
13760   rtx operand0;
13761   rtx operand1;
13762   rtx _val = 0;
13763   start_sequence ();
13764   operand0 = operands[0];
13765   operand1 = operands[1];
13766   emit (gen_rtx_PARALLEL (VOIDmode,
13767   gen_rtvec (2,
13768     gen_rtx_SET (VOIDmode,
13769   operand0,
13770   gen_rtx_NEG (SFmode,
13771   operand1)),
13772     gen_rtx_CLOBBER (VOIDmode,
13773   gen_rtx_REG (CCmode,
13774   17)))));
13775   _val = get_insns ();
13776   end_sequence ();
13777   return _val;
13778 }
13779 
13780 /* ../../gcc/gcc/config/i386/i386.md:9322 */
13781 extern rtx gen_split_1244 PARAMS ((rtx *));
13782 rtx
13783 gen_split_1244 (operands)
13784       rtx *operands;
13785 {
13786   rtx operand0;
13787   rtx operand1;
13788   rtx operand2;
13789   rtx _val = 0;
13790   start_sequence ();
13791 {
13792   if (operands_match_p (operands[0], operands[2]))
13793     {
13794       rtx tmp;
13795       tmp = operands[1];
13796       operands[1] = operands[2];
13797       operands[2] = tmp;
13798     }
13799 }
13800   operand0 = operands[0];
13801   operand1 = operands[1];
13802   operand2 = operands[2];
13803   emit_insn (gen_rtx_SET (VOIDmode,
13804   gen_rtx_SUBREG (TImode,
13805   operand0,
13806   0),
13807   gen_rtx_XOR (TImode,
13808   gen_rtx_SUBREG (TImode,
13809   operand1,
13810   0),
13811   gen_rtx_SUBREG (TImode,
13812   operand2,
13813   0))));
13814   _val = get_insns ();
13815   end_sequence ();
13816   return _val;
13817 }
13818 
13819 /* ../../gcc/gcc/config/i386/i386.md:9353 */
13820 extern rtx gen_split_1245 PARAMS ((rtx *));
13821 rtx
13822 gen_split_1245 (operands)
13823       rtx *operands;
13824 {
13825   rtx operand0;
13826   rtx operand1;
13827   rtx _val = 0;
13828   start_sequence ();
13829 
13830   operand0 = operands[0];
13831   operand1 = operands[1];
13832   emit_insn (gen_rtx_SET (VOIDmode,
13833   operand0,
13834   gen_rtx_NEG (SFmode,
13835   operand1)));
13836   _val = get_insns ();
13837   end_sequence ();
13838   return _val;
13839 }
13840 
13841 /* ../../gcc/gcc/config/i386/i386.md:9362 */
13842 extern rtx gen_split_1246 PARAMS ((rtx *));
13843 rtx
13844 gen_split_1246 (operands)
13845       rtx *operands;
13846 {
13847   rtx operand0;
13848   rtx operand1;
13849   rtx _val = 0;
13850   start_sequence ();
13851 operands[1] = gen_int_mode (0x80000000, SImode);
13852    operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
13853   operand0 = operands[0];
13854   operand1 = operands[1];
13855   emit (gen_rtx_PARALLEL (VOIDmode,
13856   gen_rtvec (2,
13857     gen_rtx_SET (VOIDmode,
13858   operand0,
13859   gen_rtx_XOR (SImode,
13860   copy_rtx (operand0),
13861   operand1)),
13862     gen_rtx_CLOBBER (VOIDmode,
13863   gen_rtx_REG (CCmode,
13864   17)))));
13865   _val = get_insns ();
13866   end_sequence ();
13867   return _val;
13868 }
13869 
13870 /* ../../gcc/gcc/config/i386/i386.md:9372 */
13871 extern rtx gen_split_1247 PARAMS ((rtx *));
13872 rtx
13873 gen_split_1247 (operands)
13874       rtx *operands;
13875 {
13876   rtx operand0;
13877   rtx operand1;
13878   rtx _val = 0;
13879   start_sequence ();
13880 {
13881   int size = GET_MODE_SIZE (GET_MODE (operands[1]));
13882 
13883   /* XFmode's size is 12, TFmode 16, but only 10 bytes are used.  */
13884   if (size >= 12)
13885     size = 10;
13886   operands[0] = adjust_address (operands[0], QImode, size - 1);
13887   operands[1] = gen_int_mode (0x80, QImode);
13888 }
13889   operand0 = operands[0];
13890   operand1 = operands[1];
13891   emit (gen_rtx_PARALLEL (VOIDmode,
13892   gen_rtvec (2,
13893     gen_rtx_SET (VOIDmode,
13894   operand0,
13895   gen_rtx_XOR (QImode,
13896   copy_rtx (operand0),
13897   operand1)),
13898     gen_rtx_CLOBBER (VOIDmode,
13899   gen_rtx_REG (CCmode,
13900   17)))));
13901   _val = get_insns ();
13902   end_sequence ();
13903   return _val;
13904 }
13905 
13906 /* ../../gcc/gcc/config/i386/i386.md:9389 */
13907 rtx
13908 gen_negdf2 (operand0, operand1)
13909      rtx operand0;
13910      rtx operand1;
13911 {
13912   rtx _val = 0;
13913   start_sequence ();
13914   {
13915     rtx operands[2];
13916     operands[0] = operand0;
13917     operands[1] = operand1;
13918 if (TARGET_SSE2)
13919      {
13920        /* In case operand is in memory,  we will not use SSE.  */
13921        if (memory_operand (operands[0], VOIDmode)
13922      && rtx_equal_p (operands[0], operands[1]))
13923    emit_insn (gen_negdf2_memory (operands[0], operands[1]));
13924        else
13925   {
13926     /* Using SSE is tricky, since we need bitwise negation of -0
13927        in register.  */
13928     rtx reg = gen_reg_rtx (DFmode);
13929 #if HOST_BITS_PER_WIDE_INT >= 64
13930     rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
13931 #else
13932     rtx imm = immed_double_const (0, 0x80000000, DImode);
13933 #endif
13934     rtx dest = operands[0];
13935 
13936     operands[1] = force_reg (DFmode, operands[1]);
13937     operands[0] = force_reg (DFmode, operands[0]);
13938     emit_move_insn (reg, gen_lowpart (DFmode, imm));
13939     emit_insn (gen_negdf2_ifs (operands[0], operands[1], reg));
13940     if (dest != operands[0])
13941       emit_move_insn (dest, operands[0]);
13942   }
13943        DONE;
13944      }
13945    ix86_expand_unary_operator (NEG, DFmode, operands); DONE;
13946     operand0 = operands[0];
13947     operand1 = operands[1];
13948   }
13949   emit (gen_rtx_PARALLEL (VOIDmode,
13950   gen_rtvec (2,
13951     gen_rtx_SET (VOIDmode,
13952   operand0,
13953   gen_rtx_NEG (DFmode,
13954   operand1)),
13955     gen_rtx_CLOBBER (VOIDmode,
13956   gen_rtx_REG (CCmode,
13957   17)))));
13958   _val = get_insns ();
13959   end_sequence ();
13960   return _val;
13961 }
13962 
13963 /* ../../gcc/gcc/config/i386/i386.md:9452 */
13964 extern rtx gen_split_1249 PARAMS ((rtx *));
13965 rtx
13966 gen_split_1249 (operands)
13967       rtx *operands;
13968 {
13969   rtx operand0;
13970   rtx operand1;
13971   rtx _val = 0;
13972   start_sequence ();
13973   operand0 = operands[0];
13974   operand1 = operands[1];
13975   emit (gen_rtx_PARALLEL (VOIDmode,
13976   gen_rtvec (2,
13977     gen_rtx_SET (VOIDmode,
13978   operand0,
13979   gen_rtx_NEG (DFmode,
13980   operand1)),
13981     gen_rtx_CLOBBER (VOIDmode,
13982   gen_rtx_REG (CCmode,
13983   17)))));
13984   _val = get_insns ();
13985   end_sequence ();
13986   return _val;
13987 }
13988 
13989 /* ../../gcc/gcc/config/i386/i386.md:9462 */
13990 extern rtx gen_split_1250 PARAMS ((rtx *));
13991 rtx
13992 gen_split_1250 (operands)
13993       rtx *operands;
13994 {
13995   rtx operand0;
13996   rtx operand1;
13997   rtx _val = 0;
13998   start_sequence ();
13999   operand0 = operands[0];
14000   operand1 = operands[1];
14001   emit (gen_rtx_PARALLEL (VOIDmode,
14002   gen_rtvec (2,
14003     gen_rtx_SET (VOIDmode,
14004   operand0,
14005   gen_rtx_NEG (DFmode,
14006   operand1)),
14007     gen_rtx_CLOBBER (VOIDmode,
14008   gen_rtx_REG (CCmode,
14009   17)))));
14010   _val = get_insns ();
14011   end_sequence ();
14012   return _val;
14013 }
14014 
14015 /* ../../gcc/gcc/config/i386/i386.md:9473 */
14016 extern rtx gen_split_1251 PARAMS ((rtx *));
14017 rtx
14018 gen_split_1251 (operands)
14019       rtx *operands;
14020 {
14021   rtx operand0;
14022   rtx operand1;
14023   rtx operand2;
14024   rtx _val = 0;
14025   start_sequence ();
14026 operands[0] = gen_lowpart (DImode, operands[0]);
14027     operands[1] = gen_lowpart (DImode, operands[1]);
14028     operands[2] = gen_lowpart (DImode, operands[2]);
14029   operand0 = operands[0];
14030   operand1 = operands[1];
14031   operand2 = operands[2];
14032   emit (gen_rtx_PARALLEL (VOIDmode,
14033   gen_rtvec (2,
14034     gen_rtx_SET (VOIDmode,
14035   operand0,
14036   gen_rtx_XOR (DImode,
14037   operand1,
14038   operand2)),
14039     gen_rtx_CLOBBER (VOIDmode,
14040   gen_rtx_REG (CCmode,
14041   17)))));
14042   _val = get_insns ();
14043   end_sequence ();
14044   return _val;
14045 }
14046 
14047 /* ../../gcc/gcc/config/i386/i386.md:9486 */
14048 extern rtx gen_split_1252 PARAMS ((rtx *));
14049 rtx
14050 gen_split_1252 (operands)
14051       rtx *operands;
14052 {
14053   rtx operand0;
14054   rtx operand1;
14055   rtx operand2;
14056   rtx _val = 0;
14057   start_sequence ();
14058 {
14059   if (operands_match_p (operands[0], operands[2]))
14060     {
14061       rtx tmp;
14062       tmp = operands[1];
14063       operands[1] = operands[2];
14064       operands[2] = tmp;
14065     }
14066 }
14067   operand0 = operands[0];
14068   operand1 = operands[1];
14069   operand2 = operands[2];
14070   emit_insn (gen_rtx_SET (VOIDmode,
14071   gen_rtx_SUBREG (TImode,
14072   operand0,
14073   0),
14074   gen_rtx_XOR (TImode,
14075   gen_rtx_SUBREG (TImode,
14076   operand1,
14077   0),
14078   gen_rtx_SUBREG (TImode,
14079   operand2,
14080   0))));
14081   _val = get_insns ();
14082   end_sequence ();
14083   return _val;
14084 }
14085 
14086 /* ../../gcc/gcc/config/i386/i386.md:9528 */
14087 extern rtx gen_split_1253 PARAMS ((rtx *));
14088 rtx
14089 gen_split_1253 (operands)
14090       rtx *operands;
14091 {
14092   rtx operand0;
14093   rtx operand1;
14094   rtx _val = 0;
14095   start_sequence ();
14096 
14097   operand0 = operands[0];
14098   operand1 = operands[1];
14099   emit_insn (gen_rtx_SET (VOIDmode,
14100   operand0,
14101   gen_rtx_NEG (DFmode,
14102   operand1)));
14103   _val = get_insns ();
14104   end_sequence ();
14105   return _val;
14106 }
14107 
14108 /* ../../gcc/gcc/config/i386/i386.md:9537 */
14109 extern rtx gen_split_1254 PARAMS ((rtx *));
14110 rtx
14111 gen_split_1254 (operands)
14112       rtx *operands;
14113 {
14114   rtx operand0;
14115   rtx operand1;
14116   rtx operand2;
14117   rtx operand3;
14118   rtx operand4;
14119   rtx _val = 0;
14120   start_sequence ();
14121 operands[4] = gen_int_mode (0x80000000, SImode);
14122    split_di (operands+0, 1, operands+2, operands+3);
14123   operand0 = operands[0];
14124   operand1 = operands[1];
14125   operand2 = operands[2];
14126   operand3 = operands[3];
14127   operand4 = operands[4];
14128   emit (gen_rtx_PARALLEL (VOIDmode,
14129   gen_rtvec (2,
14130     gen_rtx_SET (VOIDmode,
14131   operand3,
14132   gen_rtx_XOR (SImode,
14133   copy_rtx (operand3),
14134   operand4)),
14135     gen_rtx_CLOBBER (VOIDmode,
14136   gen_rtx_REG (CCmode,
14137   17)))));
14138   _val = get_insns ();
14139   end_sequence ();
14140   return _val;
14141 }
14142 
14143 /* ../../gcc/gcc/config/i386/i386.md:9547 */
14144 rtx
14145 gen_negxf2 (operand0, operand1)
14146      rtx operand0;
14147      rtx operand1;
14148 {
14149   rtx _val = 0;
14150   start_sequence ();
14151   {
14152     rtx operands[2];
14153     operands[0] = operand0;
14154     operands[1] = operand1;
14155 ix86_expand_unary_operator (NEG, XFmode, operands); DONE;
14156     operand0 = operands[0];
14157     operand1 = operands[1];
14158   }
14159   emit (gen_rtx_PARALLEL (VOIDmode,
14160   gen_rtvec (2,
14161     gen_rtx_SET (VOIDmode,
14162   operand0,
14163   gen_rtx_NEG (XFmode,
14164   operand1)),
14165     gen_rtx_CLOBBER (VOIDmode,
14166   gen_rtx_REG (CCmode,
14167   17)))));
14168   _val = get_insns ();
14169   end_sequence ();
14170   return _val;
14171 }
14172 
14173 /* ../../gcc/gcc/config/i386/i386.md:9554 */
14174 rtx
14175 gen_negtf2 (operand0, operand1)
14176      rtx operand0;
14177      rtx operand1;
14178 {
14179   rtx _val = 0;
14180   start_sequence ();
14181   {
14182     rtx operands[2];
14183     operands[0] = operand0;
14184     operands[1] = operand1;
14185 ix86_expand_unary_operator (NEG, TFmode, operands); DONE;
14186     operand0 = operands[0];
14187     operand1 = operands[1];
14188   }
14189   emit (gen_rtx_PARALLEL (VOIDmode,
14190   gen_rtvec (2,
14191     gen_rtx_SET (VOIDmode,
14192   operand0,
14193   gen_rtx_NEG (TFmode,
14194   operand1)),
14195     gen_rtx_CLOBBER (VOIDmode,
14196   gen_rtx_REG (CCmode,
14197   17)))));
14198   _val = get_insns ();
14199   end_sequence ();
14200   return _val;
14201 }
14202 
14203 /* ../../gcc/gcc/config/i386/i386.md:9572 */
14204 extern rtx gen_split_1257 PARAMS ((rtx *));
14205 rtx
14206 gen_split_1257 (operands)
14207       rtx *operands;
14208 {
14209   rtx operand0;
14210   rtx operand1;
14211   rtx _val = 0;
14212   start_sequence ();
14213 
14214   operand0 = operands[0];
14215   operand1 = operands[1];
14216   emit_insn (gen_rtx_SET (VOIDmode,
14217   operand0,
14218   gen_rtx_NEG (XFmode,
14219   operand1)));
14220   _val = get_insns ();
14221   end_sequence ();
14222   return _val;
14223 }
14224 
14225 /* ../../gcc/gcc/config/i386/i386.md:9581 */
14226 extern rtx gen_split_1258 PARAMS ((rtx *));
14227 rtx
14228 gen_split_1258 (operands)
14229       rtx *operands;
14230 {
14231   rtx operand0;
14232   rtx operand1;
14233   rtx _val = 0;
14234   start_sequence ();
14235 operands[1] = GEN_INT (0x8000);
14236    operands[0] = gen_rtx_REG (SImode,
14237             true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));
14238   operand0 = operands[0];
14239   operand1 = operands[1];
14240   emit (gen_rtx_PARALLEL (VOIDmode,
14241   gen_rtvec (2,
14242     gen_rtx_SET (VOIDmode,
14243   operand0,
14244   gen_rtx_XOR (SImode,
14245   copy_rtx (operand0),
14246   operand1)),
14247     gen_rtx_CLOBBER (VOIDmode,
14248   gen_rtx_REG (CCmode,
14249   17)))));
14250   _val = get_insns ();
14251   end_sequence ();
14252   return _val;
14253 }
14254 
14255 /* ../../gcc/gcc/config/i386/i386.md:9602 */
14256 extern rtx gen_split_1259 PARAMS ((rtx *));
14257 rtx
14258 gen_split_1259 (operands)
14259       rtx *operands;
14260 {
14261   rtx operand0;
14262   rtx operand1;
14263   rtx _val = 0;
14264   start_sequence ();
14265 
14266   operand0 = operands[0];
14267   operand1 = operands[1];
14268   emit_insn (gen_rtx_SET (VOIDmode,
14269   operand0,
14270   gen_rtx_NEG (TFmode,
14271   operand1)));
14272   _val = get_insns ();
14273   end_sequence ();
14274   return _val;
14275 }
14276 
14277 /* ../../gcc/gcc/config/i386/i386.md:9611 */
14278 extern rtx gen_split_1260 PARAMS ((rtx *));
14279 rtx
14280 gen_split_1260 (operands)
14281       rtx *operands;
14282 {
14283   rtx operand0;
14284   rtx operand1;
14285   rtx _val = 0;
14286   start_sequence ();
14287 operands[1] = GEN_INT (0x8000);
14288    operands[0] = gen_rtx_REG (SImode,
14289             true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));
14290   operand0 = operands[0];
14291   operand1 = operands[1];
14292   emit (gen_rtx_PARALLEL (VOIDmode,
14293   gen_rtvec (2,
14294     gen_rtx_SET (VOIDmode,
14295   operand0,
14296   gen_rtx_XOR (SImode,
14297   copy_rtx (operand0),
14298   operand1)),
14299     gen_rtx_CLOBBER (VOIDmode,
14300   gen_rtx_REG (CCmode,
14301   17)))));
14302   _val = get_insns ();
14303   end_sequence ();
14304   return _val;
14305 }
14306 
14307 /* ../../gcc/gcc/config/i386/i386.md:9713 */
14308 rtx
14309 gen_abssf2 (operand0, operand1)
14310      rtx operand0;
14311      rtx operand1;
14312 {
14313   rtx _val = 0;
14314   start_sequence ();
14315   {
14316     rtx operands[2];
14317     operands[0] = operand0;
14318     operands[1] = operand1;
14319 if (TARGET_SSE)
14320      {
14321        /* In case operand is in memory,  we will not use SSE.  */
14322        if (memory_operand (operands[0], VOIDmode)
14323      && rtx_equal_p (operands[0], operands[1]))
14324    emit_insn (gen_abssf2_memory (operands[0], operands[1]));
14325        else
14326   {
14327     /* Using SSE is tricky, since we need bitwise negation of -0
14328        in register.  */
14329     rtx reg = gen_reg_rtx (SFmode);
14330     rtx dest = operands[0];
14331 
14332     operands[1] = force_reg (SFmode, operands[1]);
14333     operands[0] = force_reg (SFmode, operands[0]);
14334     emit_move_insn (reg,
14335         gen_lowpart (SFmode,
14336                gen_int_mode (0x80000000, SImode)));
14337     emit_insn (gen_abssf2_ifs (operands[0], operands[1], reg));
14338     if (dest != operands[0])
14339       emit_move_insn (dest, operands[0]);
14340   }
14341        DONE;
14342      }
14343    ix86_expand_unary_operator (ABS, SFmode, operands); DONE;
14344     operand0 = operands[0];
14345     operand1 = operands[1];
14346   }
14347   emit (gen_rtx_PARALLEL (VOIDmode,
14348   gen_rtvec (2,
14349     gen_rtx_SET (VOIDmode,
14350   operand0,
14351   gen_rtx_NEG (SFmode,
14352   operand1)),
14353     gen_rtx_CLOBBER (VOIDmode,
14354   gen_rtx_REG (CCmode,
14355   17)))));
14356   _val = get_insns ();
14357   end_sequence ();
14358   return _val;
14359 }
14360 
14361 /* ../../gcc/gcc/config/i386/i386.md:9762 */
14362 extern rtx gen_split_1262 PARAMS ((rtx *));
14363 rtx
14364 gen_split_1262 (operands)
14365       rtx *operands;
14366 {
14367   rtx operand0;
14368   rtx operand1;
14369   rtx _val = 0;
14370   start_sequence ();
14371   operand0 = operands[0];
14372   operand1 = operands[1];
14373   emit (gen_rtx_PARALLEL (VOIDmode,
14374   gen_rtvec (2,
14375     gen_rtx_SET (VOIDmode,
14376   operand0,
14377   gen_rtx_ABS (SFmode,
14378   operand1)),
14379     gen_rtx_CLOBBER (VOIDmode,
14380   gen_rtx_REG (CCmode,
14381   17)))));
14382   _val = get_insns ();
14383   end_sequence ();
14384   return _val;
14385 }
14386 
14387 /* ../../gcc/gcc/config/i386/i386.md:9772 */
14388 extern rtx gen_split_1263 PARAMS ((rtx *));
14389 rtx
14390 gen_split_1263 (operands)
14391       rtx *operands;
14392 {
14393   rtx operand0;
14394   rtx operand1;
14395   rtx _val = 0;
14396   start_sequence ();
14397   operand0 = operands[0];
14398   operand1 = operands[1];
14399   emit (gen_rtx_PARALLEL (VOIDmode,
14400   gen_rtvec (2,
14401     gen_rtx_SET (VOIDmode,
14402   operand0,
14403   gen_rtx_ABS (SFmode,
14404   operand1)),
14405     gen_rtx_CLOBBER (VOIDmode,
14406   gen_rtx_REG (CCmode,
14407   17)))));
14408   _val = get_insns ();
14409   end_sequence ();
14410   return _val;
14411 }
14412 
14413 /* ../../gcc/gcc/config/i386/i386.md:9782 */
14414 extern rtx gen_split_1264 PARAMS ((rtx *));
14415 rtx
14416 gen_split_1264 (operands)
14417       rtx *operands;
14418 {
14419   rtx operand0;
14420   rtx operand1;
14421   rtx operand2;
14422   rtx _val = 0;
14423   start_sequence ();
14424   operand0 = operands[0];
14425   operand1 = operands[1];
14426   operand2 = operands[2];
14427   emit_insn (gen_rtx_SET (VOIDmode,
14428   gen_rtx_SUBREG (TImode,
14429   operand0,
14430   0),
14431   gen_rtx_AND (TImode,
14432   gen_rtx_NOT (TImode,
14433   gen_rtx_SUBREG (TImode,
14434   operand2,
14435   0)),
14436   gen_rtx_SUBREG (TImode,
14437   operand1,
14438   0))));
14439   _val = get_insns ();
14440   end_sequence ();
14441   return _val;
14442 }
14443 
14444 /* ../../gcc/gcc/config/i386/i386.md:9802 */
14445 extern rtx gen_split_1265 PARAMS ((rtx *));
14446 rtx
14447 gen_split_1265 (operands)
14448       rtx *operands;
14449 {
14450   rtx operand0;
14451   rtx operand1;
14452   rtx _val = 0;
14453   start_sequence ();
14454 
14455   operand0 = operands[0];
14456   operand1 = operands[1];
14457   emit_insn (gen_rtx_SET (VOIDmode,
14458   operand0,
14459   gen_rtx_ABS (SFmode,
14460   operand1)));
14461   _val = get_insns ();
14462   end_sequence ();
14463   return _val;
14464 }
14465 
14466 /* ../../gcc/gcc/config/i386/i386.md:9811 */
14467 extern rtx gen_split_1266 PARAMS ((rtx *));
14468 rtx
14469 gen_split_1266 (operands)
14470       rtx *operands;
14471 {
14472   rtx operand0;
14473   rtx operand1;
14474   rtx _val = 0;
14475   start_sequence ();
14476 operands[1] = gen_int_mode (~0x80000000, SImode);
14477    operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]));
14478   operand0 = operands[0];
14479   operand1 = operands[1];
14480   emit (gen_rtx_PARALLEL (VOIDmode,
14481   gen_rtvec (2,
14482     gen_rtx_SET (VOIDmode,
14483   operand0,
14484   gen_rtx_AND (SImode,
14485   copy_rtx (operand0),
14486   operand1)),
14487     gen_rtx_CLOBBER (VOIDmode,
14488   gen_rtx_REG (CCmode,
14489   17)))));
14490   _val = get_insns ();
14491   end_sequence ();
14492   return _val;
14493 }
14494 
14495 /* ../../gcc/gcc/config/i386/i386.md:9821 */
14496 extern rtx gen_split_1267 PARAMS ((rtx *));
14497 rtx
14498 gen_split_1267 (operands)
14499       rtx *operands;
14500 {
14501   rtx operand0;
14502   rtx operand1;
14503   rtx _val = 0;
14504   start_sequence ();
14505 {
14506   int size = GET_MODE_SIZE (GET_MODE (operands[1]));
14507 
14508   /* XFmode's size is 12, TFmode 16, but only 10 bytes are used.  */
14509   if (size >= 12)
14510     size = 10;
14511   operands[0] = adjust_address (operands[0], QImode, size - 1);
14512   operands[1] = gen_int_mode (~0x80, QImode);
14513 }
14514   operand0 = operands[0];
14515   operand1 = operands[1];
14516   emit (gen_rtx_PARALLEL (VOIDmode,
14517   gen_rtvec (2,
14518     gen_rtx_SET (VOIDmode,
14519   operand0,
14520   gen_rtx_AND (QImode,
14521   copy_rtx (operand0),
14522   operand1)),
14523     gen_rtx_CLOBBER (VOIDmode,
14524   gen_rtx_REG (CCmode,
14525   17)))));
14526   _val = get_insns ();
14527   end_sequence ();
14528   return _val;
14529 }
14530 
14531 /* ../../gcc/gcc/config/i386/i386.md:9838 */
14532 rtx
14533 gen_absdf2 (operand0, operand1)
14534      rtx operand0;
14535      rtx operand1;
14536 {
14537   rtx _val = 0;
14538   start_sequence ();
14539   {
14540     rtx operands[2];
14541     operands[0] = operand0;
14542     operands[1] = operand1;
14543 if (TARGET_SSE2)
14544      {
14545        /* In case operand is in memory,  we will not use SSE.  */
14546        if (memory_operand (operands[0], VOIDmode)
14547      && rtx_equal_p (operands[0], operands[1]))
14548    emit_insn (gen_absdf2_memory (operands[0], operands[1]));
14549        else
14550   {
14551     /* Using SSE is tricky, since we need bitwise negation of -0
14552        in register.  */
14553     rtx reg = gen_reg_rtx (DFmode);
14554 #if HOST_BITS_PER_WIDE_INT >= 64
14555     rtx imm = gen_int_mode (((HOST_WIDE_INT)1) << 63, DImode);
14556 #else
14557     rtx imm = immed_double_const (0, 0x80000000, DImode);
14558 #endif
14559     rtx dest = operands[0];
14560 
14561     operands[1] = force_reg (DFmode, operands[1]);
14562     operands[0] = force_reg (DFmode, operands[0]);
14563     emit_move_insn (reg, gen_lowpart (DFmode, imm));
14564     emit_insn (gen_absdf2_ifs (operands[0], operands[1], reg));
14565     if (dest != operands[0])
14566       emit_move_insn (dest, operands[0]);
14567   }
14568        DONE;
14569      }
14570    ix86_expand_unary_operator (ABS, DFmode, operands); DONE;
14571     operand0 = operands[0];
14572     operand1 = operands[1];
14573   }
14574   emit (gen_rtx_PARALLEL (VOIDmode,
14575   gen_rtvec (2,
14576     gen_rtx_SET (VOIDmode,
14577   operand0,
14578   gen_rtx_NEG (DFmode,
14579   operand1)),
14580     gen_rtx_CLOBBER (VOIDmode,
14581   gen_rtx_REG (CCmode,
14582   17)))));
14583   _val = get_insns ();
14584   end_sequence ();
14585   return _val;
14586 }
14587 
14588 /* ../../gcc/gcc/config/i386/i386.md:9901 */
14589 extern rtx gen_split_1269 PARAMS ((rtx *));
14590 rtx
14591 gen_split_1269 (operands)
14592       rtx *operands;
14593 {
14594   rtx operand0;
14595   rtx operand1;
14596   rtx _val = 0;
14597   start_sequence ();
14598   operand0 = operands[0];
14599   operand1 = operands[1];
14600   emit (gen_rtx_PARALLEL (VOIDmode,
14601   gen_rtvec (2,
14602     gen_rtx_SET (VOIDmode,
14603   operand0,
14604   gen_rtx_ABS (DFmode,
14605   operand1)),
14606     gen_rtx_CLOBBER (VOIDmode,
14607   gen_rtx_REG (CCmode,
14608   17)))));
14609   _val = get_insns ();
14610   end_sequence ();
14611   return _val;
14612 }
14613 
14614 /* ../../gcc/gcc/config/i386/i386.md:9911 */
14615 extern rtx gen_split_1270 PARAMS ((rtx *));
14616 rtx
14617 gen_split_1270 (operands)
14618       rtx *operands;
14619 {
14620   rtx operand0;
14621   rtx operand1;
14622   rtx _val = 0;
14623   start_sequence ();
14624   operand0 = operands[0];
14625   operand1 = operands[1];
14626   emit (gen_rtx_PARALLEL (VOIDmode,
14627   gen_rtvec (2,
14628     gen_rtx_SET (VOIDmode,
14629   operand0,
14630   gen_rtx_ABS (DFmode,
14631   operand1)),
14632     gen_rtx_CLOBBER (VOIDmode,
14633   gen_rtx_REG (CCmode,
14634   17)))));
14635   _val = get_insns ();
14636   end_sequence ();
14637   return _val;
14638 }
14639 
14640 /* ../../gcc/gcc/config/i386/i386.md:9921 */
14641 extern rtx gen_split_1271 PARAMS ((rtx *));
14642 rtx
14643 gen_split_1271 (operands)
14644       rtx *operands;
14645 {
14646   rtx operand0;
14647   rtx operand1;
14648   rtx operand2;
14649   rtx _val = 0;
14650   start_sequence ();
14651   operand0 = operands[0];
14652   operand1 = operands[1];
14653   operand2 = operands[2];
14654   emit_insn (gen_rtx_SET (VOIDmode,
14655   gen_rtx_SUBREG (TImode,
14656   operand0,
14657   0),
14658   gen_rtx_AND (TImode,
14659   gen_rtx_NOT (TImode,
14660   gen_rtx_SUBREG (TImode,
14661   operand2,
14662   0)),
14663   gen_rtx_SUBREG (TImode,
14664   operand1,
14665   0))));
14666   _val = get_insns ();
14667   end_sequence ();
14668   return _val;
14669 }
14670 
14671 /* ../../gcc/gcc/config/i386/i386.md:9955 */
14672 extern rtx gen_split_1272 PARAMS ((rtx *));
14673 rtx
14674 gen_split_1272 (operands)
14675       rtx *operands;
14676 {
14677   rtx operand0;
14678   rtx operand1;
14679   rtx _val = 0;
14680   start_sequence ();
14681 
14682   operand0 = operands[0];
14683   operand1 = operands[1];
14684   emit_insn (gen_rtx_SET (VOIDmode,
14685   operand0,
14686   gen_rtx_ABS (DFmode,
14687   operand1)));
14688   _val = get_insns ();
14689   end_sequence ();
14690   return _val;
14691 }
14692 
14693 /* ../../gcc/gcc/config/i386/i386.md:9964 */
14694 extern rtx gen_split_1273 PARAMS ((rtx *));
14695 rtx
14696 gen_split_1273 (operands)
14697       rtx *operands;
14698 {
14699   rtx operand0;
14700   rtx operand1;
14701   rtx operand2;
14702   rtx operand3;
14703   rtx operand4;
14704   rtx _val = 0;
14705   start_sequence ();
14706 operands[4] = gen_int_mode (~0x80000000, SImode);
14707    split_di (operands+0, 1, operands+2, operands+3);
14708   operand0 = operands[0];
14709   operand1 = operands[1];
14710   operand2 = operands[2];
14711   operand3 = operands[3];
14712   operand4 = operands[4];
14713   emit (gen_rtx_PARALLEL (VOIDmode,
14714   gen_rtvec (2,
14715     gen_rtx_SET (VOIDmode,
14716   operand3,
14717   gen_rtx_AND (SImode,
14718   copy_rtx (operand3),
14719   operand4)),
14720     gen_rtx_CLOBBER (VOIDmode,
14721   gen_rtx_REG (CCmode,
14722   17)))));
14723   _val = get_insns ();
14724   end_sequence ();
14725   return _val;
14726 }
14727 
14728 /* ../../gcc/gcc/config/i386/i386.md:9974 */
14729 rtx
14730 gen_absxf2 (operand0, operand1)
14731      rtx operand0;
14732      rtx operand1;
14733 {
14734   rtx _val = 0;
14735   start_sequence ();
14736   {
14737     rtx operands[2];
14738     operands[0] = operand0;
14739     operands[1] = operand1;
14740 ix86_expand_unary_operator (ABS, XFmode, operands); DONE;
14741     operand0 = operands[0];
14742     operand1 = operands[1];
14743   }
14744   emit (gen_rtx_PARALLEL (VOIDmode,
14745   gen_rtvec (2,
14746     gen_rtx_SET (VOIDmode,
14747   operand0,
14748   gen_rtx_NEG (XFmode,
14749   operand1)),
14750     gen_rtx_CLOBBER (VOIDmode,
14751   gen_rtx_REG (CCmode,
14752   17)))));
14753   _val = get_insns ();
14754   end_sequence ();
14755   return _val;
14756 }
14757 
14758 /* ../../gcc/gcc/config/i386/i386.md:9981 */
14759 rtx
14760 gen_abstf2 (operand0, operand1)
14761      rtx operand0;
14762      rtx operand1;
14763 {
14764   rtx _val = 0;
14765   start_sequence ();
14766   {
14767     rtx operands[2];
14768     operands[0] = operand0;
14769     operands[1] = operand1;
14770 ix86_expand_unary_operator (ABS, TFmode, operands); DONE;
14771     operand0 = operands[0];
14772     operand1 = operands[1];
14773   }
14774   emit (gen_rtx_PARALLEL (VOIDmode,
14775   gen_rtvec (2,
14776     gen_rtx_SET (VOIDmode,
14777   operand0,
14778   gen_rtx_NEG (TFmode,
14779   operand1)),
14780     gen_rtx_CLOBBER (VOIDmode,
14781   gen_rtx_REG (CCmode,
14782   17)))));
14783   _val = get_insns ();
14784   end_sequence ();
14785   return _val;
14786 }
14787 
14788 /* ../../gcc/gcc/config/i386/i386.md:9999 */
14789 extern rtx gen_split_1276 PARAMS ((rtx *));
14790 rtx
14791 gen_split_1276 (operands)
14792       rtx *operands;
14793 {
14794   rtx operand0;
14795   rtx operand1;
14796   rtx _val = 0;
14797   start_sequence ();
14798 
14799   operand0 = operands[0];
14800   operand1 = operands[1];
14801   emit_insn (gen_rtx_SET (VOIDmode,
14802   operand0,
14803   gen_rtx_ABS (XFmode,
14804   operand1)));
14805   _val = get_insns ();
14806   end_sequence ();
14807   return _val;
14808 }
14809 
14810 /* ../../gcc/gcc/config/i386/i386.md:10008 */
14811 extern rtx gen_split_1277 PARAMS ((rtx *));
14812 rtx
14813 gen_split_1277 (operands)
14814       rtx *operands;
14815 {
14816   rtx operand0;
14817   rtx operand1;
14818   rtx _val = 0;
14819   start_sequence ();
14820 operands[1] = GEN_INT (~0x8000);
14821    operands[0] = gen_rtx_REG (SImode,
14822             true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));
14823   operand0 = operands[0];
14824   operand1 = operands[1];
14825   emit (gen_rtx_PARALLEL (VOIDmode,
14826   gen_rtvec (2,
14827     gen_rtx_SET (VOIDmode,
14828   operand0,
14829   gen_rtx_AND (SImode,
14830   copy_rtx (operand0),
14831   operand1)),
14832     gen_rtx_CLOBBER (VOIDmode,
14833   gen_rtx_REG (CCmode,
14834   17)))));
14835   _val = get_insns ();
14836   end_sequence ();
14837   return _val;
14838 }
14839 
14840 /* ../../gcc/gcc/config/i386/i386.md:10026 */
14841 extern rtx gen_split_1278 PARAMS ((rtx *));
14842 rtx
14843 gen_split_1278 (operands)
14844       rtx *operands;
14845 {
14846   rtx operand0;
14847   rtx operand1;
14848   rtx _val = 0;
14849   start_sequence ();
14850 
14851   operand0 = operands[0];
14852   operand1 = operands[1];
14853   emit_insn (gen_rtx_SET (VOIDmode,
14854   operand0,
14855   gen_rtx_ABS (TFmode,
14856   operand1)));
14857   _val = get_insns ();
14858   end_sequence ();
14859   return _val;
14860 }
14861 
14862 /* ../../gcc/gcc/config/i386/i386.md:10035 */
14863 extern rtx gen_split_1279 PARAMS ((rtx *));
14864 rtx
14865 gen_split_1279 (operands)
14866       rtx *operands;
14867 {
14868   rtx operand0;
14869   rtx operand1;
14870   rtx _val = 0;
14871   start_sequence ();
14872 operands[1] = GEN_INT (~0x8000);
14873    operands[0] = gen_rtx_REG (SImode,
14874             true_regnum (operands[0]) + (TARGET_64BIT ? 1 : 2));
14875   operand0 = operands[0];
14876   operand1 = operands[1];
14877   emit (gen_rtx_PARALLEL (VOIDmode,
14878   gen_rtvec (2,
14879     gen_rtx_SET (VOIDmode,
14880   operand0,
14881   gen_rtx_AND (SImode,
14882   copy_rtx (operand0),
14883   operand1)),
14884     gen_rtx_CLOBBER (VOIDmode,
14885   gen_rtx_REG (CCmode,
14886   17)))));
14887   _val = get_insns ();
14888   end_sequence ();
14889   return _val;
14890 }
14891 
14892 /* ../../gcc/gcc/config/i386/i386.md:10125 */
14893 rtx
14894 gen_one_cmpldi2 (operand0, operand1)
14895      rtx operand0;
14896      rtx operand1;
14897 {
14898   rtx _val = 0;
14899   start_sequence ();
14900   {
14901     rtx operands[2];
14902     operands[0] = operand0;
14903     operands[1] = operand1;
14904 ix86_expand_unary_operator (NOT, DImode, operands); DONE;
14905     operand0 = operands[0];
14906     operand1 = operands[1];
14907   }
14908   emit_insn (gen_rtx_SET (VOIDmode,
14909   operand0,
14910   gen_rtx_NOT (DImode,
14911   operand1)));
14912   _val = get_insns ();
14913   end_sequence ();
14914   return _val;
14915 }
14916 
14917 /* ../../gcc/gcc/config/i386/i386.md:10151 */
14918 extern rtx gen_split_1281 PARAMS ((rtx *));
14919 rtx
14920 gen_split_1281 (operands)
14921       rtx *operands;
14922 {
14923   rtx operand0;
14924   rtx operand1;
14925   rtx _val = 0;
14926   start_sequence ();
14927 
14928   operand0 = operands[0];
14929   operand1 = operands[1];
14930   emit (gen_rtx_PARALLEL (VOIDmode,
14931   gen_rtvec (2,
14932     gen_rtx_SET (VOIDmode,
14933   gen_rtx_REG (CCNOmode,
14934   17),
14935   gen_rtx_COMPARE (CCNOmode,
14936   gen_rtx_XOR (DImode,
14937   operand1,
14938   constm1_rtx),
14939   const0_rtx)),
14940     gen_rtx_SET (VOIDmode,
14941   operand0,
14942   gen_rtx_XOR (DImode,
14943   copy_rtx (operand1),
14944   constm1_rtx)))));
14945   _val = get_insns ();
14946   end_sequence ();
14947   return _val;
14948 }
14949 
14950 /* ../../gcc/gcc/config/i386/i386.md:10165 */
14951 rtx
14952 gen_one_cmplsi2 (operand0, operand1)
14953      rtx operand0;
14954      rtx operand1;
14955 {
14956   rtx _val = 0;
14957   start_sequence ();
14958   {
14959     rtx operands[2];
14960     operands[0] = operand0;
14961     operands[1] = operand1;
14962 ix86_expand_unary_operator (NOT, SImode, operands); DONE;
14963     operand0 = operands[0];
14964     operand1 = operands[1];
14965   }
14966   emit_insn (gen_rtx_SET (VOIDmode,
14967   operand0,
14968   gen_rtx_NOT (SImode,
14969   operand1)));
14970   _val = get_insns ();
14971   end_sequence ();
14972   return _val;
14973 }
14974 
14975 /* ../../gcc/gcc/config/i386/i386.md:10200 */
14976 extern rtx gen_split_1283 PARAMS ((rtx *));
14977 rtx
14978 gen_split_1283 (operands)
14979       rtx *operands;
14980 {
14981   rtx operand0;
14982   rtx operand1;
14983   rtx _val = 0;
14984   start_sequence ();
14985 
14986   operand0 = operands[0];
14987   operand1 = operands[1];
14988   emit (gen_rtx_PARALLEL (VOIDmode,
14989   gen_rtvec (2,
14990     gen_rtx_SET (VOIDmode,
14991   gen_rtx_REG (CCNOmode,
14992   17),
14993   gen_rtx_COMPARE (CCNOmode,
14994   gen_rtx_XOR (SImode,
14995   operand1,
14996   constm1_rtx),
14997   const0_rtx)),
14998     gen_rtx_SET (VOIDmode,
14999   operand0,
15000   gen_rtx_XOR (SImode,
15001   copy_rtx (operand1),
15002   constm1_rtx)))));
15003   _val = get_insns ();
15004   end_sequence ();
15005   return _val;
15006 }
15007 
15008 /* ../../gcc/gcc/config/i386/i386.md:10227 */
15009 extern rtx gen_split_1284 PARAMS ((rtx *));
15010 rtx
15011 gen_split_1284 (operands)
15012       rtx *operands;
15013 {
15014   rtx operand0;
15015   rtx operand1;
15016   rtx _val = 0;
15017   start_sequence ();
15018 
15019   operand0 = operands[0];
15020   operand1 = operands[1];
15021   emit (gen_rtx_PARALLEL (VOIDmode,
15022   gen_rtvec (2,
15023     gen_rtx_SET (VOIDmode,
15024   gen_rtx_REG (CCNOmode,
15025   17),
15026   gen_rtx_COMPARE (CCNOmode,
15027   gen_rtx_XOR (SImode,
15028   operand1,
15029   constm1_rtx),
15030   const0_rtx)),
15031     gen_rtx_SET (VOIDmode,
15032   operand0,
15033   gen_rtx_ZERO_EXTEND (DImode,
15034   gen_rtx_XOR (SImode,
15035   copy_rtx (operand1),
15036   constm1_rtx))))));
15037   _val = get_insns ();
15038   end_sequence ();
15039   return _val;
15040 }
15041 
15042 /* ../../gcc/gcc/config/i386/i386.md:10241 */
15043 rtx
15044 gen_one_cmplhi2 (operand0, operand1)
15045      rtx operand0;
15046      rtx operand1;
15047 {
15048   rtx _val = 0;
15049   start_sequence ();
15050   {
15051     rtx operands[2];
15052     operands[0] = operand0;
15053     operands[1] = operand1;
15054 ix86_expand_unary_operator (NOT, HImode, operands); DONE;
15055     operand0 = operands[0];
15056     operand1 = operands[1];
15057   }
15058   emit_insn (gen_rtx_SET (VOIDmode,
15059   operand0,
15060   gen_rtx_NOT (HImode,
15061   operand1)));
15062   _val = get_insns ();
15063   end_sequence ();
15064   return _val;
15065 }
15066 
15067 /* ../../gcc/gcc/config/i386/i386.md:10267 */
15068 extern rtx gen_split_1286 PARAMS ((rtx *));
15069 rtx
15070 gen_split_1286 (operands)
15071       rtx *operands;
15072 {
15073   rtx operand0;
15074   rtx operand1;
15075   rtx _val = 0;
15076   start_sequence ();
15077 
15078   operand0 = operands[0];
15079   operand1 = operands[1];
15080   emit (gen_rtx_PARALLEL (VOIDmode,
15081   gen_rtvec (2,
15082     gen_rtx_SET (VOIDmode,
15083   gen_rtx_REG (CCNOmode,
15084   17),
15085   gen_rtx_COMPARE (CCNOmode,
15086   gen_rtx_XOR (HImode,
15087   operand1,
15088   constm1_rtx),
15089   const0_rtx)),
15090     gen_rtx_SET (VOIDmode,
15091   operand0,
15092   gen_rtx_XOR (HImode,
15093   copy_rtx (operand1),
15094   constm1_rtx)))));
15095   _val = get_insns ();
15096   end_sequence ();
15097   return _val;
15098 }
15099 
15100 /* ../../gcc/gcc/config/i386/i386.md:10282 */
15101 rtx
15102 gen_one_cmplqi2 (operand0, operand1)
15103      rtx operand0;
15104      rtx operand1;
15105 {
15106   rtx _val = 0;
15107   start_sequence ();
15108   {
15109     rtx operands[2];
15110     operands[0] = operand0;
15111     operands[1] = operand1;
15112 ix86_expand_unary_operator (NOT, QImode, operands); DONE;
15113     operand0 = operands[0];
15114     operand1 = operands[1];
15115   }
15116   emit_insn (gen_rtx_SET (VOIDmode,
15117   operand0,
15118   gen_rtx_NOT (QImode,
15119   operand1)));
15120   _val = get_insns ();
15121   end_sequence ();
15122   return _val;
15123 }
15124 
15125 /* ../../gcc/gcc/config/i386/i386.md:10310 */
15126 extern rtx gen_split_1288 PARAMS ((rtx *));
15127 rtx
15128 gen_split_1288 (operands)
15129       rtx *operands;
15130 {
15131   rtx operand0;
15132   rtx operand1;
15133   rtx _val = 0;
15134   start_sequence ();
15135 
15136   operand0 = operands[0];
15137   operand1 = operands[1];
15138   emit (gen_rtx_PARALLEL (VOIDmode,
15139   gen_rtvec (2,
15140     gen_rtx_SET (VOIDmode,
15141   gen_rtx_REG (CCNOmode,
15142   17),
15143   gen_rtx_COMPARE (CCNOmode,
15144   gen_rtx_XOR (QImode,
15145   operand1,
15146   constm1_rtx),
15147   const0_rtx)),
15148     gen_rtx_SET (VOIDmode,
15149   operand0,
15150   gen_rtx_XOR (QImode,
15151   copy_rtx (operand1),
15152   constm1_rtx)))));
15153   _val = get_insns ();
15154   end_sequence ();
15155   return _val;
15156 }
15157 
15158 /* ../../gcc/gcc/config/i386/i386.md:10348 */
15159 rtx
15160 gen_ashldi3 (operand0, operand1, operand2)
15161      rtx operand0;
15162      rtx operand1;
15163      rtx operand2;
15164 {
15165   rtx _val = 0;
15166   start_sequence ();
15167   {
15168     rtx operands[3];
15169     operands[0] = operand0;
15170     operands[1] = operand1;
15171     operands[2] = operand2;
15172 {
15173   if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
15174     {
15175       emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
15176       DONE;
15177     }
15178   ix86_expand_binary_operator (ASHIFT, DImode, operands);
15179   DONE;
15180 }
15181     operand0 = operands[0];
15182     operand1 = operands[1];
15183     operand2 = operands[2];
15184   }
15185   emit (gen_rtx_PARALLEL (VOIDmode,
15186   gen_rtvec (2,
15187     gen_rtx_SET (VOIDmode,
15188   operand0,
15189   gen_rtx_ASHIFT (DImode,
15190   operand1,
15191   operand2)),
15192     gen_rtx_CLOBBER (VOIDmode,
15193   gen_rtx_REG (CCmode,
15194   17)))));
15195   _val = get_insns ();
15196   end_sequence ();
15197   return _val;
15198 }
15199 
15200 /* ../../gcc/gcc/config/i386/i386.md:10412 */
15201 extern rtx gen_split_1290 PARAMS ((rtx *));
15202 rtx
15203 gen_split_1290 (operands)
15204       rtx *operands;
15205 {
15206   rtx operand0;
15207   rtx operand1;
15208   rtx operand2;
15209   rtx _val = 0;
15210   start_sequence ();
15211 operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);
15212   operand0 = operands[0];
15213   operand1 = operands[1];
15214   operand2 = operands[2];
15215   emit_insn (gen_rtx_SET (VOIDmode,
15216   operand0,
15217   gen_rtx_MULT (DImode,
15218   operand1,
15219   operand2)));
15220   _val = get_insns ();
15221   end_sequence ();
15222   return _val;
15223 }
15224 
15225 /* ../../gcc/gcc/config/i386/i386.md:10485 */
15226 extern rtx gen_split_1291 PARAMS ((rtx *));
15227 rtx
15228 gen_split_1291 (operands)
15229       rtx *operands ATTRIBUTE_UNUSED;
15230 {
15231   rtx _val = 0;
15232   start_sequence ();
15233 ix86_split_ashldi (operands, operands[3]); DONE;
15234   emit_insn (const0_rtx);
15235   _val = get_insns ();
15236   end_sequence ();
15237   return _val;
15238 }
15239 
15240 /* ../../gcc/gcc/config/i386/i386.md:10495 */
15241 extern rtx gen_split_1292 PARAMS ((rtx *));
15242 rtx
15243 gen_split_1292 (operands)
15244       rtx *operands ATTRIBUTE_UNUSED;
15245 {
15246   rtx _val = 0;
15247   start_sequence ();
15248 ix86_split_ashldi (operands, NULL_RTX); DONE;
15249   emit_insn (const0_rtx);
15250   _val = get_insns ();
15251   end_sequence ();
15252   return _val;
15253 }
15254 
15255 /* ../../gcc/gcc/config/i386/i386.md:10522 */
15256 rtx
15257 gen_x86_shift_adj_1 (operand0, operand1, operand2, operand3)
15258      rtx operand0;
15259      rtx operand1;
15260      rtx operand2;
15261      rtx operand3;
15262 {
15263   rtx _val = 0;
15264   start_sequence ();
15265   emit_insn (gen_rtx_SET (VOIDmode,
15266   gen_rtx_REG (CCZmode,
15267   17),
15268   gen_rtx_COMPARE (CCZmode,
15269   gen_rtx_AND (QImode,
15270   operand2,
15271   GEN_INT (32LL)),
15272   const0_rtx)));
15273   emit_insn (gen_rtx_SET (VOIDmode,
15274   operand0,
15275   gen_rtx_IF_THEN_ELSE (SImode,
15276   gen_rtx_NE (VOIDmode,
15277   gen_rtx_REG (CCZmode,
15278   17),
15279   const0_rtx),
15280   operand1,
15281   operand0)));
15282   emit_insn (gen_rtx_SET (VOIDmode,
15283   operand1,
15284   gen_rtx_IF_THEN_ELSE (SImode,
15285   gen_rtx_NE (VOIDmode,
15286   gen_rtx_REG (CCZmode,
15287   17),
15288   const0_rtx),
15289   operand3,
15290   operand1)));
15291   _val = get_insns ();
15292   end_sequence ();
15293   return _val;
15294 }
15295 
15296 /* ../../gcc/gcc/config/i386/i386.md:10538 */
15297 rtx
15298 gen_x86_shift_adj_2 (operand0, operand1, operand2)
15299      rtx operand0;
15300      rtx operand1;
15301      rtx operand2;
15302 {
15303   rtx _val = 0;
15304   start_sequence ();
15305   {
15306     rtx operands[3];
15307     operands[0] = operand0;
15308     operands[1] = operand1;
15309     operands[2] = operand2;
15310 {
15311   rtx label = gen_label_rtx ();
15312   rtx tmp;
15313 
15314   emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
15315 
15316   tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
15317   tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
15318   tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15319             gen_rtx_LABEL_REF (VOIDmode, label),
15320             pc_rtx);
15321   tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
15322   JUMP_LABEL (tmp) = label;
15323 
15324   emit_move_insn (operands[0], operands[1]);
15325   emit_move_insn (operands[1], const0_rtx);
15326 
15327   emit_label (label);
15328   LABEL_NUSES (label) = 1;
15329 
15330   DONE;
15331 }
15332     operand0 = operands[0];
15333     operand1 = operands[1];
15334     operand2 = operands[2];
15335   }
15336   emit_insn (gen_rtx_USE (VOIDmode,
15337   operand0));
15338   emit_insn (gen_rtx_USE (VOIDmode,
15339   operand1));
15340   emit_insn (gen_rtx_USE (VOIDmode,
15341   operand2));
15342   _val = get_insns ();
15343   end_sequence ();
15344   return _val;
15345 }
15346 
15347 /* ../../gcc/gcc/config/i386/i386.md:10566 */
15348 rtx
15349 gen_ashlsi3 (operand0, operand1, operand2)
15350      rtx operand0;
15351      rtx operand1;
15352      rtx operand2;
15353 {
15354   rtx _val = 0;
15355   start_sequence ();
15356   {
15357     rtx operands[3];
15358     operands[0] = operand0;
15359     operands[1] = operand1;
15360     operands[2] = operand2;
15361 ix86_expand_binary_operator (ASHIFT, SImode, operands); DONE;
15362     operand0 = operands[0];
15363     operand1 = operands[1];
15364     operand2 = operands[2];
15365   }
15366   emit_insn (gen_rtx_SET (VOIDmode,
15367   operand0,
15368   gen_rtx_ASHIFT (SImode,
15369   operand1,
15370   operand2)));
15371   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15372   gen_rtx_REG (CCmode,
15373   17)));
15374   _val = get_insns ();
15375   end_sequence ();
15376   return _val;
15377 }
15378 
15379 /* ../../gcc/gcc/config/i386/i386.md:10617 */
15380 extern rtx gen_split_1296 PARAMS ((rtx *));
15381 rtx
15382 gen_split_1296 (operands)
15383       rtx *operands ATTRIBUTE_UNUSED;
15384 {
15385   rtx _val = 0;
15386   start_sequence ();
15387 {
15388   rtx pat;
15389   operands[0] = gen_lowpart (SImode, operands[0]);
15390   operands[1] = gen_lowpart (Pmode, operands[1]);
15391   operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
15392   pat = gen_rtx_MULT (Pmode, operands[1], operands[2]);
15393   if (Pmode != SImode)
15394     pat = gen_rtx_SUBREG (SImode, pat, 0);
15395   emit_insn (gen_rtx_SET (VOIDmode, operands[0], pat));
15396   DONE;
15397 }
15398   emit_insn (const0_rtx);
15399   _val = get_insns ();
15400   end_sequence ();
15401   return _val;
15402 }
15403 
15404 /* ../../gcc/gcc/config/i386/i386.md:10638 */
15405 extern rtx gen_split_1297 PARAMS ((rtx *));
15406 rtx
15407 gen_split_1297 (operands)
15408       rtx *operands ATTRIBUTE_UNUSED;
15409 {
15410   rtx _val = 0;
15411   start_sequence ();
15412 {
15413   rtx pat, clob;
15414   emit_move_insn (operands[1], operands[0]);
15415   pat = gen_rtx_SET (VOIDmode, operands[0],
15416          gen_rtx_ASHIFT (GET_MODE (operands[0]),
15417              operands[0], operands[2]));
15418   clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
15419   emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
15420   DONE;
15421 }
15422   emit_insn (const0_rtx);
15423   _val = get_insns ();
15424   end_sequence ();
15425   return _val;
15426 }
15427 
15428 /* ../../gcc/gcc/config/i386/i386.md:10697 */
15429 extern rtx gen_split_1298 PARAMS ((rtx *));
15430 rtx
15431 gen_split_1298 (operands)
15432       rtx *operands;
15433 {
15434   rtx operand0;
15435   rtx operand1;
15436   rtx operand2;
15437   rtx _val = 0;
15438   start_sequence ();
15439 {
15440   operands[1] = gen_lowpart (Pmode, operands[1]);
15441   operands[2] = gen_int_mode (1 << INTVAL (operands[2]), Pmode);
15442 }
15443   operand0 = operands[0];
15444   operand1 = operands[1];
15445   operand2 = operands[2];
15446   emit_insn (gen_rtx_SET (VOIDmode,
15447   operand0,
15448   gen_rtx_ZERO_EXTEND (DImode,
15449   gen_rtx_SUBREG (SImode,
15450   gen_rtx_MULT (SImode,
15451   operand1,
15452   operand2),
15453   0))));
15454   _val = get_insns ();
15455   end_sequence ();
15456   return _val;
15457 }
15458 
15459 /* ../../gcc/gcc/config/i386/i386.md:10790 */
15460 rtx
15461 gen_ashlhi3 (operand0, operand1, operand2)
15462      rtx operand0;
15463      rtx operand1;
15464      rtx operand2;
15465 {
15466   rtx _val = 0;
15467   start_sequence ();
15468   {
15469     rtx operands[3];
15470     operands[0] = operand0;
15471     operands[1] = operand1;
15472     operands[2] = operand2;
15473 ix86_expand_binary_operator (ASHIFT, HImode, operands); DONE;
15474     operand0 = operands[0];
15475     operand1 = operands[1];
15476     operand2 = operands[2];
15477   }
15478   emit_insn (gen_rtx_SET (VOIDmode,
15479   operand0,
15480   gen_rtx_ASHIFT (HImode,
15481   operand1,
15482   operand2)));
15483   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15484   gen_rtx_REG (CCmode,
15485   17)));
15486   _val = get_insns ();
15487   end_sequence ();
15488   return _val;
15489 }
15490 
15491 /* ../../gcc/gcc/config/i386/i386.md:10916 */
15492 rtx
15493 gen_ashlqi3 (operand0, operand1, operand2)
15494      rtx operand0;
15495      rtx operand1;
15496      rtx operand2;
15497 {
15498   rtx _val = 0;
15499   start_sequence ();
15500   {
15501     rtx operands[3];
15502     operands[0] = operand0;
15503     operands[1] = operand1;
15504     operands[2] = operand2;
15505 ix86_expand_binary_operator (ASHIFT, QImode, operands); DONE;
15506     operand0 = operands[0];
15507     operand1 = operands[1];
15508     operand2 = operands[2];
15509   }
15510   emit_insn (gen_rtx_SET (VOIDmode,
15511   operand0,
15512   gen_rtx_ASHIFT (QImode,
15513   operand1,
15514   operand2)));
15515   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15516   gen_rtx_REG (CCmode,
15517   17)));
15518   _val = get_insns ();
15519   end_sequence ();
15520   return _val;
15521 }
15522 
15523 /* ../../gcc/gcc/config/i386/i386.md:11082 */
15524 rtx
15525 gen_ashrdi3 (operand0, operand1, operand2)
15526      rtx operand0;
15527      rtx operand1;
15528      rtx operand2;
15529 {
15530   rtx _val = 0;
15531   start_sequence ();
15532   {
15533     rtx operands[3];
15534     operands[0] = operand0;
15535     operands[1] = operand1;
15536     operands[2] = operand2;
15537 {
15538   if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
15539     {
15540       emit_insn (gen_ashrdi3_1 (operands[0], operands[1], operands[2]));
15541       DONE;
15542     }
15543   ix86_expand_binary_operator (ASHIFTRT, DImode, operands);
15544   DONE;
15545 }
15546     operand0 = operands[0];
15547     operand1 = operands[1];
15548     operand2 = operands[2];
15549   }
15550   emit (gen_rtx_PARALLEL (VOIDmode,
15551   gen_rtvec (2,
15552     gen_rtx_SET (VOIDmode,
15553   operand0,
15554   gen_rtx_ASHIFTRT (DImode,
15555   operand1,
15556   operand2)),
15557     gen_rtx_CLOBBER (VOIDmode,
15558   gen_rtx_REG (CCmode,
15559   17)))));
15560   _val = get_insns ();
15561   end_sequence ();
15562   return _val;
15563 }
15564 
15565 /* ../../gcc/gcc/config/i386/i386.md:11198 */
15566 extern rtx gen_split_1302 PARAMS ((rtx *));
15567 rtx
15568 gen_split_1302 (operands)
15569       rtx *operands ATTRIBUTE_UNUSED;
15570 {
15571   rtx _val = 0;
15572   start_sequence ();
15573 ix86_split_ashrdi (operands, operands[3]); DONE;
15574   emit_insn (const0_rtx);
15575   _val = get_insns ();
15576   end_sequence ();
15577   return _val;
15578 }
15579 
15580 /* ../../gcc/gcc/config/i386/i386.md:11208 */
15581 extern rtx gen_split_1303 PARAMS ((rtx *));
15582 rtx
15583 gen_split_1303 (operands)
15584       rtx *operands ATTRIBUTE_UNUSED;
15585 {
15586   rtx _val = 0;
15587   start_sequence ();
15588 ix86_split_ashrdi (operands, NULL_RTX); DONE;
15589   emit_insn (const0_rtx);
15590   _val = get_insns ();
15591   end_sequence ();
15592   return _val;
15593 }
15594 
15595 /* ../../gcc/gcc/config/i386/i386.md:11234 */
15596 rtx
15597 gen_x86_shift_adj_3 (operand0, operand1, operand2)
15598      rtx operand0;
15599      rtx operand1;
15600      rtx operand2;
15601 {
15602   rtx _val = 0;
15603   start_sequence ();
15604   {
15605     rtx operands[3];
15606     operands[0] = operand0;
15607     operands[1] = operand1;
15608     operands[2] = operand2;
15609 {
15610   rtx label = gen_label_rtx ();
15611   rtx tmp;
15612 
15613   emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (32)));
15614 
15615   tmp = gen_rtx_REG (CCZmode, FLAGS_REG);
15616   tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx);
15617   tmp = gen_rtx_IF_THEN_ELSE (VOIDmode, tmp,
15618             gen_rtx_LABEL_REF (VOIDmode, label),
15619             pc_rtx);
15620   tmp = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, tmp));
15621   JUMP_LABEL (tmp) = label;
15622 
15623   emit_move_insn (operands[0], operands[1]);
15624   emit_insn (gen_ashrsi3_31 (operands[1], operands[1], GEN_INT (31)));
15625 
15626   emit_label (label);
15627   LABEL_NUSES (label) = 1;
15628 
15629   DONE;
15630 }
15631     operand0 = operands[0];
15632     operand1 = operands[1];
15633     operand2 = operands[2];
15634   }
15635   emit_insn (gen_rtx_USE (VOIDmode,
15636   operand0));
15637   emit_insn (gen_rtx_USE (VOIDmode,
15638   operand1));
15639   emit_insn (gen_rtx_USE (VOIDmode,
15640   operand2));
15641   _val = get_insns ();
15642   end_sequence ();
15643   return _val;
15644 }
15645 
15646 /* ../../gcc/gcc/config/i386/i386.md:11295 */
15647 rtx
15648 gen_ashrsi3 (operand0, operand1, operand2)
15649      rtx operand0;
15650      rtx operand1;
15651      rtx operand2;
15652 {
15653   rtx _val = 0;
15654   start_sequence ();
15655   {
15656     rtx operands[3];
15657     operands[0] = operand0;
15658     operands[1] = operand1;
15659     operands[2] = operand2;
15660 ix86_expand_binary_operator (ASHIFTRT, SImode, operands); DONE;
15661     operand0 = operands[0];
15662     operand1 = operands[1];
15663     operand2 = operands[2];
15664   }
15665   emit_insn (gen_rtx_SET (VOIDmode,
15666   operand0,
15667   gen_rtx_ASHIFTRT (SImode,
15668   operand1,
15669   operand2)));
15670   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15671   gen_rtx_REG (CCmode,
15672   17)));
15673   _val = get_insns ();
15674   end_sequence ();
15675   return _val;
15676 }
15677 
15678 /* ../../gcc/gcc/config/i386/i386.md:11419 */
15679 rtx
15680 gen_ashrhi3 (operand0, operand1, operand2)
15681      rtx operand0;
15682      rtx operand1;
15683      rtx operand2;
15684 {
15685   rtx _val = 0;
15686   start_sequence ();
15687   {
15688     rtx operands[3];
15689     operands[0] = operand0;
15690     operands[1] = operand1;
15691     operands[2] = operand2;
15692 ix86_expand_binary_operator (ASHIFTRT, HImode, operands); DONE;
15693     operand0 = operands[0];
15694     operand1 = operands[1];
15695     operand2 = operands[2];
15696   }
15697   emit_insn (gen_rtx_SET (VOIDmode,
15698   operand0,
15699   gen_rtx_ASHIFTRT (HImode,
15700   operand1,
15701   operand2)));
15702   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15703   gen_rtx_REG (CCmode,
15704   17)));
15705   _val = get_insns ();
15706   end_sequence ();
15707   return _val;
15708 }
15709 
15710 /* ../../gcc/gcc/config/i386/i386.md:11491 */
15711 rtx
15712 gen_ashrqi3 (operand0, operand1, operand2)
15713      rtx operand0;
15714      rtx operand1;
15715      rtx operand2;
15716 {
15717   rtx _val = 0;
15718   start_sequence ();
15719   {
15720     rtx operands[3];
15721     operands[0] = operand0;
15722     operands[1] = operand1;
15723     operands[2] = operand2;
15724 ix86_expand_binary_operator (ASHIFTRT, QImode, operands); DONE;
15725     operand0 = operands[0];
15726     operand1 = operands[1];
15727     operand2 = operands[2];
15728   }
15729   emit_insn (gen_rtx_SET (VOIDmode,
15730   operand0,
15731   gen_rtx_ASHIFTRT (QImode,
15732   operand1,
15733   operand2)));
15734   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15735   gen_rtx_REG (CCmode,
15736   17)));
15737   _val = get_insns ();
15738   end_sequence ();
15739   return _val;
15740 }
15741 
15742 /* ../../gcc/gcc/config/i386/i386.md:11595 */
15743 rtx
15744 gen_lshrdi3 (operand0, operand1, operand2)
15745      rtx operand0;
15746      rtx operand1;
15747      rtx operand2;
15748 {
15749   rtx _val = 0;
15750   start_sequence ();
15751   {
15752     rtx operands[3];
15753     operands[0] = operand0;
15754     operands[1] = operand1;
15755     operands[2] = operand2;
15756 {
15757   if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
15758     {
15759       emit_insn (gen_lshrdi3_1 (operands[0], operands[1], operands[2]));
15760       DONE;
15761     }
15762   ix86_expand_binary_operator (LSHIFTRT, DImode, operands);
15763   DONE;
15764 }
15765     operand0 = operands[0];
15766     operand1 = operands[1];
15767     operand2 = operands[2];
15768   }
15769   emit (gen_rtx_PARALLEL (VOIDmode,
15770   gen_rtvec (2,
15771     gen_rtx_SET (VOIDmode,
15772   operand0,
15773   gen_rtx_LSHIFTRT (DImode,
15774   operand1,
15775   operand2)),
15776     gen_rtx_CLOBBER (VOIDmode,
15777   gen_rtx_REG (CCmode,
15778   17)))));
15779   _val = get_insns ();
15780   end_sequence ();
15781   return _val;
15782 }
15783 
15784 /* ../../gcc/gcc/config/i386/i386.md:11694 */
15785 extern rtx gen_split_1309 PARAMS ((rtx *));
15786 rtx
15787 gen_split_1309 (operands)
15788       rtx *operands ATTRIBUTE_UNUSED;
15789 {
15790   rtx _val = 0;
15791   start_sequence ();
15792 ix86_split_lshrdi (operands, operands[3]); DONE;
15793   emit_insn (const0_rtx);
15794   _val = get_insns ();
15795   end_sequence ();
15796   return _val;
15797 }
15798 
15799 /* ../../gcc/gcc/config/i386/i386.md:11704 */
15800 extern rtx gen_split_1310 PARAMS ((rtx *));
15801 rtx
15802 gen_split_1310 (operands)
15803       rtx *operands ATTRIBUTE_UNUSED;
15804 {
15805   rtx _val = 0;
15806   start_sequence ();
15807 ix86_split_lshrdi (operands, NULL_RTX); DONE;
15808   emit_insn (const0_rtx);
15809   _val = get_insns ();
15810   end_sequence ();
15811   return _val;
15812 }
15813 
15814 /* ../../gcc/gcc/config/i386/i386.md:11713 */
15815 rtx
15816 gen_lshrsi3 (operand0, operand1, operand2)
15817      rtx operand0;
15818      rtx operand1;
15819      rtx operand2;
15820 {
15821   rtx _val = 0;
15822   start_sequence ();
15823   {
15824     rtx operands[3];
15825     operands[0] = operand0;
15826     operands[1] = operand1;
15827     operands[2] = operand2;
15828 ix86_expand_binary_operator (LSHIFTRT, SImode, operands); DONE;
15829     operand0 = operands[0];
15830     operand1 = operands[1];
15831     operand2 = operands[2];
15832   }
15833   emit_insn (gen_rtx_SET (VOIDmode,
15834   operand0,
15835   gen_rtx_LSHIFTRT (SImode,
15836   operand1,
15837   operand2)));
15838   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15839   gen_rtx_REG (CCmode,
15840   17)));
15841   _val = get_insns ();
15842   end_sequence ();
15843   return _val;
15844 }
15845 
15846 /* ../../gcc/gcc/config/i386/i386.md:11838 */
15847 rtx
15848 gen_lshrhi3 (operand0, operand1, operand2)
15849      rtx operand0;
15850      rtx operand1;
15851      rtx operand2;
15852 {
15853   rtx _val = 0;
15854   start_sequence ();
15855   {
15856     rtx operands[3];
15857     operands[0] = operand0;
15858     operands[1] = operand1;
15859     operands[2] = operand2;
15860 ix86_expand_binary_operator (LSHIFTRT, HImode, operands); DONE;
15861     operand0 = operands[0];
15862     operand1 = operands[1];
15863     operand2 = operands[2];
15864   }
15865   emit_insn (gen_rtx_SET (VOIDmode,
15866   operand0,
15867   gen_rtx_LSHIFTRT (HImode,
15868   operand1,
15869   operand2)));
15870   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15871   gen_rtx_REG (CCmode,
15872   17)));
15873   _val = get_insns ();
15874   end_sequence ();
15875   return _val;
15876 }
15877 
15878 /* ../../gcc/gcc/config/i386/i386.md:11910 */
15879 rtx
15880 gen_lshrqi3 (operand0, operand1, operand2)
15881      rtx operand0;
15882      rtx operand1;
15883      rtx operand2;
15884 {
15885   rtx _val = 0;
15886   start_sequence ();
15887   {
15888     rtx operands[3];
15889     operands[0] = operand0;
15890     operands[1] = operand1;
15891     operands[2] = operand2;
15892 ix86_expand_binary_operator (LSHIFTRT, QImode, operands); DONE;
15893     operand0 = operands[0];
15894     operand1 = operands[1];
15895     operand2 = operands[2];
15896   }
15897   emit_insn (gen_rtx_SET (VOIDmode,
15898   operand0,
15899   gen_rtx_LSHIFTRT (QImode,
15900   operand1,
15901   operand2)));
15902   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15903   gen_rtx_REG (CCmode,
15904   17)));
15905   _val = get_insns ();
15906   end_sequence ();
15907   return _val;
15908 }
15909 
15910 /* ../../gcc/gcc/config/i386/i386.md:12011 */
15911 rtx
15912 gen_rotldi3 (operand0, operand1, operand2)
15913      rtx operand0;
15914      rtx operand1;
15915      rtx operand2;
15916 {
15917   rtx _val = 0;
15918   start_sequence ();
15919   {
15920     rtx operands[3];
15921     operands[0] = operand0;
15922     operands[1] = operand1;
15923     operands[2] = operand2;
15924 ix86_expand_binary_operator (ROTATE, DImode, operands); DONE;
15925     operand0 = operands[0];
15926     operand1 = operands[1];
15927     operand2 = operands[2];
15928   }
15929   emit_insn (gen_rtx_SET (VOIDmode,
15930   operand0,
15931   gen_rtx_ROTATE (DImode,
15932   operand1,
15933   operand2)));
15934   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15935   gen_rtx_REG (CCmode,
15936   17)));
15937   _val = get_insns ();
15938   end_sequence ();
15939   return _val;
15940 }
15941 
15942 /* ../../gcc/gcc/config/i386/i386.md:12045 */
15943 rtx
15944 gen_rotlsi3 (operand0, operand1, operand2)
15945      rtx operand0;
15946      rtx operand1;
15947      rtx operand2;
15948 {
15949   rtx _val = 0;
15950   start_sequence ();
15951   {
15952     rtx operands[3];
15953     operands[0] = operand0;
15954     operands[1] = operand1;
15955     operands[2] = operand2;
15956 ix86_expand_binary_operator (ROTATE, SImode, operands); DONE;
15957     operand0 = operands[0];
15958     operand1 = operands[1];
15959     operand2 = operands[2];
15960   }
15961   emit_insn (gen_rtx_SET (VOIDmode,
15962   operand0,
15963   gen_rtx_ROTATE (SImode,
15964   operand1,
15965   operand2)));
15966   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15967   gen_rtx_REG (CCmode,
15968   17)));
15969   _val = get_insns ();
15970   end_sequence ();
15971   return _val;
15972 }
15973 
15974 /* ../../gcc/gcc/config/i386/i386.md:12104 */
15975 rtx
15976 gen_rotlhi3 (operand0, operand1, operand2)
15977      rtx operand0;
15978      rtx operand1;
15979      rtx operand2;
15980 {
15981   rtx _val = 0;
15982   start_sequence ();
15983   {
15984     rtx operands[3];
15985     operands[0] = operand0;
15986     operands[1] = operand1;
15987     operands[2] = operand2;
15988 ix86_expand_binary_operator (ROTATE, HImode, operands); DONE;
15989     operand0 = operands[0];
15990     operand1 = operands[1];
15991     operand2 = operands[2];
15992   }
15993   emit_insn (gen_rtx_SET (VOIDmode,
15994   operand0,
15995   gen_rtx_ROTATE (HImode,
15996   operand1,
15997   operand2)));
15998   emit_insn (gen_rtx_CLOBBER (VOIDmode,
15999   gen_rtx_REG (CCmode,
16000   17)));
16001   _val = get_insns ();
16002   end_sequence ();
16003   return _val;
16004 }
16005 
16006 /* ../../gcc/gcc/config/i386/i386.md:12138 */
16007 rtx
16008 gen_rotlqi3 (operand0, operand1, operand2)
16009      rtx operand0;
16010      rtx operand1;
16011      rtx operand2;
16012 {
16013   rtx _val = 0;
16014   start_sequence ();
16015   {
16016     rtx operands[3];
16017     operands[0] = operand0;
16018     operands[1] = operand1;
16019     operands[2] = operand2;
16020 ix86_expand_binary_operator (ROTATE, QImode, operands); DONE;
16021     operand0 = operands[0];
16022     operand1 = operands[1];
16023     operand2 = operands[2];
16024   }
16025   emit_insn (gen_rtx_SET (VOIDmode,
16026   operand0,
16027   gen_rtx_ROTATE (QImode,
16028   operand1,
16029   operand2)));
16030   emit_insn (gen_rtx_CLOBBER (VOIDmode,
16031   gen_rtx_REG (CCmode,
16032   17)));
16033   _val = get_insns ();
16034   end_sequence ();
16035   return _val;
16036 }
16037 
16038 /* ../../gcc/gcc/config/i386/i386.md:12199 */
16039 rtx
16040 gen_rotrdi3 (operand0, operand1, operand2)
16041      rtx operand0;
16042      rtx operand1;
16043      rtx operand2;
16044 {
16045   rtx _val = 0;
16046   start_sequence ();
16047   {
16048     rtx operands[3];
16049     operands[0] = operand0;
16050     operands[1] = operand1;
16051     operands[2] = operand2;
16052 ix86_expand_binary_operator (ROTATERT, DImode, operands); DONE;
16053     operand0 = operands[0];
16054     operand1 = operands[1];
16055     operand2 = operands[2];
16056   }
16057   emit_insn (gen_rtx_SET (VOIDmode,
16058   operand0,
16059   gen_rtx_ROTATERT (DImode,
16060   operand1,
16061   operand2)));
16062   emit_insn (gen_rtx_CLOBBER (VOIDmode,
16063   gen_rtx_REG (CCmode,
16064   17)));
16065   _val = get_insns ();
16066   end_sequence ();
16067   return _val;
16068 }
16069 
16070 /* ../../gcc/gcc/config/i386/i386.md:12233 */
16071 rtx
16072 gen_rotrsi3 (operand0, operand1, operand2)
16073      rtx operand0;
16074      rtx operand1;
16075      rtx operand2;
16076 {
16077   rtx _val = 0;
16078   start_sequence ();
16079   {
16080     rtx operands[3];
16081     operands[0] = operand0;
16082     operands[1] = operand1;
16083     operands[2] = operand2;
16084 ix86_expand_binary_operator (ROTATERT, SImode, operands); DONE;
16085     operand0 = operands[0];
16086     operand1 = operands[1];
16087     operand2 = operands[2];
16088   }
16089   emit_insn (gen_rtx_SET (VOIDmode,
16090   operand0,
16091   gen_rtx_ROTATERT (SImode,
16092   operand1,
16093   operand2)));
16094   emit_insn (gen_rtx_CLOBBER (VOIDmode,
16095   gen_rtx_REG (CCmode,
16096   17)));
16097   _val = get_insns ();
16098   end_sequence ();
16099   return _val;
16100 }
16101 
16102 /* ../../gcc/gcc/config/i386/i386.md:12295 */
16103 rtx
16104 gen_rotrhi3 (operand0, operand1, operand2)
16105      rtx operand0;
16106      rtx operand1;
16107      rtx operand2;
16108 {
16109   rtx _val = 0;
16110   start_sequence ();
16111   {
16112     rtx operands[3];
16113     operands[0] = operand0;
16114     operands[1] = operand1;
16115     operands[2] = operand2;
16116 ix86_expand_binary_operator (ROTATERT, HImode, operands); DONE;
16117     operand0 = operands[0];
16118     operand1 = operands[1];
16119     operand2 = operands[2];
16120   }
16121   emit_insn (gen_rtx_SET (VOIDmode,
16122   operand0,
16123   gen_rtx_ROTATERT (HImode,
16124   operand1,
16125   operand2)));
16126   emit_insn (gen_rtx_CLOBBER (VOIDmode,
16127   gen_rtx_REG (CCmode,
16128   17)));
16129   _val = get_insns ();
16130   end_sequence ();
16131   return _val;
16132 }
16133 
16134 /* ../../gcc/gcc/config/i386/i386.md:12329 */
16135 rtx
16136 gen_rotrqi3 (operand0, operand1, operand2)
16137      rtx operand0;
16138      rtx operand1;
16139      rtx operand2;
16140 {
16141   rtx _val = 0;
16142   start_sequence ();
16143   {
16144     rtx operands[3];
16145     operands[0] = operand0;
16146     operands[1] = operand1;
16147     operands[2] = operand2;
16148 ix86_expand_binary_operator (ROTATERT, QImode, operands); DONE;
16149     operand0 = operands[0];
16150     operand1 = operands[1];
16151     operand2 = operands[2];
16152   }
16153   emit_insn (gen_rtx_SET (VOIDmode,
16154   operand0,
16155   gen_rtx_ROTATERT (QImode,
16156   operand1,
16157   operand2)));
16158   emit_insn (gen_rtx_CLOBBER (VOIDmode,
16159   gen_rtx_REG (CCmode,
16160   17)));
16161   _val = get_insns ();
16162   end_sequence ();
16163   return _val;
16164 }
16165 
16166 /* ../../gcc/gcc/config/i386/i386.md:12392 */
16167 rtx
16168 gen_extv (operand0, operand1, operand2, operand3)
16169      rtx operand0;
16170      rtx operand1;
16171      rtx operand2;
16172      rtx operand3;
16173 {
16174   rtx _val = 0;
16175   start_sequence ();
16176   {
16177     rtx operands[4];
16178     operands[0] = operand0;
16179     operands[1] = operand1;
16180     operands[2] = operand2;
16181     operands[3] = operand3;
16182 {
16183   /* Handle extractions from %ah et al.  */
16184   if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
16185     FAIL;
16186 
16187   /* From mips.md: extract_bit_field doesn't verify that our source
16188      matches the predicate, so check it again here.  */
16189   if (! register_operand (operands[1], VOIDmode))
16190     FAIL;
16191 }
16192     operand0 = operands[0];
16193     operand1 = operands[1];
16194     operand2 = operands[2];
16195     operand3 = operands[3];
16196   }
16197   emit_insn (gen_rtx_SET (VOIDmode,
16198   operand0,
16199   gen_rtx_SIGN_EXTRACT (SImode,
16200   operand1,
16201   operand2,
16202   operand3)));
16203   _val = get_insns ();
16204   end_sequence ();
16205   return _val;
16206 }
16207 
16208 /* ../../gcc/gcc/config/i386/i386.md:12409 */
16209 rtx
16210 gen_extzv (operand0, operand1, operand2, operand3)
16211      rtx operand0;
16212      rtx operand1;
16213      rtx operand2;
16214      rtx operand3;
16215 {
16216   rtx _val = 0;
16217   start_sequence ();
16218   {
16219     rtx operands[4];
16220     operands[0] = operand0;
16221     operands[1] = operand1;
16222     operands[2] = operand2;
16223     operands[3] = operand3;
16224 {
16225   /* Handle extractions from %ah et al.  */
16226   if (INTVAL (operands[2]) != 8 || INTVAL (operands[3]) != 8)
16227     FAIL;
16228 
16229   /* From mips.md: extract_bit_field doesn't verify that our source
16230      matches the predicate, so check it again here.  */
16231   if (! register_operand (operands[1], VOIDmode))
16232     FAIL;
16233 }
16234     operand0 = operands[0];
16235     operand1 = operands[1];
16236     operand2 = operands[2];
16237     operand3 = operands[3];
16238   }
16239   emit_insn (gen_rtx_SET (VOIDmode,
16240   operand0,
16241   gen_rtx_ZERO_EXTRACT (SImode,
16242   operand1,
16243   operand2,
16244   operand3)));
16245   _val = get_insns ();
16246   end_sequence ();
16247   return _val;
16248 }
16249 
16250 /* ../../gcc/gcc/config/i386/i386.md:12426 */
16251 rtx
16252 gen_insv (operand0, operand1, operand2, operand3)
16253      rtx operand0;
16254      rtx operand1;
16255      rtx operand2;
16256      rtx operand3;
16257 {
16258   rtx _val = 0;
16259   start_sequence ();
16260   {
16261     rtx operands[4];
16262     operands[0] = operand0;
16263     operands[1] = operand1;
16264     operands[2] = operand2;
16265     operands[3] = operand3;
16266 {
16267   /* Handle extractions from %ah et al.  */
16268   if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
16269     FAIL;
16270 
16271   /* From mips.md: insert_bit_field doesn't verify that our source
16272      matches the predicate, so check it again here.  */
16273   if (! register_operand (operands[0], VOIDmode))
16274     FAIL;
16275 }
16276     operand0 = operands[0];
16277     operand1 = operands[1];
16278     operand2 = operands[2];
16279     operand3 = operands[3];
16280   }
16281   emit_insn (gen_rtx_SET (VOIDmode,
16282   gen_rtx_ZERO_EXTRACT (SImode,
16283   operand0,
16284   operand1,
16285   operand2),
16286   operand3));
16287   _val = get_insns ();
16288   end_sequence ();
16289   return _val;
16290 }
16291 
16292 /* ../../gcc/gcc/config/i386/i386.md:12454 */
16293 rtx
16294 gen_seq (operand0)
16295      rtx operand0;
16296 {
16297   rtx _val = 0;
16298   start_sequence ();
16299   {
16300     rtx operands[1];
16301     operands[0] = operand0;
16302 if (ix86_expand_setcc (EQ, operands[0])) DONE; else FAIL;
16303     operand0 = operands[0];
16304   }
16305   emit_insn (gen_rtx_SET (VOIDmode,
16306   operand0,
16307   gen_rtx_EQ (QImode,
16308   gen_rtx_REG (CCmode,
16309   17),
16310   const0_rtx)));
16311   _val = get_insns ();
16312   end_sequence ();
16313   return _val;
16314 }
16315 
16316 /* ../../gcc/gcc/config/i386/i386.md:12460 */
16317 rtx
16318 gen_sne (operand0)
16319      rtx operand0;
16320 {
16321   rtx _val = 0;
16322   start_sequence ();
16323   {
16324     rtx operands[1];
16325     operands[0] = operand0;
16326 if (ix86_expand_setcc (NE, operands[0])) DONE; else FAIL;
16327     operand0 = operands[0];
16328   }
16329   emit_insn (gen_rtx_SET (VOIDmode,
16330   operand0,
16331   gen_rtx_NE (QImode,
16332   gen_rtx_REG (CCmode,
16333   17),
16334   const0_rtx)));
16335   _val = get_insns ();
16336   end_sequence ();
16337   return _val;
16338 }
16339 
16340 /* ../../gcc/gcc/config/i386/i386.md:12466 */
16341 rtx
16342 gen_sgt (operand0)
16343      rtx operand0;
16344 {
16345   rtx _val = 0;
16346   start_sequence ();
16347   {
16348     rtx operands[1];
16349     operands[0] = operand0;
16350 if (ix86_expand_setcc (GT, operands[0])) DONE; else FAIL;
16351     operand0 = operands[0];
16352   }
16353   emit_insn (gen_rtx_SET (VOIDmode,
16354   operand0,
16355   gen_rtx_GT (QImode,
16356   gen_rtx_REG (CCmode,
16357   17),
16358   const0_rtx)));
16359   _val = get_insns ();
16360   end_sequence ();
16361   return _val;
16362 }
16363 
16364 /* ../../gcc/gcc/config/i386/i386.md:12472 */
16365 rtx
16366 gen_sgtu (operand0)
16367      rtx operand0;
16368 {
16369   rtx _val = 0;
16370   start_sequence ();
16371   {
16372     rtx operands[1];
16373     operands[0] = operand0;
16374 if (ix86_expand_setcc (GTU, operands[0])) DONE; else FAIL;
16375     operand0 = operands[0];
16376   }
16377   emit_insn (gen_rtx_SET (VOIDmode,
16378   operand0,
16379   gen_rtx_GTU (QImode,
16380   gen_rtx_REG (CCmode,
16381   17),
16382   const0_rtx)));
16383   _val = get_insns ();
16384   end_sequence ();
16385   return _val;
16386 }
16387 
16388 /* ../../gcc/gcc/config/i386/i386.md:12478 */
16389 rtx
16390 gen_slt (operand0)
16391      rtx operand0;
16392 {
16393   rtx _val = 0;
16394   start_sequence ();
16395   {
16396     rtx operands[1];
16397     operands[0] = operand0;
16398 if (ix86_expand_setcc (LT, operands[0])) DONE; else FAIL;
16399     operand0 = operands[0];
16400   }
16401   emit_insn (gen_rtx_SET (VOIDmode,
16402   operand0,
16403   gen_rtx_LT (QImode,
16404   gen_rtx_REG (CCmode,
16405   17),
16406   const0_rtx)));
16407   _val = get_insns ();
16408   end_sequence ();
16409   return _val;
16410 }
16411 
16412 /* ../../gcc/gcc/config/i386/i386.md:12484 */
16413 rtx
16414 gen_sltu (operand0)
16415      rtx operand0;
16416 {
16417   rtx _val = 0;
16418   start_sequence ();
16419   {
16420     rtx operands[1];
16421     operands[0] = operand0;
16422 if (ix86_expand_setcc (LTU, operands[0])) DONE; else FAIL;
16423     operand0 = operands[0];
16424   }
16425   emit_insn (gen_rtx_SET (VOIDmode,
16426   operand0,
16427   gen_rtx_LTU (QImode,
16428   gen_rtx_REG (CCmode,
16429   17),
16430   const0_rtx)));
16431   _val = get_insns ();
16432   end_sequence ();
16433   return _val;
16434 }
16435 
16436 /* ../../gcc/gcc/config/i386/i386.md:12490 */
16437 rtx
16438 gen_sge (operand0)
16439      rtx operand0;
16440 {
16441   rtx _val = 0;
16442   start_sequence ();
16443   {
16444     rtx operands[1];
16445     operands[0] = operand0;
16446 if (ix86_expand_setcc (GE, operands[0])) DONE; else FAIL;
16447     operand0 = operands[0];
16448   }
16449   emit_insn (gen_rtx_SET (VOIDmode,
16450   operand0,
16451   gen_rtx_GE (QImode,
16452   gen_rtx_REG (CCmode,
16453   17),
16454   const0_rtx)));
16455   _val = get_insns ();
16456   end_sequence ();
16457   return _val;
16458 }
16459 
16460 /* ../../gcc/gcc/config/i386/i386.md:12496 */
16461 rtx
16462 gen_sgeu (operand0)
16463      rtx operand0;
16464 {
16465   rtx _val = 0;
16466   start_sequence ();
16467   {
16468     rtx operands[1];
16469     operands[0] = operand0;
16470 if (ix86_expand_setcc (GEU, operands[0])) DONE; else FAIL;
16471     operand0 = operands[0];
16472   }
16473   emit_insn (gen_rtx_SET (VOIDmode,
16474   operand0,
16475   gen_rtx_GEU (QImode,
16476   gen_rtx_REG (CCmode,
16477   17),
16478   const0_rtx)));
16479   _val = get_insns ();
16480   end_sequence ();
16481   return _val;
16482 }
16483 
16484 /* ../../gcc/gcc/config/i386/i386.md:12502 */
16485 rtx
16486 gen_sle (operand0)
16487      rtx operand0;
16488 {
16489   rtx _val = 0;
16490   start_sequence ();
16491   {
16492     rtx operands[1];
16493     operands[0] = operand0;
16494 if (ix86_expand_setcc (LE, operands[0])) DONE; else FAIL;
16495     operand0 = operands[0];
16496   }
16497   emit_insn (gen_rtx_SET (VOIDmode,
16498   operand0,
16499   gen_rtx_LE (QImode,
16500   gen_rtx_REG (CCmode,
16501   17),
16502   const0_rtx)));
16503   _val = get_insns ();
16504   end_sequence ();
16505   return _val;
16506 }
16507 
16508 /* ../../gcc/gcc/config/i386/i386.md:12508 */
16509 rtx
16510 gen_sleu (operand0)
16511      rtx operand0;
16512 {
16513   rtx _val = 0;
16514   start_sequence ();
16515   {
16516     rtx operands[1];
16517     operands[0] = operand0;
16518 if (ix86_expand_setcc (LEU, operands[0])) DONE; else FAIL;
16519     operand0 = operands[0];
16520   }
16521   emit_insn (gen_rtx_SET (VOIDmode,
16522   operand0,
16523   gen_rtx_LEU (QImode,
16524   gen_rtx_REG (CCmode,
16525   17),
16526   const0_rtx)));
16527   _val = get_insns ();
16528   end_sequence ();
16529   return _val;
16530 }
16531 
16532 /* ../../gcc/gcc/config/i386/i386.md:12514 */
16533 rtx
16534 gen_sunordered (operand0)
16535      rtx operand0;
16536 {
16537   rtx _val = 0;
16538   start_sequence ();
16539   {
16540     rtx operands[1];
16541     operands[0] = operand0;
16542 if (ix86_expand_setcc (UNORDERED, operands[0])) DONE; else FAIL;
16543     operand0 = operands[0];
16544   }
16545   emit_insn (gen_rtx_SET (VOIDmode,
16546   operand0,
16547   gen_rtx_UNORDERED (QImode,
16548   gen_rtx_REG (CCmode,
16549   17),
16550   const0_rtx)));
16551   _val = get_insns ();
16552   end_sequence ();
16553   return _val;
16554 }
16555 
16556 /* ../../gcc/gcc/config/i386/i386.md:12520 */
16557 rtx
16558 gen_sordered (operand0)
16559      rtx operand0;
16560 {
16561   rtx _val = 0;
16562   start_sequence ();
16563   {
16564     rtx operands[1];
16565     operands[0] = operand0;
16566 if (ix86_expand_setcc (ORDERED, operands[0])) DONE; else FAIL;
16567     operand0 = operands[0];
16568   }
16569   emit_insn (gen_rtx_SET (VOIDmode,
16570   operand0,
16571   gen_rtx_ORDERED (QImode,
16572   gen_rtx_REG (CCmode,
16573   17),
16574   const0_rtx)));
16575   _val = get_insns ();
16576   end_sequence ();
16577   return _val;
16578 }
16579 
16580 /* ../../gcc/gcc/config/i386/i386.md:12526 */
16581 rtx
16582 gen_suneq (operand0)
16583      rtx operand0;
16584 {
16585   rtx _val = 0;
16586   start_sequence ();
16587   {
16588     rtx operands[1];
16589     operands[0] = operand0;
16590 if (ix86_expand_setcc (UNEQ, operands[0])) DONE; else FAIL;
16591     operand0 = operands[0];
16592   }
16593   emit_insn (gen_rtx_SET (VOIDmode,
16594   operand0,
16595   gen_rtx_UNEQ (QImode,
16596   gen_rtx_REG (CCmode,
16597   17),
16598   const0_rtx)));
16599   _val = get_insns ();
16600   end_sequence ();
16601   return _val;
16602 }
16603 
16604 /* ../../gcc/gcc/config/i386/i386.md:12532 */
16605 rtx
16606 gen_sunge (operand0)
16607      rtx operand0;
16608 {
16609   rtx _val = 0;
16610   start_sequence ();
16611   {
16612     rtx operands[1];
16613     operands[0] = operand0;
16614 if (ix86_expand_setcc (UNGE, operands[0])) DONE; else FAIL;
16615     operand0 = operands[0];
16616   }
16617   emit_insn (gen_rtx_SET (VOIDmode,
16618   operand0,
16619   gen_rtx_UNGE (QImode,
16620   gen_rtx_REG (CCmode,
16621   17),
16622   const0_rtx)));
16623   _val = get_insns ();
16624   end_sequence ();
16625   return _val;
16626 }
16627 
16628 /* ../../gcc/gcc/config/i386/i386.md:12538 */
16629 rtx
16630 gen_sungt (operand0)
16631      rtx operand0;
16632 {
16633   rtx _val = 0;
16634   start_sequence ();
16635   {
16636     rtx operands[1];
16637     operands[0] = operand0;
16638 if (ix86_expand_setcc (UNGT, operands[0])) DONE; else FAIL;
16639     operand0 = operands[0];
16640   }
16641   emit_insn (gen_rtx_SET (VOIDmode,
16642   operand0,
16643   gen_rtx_UNGT (QImode,
16644   gen_rtx_REG (CCmode,
16645   17),
16646   const0_rtx)));
16647   _val = get_insns ();
16648   end_sequence ();
16649   return _val;
16650 }
16651 
16652 /* ../../gcc/gcc/config/i386/i386.md:12544 */
16653 rtx
16654 gen_sunle (operand0)
16655      rtx operand0;
16656 {
16657   rtx _val = 0;
16658   start_sequence ();
16659   {
16660     rtx operands[1];
16661     operands[0] = operand0;
16662 if (ix86_expand_setcc (UNLE, operands[0])) DONE; else FAIL;
16663     operand0 = operands[0];
16664   }
16665   emit_insn (gen_rtx_SET (VOIDmode,
16666   operand0,
16667   gen_rtx_UNLE (QImode,
16668   gen_rtx_REG (CCmode,
16669   17),
16670   const0_rtx)));
16671   _val = get_insns ();
16672   end_sequence ();
16673   return _val;
16674 }
16675 
16676 /* ../../gcc/gcc/config/i386/i386.md:12550 */
16677 rtx
16678 gen_sunlt (operand0)
16679      rtx operand0;
16680 {
16681   rtx _val = 0;
16682   start_sequence ();
16683   {
16684     rtx operands[1];
16685     operands[0] = operand0;
16686 if (ix86_expand_setcc (UNLT, operands[0])) DONE; else FAIL;
16687     operand0 = operands[0];
16688   }
16689   emit_insn (gen_rtx_SET (VOIDmode,
16690   operand0,
16691   gen_rtx_UNLT (QImode,
16692   gen_rtx_REG (CCmode,
16693   17),
16694   const0_rtx)));
16695   _val = get_insns ();
16696   end_sequence ();
16697   return _val;
16698 }
16699 
16700 /* ../../gcc/gcc/config/i386/i386.md:12556 */
16701 rtx
16702 gen_sltgt (operand0)
16703      rtx operand0;
16704 {
16705   rtx _val = 0;
16706   start_sequence ();
16707   {
16708     rtx operands[1];
16709     operands[0] = operand0;
16710 if (ix86_expand_setcc (LTGT, operands[0])) DONE; else FAIL;
16711     operand0 = operands[0];
16712   }
16713   emit_insn (gen_rtx_SET (VOIDmode,
16714   operand0,
16715   gen_rtx_LTGT (QImode,
16716   gen_rtx_REG (CCmode,
16717   17),
16718   const0_rtx)));
16719   _val = get_insns ();
16720   end_sequence ();
16721   return _val;
16722 }
16723 
16724 /* ../../gcc/gcc/config/i386/i386.md:12588 */
16725 extern rtx gen_split_1343 PARAMS ((rtx *));
16726 rtx
16727 gen_split_1343 (operands)
16728       rtx *operands;
16729 {
16730   rtx operand0;
16731   rtx operand1;
16732   rtx _val = 0;
16733   start_sequence ();
16734 {
16735   PUT_MODE (operands[1], QImode);
16736 }
16737   operand0 = operands[0];
16738   operand1 = operands[1];
16739   emit_insn (gen_rtx_SET (VOIDmode,
16740   operand0,
16741   operand1));
16742   _val = get_insns ();
16743   end_sequence ();
16744   return _val;
16745 }
16746 
16747 /* ../../gcc/gcc/config/i386/i386.md:12599 */
16748 extern rtx gen_split_1344 PARAMS ((rtx *));
16749 rtx
16750 gen_split_1344 (operands)
16751       rtx *operands;
16752 {
16753   rtx operand0;
16754   rtx operand1;
16755   rtx _val = 0;
16756   start_sequence ();
16757 {
16758   PUT_MODE (operands[1], QImode);
16759 }
16760   operand0 = operands[0];
16761   operand1 = operands[1];
16762   emit_insn (gen_rtx_SET (VOIDmode,
16763   operand0,
16764   operand1));
16765   _val = get_insns ();
16766   end_sequence ();
16767   return _val;
16768 }
16769 
16770 /* ../../gcc/gcc/config/i386/i386.md:12610 */
16771 extern rtx gen_split_1345 PARAMS ((rtx *));
16772 rtx
16773 gen_split_1345 (operands)
16774       rtx *operands;
16775 {
16776   rtx operand0;
16777   rtx operand1;
16778   rtx _val = 0;
16779   start_sequence ();
16780 {
16781   rtx new_op1 = copy_rtx (operands[1]);
16782   operands[1] = new_op1;
16783   PUT_MODE (new_op1, QImode);
16784   PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
16785           GET_MODE (XEXP (new_op1, 0))));
16786 
16787   /* Make sure that (a) the CCmode we have for the flags is strong
16788      enough for the reversed compare or (b) we have a valid FP compare.  */
16789   if (! ix86_comparison_operator (new_op1, VOIDmode))
16790     FAIL;
16791 }
16792   operand0 = operands[0];
16793   operand1 = operands[1];
16794   emit_insn (gen_rtx_SET (VOIDmode,
16795   operand0,
16796   operand1));
16797   _val = get_insns ();
16798   end_sequence ();
16799   return _val;
16800 }
16801 
16802 /* ../../gcc/gcc/config/i386/i386.md:12630 */
16803 extern rtx gen_split_1346 PARAMS ((rtx *));
16804 rtx
16805 gen_split_1346 (operands)
16806       rtx *operands;
16807 {
16808   rtx operand0;
16809   rtx operand1;
16810   rtx _val = 0;
16811   start_sequence ();
16812 {
16813   rtx new_op1 = copy_rtx (operands[1]);
16814   operands[1] = new_op1;
16815   PUT_MODE (new_op1, QImode);
16816   PUT_CODE (new_op1, REVERSE_CONDITION (GET_CODE (new_op1),
16817           GET_MODE (XEXP (new_op1, 0))));
16818 
16819   /* Make sure that (a) the CCmode we have for the flags is strong
16820      enough for the reversed compare or (b) we have a valid FP compare.  */
16821   if (! ix86_comparison_operator (new_op1, VOIDmode))
16822     FAIL;
16823 }
16824   operand0 = operands[0];
16825   operand1 = operands[1];
16826   emit_insn (gen_rtx_SET (VOIDmode,
16827   operand0,
16828   operand1));
16829   _val = get_insns ();
16830   end_sequence ();
16831   return _val;
16832 }
16833 
16834 /* ../../gcc/gcc/config/i386/i386.md:12684 */
16835 rtx
16836 gen_beq (operand0)
16837      rtx operand0;
16838 {
16839   rtx operand1;
16840   rtx _val = 0;
16841   start_sequence ();
16842   {
16843     rtx operands[2];
16844     operands[0] = operand0;
16845 ix86_expand_branch (EQ, operands[0]); DONE;
16846     operand0 = operands[0];
16847     operand1 = operands[1];
16848   }
16849   emit_jump_insn (gen_rtx_SET (VOIDmode,
16850   pc_rtx,
16851   gen_rtx_IF_THEN_ELSE (VOIDmode,
16852   operand1,
16853   gen_rtx_LABEL_REF (VOIDmode,
16854   operand0),
16855   pc_rtx)));
16856   _val = get_insns ();
16857   end_sequence ();
16858   return _val;
16859 }
16860 
16861 /* ../../gcc/gcc/config/i386/i386.md:12692 */
16862 rtx
16863 gen_bne (operand0)
16864      rtx operand0;
16865 {
16866   rtx operand1;
16867   rtx _val = 0;
16868   start_sequence ();
16869   {
16870     rtx operands[2];
16871     operands[0] = operand0;
16872 ix86_expand_branch (NE, operands[0]); DONE;
16873     operand0 = operands[0];
16874     operand1 = operands[1];
16875   }
16876   emit_jump_insn (gen_rtx_SET (VOIDmode,
16877   pc_rtx,
16878   gen_rtx_IF_THEN_ELSE (VOIDmode,
16879   operand1,
16880   gen_rtx_LABEL_REF (VOIDmode,
16881   operand0),
16882   pc_rtx)));
16883   _val = get_insns ();
16884   end_sequence ();
16885   return _val;
16886 }
16887 
16888 /* ../../gcc/gcc/config/i386/i386.md:12700 */
16889 rtx
16890 gen_bgt (operand0)
16891      rtx operand0;
16892 {
16893   rtx operand1;
16894   rtx _val = 0;
16895   start_sequence ();
16896   {
16897     rtx operands[2];
16898     operands[0] = operand0;
16899 ix86_expand_branch (GT, operands[0]); DONE;
16900     operand0 = operands[0];
16901     operand1 = operands[1];
16902   }
16903   emit_jump_insn (gen_rtx_SET (VOIDmode,
16904   pc_rtx,
16905   gen_rtx_IF_THEN_ELSE (VOIDmode,
16906   operand1,
16907   gen_rtx_LABEL_REF (VOIDmode,
16908   operand0),
16909   pc_rtx)));
16910   _val = get_insns ();
16911   end_sequence ();
16912   return _val;
16913 }
16914 
16915 /* ../../gcc/gcc/config/i386/i386.md:12708 */
16916 rtx
16917 gen_bgtu (operand0)
16918      rtx operand0;
16919 {
16920   rtx operand1;
16921   rtx _val = 0;
16922   start_sequence ();
16923   {
16924     rtx operands[2];
16925     operands[0] = operand0;
16926 ix86_expand_branch (GTU, operands[0]); DONE;
16927     operand0 = operands[0];
16928     operand1 = operands[1];
16929   }
16930   emit_jump_insn (gen_rtx_SET (VOIDmode,
16931   pc_rtx,
16932   gen_rtx_IF_THEN_ELSE (VOIDmode,
16933   operand1,
16934   gen_rtx_LABEL_REF (VOIDmode,
16935   operand0),
16936   pc_rtx)));
16937   _val = get_insns ();
16938   end_sequence ();
16939   return _val;
16940 }
16941 
16942 /* ../../gcc/gcc/config/i386/i386.md:12716 */
16943 rtx
16944 gen_blt (operand0)
16945      rtx operand0;
16946 {
16947   rtx operand1;
16948   rtx _val = 0;
16949   start_sequence ();
16950   {
16951     rtx operands[2];
16952     operands[0] = operand0;
16953 ix86_expand_branch (LT, operands[0]); DONE;
16954     operand0 = operands[0];
16955     operand1 = operands[1];
16956   }
16957   emit_jump_insn (gen_rtx_SET (VOIDmode,
16958   pc_rtx,
16959   gen_rtx_IF_THEN_ELSE (VOIDmode,
16960   operand1,
16961   gen_rtx_LABEL_REF (VOIDmode,
16962   operand0),
16963   pc_rtx)));
16964   _val = get_insns ();
16965   end_sequence ();
16966   return _val;
16967 }
16968 
16969 /* ../../gcc/gcc/config/i386/i386.md:12724 */
16970 rtx
16971 gen_bltu (operand0)
16972      rtx operand0;
16973 {
16974   rtx operand1;
16975   rtx _val = 0;
16976   start_sequence ();
16977   {
16978     rtx operands[2];
16979     operands[0] = operand0;
16980 ix86_expand_branch (LTU, operands[0]); DONE;
16981     operand0 = operands[0];
16982     operand1 = operands[1];
16983   }
16984   emit_jump_insn (gen_rtx_SET (VOIDmode,
16985   pc_rtx,
16986   gen_rtx_IF_THEN_ELSE (VOIDmode,
16987   operand1,
16988   gen_rtx_LABEL_REF (VOIDmode,
16989   operand0),
16990   pc_rtx)));
16991   _val = get_insns ();
16992   end_sequence ();
16993   return _val;
16994 }
16995 
16996 /* ../../gcc/gcc/config/i386/i386.md:12732 */
16997 rtx
16998 gen_bge (operand0)
16999      rtx operand0;
17000 {
17001   rtx operand1;
17002   rtx _val = 0;
17003   start_sequence ();
17004   {
17005     rtx operands[2];
17006     operands[0] = operand0;
17007 ix86_expand_branch (GE, operands[0]); DONE;
17008     operand0 = operands[0];
17009     operand1 = operands[1];
17010   }
17011   emit_jump_insn (gen_rtx_SET (VOIDmode,
17012   pc_rtx,
17013   gen_rtx_IF_THEN_ELSE (VOIDmode,
17014   operand1,
17015   gen_rtx_LABEL_REF (VOIDmode,
17016   operand0),
17017   pc_rtx)));
17018   _val = get_insns ();
17019   end_sequence ();
17020   return _val;
17021 }
17022 
17023 /* ../../gcc/gcc/config/i386/i386.md:12740 */
17024 rtx
17025 gen_bgeu (operand0)
17026      rtx operand0;
17027 {
17028   rtx operand1;
17029   rtx _val = 0;
17030   start_sequence ();
17031   {
17032     rtx operands[2];
17033     operands[0] = operand0;
17034 ix86_expand_branch (GEU, operands[0]); DONE;
17035     operand0 = operands[0];
17036     operand1 = operands[1];
17037   }
17038   emit_jump_insn (gen_rtx_SET (VOIDmode,
17039   pc_rtx,
17040   gen_rtx_IF_THEN_ELSE (VOIDmode,
17041   operand1,
17042   gen_rtx_LABEL_REF (VOIDmode,
17043   operand0),
17044   pc_rtx)));
17045   _val = get_insns ();
17046   end_sequence ();
17047   return _val;
17048 }
17049 
17050 /* ../../gcc/gcc/config/i386/i386.md:12748 */
17051 rtx
17052 gen_ble (operand0)
17053      rtx operand0;
17054 {
17055   rtx operand1;
17056   rtx _val = 0;
17057   start_sequence ();
17058   {
17059     rtx operands[2];
17060     operands[0] = operand0;
17061 ix86_expand_branch (LE, operands[0]); DONE;
17062     operand0 = operands[0];
17063     operand1 = operands[1];
17064   }
17065   emit_jump_insn (gen_rtx_SET (VOIDmode,
17066   pc_rtx,
17067   gen_rtx_IF_THEN_ELSE (VOIDmode,
17068   operand1,
17069   gen_rtx_LABEL_REF (VOIDmode,
17070   operand0),
17071   pc_rtx)));
17072   _val = get_insns ();
17073   end_sequence ();
17074   return _val;
17075 }
17076 
17077 /* ../../gcc/gcc/config/i386/i386.md:12756 */
17078 rtx
17079 gen_bleu (operand0)
17080      rtx operand0;
17081 {
17082   rtx operand1;
17083   rtx _val = 0;
17084   start_sequence ();
17085   {
17086     rtx operands[2];
17087     operands[0] = operand0;
17088 ix86_expand_branch (LEU, operands[0]); DONE;
17089     operand0 = operands[0];
17090     operand1 = operands[1];
17091   }
17092   emit_jump_insn (gen_rtx_SET (VOIDmode,
17093   pc_rtx,
17094   gen_rtx_IF_THEN_ELSE (VOIDmode,
17095   operand1,
17096   gen_rtx_LABEL_REF (VOIDmode,
17097   operand0),
17098   pc_rtx)));
17099   _val = get_insns ();
17100   end_sequence ();
17101   return _val;
17102 }
17103 
17104 /* ../../gcc/gcc/config/i386/i386.md:12764 */
17105 rtx
17106 gen_bunordered (operand0)
17107      rtx operand0;
17108 {
17109   rtx operand1;
17110   rtx _val = 0;
17111   start_sequence ();
17112   {
17113     rtx operands[2];
17114     operands[0] = operand0;
17115 ix86_expand_branch (UNORDERED, operands[0]); DONE;
17116     operand0 = operands[0];
17117     operand1 = operands[1];
17118   }
17119   emit_jump_insn (gen_rtx_SET (VOIDmode,
17120   pc_rtx,
17121   gen_rtx_IF_THEN_ELSE (VOIDmode,
17122   operand1,
17123   gen_rtx_LABEL_REF (VOIDmode,
17124   operand0),
17125   pc_rtx)));
17126   _val = get_insns ();
17127   end_sequence ();
17128   return _val;
17129 }
17130 
17131 /* ../../gcc/gcc/config/i386/i386.md:12772 */
17132 rtx
17133 gen_bordered (operand0)
17134      rtx operand0;
17135 {
17136   rtx operand1;
17137   rtx _val = 0;
17138   start_sequence ();
17139   {
17140     rtx operands[2];
17141     operands[0] = operand0;
17142 ix86_expand_branch (ORDERED, operands[0]); DONE;
17143     operand0 = operands[0];
17144     operand1 = operands[1];
17145   }
17146   emit_jump_insn (gen_rtx_SET (VOIDmode,
17147   pc_rtx,
17148   gen_rtx_IF_THEN_ELSE (VOIDmode,
17149   operand1,
17150   gen_rtx_LABEL_REF (VOIDmode,
17151   operand0),
17152   pc_rtx)));
17153   _val = get_insns ();
17154   end_sequence ();
17155   return _val;
17156 }
17157 
17158 /* ../../gcc/gcc/config/i386/i386.md:12780 */
17159 rtx
17160 gen_buneq (operand0)
17161      rtx operand0;
17162 {
17163   rtx operand1;
17164   rtx _val = 0;
17165   start_sequence ();
17166   {
17167     rtx operands[2];
17168     operands[0] = operand0;
17169 ix86_expand_branch (UNEQ, operands[0]); DONE;
17170     operand0 = operands[0];
17171     operand1 = operands[1];
17172   }
17173   emit_jump_insn (gen_rtx_SET (VOIDmode,
17174   pc_rtx,
17175   gen_rtx_IF_THEN_ELSE (VOIDmode,
17176   operand1,
17177   gen_rtx_LABEL_REF (VOIDmode,
17178   operand0),
17179   pc_rtx)));
17180   _val = get_insns ();
17181   end_sequence ();
17182   return _val;
17183 }
17184 
17185 /* ../../gcc/gcc/config/i386/i386.md:12788 */
17186 rtx
17187 gen_bunge (operand0)
17188      rtx operand0;
17189 {
17190   rtx operand1;
17191   rtx _val = 0;
17192   start_sequence ();
17193   {
17194     rtx operands[2];
17195     operands[0] = operand0;
17196 ix86_expand_branch (UNGE, operands[0]); DONE;
17197     operand0 = operands[0];
17198     operand1 = operands[1];
17199   }
17200   emit_jump_insn (gen_rtx_SET (VOIDmode,
17201   pc_rtx,
17202   gen_rtx_IF_THEN_ELSE (VOIDmode,
17203   operand1,
17204   gen_rtx_LABEL_REF (VOIDmode,
17205   operand0),
17206   pc_rtx)));
17207   _val = get_insns ();
17208   end_sequence ();
17209   return _val;
17210 }
17211 
17212 /* ../../gcc/gcc/config/i386/i386.md:12796 */
17213 rtx
17214 gen_bungt (operand0)
17215      rtx operand0;
17216 {
17217   rtx operand1;
17218   rtx _val = 0;
17219   start_sequence ();
17220   {
17221     rtx operands[2];
17222     operands[0] = operand0;
17223 ix86_expand_branch (UNGT, operands[0]); DONE;
17224     operand0 = operands[0];
17225     operand1 = operands[1];
17226   }
17227   emit_jump_insn (gen_rtx_SET (VOIDmode,
17228   pc_rtx,
17229   gen_rtx_IF_THEN_ELSE (VOIDmode,
17230   operand1,
17231   gen_rtx_LABEL_REF (VOIDmode,
17232   operand0),
17233   pc_rtx)));
17234   _val = get_insns ();
17235   end_sequence ();
17236   return _val;
17237 }
17238 
17239 /* ../../gcc/gcc/config/i386/i386.md:12804 */
17240 rtx
17241 gen_bunle (operand0)
17242      rtx operand0;
17243 {
17244   rtx operand1;
17245   rtx _val = 0;
17246   start_sequence ();
17247   {
17248     rtx operands[2];
17249     operands[0] = operand0;
17250 ix86_expand_branch (UNLE, operands[0]); DONE;
17251     operand0 = operands[0];
17252     operand1 = operands[1];
17253   }
17254   emit_jump_insn (gen_rtx_SET (VOIDmode,
17255   pc_rtx,
17256   gen_rtx_IF_THEN_ELSE (VOIDmode,
17257   operand1,
17258   gen_rtx_LABEL_REF (VOIDmode,
17259   operand0),
17260   pc_rtx)));
17261   _val = get_insns ();
17262   end_sequence ();
17263   return _val;
17264 }
17265 
17266 /* ../../gcc/gcc/config/i386/i386.md:12812 */
17267 rtx
17268 gen_bunlt (operand0)
17269      rtx operand0;
17270 {
17271   rtx operand1;
17272   rtx _val = 0;
17273   start_sequence ();
17274   {
17275     rtx operands[2];
17276     operands[0] = operand0;
17277 ix86_expand_branch (UNLT, operands[0]); DONE;
17278     operand0 = operands[0];
17279     operand1 = operands[1];
17280   }
17281   emit_jump_insn (gen_rtx_SET (VOIDmode,
17282   pc_rtx,
17283   gen_rtx_IF_THEN_ELSE (VOIDmode,
17284   operand1,
17285   gen_rtx_LABEL_REF (VOIDmode,
17286   operand0),
17287   pc_rtx)));
17288   _val = get_insns ();
17289   end_sequence ();
17290   return _val;
17291 }
17292 
17293 /* ../../gcc/gcc/config/i386/i386.md:12820 */
17294 rtx
17295 gen_bltgt (operand0)
17296      rtx operand0;
17297 {
17298   rtx operand1;
17299   rtx _val = 0;
17300   start_sequence ();
17301   {
17302     rtx operands[2];
17303     operands[0] = operand0;
17304 ix86_expand_branch (LTGT, operands[0]); DONE;
17305     operand0 = operands[0];
17306     operand1 = operands[1];
17307   }
17308   emit_jump_insn (gen_rtx_SET (VOIDmode,
17309   pc_rtx,
17310   gen_rtx_IF_THEN_ELSE (VOIDmode,
17311   operand1,
17312   gen_rtx_LABEL_REF (VOIDmode,
17313   operand0),
17314   pc_rtx)));
17315   _val = get_insns ();
17316   end_sequence ();
17317   return _val;
17318 }
17319 
17320 /* ../../gcc/gcc/config/i386/i386.md:12872 */
17321 extern rtx gen_split_1365 PARAMS ((rtx *));
17322 rtx
17323 gen_split_1365 (operands)
17324       rtx *operands;
17325 {
17326   rtx operand0;
17327   rtx operand1;
17328   rtx _val = 0;
17329   start_sequence ();
17330 {
17331   PUT_MODE (operands[0], VOIDmode);
17332 }
17333   operand0 = operands[0];
17334   operand1 = operands[1];
17335   emit_jump_insn (gen_rtx_SET (VOIDmode,
17336   pc_rtx,
17337   gen_rtx_IF_THEN_ELSE (VOIDmode,
17338   operand0,
17339   gen_rtx_LABEL_REF (VOIDmode,
17340   operand1),
17341   pc_rtx)));
17342   _val = get_insns ();
17343   end_sequence ();
17344   return _val;
17345 }
17346 
17347 /* ../../gcc/gcc/config/i386/i386.md:12888 */
17348 extern rtx gen_split_1366 PARAMS ((rtx *));
17349 rtx
17350 gen_split_1366 (operands)
17351       rtx *operands;
17352 {
17353   rtx operand0;
17354   rtx operand1;
17355   rtx _val = 0;
17356   start_sequence ();
17357 {
17358   rtx new_op0 = copy_rtx (operands[0]);
17359   operands[0] = new_op0;
17360   PUT_MODE (new_op0, VOIDmode);
17361   PUT_CODE (new_op0, REVERSE_CONDITION (GET_CODE (new_op0),
17362           GET_MODE (XEXP (new_op0, 0))));
17363 
17364   /* Make sure that (a) the CCmode we have for the flags is strong
17365      enough for the reversed compare or (b) we have a valid FP compare.  */
17366   if (! ix86_comparison_operator (new_op0, VOIDmode))
17367     FAIL;
17368 }
17369   operand0 = operands[0];
17370   operand1 = operands[1];
17371   emit_jump_insn (gen_rtx_SET (VOIDmode,
17372   pc_rtx,
17373   gen_rtx_IF_THEN_ELSE (VOIDmode,
17374   operand0,
17375   gen_rtx_LABEL_REF (VOIDmode,
17376   operand1),
17377   pc_rtx)));
17378   _val = get_insns ();
17379   end_sequence ();
17380   return _val;
17381 }
17382 
17383 /* ../../gcc/gcc/config/i386/i386.md:13077 */
17384 extern rtx gen_split_1367 PARAMS ((rtx *));
17385 rtx
17386 gen_split_1367 (operands)
17387       rtx *operands ATTRIBUTE_UNUSED;
17388 {
17389   rtx _val = 0;
17390   start_sequence ();
17391 {
17392   ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
17393       operands[3], operands[4], NULL_RTX);
17394   DONE;
17395 }
17396   emit_insn (const0_rtx);
17397   _val = get_insns ();
17398   end_sequence ();
17399   return _val;
17400 }
17401 
17402 /* ../../gcc/gcc/config/i386/i386.md:13094 */
17403 extern rtx gen_split_1368 PARAMS ((rtx *));
17404 rtx
17405 gen_split_1368 (operands)
17406       rtx *operands;
17407 {
17408   rtx operand0;
17409   rtx operand1;
17410   rtx operand2;
17411   rtx operand3;
17412   rtx operand4;
17413   rtx operand5;
17414   rtx operand6;
17415   rtx _val = 0;
17416   start_sequence ();
17417 {
17418   ix86_split_fp_branch (GET_CODE (operands[0]), operands[1], operands[2],
17419       operands[3], operands[4], operands[5]);
17420   DONE;
17421 }
17422   operand0 = operands[0];
17423   operand1 = operands[1];
17424   operand2 = operands[2];
17425   operand3 = operands[3];
17426   operand4 = operands[4];
17427   operand5 = operands[5];
17428   operand6 = operands[6];
17429   emit_jump_insn (gen_rtx_SET (VOIDmode,
17430   pc_rtx,
17431   gen_rtx_IF_THEN_ELSE (VOIDmode,
17432   operand6,
17433   operand3,
17434   operand4)));
17435   _val = get_insns ();
17436   end_sequence ();
17437   return _val;
17438 }
17439 
17440 /* ../../gcc/gcc/config/i386/i386.md:13132 */
17441 rtx
17442 gen_indirect_jump (operand0)
17443      rtx operand0;
17444 {
17445   return gen_rtx_SET (VOIDmode,
17446   pc_rtx,
17447   operand0);
17448 }
17449 
17450 /* ../../gcc/gcc/config/i386/i386.md:13151 */
17451 rtx
17452 gen_tablejump (operand0, operand1)
17453      rtx operand0;
17454      rtx operand1;
17455 {
17456   rtx _val = 0;
17457   start_sequence ();
17458   {
17459     rtx operands[2];
17460     operands[0] = operand0;
17461     operands[1] = operand1;
17462 {
17463   /* In PIC mode, the table entries are stored GOT (32-bit) or PC (64-bit)
17464      relative.  Convert the relative address to an absolute address.  */
17465   if (flag_pic)
17466     {
17467       rtx op0, op1;
17468       enum rtx_code code;
17469 
17470       if (TARGET_64BIT)
17471   {
17472     code = PLUS;
17473     op0 = operands[0];
17474     op1 = gen_rtx_LABEL_REF (Pmode, operands[1]);
17475   }
17476       else if (TARGET_MACHO || HAVE_AS_GOTOFF_IN_DATA)
17477   {
17478     code = PLUS;
17479     op0 = operands[0];
17480     op1 = pic_offset_table_rtx;
17481   }
17482       else
17483   {
17484     code = MINUS;
17485     op0 = pic_offset_table_rtx;
17486     op1 = operands[0];
17487   }
17488 
17489       operands[0] = expand_simple_binop (Pmode, code, op0, op1, NULL_RTX, 0,
17490            OPTAB_DIRECT);
17491     }
17492 }
17493     operand0 = operands[0];
17494     operand1 = operands[1];
17495   }
17496   emit_jump_insn (gen_rtx_PARALLEL (VOIDmode,
17497   gen_rtvec (2,
17498     gen_rtx_SET (VOIDmode,
17499   pc_rtx,
17500   operand0),
17501     gen_rtx_USE (VOIDmode,
17502   gen_rtx_LABEL_REF (VOIDmode,
17503   operand1)))));
17504   _val = get_insns ();
17505   end_sequence ();
17506   return _val;
17507 }
17508 
17509 /* ../../gcc/gcc/config/i386/i386.md:13208 */
17510 rtx
17511 gen_doloop_end (operand0, operand1, operand2, operand3, operand4)
17512      rtx operand0;
17513      rtx operand1;
17514      rtx operand2;
17515      rtx operand3;
17516      rtx operand4;
17517 {
17518   rtx _val = 0;
17519   start_sequence ();
17520   {
17521     rtx operands[5];
17522     operands[0] = operand0;
17523     operands[1] = operand1;
17524     operands[2] = operand2;
17525     operands[3] = operand3;
17526     operands[4] = operand4;
17527                                  
17528 {
17529   /* Only use cloop on innermost loops.  */
17530   if (INTVAL (operands[3]) > 1)
17531     FAIL;
17532   if (GET_MODE (operands[0]) != SImode)
17533     FAIL;
17534   emit_jump_insn (gen_doloop_end_internal (operands[4], operands[0],
17535              operands[0]));
17536   DONE;
17537 }
17538     operand0 = operands[0];
17539     operand1 = operands[1];
17540     operand2 = operands[2];
17541     operand3 = operands[3];
17542     operand4 = operands[4];
17543   }
17544   emit_insn (gen_rtx_USE (VOIDmode,
17545   operand0));
17546   emit_insn (gen_rtx_USE (VOIDmode,
17547   operand1));
17548   emit_insn (gen_rtx_USE (VOIDmode,
17549   operand2));
17550   emit_insn (gen_rtx_USE (VOIDmode,
17551   operand3));
17552   emit_insn (gen_rtx_USE (VOIDmode,
17553   operand4));
17554   _val = get_insns ();
17555   end_sequence ();
17556   return _val;
17557 }
17558 
17559 /* ../../gcc/gcc/config/i386/i386.md:13260 */
17560 extern rtx gen_split_1372 PARAMS ((rtx *));
17561 rtx
17562 gen_split_1372 (operands)
17563       rtx *operands;
17564 {
17565   rtx operand0;
17566   rtx operand1;
17567   rtx _val = 0;
17568   start_sequence ();
17569 
17570   operand0 = operands[0];
17571   operand1 = operands[1];
17572   emit (gen_rtx_PARALLEL (VOIDmode,
17573   gen_rtvec (2,
17574     gen_rtx_SET (VOIDmode,
17575   gen_rtx_REG (CCZmode,
17576   17),
17577   gen_rtx_COMPARE (CCZmode,
17578   gen_rtx_PLUS (SImode,
17579   operand1,
17580   constm1_rtx),
17581   const0_rtx)),
17582     gen_rtx_SET (VOIDmode,
17583   copy_rtx (operand1),
17584   gen_rtx_PLUS (SImode,
17585   copy_rtx (operand1),
17586   constm1_rtx)))));
17587   emit_jump_insn (gen_rtx_SET (VOIDmode,
17588   pc_rtx,
17589   gen_rtx_IF_THEN_ELSE (VOIDmode,
17590   gen_rtx_NE (VOIDmode,
17591   gen_rtx_REG (CCZmode,
17592   17),
17593   const0_rtx),
17594   operand0,
17595   pc_rtx)));
17596   _val = get_insns ();
17597   end_sequence ();
17598   return _val;
17599 }
17600 
17601 /* ../../gcc/gcc/config/i386/i386.md:13283 */
17602 extern rtx gen_split_1373 PARAMS ((rtx *));
17603 rtx
17604 gen_split_1373 (operands)
17605       rtx *operands;
17606 {
17607   rtx operand0;
17608   rtx operand1;
17609   rtx operand2;
17610   rtx operand3;
17611   rtx _val = 0;
17612   start_sequence ();
17613 
17614   operand0 = operands[0];
17615   operand1 = operands[1];
17616   operand2 = operands[2];
17617   operand3 = operands[3];
17618   emit_insn (gen_rtx_SET (VOIDmode,
17619   operand3,
17620   operand1));
17621   emit (gen_rtx_PARALLEL (VOIDmode,
17622   gen_rtvec (2,
17623     gen_rtx_SET (VOIDmode,
17624   gen_rtx_REG (CCZmode,
17625   17),
17626   gen_rtx_COMPARE (CCZmode,
17627   gen_rtx_PLUS (SImode,
17628   copy_rtx (operand3),
17629   constm1_rtx),
17630   const0_rtx)),
17631     gen_rtx_SET (VOIDmode,
17632   copy_rtx (operand3),
17633   gen_rtx_PLUS (SImode,
17634   copy_rtx (operand3),
17635   constm1_rtx)))));
17636   emit_insn (gen_rtx_SET (VOIDmode,
17637   operand2,
17638   copy_rtx (operand3)));
17639   emit_jump_insn (gen_rtx_SET (VOIDmode,
17640   pc_rtx,
17641   gen_rtx_IF_THEN_ELSE (VOIDmode,
17642   gen_rtx_NE (VOIDmode,
17643   gen_rtx_REG (CCZmode,
17644   17),
17645   const0_rtx),
17646   operand0,
17647   pc_rtx)));
17648   _val = get_insns ();
17649   end_sequence ();
17650   return _val;
17651 }
17652 
17653 /* ../../gcc/gcc/config/i386/i386.md:13311 */
17654 extern rtx gen_peephole2_1374 PARAMS ((rtx, rtx *));
17655 rtx
17656 gen_peephole2_1374 (curr_insn, operands)
17657      rtx curr_insn ATTRIBUTE_UNUSED;
17658      rtx *operands;
17659 {
17660   rtx operand0;
17661   rtx operand1;
17662   rtx operand2;
17663   rtx operand3;
17664   rtx operand4;
17665   rtx operand5;
17666   rtx _val = 0;
17667   HARD_REG_SET _regs_allocated;
17668   CLEAR_HARD_REG_SET (_regs_allocated);
17669   start_sequence ();
17670 {
17671   operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
17672   operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
17673   ix86_expand_clear (operands[3]);
17674 }
17675   operand0 = operands[0];
17676   operand1 = operands[1];
17677   operand2 = operands[2];
17678   operand3 = operands[3];
17679   operand4 = operands[4];
17680   operand5 = operands[5];
17681   emit_insn (gen_rtx_SET (VOIDmode,
17682   operand4,
17683   operand0));
17684   emit_insn (gen_rtx_SET (VOIDmode,
17685   gen_rtx_STRICT_LOW_PART (VOIDmode,
17686   operand5),
17687   operand2));
17688   _val = get_insns ();
17689   end_sequence ();
17690   return _val;
17691 }
17692 
17693 /* ../../gcc/gcc/config/i386/i386.md:13332 */
17694 extern rtx gen_peephole2_1375 PARAMS ((rtx, rtx *));
17695 rtx
17696 gen_peephole2_1375 (curr_insn, operands)
17697      rtx curr_insn ATTRIBUTE_UNUSED;
17698      rtx *operands;
17699 {
17700   rtx operand0;
17701   rtx operand1;
17702   rtx operand2;
17703   rtx operand3;
17704   rtx operand4;
17705   rtx operand5;
17706   rtx _val = 0;
17707   HARD_REG_SET _regs_allocated;
17708   CLEAR_HARD_REG_SET (_regs_allocated);
17709   start_sequence ();
17710 {
17711   operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
17712   operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
17713   ix86_expand_clear (operands[3]);
17714 }
17715   operand0 = operands[0];
17716   operand1 = operands[1];
17717   operand2 = operands[2];
17718   operand3 = operands[3];
17719   operand4 = operands[4];
17720   operand5 = operands[5];
17721   emit_insn (gen_rtx_SET (VOIDmode,
17722   operand4,
17723   operand0));
17724   emit_insn (gen_rtx_SET (VOIDmode,
17725   gen_rtx_STRICT_LOW_PART (VOIDmode,
17726   operand5),
17727   operand2));
17728   _val = get_insns ();
17729   end_sequence ();
17730   return _val;
17731 }
17732 
17733 /* ../../gcc/gcc/config/i386/i386.md:13360 */
17734 rtx
17735 gen_call_pop (operand0, operand1, operand2, operand3)
17736      rtx operand0;
17737      rtx operand1;
17738      rtx operand2;
17739      rtx operand3;
17740 {
17741   rtx _val = 0;
17742   start_sequence ();
17743   {
17744     rtx operands[4];
17745     operands[0] = operand0;
17746     operands[1] = operand1;
17747     operands[2] = operand2;
17748     operands[3] = operand3;
17749 {
17750   ix86_expand_call (NULL, operands[0], operands[1], operands[2], operands[3]);
17751   DONE;
17752 }
17753     operand0 = operands[0];
17754     operand1 = operands[1];
17755     operand2 = operands[2];
17756     operand3 = operands[3];
17757   }
17758   emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
17759   gen_rtvec (2,
17760     gen_rtx_CALL (VOIDmode,
17761   operand0,
17762   operand1),
17763     gen_rtx_SET (VOIDmode,
17764   gen_rtx_REG (SImode,
17765   7),
17766   gen_rtx_PLUS (SImode,
17767   gen_rtx_REG (SImode,
17768   7),
17769   operand3)))));
17770   _val = get_insns ();
17771   end_sequence ();
17772   return _val;
17773 }
17774 
17775 /* ../../gcc/gcc/config/i386/i386.md:13407 */
17776 rtx
17777 gen_call (operand0, operand1, operand2)
17778      rtx operand0;
17779      rtx operand1;
17780      rtx operand2;
17781 {
17782   rtx _val = 0;
17783   start_sequence ();
17784   {
17785     rtx operands[3];
17786     operands[0] = operand0;
17787     operands[1] = operand1;
17788     operands[2] = operand2;
17789 {
17790   ix86_expand_call (NULL, operands[0], operands[1], operands[2], NULL);
17791   DONE;
17792 }
17793     operand0 = operands[0];
17794     operand1 = operands[1];
17795     operand2 = operands[2];
17796   }
17797   emit_call_insn (gen_rtx_CALL (VOIDmode,
17798   operand0,
17799   operand1));
17800   emit_insn (gen_rtx_USE (VOIDmode,
17801   operand2));
17802   _val = get_insns ();
17803   end_sequence ();
17804   return _val;
17805 }
17806 
17807 /* ../../gcc/gcc/config/i386/i386.md:13469 */
17808 rtx
17809 gen_call_value_pop (operand0, operand1, operand2, operand3, operand4)
17810      rtx operand0;
17811      rtx operand1;
17812      rtx operand2;
17813      rtx operand3;
17814      rtx operand4;
17815 {
17816   rtx _val = 0;
17817   start_sequence ();
17818   {
17819     rtx operands[5];
17820     operands[0] = operand0;
17821     operands[1] = operand1;
17822     operands[2] = operand2;
17823     operands[3] = operand3;
17824     operands[4] = operand4;
17825 {
17826   ix86_expand_call (operands[0], operands[1], operands[2],
17827         operands[3], operands[4]);
17828   DONE;
17829 }
17830     operand0 = operands[0];
17831     operand1 = operands[1];
17832     operand2 = operands[2];
17833     operand3 = operands[3];
17834     operand4 = operands[4];
17835   }
17836   emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
17837   gen_rtvec (2,
17838     gen_rtx_SET (VOIDmode,
17839   operand0,
17840   gen_rtx_CALL (VOIDmode,
17841   operand1,
17842   operand2)),
17843     gen_rtx_SET (VOIDmode,
17844   gen_rtx_REG (SImode,
17845   7),
17846   gen_rtx_PLUS (SImode,
17847   gen_rtx_REG (SImode,
17848   7),
17849   operand4)))));
17850   _val = get_insns ();
17851   end_sequence ();
17852   return _val;
17853 }
17854 
17855 /* ../../gcc/gcc/config/i386/i386.md:13483 */
17856 rtx
17857 gen_call_value (operand0, operand1, operand2, operand3)
17858      rtx operand0;
17859      rtx operand1;
17860      rtx operand2;
17861      rtx operand3;
17862 {
17863   rtx _val = 0;
17864   start_sequence ();
17865   {
17866     rtx operands[4];
17867     operands[0] = operand0;
17868     operands[1] = operand1;
17869     operands[2] = operand2;
17870     operands[3] = operand3;
17871 {
17872   ix86_expand_call (operands[0], operands[1], operands[2], operands[3], NULL);
17873   DONE;
17874 }
17875     operand0 = operands[0];
17876     operand1 = operands[1];
17877     operand2 = operands[2];
17878     operand3 = operands[3];
17879   }
17880   emit_call_insn (gen_rtx_SET (VOIDmode,
17881   operand0,
17882   gen_rtx_CALL (VOIDmode,
17883   operand1,
17884   operand2)));
17885   emit_insn (gen_rtx_USE (VOIDmode,
17886   operand3));
17887   _val = get_insns ();
17888   end_sequence ();
17889   return _val;
17890 }
17891 
17892 /* ../../gcc/gcc/config/i386/i386.md:13497 */
17893 rtx
17894 gen_untyped_call (operand0, operand1, operand2)
17895      rtx operand0;
17896      rtx operand1;
17897      rtx operand2;
17898 {
17899   rtx _val = 0;
17900   start_sequence ();
17901   {
17902     rtx operands[3];
17903     operands[0] = operand0;
17904     operands[1] = operand1;
17905     operands[2] = operand2;
17906 {
17907   int i;
17908 
17909   /* In order to give reg-stack an easier job in validating two
17910      coprocessor registers as containing a possible return value,
17911      simply pretend the untyped call returns a complex long double
17912      value.  */
17913 
17914   ix86_expand_call ((TARGET_FLOAT_RETURNS_IN_80387
17915          ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
17916         operands[0], const0_rtx, GEN_INT (SSE_REGPARM_MAX - 1),
17917         NULL);
17918 
17919   for (i = 0; i < XVECLEN (operands[2], 0); i++)
17920     {
17921       rtx set = XVECEXP (operands[2], 0, i);
17922       emit_move_insn (SET_DEST (set), SET_SRC (set));
17923     }
17924 
17925   /* The optimizer does not know that the call sets the function value
17926      registers we stored in the result block.  We avoid problems by
17927      claiming that all hard registers are used and clobbered at this
17928      point.  */
17929   emit_insn (gen_blockage (const0_rtx));
17930 
17931   DONE;
17932 }
17933     operand0 = operands[0];
17934     operand1 = operands[1];
17935     operand2 = operands[2];
17936   }
17937   emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
17938   gen_rtvec (3,
17939     gen_rtx_CALL (VOIDmode,
17940   operand0,
17941   const0_rtx),
17942     operand1,
17943     operand2)));
17944   _val = get_insns ();
17945   end_sequence ();
17946   return _val;
17947 }
17948 
17949 /* ../../gcc/gcc/config/i386/i386.md:13546 */
17950 rtx
17951 gen_return ()
17952 {
17953   rtx _val = 0;
17954   start_sequence ();
17955   {
17956 {
17957   if (current_function_pops_args)
17958     {
17959       rtx popc = GEN_INT (current_function_pops_args);
17960       emit_jump_insn (gen_return_pop_internal (popc));
17961       DONE;
17962     }
17963 }
17964   }
17965   emit_jump_insn (gen_rtx_RETURN (VOIDmode));
17966   _val = get_insns ();
17967   end_sequence ();
17968   return _val;
17969 }
17970 
17971 /* ../../gcc/gcc/config/i386/i386.md:13592 */
17972 rtx
17973 gen_prologue ()
17974 {
17975   rtx _val = 0;
17976   start_sequence ();
17977   {
17978 ix86_expand_prologue (); DONE;
17979   }
17980   emit_insn (const1_rtx);
17981   _val = get_insns ();
17982   end_sequence ();
17983   return _val;
17984 }
17985 
17986 /* ../../gcc/gcc/config/i386/i386.md:13606 */
17987 rtx
17988 gen_epilogue ()
17989 {
17990   rtx _val = 0;
17991   start_sequence ();
17992   {
17993 ix86_expand_epilogue (1); DONE;
17994   }
17995   emit_insn (const1_rtx);
17996   _val = get_insns ();
17997   end_sequence ();
17998   return _val;
17999 }
18000 
18001 /* ../../gcc/gcc/config/i386/i386.md:13611 */
18002 rtx
18003 gen_sibcall_epilogue ()
18004 {
18005   rtx _val = 0;
18006   start_sequence ();
18007   {
18008 ix86_expand_epilogue (0); DONE;
18009   }
18010   emit_insn (const1_rtx);
18011   _val = get_insns ();
18012   end_sequence ();
18013   return _val;
18014 }
18015 
18016 /* ../../gcc/gcc/config/i386/i386.md:13616 */
18017 rtx
18018 gen_eh_return (operand0)
18019      rtx operand0;
18020 {
18021   rtx _val = 0;
18022   start_sequence ();
18023   {
18024     rtx operands[1];
18025     operands[0] = operand0;
18026 {
18027   rtx tmp, sa = EH_RETURN_STACKADJ_RTX, ra = operands[0];
18028 
18029   /* Tricky bit: we write the address of the handler to which we will
18030      be returning into someone else's stack frame, one word below the
18031      stack address we wish to restore.  */
18032   tmp = gen_rtx_PLUS (Pmode, arg_pointer_rtx, sa);
18033   tmp = plus_constant (tmp, -UNITS_PER_WORD);
18034   tmp = gen_rtx_MEM (Pmode, tmp);
18035   emit_move_insn (tmp, ra);
18036 
18037   if (Pmode == SImode)
18038     emit_insn (gen_eh_return_si (sa));
18039   else
18040     emit_insn (gen_eh_return_di (sa));
18041   emit_barrier ();
18042   DONE;
18043 }
18044     operand0 = operands[0];
18045   }
18046   emit_insn (gen_rtx_USE (VOIDmode,
18047   operand0));
18048   _val = get_insns ();
18049   end_sequence ();
18050   return _val;
18051 }
18052 
18053 /* ../../gcc/gcc/config/i386/i386.md:13638 */
18054 extern rtx gen_split_1386 PARAMS ((rtx *));
18055 rtx
18056 gen_split_1386 (operands)
18057       rtx *operands ATTRIBUTE_UNUSED;
18058 {
18059   rtx _val = 0;
18060   start_sequence ();
18061 ix86_expand_epilogue (2); DONE;
18062   emit_insn (const1_rtx);
18063   _val = get_insns ();
18064   end_sequence ();
18065   return _val;
18066 }
18067 
18068 /* ../../gcc/gcc/config/i386/i386.md:13647 */
18069 extern rtx gen_split_1387 PARAMS ((rtx *));
18070 rtx
18071 gen_split_1387 (operands)
18072       rtx *operands ATTRIBUTE_UNUSED;
18073 {
18074   rtx _val = 0;
18075   start_sequence ();
18076 ix86_expand_epilogue (2); DONE;
18077   emit_insn (const1_rtx);
18078   _val = get_insns ();
18079   end_sequence ();
18080   return _val;
18081 }
18082 
18083 /* ../../gcc/gcc/config/i386/i386.md:13680 */
18084 rtx
18085 gen_ffssi2 (operand0, operand1)
18086      rtx operand0;
18087      rtx operand1;
18088 {
18089   rtx _val = 0;
18090   start_sequence ();
18091   {
18092     rtx operands[2];
18093     operands[0] = operand0;
18094     operands[1] = operand1;
18095 {
18096   rtx out = gen_reg_rtx (SImode), tmp = gen_reg_rtx (SImode);
18097   rtx in = operands[1];
18098 
18099   if (TARGET_CMOVE)
18100     {
18101       emit_move_insn (tmp, constm1_rtx);
18102       emit_insn (gen_ffssi_1 (out, in));
18103       emit_insn (gen_rtx_SET (VOIDmode, out,
18104       gen_rtx_IF_THEN_ELSE (SImode, 
18105         gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCZmode, FLAGS_REG),
18106         const0_rtx),
18107         tmp,
18108         out)));
18109       emit_insn (gen_addsi3 (out, out, const1_rtx));
18110       emit_move_insn (operands[0], out);
18111     }
18112 
18113   /* Pentium bsf instruction is extremly slow.  The following code is
18114      recommended by the Intel Optimizing Manual as a reasonable replacement:
18115            TEST    EAX,EAX
18116      JZ      SHORT BS2
18117      XOR     ECX,ECX
18118      MOV     DWORD PTR [TEMP+4],ECX
18119      SUB     ECX,EAX
18120      AND     EAX,ECX
18121      MOV     DWORD PTR [TEMP],EAX
18122      FILD    QWORD PTR [TEMP]
18123      FSTP    QWORD PTR [TEMP]
18124      WAIT    ; WAIT only needed for compatibility with
18125              ; earlier processors
18126      MOV     ECX, DWORD PTR [TEMP+4]
18127      SHR     ECX,20
18128      SUB     ECX,3FFH
18129      TEST    EAX,EAX       ; clear zero flag
18130        BS2:
18131      Following piece of code expand ffs to similar beast.
18132        */
18133 
18134   else if (TARGET_PENTIUM && !optimize_size && TARGET_80387)
18135     {
18136       rtx label = gen_label_rtx ();
18137       rtx lo, hi;
18138       rtx mem = assign_386_stack_local (DImode, 0);
18139       rtx fptmp = gen_reg_rtx (DFmode);
18140       split_di (&mem, 1, &lo, &hi);
18141 
18142       emit_move_insn (out, const0_rtx);
18143 
18144       emit_cmp_and_jump_insns (in, const0_rtx, EQ, 0, SImode, 1, label);
18145 
18146       emit_move_insn (hi, out);
18147       emit_insn (gen_subsi3 (out, out, in));
18148       emit_insn (gen_andsi3 (out, out, in));
18149       emit_move_insn (lo, out);
18150       emit_insn (gen_floatdidf2 (fptmp,mem));
18151       emit_move_insn (gen_rtx_MEM (DFmode, XEXP (mem, 0)), fptmp);
18152       emit_move_insn (out, hi);
18153       emit_insn (gen_lshrsi3 (out, out, GEN_INT (20)));
18154       emit_insn (gen_subsi3 (out, out, GEN_INT (0x3ff - 1)));
18155 
18156       emit_label (label);
18157       LABEL_NUSES (label) = 1;
18158 
18159       emit_move_insn (operands[0], out);
18160     }
18161   else
18162     {
18163       emit_move_insn (tmp, const0_rtx);
18164       emit_insn (gen_ffssi_1 (out, in));
18165       emit_insn (gen_rtx_SET (VOIDmode, 
18166       gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (QImode, tmp)),
18167       gen_rtx_EQ (QImode, gen_rtx_REG (CCZmode, FLAGS_REG),
18168             const0_rtx)));
18169       emit_insn (gen_negsi2 (tmp, tmp));
18170       emit_insn (gen_iorsi3 (out, out, tmp));
18171       emit_insn (gen_addsi3 (out, out, const1_rtx));
18172       emit_move_insn (operands[0], out);
18173     }
18174   DONE;  
18175 }
18176     operand0 = operands[0];
18177     operand1 = operands[1];
18178   }
18179   emit_insn (gen_rtx_SET (VOIDmode,
18180   operand0,
18181   gen_rtx_FFS (SImode,
18182   operand1)));
18183   _val = get_insns ();
18184   end_sequence ();
18185   return _val;
18186 }
18187 
18188 /* ../../gcc/gcc/config/i386/i386.md:13814 */
18189 rtx
18190 gen_tls_global_dynamic_32 (operand0, operand1)
18191      rtx operand0;
18192      rtx operand1;
18193 {
18194   rtx operand2;
18195   rtx operand3;
18196   rtx operand4 ATTRIBUTE_UNUSED;
18197   rtx operand5 ATTRIBUTE_UNUSED;
18198   rtx _val = 0;
18199   start_sequence ();
18200   {
18201     rtx operands[6];
18202     operands[0] = operand0;
18203     operands[1] = operand1;
18204 {
18205   if (flag_pic)
18206     operands[2] = pic_offset_table_rtx;
18207   else
18208     {
18209       operands[2] = gen_reg_rtx (Pmode);
18210       emit_insn (gen_set_got (operands[2]));
18211     }
18212   operands[3] = ix86_tls_get_addr ();
18213 }
18214     operand0 = operands[0];
18215     operand1 = operands[1];
18216     operand2 = operands[2];
18217     operand3 = operands[3];
18218     operand4 = operands[4];
18219     operand5 = operands[5];
18220   }
18221   emit (gen_rtx_PARALLEL (VOIDmode,
18222   gen_rtvec (4,
18223     gen_rtx_SET (VOIDmode,
18224   operand0,
18225   gen_rtx_UNSPEC (SImode,
18226   gen_rtvec (3,
18227     operand2,
18228     operand1,
18229     operand3),
18230   16)),
18231     gen_rtx_CLOBBER (VOIDmode,
18232   gen_rtx_SCRATCH (SImode)),
18233     gen_rtx_CLOBBER (VOIDmode,
18234   gen_rtx_SCRATCH (SImode)),
18235     gen_rtx_CLOBBER (VOIDmode,
18236   gen_rtx_REG (CCmode,
18237   17)))));
18238   _val = get_insns ();
18239   end_sequence ();
18240   return _val;
18241 }
18242 
18243 /* ../../gcc/gcc/config/i386/i386.md:13847 */
18244 rtx
18245 gen_tls_global_dynamic_64 (operand0, operand1)
18246      rtx operand0;
18247      rtx operand1;
18248 {
18249   rtx operand2;
18250   rtx _val = 0;
18251   start_sequence ();
18252   {
18253     rtx operands[3];
18254     operands[0] = operand0;
18255     operands[1] = operand1;
18256 {
18257   operands[2] = ix86_tls_get_addr ();
18258 }
18259     operand0 = operands[0];
18260     operand1 = operands[1];
18261     operand2 = operands[2];
18262   }
18263   emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
18264   gen_rtvec (2,
18265     gen_rtx_SET (VOIDmode,
18266   operand0,
18267   gen_rtx_CALL (VOIDmode,
18268   gen_rtx_MEM (QImode,
18269   operand2),
18270   const0_rtx)),
18271     gen_rtx_UNSPEC (DImode,
18272   gen_rtvec (1,
18273     operand1),
18274   16))));
18275   _val = get_insns ();
18276   end_sequence ();
18277   return _val;
18278 }
18279 
18280 /* ../../gcc/gcc/config/i386/i386.md:13884 */
18281 rtx
18282 gen_tls_local_dynamic_base_32 (operand0)
18283      rtx operand0;
18284 {
18285   rtx operand1;
18286   rtx operand2;
18287   rtx operand3 ATTRIBUTE_UNUSED;
18288   rtx operand4 ATTRIBUTE_UNUSED;
18289   rtx _val = 0;
18290   start_sequence ();
18291   {
18292     rtx operands[5];
18293     operands[0] = operand0;
18294 {
18295   if (flag_pic)
18296     operands[1] = pic_offset_table_rtx;
18297   else
18298     {
18299       operands[1] = gen_reg_rtx (Pmode);
18300       emit_insn (gen_set_got (operands[1]));
18301     }
18302   operands[2] = ix86_tls_get_addr ();
18303 }
18304     operand0 = operands[0];
18305     operand1 = operands[1];
18306     operand2 = operands[2];
18307     operand3 = operands[3];
18308     operand4 = operands[4];
18309   }
18310   emit (gen_rtx_PARALLEL (VOIDmode,
18311   gen_rtvec (4,
18312     gen_rtx_SET (VOIDmode,
18313   operand0,
18314   gen_rtx_UNSPEC (SImode,
18315   gen_rtvec (2,
18316     operand1,
18317     operand2),
18318   17)),
18319     gen_rtx_CLOBBER (VOIDmode,
18320   gen_rtx_SCRATCH (SImode)),
18321     gen_rtx_CLOBBER (VOIDmode,
18322   gen_rtx_SCRATCH (SImode)),
18323     gen_rtx_CLOBBER (VOIDmode,
18324   gen_rtx_REG (CCmode,
18325   17)))));
18326   _val = get_insns ();
18327   end_sequence ();
18328   return _val;
18329 }
18330 
18331 /* ../../gcc/gcc/config/i386/i386.md:13913 */
18332 rtx
18333 gen_tls_local_dynamic_base_64 (operand0)
18334      rtx operand0;
18335 {
18336   rtx operand1;
18337   rtx _val = 0;
18338   start_sequence ();
18339   {
18340     rtx operands[2];
18341     operands[0] = operand0;
18342 {
18343   operands[1] = ix86_tls_get_addr ();
18344 }
18345     operand0 = operands[0];
18346     operand1 = operands[1];
18347   }
18348   emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
18349   gen_rtvec (2,
18350     gen_rtx_SET (VOIDmode,
18351   operand0,
18352   gen_rtx_CALL (VOIDmode,
18353   gen_rtx_MEM (QImode,
18354   operand1),
18355   const0_rtx)),
18356     gen_rtx_UNSPEC (DImode,
18357   gen_rtvec (1,
18358     const0_rtx),
18359   17))));
18360   _val = get_insns ();
18361   end_sequence ();
18362   return _val;
18363 }
18364 
18365 /* ../../gcc/gcc/config/i386/i386.md:13925 */
18366 extern rtx gen_split_1393 PARAMS ((rtx *));
18367 rtx
18368 gen_split_1393 (operands)
18369       rtx *operands;
18370 {
18371   rtx operand0;
18372   rtx operand1;
18373   rtx operand2;
18374   rtx operand3;
18375   rtx operand4;
18376   rtx operand5;
18377   rtx _val = 0;
18378   start_sequence ();
18379 
18380   operand0 = operands[0];
18381   operand1 = operands[1];
18382   operand2 = operands[2];
18383   operand3 = operands[3];
18384   operand4 = operands[4];
18385   operand5 = operands[5];
18386   emit (gen_rtx_PARALLEL (VOIDmode,
18387   gen_rtvec (4,
18388     gen_rtx_SET (VOIDmode,
18389   operand0,
18390   gen_rtx_UNSPEC (SImode,
18391   gen_rtvec (3,
18392     operand1,
18393     operand3,
18394     operand2),
18395   16)),
18396     gen_rtx_CLOBBER (VOIDmode,
18397   operand4),
18398     gen_rtx_CLOBBER (VOIDmode,
18399   operand5),
18400     gen_rtx_CLOBBER (VOIDmode,
18401   gen_rtx_REG (CCmode,
18402   17)))));
18403   _val = get_insns ();
18404   end_sequence ();
18405   return _val;
18406 }
18407 
18408 /* ../../gcc/gcc/config/i386/i386.md:14627 */
18409 extern rtx gen_split_1394 PARAMS ((rtx *));
18410 rtx
18411 gen_split_1394 (operands)
18412       rtx *operands ATTRIBUTE_UNUSED;
18413 {
18414   rtx _val = 0;
18415   start_sequence ();
18416 { 
18417   operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
18418   operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
18419   emit_insn (gen_rtx_SET (VOIDmode, operands[0],
18420         gen_rtx_fmt_ee (GET_CODE (operands[3]),
18421             GET_MODE (operands[3]),
18422             operands[4],
18423             operands[2])));
18424   ix86_free_from_memory (GET_MODE (operands[1]));
18425   DONE;
18426 }
18427   emit_insn (const0_rtx);
18428   _val = get_insns ();
18429   end_sequence ();
18430   return _val;
18431 }
18432 
18433 /* ../../gcc/gcc/config/i386/i386.md:14647 */
18434 extern rtx gen_split_1395 PARAMS ((rtx *));
18435 rtx
18436 gen_split_1395 (operands)
18437       rtx *operands ATTRIBUTE_UNUSED;
18438 {
18439   rtx _val = 0;
18440   start_sequence ();
18441 {
18442   operands[4] = ix86_force_to_memory (GET_MODE (operands[2]), operands[2]);
18443   operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
18444   emit_insn (gen_rtx_SET (VOIDmode, operands[0],
18445         gen_rtx_fmt_ee (GET_CODE (operands[3]),
18446             GET_MODE (operands[3]),
18447             operands[1],
18448             operands[4])));
18449   ix86_free_from_memory (GET_MODE (operands[2]));
18450   DONE;
18451 }
18452   emit_insn (const0_rtx);
18453   _val = get_insns ();
18454   end_sequence ();
18455   return _val;
18456 }
18457 
18458 /* ../../gcc/gcc/config/i386/i386.md:14669 */
18459 rtx
18460 gen_sqrtsf2 (operand0, operand1)
18461      rtx operand0;
18462      rtx operand1;
18463 {
18464   rtx _val = 0;
18465   start_sequence ();
18466   {
18467     rtx operands[2];
18468     operands[0] = operand0;
18469     operands[1] = operand1;
18470 {
18471   if (!TARGET_SSE_MATH)
18472     operands[1] = force_reg (SFmode, operands[1]);
18473 }
18474     operand0 = operands[0];
18475     operand1 = operands[1];
18476   }
18477   emit_insn (gen_rtx_SET (VOIDmode,
18478   operand0,
18479   gen_rtx_SQRT (SFmode,
18480   operand1)));
18481   _val = get_insns ();
18482   end_sequence ();
18483   return _val;
18484 }
18485 
18486 /* ../../gcc/gcc/config/i386/i386.md:14709 */
18487 rtx
18488 gen_sqrtdf2 (operand0, operand1)
18489      rtx operand0;
18490      rtx operand1;
18491 {
18492   rtx _val = 0;
18493   start_sequence ();
18494   {
18495     rtx operands[2];
18496     operands[0] = operand0;
18497     operands[1] = operand1;
18498 {
18499   if (!TARGET_SSE2 || !TARGET_SSE_MATH)
18500     operands[1] = force_reg (DFmode, operands[1]);
18501 }
18502     operand0 = operands[0];
18503     operand1 = operands[1];
18504   }
18505   emit_insn (gen_rtx_SET (VOIDmode,
18506   operand0,
18507   gen_rtx_SQRT (DFmode,
18508   operand1)));
18509   _val = get_insns ();
18510   end_sequence ();
18511   return _val;
18512 }
18513 
18514 /* ../../gcc/gcc/config/i386/i386.md:14923 */
18515 rtx
18516 gen_movstrsi (operand0, operand1, operand2, operand3)
18517      rtx operand0;
18518      rtx operand1;
18519      rtx operand2;
18520      rtx operand3;
18521 {
18522   rtx _val = 0;
18523   start_sequence ();
18524   {
18525     rtx operands[4];
18526     operands[0] = operand0;
18527     operands[1] = operand1;
18528     operands[2] = operand2;
18529     operands[3] = operand3;
18530 {
18531  if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
18532    DONE;
18533  else
18534    FAIL;
18535 }
18536     operand0 = operands[0];
18537     operand1 = operands[1];
18538     operand2 = operands[2];
18539     operand3 = operands[3];
18540   }
18541   emit_insn (gen_rtx_USE (VOIDmode,
18542   operand0));
18543   emit_insn (gen_rtx_USE (VOIDmode,
18544   operand1));
18545   emit_insn (gen_rtx_USE (VOIDmode,
18546   operand2));
18547   emit_insn (gen_rtx_USE (VOIDmode,
18548   operand3));
18549   _val = get_insns ();
18550   end_sequence ();
18551   return _val;
18552 }
18553 
18554 /* ../../gcc/gcc/config/i386/i386.md:14936 */
18555 rtx
18556 gen_movstrdi (operand0, operand1, operand2, operand3)
18557      rtx operand0;
18558      rtx operand1;
18559      rtx operand2;
18560      rtx operand3;
18561 {
18562   rtx _val = 0;
18563   start_sequence ();
18564   {
18565     rtx operands[4];
18566     operands[0] = operand0;
18567     operands[1] = operand1;
18568     operands[2] = operand2;
18569     operands[3] = operand3;
18570 {
18571  if (ix86_expand_movstr (operands[0], operands[1], operands[2], operands[3]))
18572    DONE;
18573  else
18574    FAIL;
18575 }
18576     operand0 = operands[0];
18577     operand1 = operands[1];
18578     operand2 = operands[2];
18579     operand3 = operands[3];
18580   }
18581   emit_insn (gen_rtx_USE (VOIDmode,
18582   operand0));
18583   emit_insn (gen_rtx_USE (VOIDmode,
18584   operand1));
18585   emit_insn (gen_rtx_USE (VOIDmode,
18586   operand2));
18587   emit_insn (gen_rtx_USE (VOIDmode,
18588   operand3));
18589   _val = get_insns ();
18590   end_sequence ();
18591   return _val;
18592 }
18593 
18594 /* ../../gcc/gcc/config/i386/i386.md:14952 */
18595 rtx
18596 gen_strmovdi_rex64 (operand0, operand1)
18597      rtx operand0;
18598      rtx operand1;
18599 {
18600   rtx operand2;
18601   rtx _val = 0;
18602   start_sequence ();
18603   {
18604     rtx operands[3];
18605     operands[0] = operand0;
18606     operands[1] = operand1;
18607 {
18608   if (TARGET_SINGLE_STRINGOP || optimize_size)
18609     {
18610       emit_insn (gen_strmovdi_rex_1 (operands[0], operands[1], operands[0],
18611              operands[1]));
18612       DONE;
18613     }
18614   else 
18615     operands[2] = gen_reg_rtx (DImode);
18616 }
18617     operand0 = operands[0];
18618     operand1 = operands[1];
18619     operand2 = operands[2];
18620   }
18621   emit_insn (gen_rtx_SET (VOIDmode,
18622   operand2,
18623   gen_rtx_MEM (DImode,
18624   operand1)));
18625   emit_insn (gen_rtx_SET (VOIDmode,
18626   gen_rtx_MEM (DImode,
18627   operand0),
18628   operand2));
18629   emit (gen_rtx_PARALLEL (VOIDmode,
18630   gen_rtvec (2,
18631     gen_rtx_SET (VOIDmode,
18632   operand0,
18633   gen_rtx_PLUS (DImode,
18634   operand0,
18635   GEN_INT (8LL))),
18636     gen_rtx_CLOBBER (VOIDmode,
18637   gen_rtx_REG (CCmode,
18638   17)))));
18639   emit (gen_rtx_PARALLEL (VOIDmode,
18640   gen_rtvec (2,
18641     gen_rtx_SET (VOIDmode,
18642   operand1,
18643   gen_rtx_PLUS (DImode,
18644   operand1,
18645   GEN_INT (8LL))),
18646     gen_rtx_CLOBBER (VOIDmode,
18647   gen_rtx_REG (CCmode,
18648   17)))));
18649   _val = get_insns ();
18650   end_sequence ();
18651   return _val;
18652 }
18653 
18654 /* ../../gcc/gcc/config/i386/i386.md:14974 */
18655 rtx
18656 gen_strmovsi (operand0, operand1)
18657      rtx operand0;
18658      rtx operand1;
18659 {
18660   rtx operand2;
18661   rtx _val = 0;
18662   start_sequence ();
18663   {
18664     rtx operands[3];
18665     operands[0] = operand0;
18666     operands[1] = operand1;
18667 {
18668   if (TARGET_64BIT)
18669     {
18670       emit_insn (gen_strmovsi_rex64 (operands[0], operands[1]));
18671       DONE;
18672     }
18673   if (TARGET_SINGLE_STRINGOP || optimize_size)
18674     {
18675       emit_insn (gen_strmovsi_1 (operands[0], operands[1], operands[0],
18676         operands[1]));
18677       DONE;
18678     }
18679   else 
18680     operands[2] = gen_reg_rtx (SImode);
18681 }
18682     operand0 = operands[0];
18683     operand1 = operands[1];
18684     operand2 = operands[2];
18685   }
18686   emit_insn (gen_rtx_SET (VOIDmode,
18687   operand2,
18688   gen_rtx_MEM (SImode,
18689   operand1)));
18690   emit_insn (gen_rtx_SET (VOIDmode,
18691   gen_rtx_MEM (SImode,
18692   operand0),
18693   operand2));
18694   emit (gen_rtx_PARALLEL (VOIDmode,
18695   gen_rtvec (2,
18696     gen_rtx_SET (VOIDmode,
18697   operand0,
18698   gen_rtx_PLUS (SImode,
18699   operand0,
18700   GEN_INT (4LL))),
18701     gen_rtx_CLOBBER (VOIDmode,
18702   gen_rtx_REG (CCmode,
18703   17)))));
18704   emit (gen_rtx_PARALLEL (VOIDmode,
18705   gen_rtvec (2,
18706     gen_rtx_SET (VOIDmode,
18707   operand1,
18708   gen_rtx_PLUS (SImode,
18709   operand1,
18710   GEN_INT (4LL))),
18711     gen_rtx_CLOBBER (VOIDmode,
18712   gen_rtx_REG (CCmode,
18713   17)))));
18714   _val = get_insns ();
18715   end_sequence ();
18716   return _val;
18717 }
18718 
18719 /* ../../gcc/gcc/config/i386/i386.md:15000 */
18720 rtx
18721 gen_strmovsi_rex64 (operand0, operand1)
18722      rtx operand0;
18723      rtx operand1;
18724 {
18725   rtx operand2;
18726   rtx _val = 0;
18727   start_sequence ();
18728   {
18729     rtx operands[3];
18730     operands[0] = operand0;
18731     operands[1] = operand1;
18732 {
18733   if (TARGET_SINGLE_STRINGOP || optimize_size)
18734     {
18735       emit_insn (gen_strmovsi_rex_1 (operands[0], operands[1], operands[0],
18736              operands[1]));
18737       DONE;
18738     }
18739   else 
18740     operands[2] = gen_reg_rtx (SImode);
18741 }
18742     operand0 = operands[0];
18743     operand1 = operands[1];
18744     operand2 = operands[2];
18745   }
18746   emit_insn (gen_rtx_SET (VOIDmode,
18747   operand2,
18748   gen_rtx_MEM (SImode,
18749   operand1)));
18750   emit_insn (gen_rtx_SET (VOIDmode,
18751   gen_rtx_MEM (SImode,
18752   operand0),
18753   operand2));
18754   emit (gen_rtx_PARALLEL (VOIDmode,
18755   gen_rtvec (2,
18756     gen_rtx_SET (VOIDmode,
18757   operand0,
18758   gen_rtx_PLUS (DImode,
18759   operand0,
18760   GEN_INT (4LL))),
18761     gen_rtx_CLOBBER (VOIDmode,
18762   gen_rtx_REG (CCmode,
18763   17)))));
18764   emit (gen_rtx_PARALLEL (VOIDmode,
18765   gen_rtvec (2,
18766     gen_rtx_SET (VOIDmode,
18767   operand1,
18768   gen_rtx_PLUS (DImode,
18769   operand1,
18770   GEN_INT (4LL))),
18771     gen_rtx_CLOBBER (VOIDmode,
18772   gen_rtx_REG (CCmode,
18773   17)))));
18774   _val = get_insns ();
18775   end_sequence ();
18776   return _val;
18777 }
18778 
18779 /* ../../gcc/gcc/config/i386/i386.md:15021 */
18780 rtx
18781 gen_strmovhi (operand0, operand1)
18782      rtx operand0;
18783      rtx operand1;
18784 {
18785   rtx operand2;
18786   rtx _val = 0;
18787   start_sequence ();
18788   {
18789     rtx operands[3];
18790     operands[0] = operand0;
18791     operands[1] = operand1;
18792 {
18793   if (TARGET_64BIT)
18794     {
18795       emit_insn (gen_strmovhi_rex64 (operands[0], operands[1]));
18796       DONE;
18797     }
18798   if (TARGET_SINGLE_STRINGOP || optimize_size)
18799     {
18800       emit_insn (gen_strmovhi_1 (operands[0], operands[1], operands[0],
18801         operands[1]));
18802       DONE;
18803     }
18804   else 
18805     operands[2] = gen_reg_rtx (HImode);
18806 }
18807     operand0 = operands[0];
18808     operand1 = operands[1];
18809     operand2 = operands[2];
18810   }
18811   emit_insn (gen_rtx_SET (VOIDmode,
18812   operand2,
18813   gen_rtx_MEM (HImode,
18814   operand1)));
18815   emit_insn (gen_rtx_SET (VOIDmode,
18816   gen_rtx_MEM (HImode,
18817   operand0),
18818   operand2));
18819   emit (gen_rtx_PARALLEL (VOIDmode,
18820   gen_rtvec (2,
18821     gen_rtx_SET (VOIDmode,
18822   operand0,
18823   gen_rtx_PLUS (SImode,
18824   operand0,
18825   GEN_INT (2LL))),
18826     gen_rtx_CLOBBER (VOIDmode,
18827   gen_rtx_REG (CCmode,
18828   17)))));
18829   emit (gen_rtx_PARALLEL (VOIDmode,
18830   gen_rtvec (2,
18831     gen_rtx_SET (VOIDmode,
18832   operand1,
18833   gen_rtx_PLUS (SImode,
18834   operand1,
18835   GEN_INT (2LL))),
18836     gen_rtx_CLOBBER (VOIDmode,
18837   gen_rtx_REG (CCmode,
18838   17)))));
18839   _val = get_insns ();
18840   end_sequence ();
18841   return _val;
18842 }
18843 
18844 /* ../../gcc/gcc/config/i386/i386.md:15047 */
18845 rtx
18846 gen_strmovhi_rex64 (operand0, operand1)
18847      rtx operand0;
18848      rtx operand1;
18849 {
18850   rtx operand2;
18851   rtx _val = 0;
18852   start_sequence ();
18853   {
18854     rtx operands[3];
18855     operands[0] = operand0;
18856     operands[1] = operand1;
18857 {
18858   if (TARGET_SINGLE_STRINGOP || optimize_size)
18859     {
18860       emit_insn (gen_strmovhi_rex_1 (operands[0], operands[1], operands[0],
18861              operands[1]));
18862       DONE;
18863     }
18864   else 
18865     operands[2] = gen_reg_rtx (HImode);
18866 }
18867     operand0 = operands[0];
18868     operand1 = operands[1];
18869     operand2 = operands[2];
18870   }
18871   emit_insn (gen_rtx_SET (VOIDmode,
18872   operand2,
18873   gen_rtx_MEM (HImode,
18874   operand1)));
18875   emit_insn (gen_rtx_SET (VOIDmode,
18876   gen_rtx_MEM (HImode,
18877   operand0),
18878   operand2));
18879   emit (gen_rtx_PARALLEL (VOIDmode,
18880   gen_rtvec (2,
18881     gen_rtx_SET (VOIDmode,
18882   operand0,
18883   gen_rtx_PLUS (DImode,
18884   operand0,
18885   GEN_INT (2LL))),
18886     gen_rtx_CLOBBER (VOIDmode,
18887   gen_rtx_REG (CCmode,
18888   17)))));
18889   emit (gen_rtx_PARALLEL (VOIDmode,
18890   gen_rtvec (2,
18891     gen_rtx_SET (VOIDmode,
18892   operand1,
18893   gen_rtx_PLUS (DImode,
18894   operand1,
18895   GEN_INT (2LL))),
18896     gen_rtx_CLOBBER (VOIDmode,
18897   gen_rtx_REG (CCmode,
18898   17)))));
18899   _val = get_insns ();
18900   end_sequence ();
18901   return _val;
18902 }
18903 
18904 /* ../../gcc/gcc/config/i386/i386.md:15068 */
18905 rtx
18906 gen_strmovqi (operand0, operand1)
18907      rtx operand0;
18908      rtx operand1;
18909 {
18910   rtx operand2;
18911   rtx _val = 0;
18912   start_sequence ();
18913   {
18914     rtx operands[3];
18915     operands[0] = operand0;
18916     operands[1] = operand1;
18917 {
18918   if (TARGET_64BIT)
18919     {
18920       emit_insn (gen_strmovqi_rex64 (operands[0], operands[1]));
18921       DONE;
18922     }
18923   if (TARGET_SINGLE_STRINGOP || optimize_size)
18924     {
18925       emit_insn (gen_strmovqi_1 (operands[0], operands[1], operands[0],
18926         operands[1]));
18927       DONE;
18928     }
18929   else 
18930     operands[2] = gen_reg_rtx (QImode);
18931 }
18932     operand0 = operands[0];
18933     operand1 = operands[1];
18934     operand2 = operands[2];
18935   }
18936   emit_insn (gen_rtx_SET (VOIDmode,
18937   operand2,
18938   gen_rtx_MEM (QImode,
18939   operand1)));
18940   emit_insn (gen_rtx_SET (VOIDmode,
18941   gen_rtx_MEM (QImode,
18942   operand0),
18943   operand2));
18944   emit (gen_rtx_PARALLEL (VOIDmode,
18945   gen_rtvec (2,
18946     gen_rtx_SET (VOIDmode,
18947   operand0,
18948   gen_rtx_PLUS (SImode,
18949   operand0,
18950   const1_rtx)),
18951     gen_rtx_CLOBBER (VOIDmode,
18952   gen_rtx_REG (CCmode,
18953   17)))));
18954   emit (gen_rtx_PARALLEL (VOIDmode,
18955   gen_rtvec (2,
18956     gen_rtx_SET (VOIDmode,
18957   operand1,
18958   gen_rtx_PLUS (SImode,
18959   operand1,
18960   const1_rtx)),
18961     gen_rtx_CLOBBER (VOIDmode,
18962   gen_rtx_REG (CCmode,
18963   17)))));
18964   _val = get_insns ();
18965   end_sequence ();
18966   return _val;
18967 }
18968 
18969 /* ../../gcc/gcc/config/i386/i386.md:15094 */
18970 rtx
18971 gen_strmovqi_rex64 (operand0, operand1)
18972      rtx operand0;
18973      rtx operand1;
18974 {
18975   rtx operand2;
18976   rtx _val = 0;
18977   start_sequence ();
18978   {
18979     rtx operands[3];
18980     operands[0] = operand0;
18981     operands[1] = operand1;
18982 {
18983   if (TARGET_SINGLE_STRINGOP || optimize_size)
18984     {
18985       emit_insn (gen_strmovqi_rex_1 (operands[0], operands[1], operands[0],
18986              operands[1]));
18987       DONE;
18988     }
18989   else 
18990     operands[2] = gen_reg_rtx (QImode);
18991 }
18992     operand0 = operands[0];
18993     operand1 = operands[1];
18994     operand2 = operands[2];
18995   }
18996   emit_insn (gen_rtx_SET (VOIDmode,
18997   operand2,
18998   gen_rtx_MEM (QImode,
18999   operand1)));
19000   emit_insn (gen_rtx_SET (VOIDmode,
19001   gen_rtx_MEM (QImode,
19002   operand0),
19003   operand2));
19004   emit (gen_rtx_PARALLEL (VOIDmode,
19005   gen_rtvec (2,
19006     gen_rtx_SET (VOIDmode,
19007   operand0,
19008   gen_rtx_PLUS (DImode,
19009   operand0,
19010   const1_rtx)),
19011     gen_rtx_CLOBBER (VOIDmode,
19012   gen_rtx_REG (CCmode,
19013   17)))));
19014   emit (gen_rtx_PARALLEL (VOIDmode,
19015   gen_rtvec (2,
19016     gen_rtx_SET (VOIDmode,
19017   operand1,
19018   gen_rtx_PLUS (DImode,
19019   operand1,
19020   const1_rtx)),
19021     gen_rtx_CLOBBER (VOIDmode,
19022   gen_rtx_REG (CCmode,
19023   17)))));
19024   _val = get_insns ();
19025   end_sequence ();
19026   return _val;
19027 }
19028 
19029 /* ../../gcc/gcc/config/i386/i386.md:15323 */
19030 rtx
19031 gen_clrstrsi (operand0, operand1, operand2)
19032      rtx operand0;
19033      rtx operand1;
19034      rtx operand2;
19035 {
19036   rtx _val = 0;
19037   start_sequence ();
19038   {
19039     rtx operands[3];
19040     operands[0] = operand0;
19041     operands[1] = operand1;
19042     operands[2] = operand2;
19043 {
19044  if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
19045    DONE;
19046  else
19047    FAIL;
19048 }
19049     operand0 = operands[0];
19050     operand1 = operands[1];
19051     operand2 = operands[2];
19052   }
19053   emit_insn (gen_rtx_USE (VOIDmode,
19054   operand0));
19055   emit_insn (gen_rtx_USE (VOIDmode,
19056   operand1));
19057   emit_insn (gen_rtx_USE (VOIDmode,
19058   operand2));
19059   _val = get_insns ();
19060   end_sequence ();
19061   return _val;
19062 }
19063 
19064 /* ../../gcc/gcc/config/i386/i386.md:15335 */
19065 rtx
19066 gen_clrstrdi (operand0, operand1, operand2)
19067      rtx operand0;
19068      rtx operand1;
19069      rtx operand2;
19070 {
19071   rtx _val = 0;
19072   start_sequence ();
19073   {
19074     rtx operands[3];
19075     operands[0] = operand0;
19076     operands[1] = operand1;
19077     operands[2] = operand2;
19078 {
19079  if (ix86_expand_clrstr (operands[0], operands[1], operands[2]))
19080    DONE;
19081  else
19082    FAIL;
19083 }
19084     operand0 = operands[0];
19085     operand1 = operands[1];
19086     operand2 = operands[2];
19087   }
19088   emit_insn (gen_rtx_USE (VOIDmode,
19089   operand0));
19090   emit_insn (gen_rtx_USE (VOIDmode,
19091   operand1));
19092   emit_insn (gen_rtx_USE (VOIDmode,
19093   operand2));
19094   _val = get_insns ();
19095   end_sequence ();
19096   return _val;
19097 }
19098 
19099 /* ../../gcc/gcc/config/i386/i386.md:15350 */
19100 rtx
19101 gen_strsetdi_rex64 (operand0, operand1)
19102      rtx operand0;
19103      rtx operand1;
19104 {
19105   rtx _val = 0;
19106   start_sequence ();
19107   {
19108     rtx operands[2];
19109     operands[0] = operand0;
19110     operands[1] = operand1;
19111 {
19112   if (TARGET_SINGLE_STRINGOP || optimize_size)
19113     {
19114       emit_insn (gen_strsetdi_rex_1 (operands[0], operands[0], operands[1]));
19115       DONE;
19116     }
19117 }
19118     operand0 = operands[0];
19119     operand1 = operands[1];
19120   }
19121   emit_insn (gen_rtx_SET (VOIDmode,
19122   gen_rtx_MEM (DImode,
19123   operand0),
19124   operand1));
19125   emit (gen_rtx_PARALLEL (VOIDmode,
19126   gen_rtvec (2,
19127     gen_rtx_SET (VOIDmode,
19128   operand0,
19129   gen_rtx_PLUS (DImode,
19130   operand0,
19131   GEN_INT (8LL))),
19132     gen_rtx_CLOBBER (VOIDmode,
19133   gen_rtx_REG (CCmode,
19134   17)))));
19135   _val = get_insns ();
19136   end_sequence ();
19137   return _val;
19138 }
19139 
19140 /* ../../gcc/gcc/config/i386/i386.md:15364 */
19141 rtx
19142 gen_strsetsi (operand0, operand1)
19143      rtx operand0;
19144      rtx operand1;
19145 {
19146   rtx _val = 0;
19147   start_sequence ();
19148   {
19149     rtx operands[2];
19150     operands[0] = operand0;
19151     operands[1] = operand1;
19152 {
19153   if (TARGET_64BIT)
19154     {
19155       emit_insn (gen_strsetsi_rex64 (operands[0], operands[1]));
19156       DONE;
19157     }
19158   else if (TARGET_SINGLE_STRINGOP || optimize_size)
19159     {
19160       emit_insn (gen_strsetsi_1 (operands[0], operands[0], operands[1]));
19161       DONE;
19162     }
19163 }
19164     operand0 = operands[0];
19165     operand1 = operands[1];
19166   }
19167   emit_insn (gen_rtx_SET (VOIDmode,
19168   gen_rtx_MEM (SImode,
19169   operand0),
19170   operand1));
19171   emit (gen_rtx_PARALLEL (VOIDmode,
19172   gen_rtvec (2,
19173     gen_rtx_SET (VOIDmode,
19174   operand0,
19175   gen_rtx_PLUS (SImode,
19176   operand0,
19177   GEN_INT (4LL))),
19178     gen_rtx_CLOBBER (VOIDmode,
19179   gen_rtx_REG (CCmode,
19180   17)))));
19181   _val = get_insns ();
19182   end_sequence ();
19183   return _val;
19184 }
19185 
19186 /* ../../gcc/gcc/config/i386/i386.md:15383 */
19187 rtx
19188 gen_strsetsi_rex64 (operand0, operand1)
19189      rtx operand0;
19190      rtx operand1;
19191 {
19192   rtx _val = 0;
19193   start_sequence ();
19194   {
19195     rtx operands[2];
19196     operands[0] = operand0;
19197     operands[1] = operand1;
19198 {
19199   if (TARGET_SINGLE_STRINGOP || optimize_size)
19200     {
19201       emit_insn (gen_strsetsi_rex_1 (operands[0], operands[0], operands[1]));
19202       DONE;
19203     }
19204 }
19205     operand0 = operands[0];
19206     operand1 = operands[1];
19207   }
19208   emit_insn (gen_rtx_SET (VOIDmode,
19209   gen_rtx_MEM (SImode,
19210   operand0),
19211   operand1));
19212   emit (gen_rtx_PARALLEL (VOIDmode,
19213   gen_rtvec (2,
19214     gen_rtx_SET (VOIDmode,
19215   operand0,
19216   gen_rtx_PLUS (DImode,
19217   operand0,
19218   GEN_INT (4LL))),
19219     gen_rtx_CLOBBER (VOIDmode,
19220   gen_rtx_REG (CCmode,
19221   17)))));
19222   _val = get_insns ();
19223   end_sequence ();
19224   return _val;
19225 }
19226 
19227 /* ../../gcc/gcc/config/i386/i386.md:15397 */
19228 rtx
19229 gen_strsethi (operand0, operand1)
19230      rtx operand0;
19231      rtx operand1;
19232 {
19233   rtx _val = 0;
19234   start_sequence ();
19235   {
19236     rtx operands[2];
19237     operands[0] = operand0;
19238     operands[1] = operand1;
19239 {
19240   if (TARGET_64BIT)
19241     {
19242       emit_insn (gen_strsethi_rex64 (operands[0], operands[1]));
19243       DONE;
19244     }
19245   else if (TARGET_SINGLE_STRINGOP || optimize_size)
19246     {
19247       emit_insn (gen_strsethi_1 (operands[0], operands[0], operands[1]));
19248       DONE;
19249     }
19250 }
19251     operand0 = operands[0];
19252     operand1 = operands[1];
19253   }
19254   emit_insn (gen_rtx_SET (VOIDmode,
19255   gen_rtx_MEM (HImode,
19256   operand0),
19257   operand1));
19258   emit (gen_rtx_PARALLEL (VOIDmode,
19259   gen_rtvec (2,
19260     gen_rtx_SET (VOIDmode,
19261   operand0,
19262   gen_rtx_PLUS (SImode,
19263   operand0,
19264   GEN_INT (2LL))),
19265     gen_rtx_CLOBBER (VOIDmode,
19266   gen_rtx_REG (CCmode,
19267   17)))));
19268   _val = get_insns ();
19269   end_sequence ();
19270   return _val;
19271 }
19272 
19273 /* ../../gcc/gcc/config/i386/i386.md:15416 */
19274 rtx
19275 gen_strsethi_rex64 (operand0, operand1)
19276      rtx operand0;
19277      rtx operand1;
19278 {
19279   rtx _val = 0;
19280   start_sequence ();
19281   {
19282     rtx operands[2];
19283     operands[0] = operand0;
19284     operands[1] = operand1;
19285 {
19286   if (TARGET_SINGLE_STRINGOP || optimize_size)
19287     {
19288       emit_insn (gen_strsethi_rex_1 (operands[0], operands[0], operands[1]));
19289       DONE;
19290     }
19291 }
19292     operand0 = operands[0];
19293     operand1 = operands[1];
19294   }
19295   emit_insn (gen_rtx_SET (VOIDmode,
19296   gen_rtx_MEM (HImode,
19297   operand0),
19298   operand1));
19299   emit (gen_rtx_PARALLEL (VOIDmode,
19300   gen_rtvec (2,
19301     gen_rtx_SET (VOIDmode,
19302   operand0,
19303   gen_rtx_PLUS (DImode,
19304   operand0,
19305   GEN_INT (2LL))),
19306     gen_rtx_CLOBBER (VOIDmode,
19307   gen_rtx_REG (CCmode,
19308   17)))));
19309   _val = get_insns ();
19310   end_sequence ();
19311   return _val;
19312 }
19313 
19314 /* ../../gcc/gcc/config/i386/i386.md:15430 */
19315 rtx
19316 gen_strsetqi (operand0, operand1)
19317      rtx operand0;
19318      rtx operand1;
19319 {
19320   rtx _val = 0;
19321   start_sequence ();
19322   {
19323     rtx operands[2];
19324     operands[0] = operand0;
19325     operands[1] = operand1;
19326 {
19327   if (TARGET_64BIT)
19328     {
19329       emit_insn (gen_strsetqi_rex64 (operands[0], operands[1]));
19330       DONE;
19331     }
19332   else if (TARGET_SINGLE_STRINGOP || optimize_size)
19333     {
19334       emit_insn (gen_strsetqi_1 (operands[0], operands[0], operands[1]));
19335       DONE;
19336     }
19337 }
19338     operand0 = operands[0];
19339     operand1 = operands[1];
19340   }
19341   emit_insn (gen_rtx_SET (VOIDmode,
19342   gen_rtx_MEM (QImode,
19343   operand0),
19344   operand1));
19345   emit (gen_rtx_PARALLEL (VOIDmode,
19346   gen_rtvec (2,
19347     gen_rtx_SET (VOIDmode,
19348   operand0,
19349   gen_rtx_PLUS (SImode,
19350   operand0,
19351   const1_rtx)),
19352     gen_rtx_CLOBBER (VOIDmode,
19353   gen_rtx_REG (CCmode,
19354   17)))));
19355   _val = get_insns ();
19356   end_sequence ();
19357   return _val;
19358 }
19359 
19360 /* ../../gcc/gcc/config/i386/i386.md:15449 */
19361 rtx
19362 gen_strsetqi_rex64 (operand0, operand1)
19363      rtx operand0;
19364      rtx operand1;
19365 {
19366   rtx _val = 0;
19367   start_sequence ();
19368   {
19369     rtx operands[2];
19370     operands[0] = operand0;
19371     operands[1] = operand1;
19372 {
19373   if (TARGET_SINGLE_STRINGOP || optimize_size)
19374     {
19375       emit_insn (gen_strsetqi_rex_1 (operands[0], operands[0], operands[1]));
19376       DONE;
19377     }
19378 }
19379     operand0 = operands[0];
19380     operand1 = operands[1];
19381   }
19382   emit_insn (gen_rtx_SET (VOIDmode,
19383   gen_rtx_MEM (QImode,
19384   operand0),
19385   operand1));
19386   emit (gen_rtx_PARALLEL (VOIDmode,
19387   gen_rtvec (2,
19388     gen_rtx_SET (VOIDmode,
19389   operand0,
19390   gen_rtx_PLUS (DImode,
19391   operand0,
19392   const1_rtx)),
19393     gen_rtx_CLOBBER (VOIDmode,
19394   gen_rtx_REG (CCmode,
19395   17)))));
19396   _val = get_insns ();
19397   end_sequence ();
19398   return _val;
19399 }
19400 
19401 /* ../../gcc/gcc/config/i386/i386.md:15642 */
19402 rtx
19403 gen_cmpstrsi (operand0, operand1, operand2, operand3, operand4)
19404      rtx operand0;
19405      rtx operand1;
19406      rtx operand2;
19407      rtx operand3;
19408      rtx operand4;
19409 {
19410   rtx _val = 0;
19411   start_sequence ();
19412   {
19413     rtx operands[5];
19414     operands[0] = operand0;
19415     operands[1] = operand1;
19416     operands[2] = operand2;
19417     operands[3] = operand3;
19418     operands[4] = operand4;
19419 {
19420   rtx addr1, addr2, out, outlow, count, countreg, align;
19421 
19422   out = operands[0];
19423   if (GET_CODE (out) != REG)
19424     out = gen_reg_rtx (SImode);
19425 
19426   addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
19427   addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0));
19428   
19429   count = operands[3];
19430   countreg = ix86_zero_extend_to_Pmode (count);
19431 
19432   /* %%% Iff we are testing strict equality, we can use known alignment
19433      to good advantage.  This may be possible with combine, particularly
19434      once cc0 is dead.  */
19435   align = operands[4];
19436 
19437   emit_insn (gen_cld ());
19438   if (GET_CODE (count) == CONST_INT)
19439     {
19440       if (INTVAL (count) == 0)
19441   {
19442     emit_move_insn (operands[0], const0_rtx);
19443     DONE;
19444   }
19445       if (TARGET_64BIT)
19446   emit_insn (gen_cmpstrqi_nz_rex_1 (addr1, addr2, countreg, align,
19447             addr1, addr2, countreg));
19448       else
19449   emit_insn (gen_cmpstrqi_nz_1 (addr1, addr2, countreg, align,
19450               addr1, addr2, countreg));
19451     }
19452   else
19453     {
19454       if (TARGET_64BIT)
19455   {
19456     emit_insn (gen_cmpdi_1_rex64 (countreg, countreg));
19457     emit_insn (gen_cmpstrqi_rex_1 (addr1, addr2, countreg, align,
19458            addr1, addr2, countreg));
19459   }
19460       else
19461   {
19462     emit_insn (gen_cmpsi_1 (countreg, countreg));
19463     emit_insn (gen_cmpstrqi_1 (addr1, addr2, countreg, align,
19464              addr1, addr2, countreg));
19465   }
19466     }
19467 
19468   outlow = gen_lowpart (QImode, out);
19469   emit_insn (gen_cmpintqi (outlow));
19470   emit_move_insn (out, gen_rtx_SIGN_EXTEND (SImode, outlow));
19471 
19472   if (operands[0] != out)
19473     emit_move_insn (operands[0], out);
19474 
19475   DONE;
19476 }
19477     operand0 = operands[0];
19478     operand1 = operands[1];
19479     operand2 = operands[2];
19480     operand3 = operands[3];
19481     operand4 = operands[4];
19482   }
19483   emit_insn (gen_rtx_SET (VOIDmode,
19484   operand0,
19485   gen_rtx_COMPARE (SImode,
19486   operand1,
19487   operand2)));
19488   emit_insn (gen_rtx_USE (VOIDmode,
19489   operand3));
19490   emit_insn (gen_rtx_USE (VOIDmode,
19491   operand4));
19492   _val = get_insns ();
19493   end_sequence ();
19494   return _val;
19495 }
19496 
19497 /* ../../gcc/gcc/config/i386/i386.md:15710 */
19498 rtx
19499 gen_cmpintqi (operand0)
19500      rtx operand0;
19501 {
19502   rtx operand1;
19503   rtx operand2;
19504   rtx _val = 0;
19505   start_sequence ();
19506   {
19507     rtx operands[3];
19508     operands[0] = operand0;
19509 operands[1] = gen_reg_rtx (QImode);
19510    operands[2] = gen_reg_rtx (QImode);
19511     operand0 = operands[0];
19512     operand1 = operands[1];
19513     operand2 = operands[2];
19514   }
19515   emit_insn (gen_rtx_SET (VOIDmode,
19516   operand1,
19517   gen_rtx_GTU (QImode,
19518   gen_rtx_REG (CCmode,
19519   17),
19520   const0_rtx)));
19521   emit_insn (gen_rtx_SET (VOIDmode,
19522   operand2,
19523   gen_rtx_LTU (QImode,
19524   gen_rtx_REG (CCmode,
19525   17),
19526   const0_rtx)));
19527   emit (gen_rtx_PARALLEL (VOIDmode,
19528   gen_rtvec (2,
19529     gen_rtx_SET (VOIDmode,
19530   operand0,
19531   gen_rtx_MINUS (QImode,
19532   operand1,
19533   operand2)),
19534     gen_rtx_CLOBBER (VOIDmode,
19535   gen_rtx_REG (CCmode,
19536   17)))));
19537   _val = get_insns ();
19538   end_sequence ();
19539   return _val;
19540 }
19541 
19542 /* ../../gcc/gcc/config/i386/i386.md:15798 */
19543 rtx
19544 gen_strlensi (operand0, operand1, operand2, operand3)
19545      rtx operand0;
19546      rtx operand1;
19547      rtx operand2;
19548      rtx operand3;
19549 {
19550   rtx _val = 0;
19551   start_sequence ();
19552   {
19553     rtx operands[4];
19554     operands[0] = operand0;
19555     operands[1] = operand1;
19556     operands[2] = operand2;
19557     operands[3] = operand3;
19558 {
19559  if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
19560    DONE;
19561  else
19562    FAIL;
19563 }
19564     operand0 = operands[0];
19565     operand1 = operands[1];
19566     operand2 = operands[2];
19567     operand3 = operands[3];
19568   }
19569   emit_insn (gen_rtx_SET (VOIDmode,
19570   operand0,
19571   gen_rtx_UNSPEC (SImode,
19572   gen_rtvec (3,
19573     operand1,
19574     operand2,
19575     operand3),
19576   20)));
19577   _val = get_insns ();
19578   end_sequence ();
19579   return _val;
19580 }
19581 
19582 /* ../../gcc/gcc/config/i386/i386.md:15811 */
19583 rtx
19584 gen_strlendi (operand0, operand1, operand2, operand3)
19585      rtx operand0;
19586      rtx operand1;
19587      rtx operand2;
19588      rtx operand3;
19589 {
19590   rtx _val = 0;
19591   start_sequence ();
19592   {
19593     rtx operands[4];
19594     operands[0] = operand0;
19595     operands[1] = operand1;
19596     operands[2] = operand2;
19597     operands[3] = operand3;
19598 {
19599  if (ix86_expand_strlen (operands[0], operands[1], operands[2], operands[3]))
19600    DONE;
19601  else
19602    FAIL;
19603 }
19604     operand0 = operands[0];
19605     operand1 = operands[1];
19606     operand2 = operands[2];
19607     operand3 = operands[3];
19608   }
19609   emit_insn (gen_rtx_SET (VOIDmode,
19610   operand0,
19611   gen_rtx_UNSPEC (DImode,
19612   gen_rtvec (3,
19613     operand1,
19614     operand2,
19615     operand3),
19616   20)));
19617   _val = get_insns ();
19618   end_sequence ();
19619   return _val;
19620 }
19621 
19622 /* ../../gcc/gcc/config/i386/i386.md:15868 */
19623 extern rtx gen_peephole2_1420 PARAMS ((rtx, rtx *));
19624 rtx
19625 gen_peephole2_1420 (curr_insn, operands)
19626      rtx curr_insn ATTRIBUTE_UNUSED;
19627      rtx *operands;
19628 {
19629   rtx operand0;
19630   rtx operand1;
19631   rtx operand2;
19632   rtx operand3;
19633   rtx operand4;
19634   rtx operand5;
19635   rtx operand6;
19636   rtx _val = 0;
19637   HARD_REG_SET _regs_allocated;
19638   CLEAR_HARD_REG_SET (_regs_allocated);
19639   start_sequence ();
19640 
19641   operand0 = operands[0];
19642   operand1 = operands[1];
19643   operand2 = operands[2];
19644   operand3 = operands[3];
19645   operand4 = operands[4];
19646   operand5 = operands[5];
19647   operand6 = operands[6];
19648   emit (gen_rtx_PARALLEL (VOIDmode,
19649   gen_rtvec (7,
19650     gen_rtx_SET (VOIDmode,
19651   gen_rtx_REG (CCmode,
19652   17),
19653   gen_rtx_COMPARE (CCmode,
19654   gen_rtx_MEM (BLKmode,
19655   operand4),
19656   gen_rtx_MEM (BLKmode,
19657   operand5))),
19658     gen_rtx_USE (VOIDmode,
19659   operand6),
19660     gen_rtx_USE (VOIDmode,
19661   operand3),
19662     gen_rtx_USE (VOIDmode,
19663   gen_rtx_REG (SImode,
19664   19)),
19665     gen_rtx_CLOBBER (VOIDmode,
19666   operand0),
19667     gen_rtx_CLOBBER (VOIDmode,
19668   operand1),
19669     gen_rtx_CLOBBER (VOIDmode,
19670   operand2))));
19671   _val = get_insns ();
19672   end_sequence ();
19673   return _val;
19674 }
19675 
19676 /* ../../gcc/gcc/config/i386/i386.md:15900 */
19677 extern rtx gen_peephole2_1421 PARAMS ((rtx, rtx *));
19678 rtx
19679 gen_peephole2_1421 (curr_insn, operands)
19680      rtx curr_insn ATTRIBUTE_UNUSED;
19681      rtx *operands;
19682 {
19683   rtx operand0;
19684   rtx operand1;
19685   rtx operand2;
19686   rtx operand3;
19687   rtx operand4;
19688   rtx operand5;
19689   rtx operand6;
19690   rtx _val = 0;
19691   HARD_REG_SET _regs_allocated;
19692   CLEAR_HARD_REG_SET (_regs_allocated);
19693   start_sequence ();
19694 
19695   operand0 = operands[0];
19696   operand1 = operands[1];
19697   operand2 = operands[2];
19698   operand3 = operands[3];
19699   operand4 = operands[4];
19700   operand5 = operands[5];
19701   operand6 = operands[6];
19702   emit (gen_rtx_PARALLEL (VOIDmode,
19703   gen_rtvec (7,
19704     gen_rtx_SET (VOIDmode,
19705   gen_rtx_REG (CCmode,
19706   17),
19707   gen_rtx_IF_THEN_ELSE (CCmode,
19708   gen_rtx_NE (VOIDmode,
19709   operand6,
19710   const0_rtx),
19711   gen_rtx_COMPARE (CCmode,
19712   gen_rtx_MEM (BLKmode,
19713   operand4),
19714   gen_rtx_MEM (BLKmode,
19715   operand5)),
19716   const0_rtx)),
19717     gen_rtx_USE (VOIDmode,
19718   operand3),
19719     gen_rtx_USE (VOIDmode,
19720   gen_rtx_REG (CCmode,
19721   17)),
19722     gen_rtx_USE (VOIDmode,
19723   gen_rtx_REG (SImode,
19724   19)),
19725     gen_rtx_CLOBBER (VOIDmode,
19726   operand0),
19727     gen_rtx_CLOBBER (VOIDmode,
19728   operand1),
19729     gen_rtx_CLOBBER (VOIDmode,
19730   operand2))));
19731   _val = get_insns ();
19732   end_sequence ();
19733   return _val;
19734 }
19735 
19736 /* ../../gcc/gcc/config/i386/i386.md:15941 */
19737 rtx
19738 gen_movdicc (operand0, operand1, operand2, operand3)
19739      rtx operand0;
19740      rtx operand1;
19741      rtx operand2;
19742      rtx operand3;
19743 {
19744   rtx _val = 0;
19745   start_sequence ();
19746   {
19747     rtx operands[4];
19748     operands[0] = operand0;
19749     operands[1] = operand1;
19750     operands[2] = operand2;
19751     operands[3] = operand3;
19752 if (!ix86_expand_int_movcc (operands)) FAIL; DONE;
19753     operand0 = operands[0];
19754     operand1 = operands[1];
19755     operand2 = operands[2];
19756     operand3 = operands[3];
19757   }
19758   emit_insn (gen_rtx_SET (VOIDmode,
19759   operand0,
19760   gen_rtx_IF_THEN_ELSE (DImode,
19761   operand1,
19762   operand2,
19763   operand3)));
19764   _val = get_insns ();
19765   end_sequence ();
19766   return _val;
19767 }
19768 
19769 /* ../../gcc/gcc/config/i386/i386.md:15980 */
19770 rtx
19771 gen_movsicc (operand0, operand1, operand2, operand3)
19772      rtx operand0;
19773      rtx operand1;
19774      rtx operand2;
19775      rtx operand3;
19776 {
19777   rtx _val = 0;
19778   start_sequence ();
19779   {
19780     rtx operands[4];
19781     operands[0] = operand0;
19782     operands[1] = operand1;
19783     operands[2] = operand2;
19784     operands[3] = operand3;
19785 if (!ix86_expand_int_movcc (operands)) FAIL; DONE;
19786     operand0 = operands[0];
19787     operand1 = operands[1];
19788     operand2 = operands[2];
19789     operand3 = operands[3];
19790   }
19791   emit_insn (gen_rtx_SET (VOIDmode,
19792   operand0,
19793   gen_rtx_IF_THEN_ELSE (SImode,
19794   operand1,
19795   operand2,
19796   operand3)));
19797   _val = get_insns ();
19798   end_sequence ();
19799   return _val;
19800 }
19801 
19802 /* ../../gcc/gcc/config/i386/i386.md:16023 */
19803 rtx
19804 gen_movhicc (operand0, operand1, operand2, operand3)
19805      rtx operand0;
19806      rtx operand1;
19807      rtx operand2;
19808      rtx operand3;
19809 {
19810   rtx _val = 0;
19811   start_sequence ();
19812   {
19813     rtx operands[4];
19814     operands[0] = operand0;
19815     operands[1] = operand1;
19816     operands[2] = operand2;
19817     operands[3] = operand3;
19818 if (!ix86_expand_int_movcc (operands)) FAIL; DONE;
19819     operand0 = operands[0];
19820     operand1 = operands[1];
19821     operand2 = operands[2];
19822     operand3 = operands[3];
19823   }
19824   emit_insn (gen_rtx_SET (VOIDmode,
19825   operand0,
19826   gen_rtx_IF_THEN_ELSE (HImode,
19827   operand1,
19828   operand2,
19829   operand3)));
19830   _val = get_insns ();
19831   end_sequence ();
19832   return _val;
19833 }
19834 
19835 /* ../../gcc/gcc/config/i386/i386.md:16045 */
19836 rtx
19837 gen_movsfcc (operand0, operand1, operand2, operand3)
19838      rtx operand0;
19839      rtx operand1;
19840      rtx operand2;
19841      rtx operand3;
19842 {
19843   rtx _val = 0;
19844   start_sequence ();
19845   {
19846     rtx operands[4];
19847     operands[0] = operand0;
19848     operands[1] = operand1;
19849     operands[2] = operand2;
19850     operands[3] = operand3;
19851 if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;
19852     operand0 = operands[0];
19853     operand1 = operands[1];
19854     operand2 = operands[2];
19855     operand3 = operands[3];
19856   }
19857   emit_insn (gen_rtx_SET (VOIDmode,
19858   operand0,
19859   gen_rtx_IF_THEN_ELSE (SFmode,
19860   operand1,
19861   operand2,
19862   operand3)));
19863   _val = get_insns ();
19864   end_sequence ();
19865   return _val;
19866 }
19867 
19868 /* ../../gcc/gcc/config/i386/i386.md:16069 */
19869 rtx
19870 gen_movdfcc (operand0, operand1, operand2, operand3)
19871      rtx operand0;
19872      rtx operand1;
19873      rtx operand2;
19874      rtx operand3;
19875 {
19876   rtx _val = 0;
19877   start_sequence ();
19878   {
19879     rtx operands[4];
19880     operands[0] = operand0;
19881     operands[1] = operand1;
19882     operands[2] = operand2;
19883     operands[3] = operand3;
19884 if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;
19885     operand0 = operands[0];
19886     operand1 = operands[1];
19887     operand2 = operands[2];
19888     operand3 = operands[3];
19889   }
19890   emit_insn (gen_rtx_SET (VOIDmode,
19891   operand0,
19892   gen_rtx_IF_THEN_ELSE (DFmode,
19893   operand1,
19894   operand2,
19895   operand3)));
19896   _val = get_insns ();
19897   end_sequence ();
19898   return _val;
19899 }
19900 
19901 /* ../../gcc/gcc/config/i386/i386.md:16109 */
19902 extern rtx gen_split_1427 PARAMS ((rtx *));
19903 rtx
19904 gen_split_1427 (operands)
19905       rtx *operands;
19906 {
19907   rtx operand0;
19908   rtx operand1;
19909   rtx operand2;
19910   rtx operand3;
19911   rtx operand4;
19912   rtx operand5;
19913   rtx operand6;
19914   rtx operand7;
19915   rtx operand8;
19916   rtx _val = 0;
19917   start_sequence ();
19918 split_di (operands+2, 1, operands+5, operands+6);
19919    split_di (operands+3, 1, operands+7, operands+8);
19920    split_di (operands, 1, operands+2, operands+3);
19921   operand0 = operands[0];
19922   operand1 = operands[1];
19923   operand2 = operands[2];
19924   operand3 = operands[3];
19925   operand4 = operands[4];
19926   operand5 = operands[5];
19927   operand6 = operands[6];
19928   operand7 = operands[7];
19929   operand8 = operands[8];
19930   emit_insn (gen_rtx_SET (VOIDmode,
19931   operand2,
19932   gen_rtx_IF_THEN_ELSE (SImode,
19933   gen_rtx (GET_CODE (operand1), GET_MODE (operand1),
19934     operand4,
19935     const0_rtx),
19936   operand5,
19937   operand7)));
19938   emit_insn (gen_rtx_SET (VOIDmode,
19939   operand3,
19940   gen_rtx_IF_THEN_ELSE (SImode,
19941   gen_rtx (GET_CODE (operand1), GET_MODE (operand1),
19942     copy_rtx (operand4),
19943     const0_rtx),
19944   operand6,
19945   operand8)));
19946   _val = get_insns ();
19947   end_sequence ();
19948   return _val;
19949 }
19950 
19951 /* ../../gcc/gcc/config/i386/i386.md:16128 */
19952 rtx
19953 gen_movxfcc (operand0, operand1, operand2, operand3)
19954      rtx operand0;
19955      rtx operand1;
19956      rtx operand2;
19957      rtx operand3;
19958 {
19959   rtx _val = 0;
19960   start_sequence ();
19961   {
19962     rtx operands[4];
19963     operands[0] = operand0;
19964     operands[1] = operand1;
19965     operands[2] = operand2;
19966     operands[3] = operand3;
19967 if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;
19968     operand0 = operands[0];
19969     operand1 = operands[1];
19970     operand2 = operands[2];
19971     operand3 = operands[3];
19972   }
19973   emit_insn (gen_rtx_SET (VOIDmode,
19974   operand0,
19975   gen_rtx_IF_THEN_ELSE (XFmode,
19976   operand1,
19977   operand2,
19978   operand3)));
19979   _val = get_insns ();
19980   end_sequence ();
19981   return _val;
19982 }
19983 
19984 /* ../../gcc/gcc/config/i386/i386.md:16136 */
19985 rtx
19986 gen_movtfcc (operand0, operand1, operand2, operand3)
19987      rtx operand0;
19988      rtx operand1;
19989      rtx operand2;
19990      rtx operand3;
19991 {
19992   rtx _val = 0;
19993   start_sequence ();
19994   {
19995     rtx operands[4];
19996     operands[0] = operand0;
19997     operands[1] = operand1;
19998     operands[2] = operand2;
19999     operands[3] = operand3;
20000 if (! ix86_expand_fp_movcc (operands)) FAIL; DONE;
20001     operand0 = operands[0];
20002     operand1 = operands[1];
20003     operand2 = operands[2];
20004     operand3 = operands[3];
20005   }
20006   emit_insn (gen_rtx_SET (VOIDmode,
20007   operand0,
20008   gen_rtx_IF_THEN_ELSE (TFmode,
20009   operand1,
20010   operand2,
20011   operand3)));
20012   _val = get_insns ();
20013   end_sequence ();
20014   return _val;
20015 }
20016 
20017 /* ../../gcc/gcc/config/i386/i386.md:16170 */
20018 rtx
20019 gen_minsf3 (operand0, operand1, operand2)
20020      rtx operand0;
20021      rtx operand1;
20022      rtx operand2;
20023 {
20024   return gen_rtx_PARALLEL (VOIDmode,
20025   gen_rtvec (2,
20026     gen_rtx_SET (VOIDmode,
20027   operand0,
20028   gen_rtx_IF_THEN_ELSE (SFmode,
20029   gen_rtx_LT (VOIDmode,
20030   operand1,
20031   operand2),
20032   operand1,
20033   operand2)),
20034     gen_rtx_CLOBBER (VOIDmode,
20035   gen_rtx_REG (CCmode,
20036   17))));
20037 }
20038 
20039 /* ../../gcc/gcc/config/i386/i386.md:16202 */
20040 extern rtx gen_split_1431 PARAMS ((rtx *));
20041 rtx
20042 gen_split_1431 (operands)
20043       rtx *operands;
20044 {
20045   rtx operand0;
20046   rtx operand1;
20047   rtx operand2;
20048   rtx _val = 0;
20049   start_sequence ();
20050   operand0 = operands[0];
20051   operand1 = operands[1];
20052   operand2 = operands[2];
20053   emit_insn (gen_rtx_SET (VOIDmode,
20054   operand0,
20055   gen_rtx_IF_THEN_ELSE (SFmode,
20056   gen_rtx_LT (VOIDmode,
20057   operand1,
20058   operand2),
20059   copy_rtx (operand1),
20060   copy_rtx (operand2))));
20061   _val = get_insns ();
20062   end_sequence ();
20063   return _val;
20064 }
20065 
20066 /* ../../gcc/gcc/config/i386/i386.md:16222 */
20067 extern rtx gen_split_1432 PARAMS ((rtx *));
20068 rtx
20069 gen_split_1432 (operands)
20070       rtx *operands;
20071 {
20072   rtx operand0;
20073   rtx operand1;
20074   rtx operand2;
20075   rtx _val = 0;
20076   start_sequence ();
20077   operand0 = operands[0];
20078   operand1 = operands[1];
20079   operand2 = operands[2];
20080   emit_insn (gen_rtx_SET (VOIDmode,
20081   gen_rtx_REG (CCFPmode,
20082   17),
20083   gen_rtx_COMPARE (CCFPmode,
20084   operand2,
20085   operand1)));
20086   emit_insn (gen_rtx_SET (VOIDmode,
20087   operand0,
20088   gen_rtx_IF_THEN_ELSE (SFmode,
20089   gen_rtx_GE (VOIDmode,
20090   gen_rtx_REG (CCFPmode,
20091   17),
20092   const0_rtx),
20093   copy_rtx (operand1),
20094   copy_rtx (operand2))));
20095   _val = get_insns ();
20096   end_sequence ();
20097   return _val;
20098 }
20099 
20100 /* ../../gcc/gcc/config/i386/i386.md:16253 */
20101 rtx
20102 gen_mindf3 (operand0, operand1, operand2)
20103      rtx operand0;
20104      rtx operand1;
20105      rtx operand2;
20106 {
20107   rtx _val = 0;
20108   start_sequence ();
20109   {
20110     rtx operands[3];
20111     operands[0] = operand0;
20112     operands[1] = operand1;
20113     operands[2] = operand2;
20114 #
20115     operand0 = operands[0];
20116     operand1 = operands[1];
20117     operand2 = operands[2];
20118   }
20119   emit (gen_rtx_PARALLEL (VOIDmode,
20120   gen_rtvec (2,
20121     gen_rtx_SET (VOIDmode,
20122   operand0,
20123   gen_rtx_IF_THEN_ELSE (DFmode,
20124   gen_rtx_LT (VOIDmode,
20125   operand1,
20126   operand2),
20127   operand1,
20128   operand2)),
20129     gen_rtx_CLOBBER (VOIDmode,
20130   gen_rtx_REG (CCmode,
20131   17)))));
20132   _val = get_insns ();
20133   end_sequence ();
20134   return _val;
20135 }
20136 
20137 /* ../../gcc/gcc/config/i386/i386.md:16285 */
20138 extern rtx gen_split_1434 PARAMS ((rtx *));
20139 rtx
20140 gen_split_1434 (operands)
20141       rtx *operands;
20142 {
20143   rtx operand0;
20144   rtx operand1;
20145   rtx operand2;
20146   rtx _val = 0;
20147   start_sequence ();
20148   operand0 = operands[0];
20149   operand1 = operands[1];
20150   operand2 = operands[2];
20151   emit_insn (gen_rtx_SET (VOIDmode,
20152   operand0,
20153   gen_rtx_IF_THEN_ELSE (DFmode,
20154   gen_rtx_LT (VOIDmode,
20155   operand1,
20156   operand2),
20157   copy_rtx (operand1),
20158   copy_rtx (operand2))));
20159   _val = get_insns ();
20160   end_sequence ();
20161   return _val;
20162 }
20163 
20164 /* ../../gcc/gcc/config/i386/i386.md:16304 */
20165 extern rtx gen_split_1435 PARAMS ((rtx *));
20166 rtx
20167 gen_split_1435 (operands)
20168       rtx *operands;
20169 {
20170   rtx operand0;
20171   rtx operand1;
20172   rtx operand2;
20173   rtx _val = 0;
20174   start_sequence ();
20175   operand0 = operands[0];
20176   operand1 = operands[1];
20177   operand2 = operands[2];
20178   emit_insn (gen_rtx_SET (VOIDmode,
20179   gen_rtx_REG (CCFPmode,
20180   17),
20181   gen_rtx_COMPARE (CCFPmode,
20182   operand2,
20183   copy_rtx (operand2))));
20184   emit_insn (gen_rtx_SET (VOIDmode,
20185   operand0,
20186   gen_rtx_IF_THEN_ELSE (DFmode,
20187   gen_rtx_GE (VOIDmode,
20188   gen_rtx_REG (CCFPmode,
20189   17),
20190   const0_rtx),
20191   operand1,
20192   copy_rtx (operand2))));
20193   _val = get_insns ();
20194   end_sequence ();
20195   return _val;
20196 }
20197 
20198 /* ../../gcc/gcc/config/i386/i386.md:16335 */
20199 rtx
20200 gen_maxsf3 (operand0, operand1, operand2)
20201      rtx operand0;
20202      rtx operand1;
20203      rtx operand2;
20204 {
20205   rtx _val = 0;
20206   start_sequence ();
20207   {
20208     rtx operands[3];
20209     operands[0] = operand0;
20210     operands[1] = operand1;
20211     operands[2] = operand2;
20212 #
20213     operand0 = operands[0];
20214     operand1 = operands[1];
20215     operand2 = operands[2];
20216   }
20217   emit (gen_rtx_PARALLEL (VOIDmode,
20218   gen_rtvec (2,
20219     gen_rtx_SET (VOIDmode,
20220   operand0,
20221   gen_rtx_IF_THEN_ELSE (SFmode,
20222   gen_rtx_GT (VOIDmode,
20223   operand1,
20224   operand2),
20225   operand1,
20226   operand2)),
20227     gen_rtx_CLOBBER (VOIDmode,
20228   gen_rtx_REG (CCmode,
20229   17)))));
20230   _val = get_insns ();
20231   end_sequence ();
20232   return _val;
20233 }
20234 
20235 /* ../../gcc/gcc/config/i386/i386.md:16367 */
20236 extern rtx gen_split_1437 PARAMS ((rtx *));
20237 rtx
20238 gen_split_1437 (operands)
20239       rtx *operands;
20240 {
20241   rtx operand0;
20242   rtx operand1;
20243   rtx operand2;
20244   rtx _val = 0;
20245   start_sequence ();
20246   operand0 = operands[0];
20247   operand1 = operands[1];
20248   operand2 = operands[2];
20249   emit_insn (gen_rtx_SET (VOIDmode,
20250   operand0,
20251   gen_rtx_IF_THEN_ELSE (SFmode,
20252   gen_rtx_GT (VOIDmode,
20253   operand1,
20254   operand2),
20255   copy_rtx (operand1),
20256   copy_rtx (operand2))));
20257   _val = get_insns ();
20258   end_sequence ();
20259   return _val;
20260 }
20261 
20262 /* ../../gcc/gcc/config/i386/i386.md:16385 */
20263 extern rtx gen_split_1438 PARAMS ((rtx *));
20264 rtx
20265 gen_split_1438 (operands)
20266       rtx *operands;
20267 {
20268   rtx operand0;
20269   rtx operand1;
20270   rtx operand2;
20271   rtx _val = 0;
20272   start_sequence ();
20273   operand0 = operands[0];
20274   operand1 = operands[1];
20275   operand2 = operands[2];
20276   emit_insn (gen_rtx_SET (VOIDmode,
20277   gen_rtx_REG (CCFPmode,
20278   17),
20279   gen_rtx_COMPARE (CCFPmode,
20280   operand1,
20281   operand2)));
20282   emit_insn (gen_rtx_SET (VOIDmode,
20283   operand0,
20284   gen_rtx_IF_THEN_ELSE (SFmode,
20285   gen_rtx_GT (VOIDmode,
20286   gen_rtx_REG (CCFPmode,
20287   17),
20288   const0_rtx),
20289   copy_rtx (operand1),
20290   copy_rtx (operand2))));
20291   _val = get_insns ();
20292   end_sequence ();
20293   return _val;
20294 }
20295 
20296 /* ../../gcc/gcc/config/i386/i386.md:16416 */
20297 rtx
20298 gen_maxdf3 (operand0, operand1, operand2)
20299      rtx operand0;
20300      rtx operand1;
20301      rtx operand2;
20302 {
20303   rtx _val = 0;
20304   start_sequence ();
20305   {
20306     rtx operands[3];
20307     operands[0] = operand0;
20308     operands[1] = operand1;
20309     operands[2] = operand2;
20310 #
20311     operand0 = operands[0];
20312     operand1 = operands[1];
20313     operand2 = operands[2];
20314   }
20315   emit (gen_rtx_PARALLEL (VOIDmode,
20316   gen_rtvec (2,
20317     gen_rtx_SET (VOIDmode,
20318   operand0,
20319   gen_rtx_IF_THEN_ELSE (DFmode,
20320   gen_rtx_GT (VOIDmode,
20321   operand1,
20322   operand2),
20323   operand1,
20324   operand2)),
20325     gen_rtx_CLOBBER (VOIDmode,
20326   gen_rtx_REG (CCmode,
20327   17)))));
20328   _val = get_insns ();
20329   end_sequence ();
20330   return _val;
20331 }
20332 
20333 /* ../../gcc/gcc/config/i386/i386.md:16448 */
20334 extern rtx gen_split_1440 PARAMS ((rtx *));
20335 rtx
20336 gen_split_1440 (operands)
20337       rtx *operands;
20338 {
20339   rtx operand0;
20340   rtx operand1;
20341   rtx operand2;
20342   rtx _val = 0;
20343   start_sequence ();
20344   operand0 = operands[0];
20345   operand1 = operands[1];
20346   operand2 = operands[2];
20347   emit_insn (gen_rtx_SET (VOIDmode,
20348   operand0,
20349   gen_rtx_IF_THEN_ELSE (DFmode,
20350   gen_rtx_GT (VOIDmode,
20351   operand1,
20352   operand2),
20353   copy_rtx (operand1),
20354   copy_rtx (operand2))));
20355   _val = get_insns ();
20356   end_sequence ();
20357   return _val;
20358 }
20359 
20360 /* ../../gcc/gcc/config/i386/i386.md:16466 */
20361 extern rtx gen_split_1441 PARAMS ((rtx *));
20362 rtx
20363 gen_split_1441 (operands)
20364       rtx *operands;
20365 {
20366   rtx operand0;
20367   rtx operand1;
20368   rtx operand2;
20369   rtx _val = 0;
20370   start_sequence ();
20371   operand0 = operands[0];
20372   operand1 = operands[1];
20373   operand2 = operands[2];
20374   emit_insn (gen_rtx_SET (VOIDmode,
20375   gen_rtx_REG (CCFPmode,
20376   17),
20377   gen_rtx_COMPARE (CCFPmode,
20378   operand1,
20379   operand2)));
20380   emit_insn (gen_rtx_SET (VOIDmode,
20381   operand0,
20382   gen_rtx_IF_THEN_ELSE (DFmode,
20383   gen_rtx_GT (VOIDmode,
20384   gen_rtx_REG (CCFPmode,
20385   17),
20386   const0_rtx),
20387   copy_rtx (operand1),
20388   copy_rtx (operand2))));
20389   _val = get_insns ();
20390   end_sequence ();
20391   return _val;
20392 }
20393 
20394 /* ../../gcc/gcc/config/i386/i386.md:16508 */
20395 rtx
20396 gen_pro_epilogue_adjust_stack (operand0, operand1, operand2)
20397      rtx operand0;
20398      rtx operand1;
20399      rtx operand2;
20400 {
20401   rtx _val = 0;
20402   start_sequence ();
20403   {
20404     rtx operands[3];
20405     operands[0] = operand0;
20406     operands[1] = operand1;
20407     operands[2] = operand2;
20408 {
20409   if (TARGET_64BIT)
20410     {
20411       emit_insn (gen_pro_epilogue_adjust_stack_rex64
20412      (operands[0], operands[1], operands[2]));
20413       DONE;
20414     }
20415 }
20416     operand0 = operands[0];
20417     operand1 = operands[1];
20418     operand2 = operands[2];
20419   }
20420   emit (gen_rtx_PARALLEL (VOIDmode,
20421   gen_rtvec (3,
20422     gen_rtx_SET (VOIDmode,
20423   operand0,
20424   gen_rtx_PLUS (SImode,
20425   operand1,
20426   operand2)),
20427     gen_rtx_CLOBBER (VOIDmode,
20428   gen_rtx_REG (CCmode,
20429   17)),
20430     gen_rtx_CLOBBER (VOIDmode,
20431   gen_rtx_MEM (BLKmode,
20432   gen_rtx_SCRATCH (VOIDmode))))));
20433   _val = get_insns ();
20434   end_sequence ();
20435   return _val;
20436 }
20437 
20438 /* ../../gcc/gcc/config/i386/i386.md:16670 */
20439 extern rtx gen_split_1443 PARAMS ((rtx *));
20440 rtx
20441 gen_split_1443 (operands)
20442       rtx *operands ATTRIBUTE_UNUSED;
20443 {
20444   rtx _val = 0;
20445   start_sequence ();
20446 {
20447    ix86_compare_op0 = operands[5];
20448    ix86_compare_op1 = operands[4];
20449    operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])),
20450          VOIDmode, operands[5], operands[4]);
20451    ix86_expand_fp_movcc (operands);
20452    DONE;
20453 }
20454   emit_insn (const0_rtx);
20455   _val = get_insns ();
20456   end_sequence ();
20457   return _val;
20458 }
20459 
20460 /* ../../gcc/gcc/config/i386/i386.md:16696 */
20461 extern rtx gen_split_1444 PARAMS ((rtx *));
20462 rtx
20463 gen_split_1444 (operands)
20464       rtx *operands;
20465 {
20466   rtx operand0;
20467   rtx operand1;
20468   rtx operand2;
20469   rtx operand3;
20470   rtx operand4;
20471   rtx operand5;
20472   rtx operand6;
20473   rtx operand7;
20474   rtx _val = 0;
20475   start_sequence ();
20476 {
20477   /* If op2 == op3, op3 would be clobbered before it is used.  */
20478   if (operands_match_p (operands[2], operands[3]))
20479     {
20480       emit_move_insn (operands[0], operands[2]);
20481       DONE;
20482     }
20483   PUT_MODE (operands[1], GET_MODE (operands[0]));
20484   if (operands_match_p (operands[0], operands[4]))
20485     operands[6] = operands[4], operands[7] = operands[2];
20486   else
20487     operands[6] = operands[2], operands[7] = operands[4];
20488 }
20489   operand0 = operands[0];
20490   operand1 = operands[1];
20491   operand2 = operands[2];
20492   operand3 = operands[3];
20493   operand4 = operands[4];
20494   operand5 = operands[5];
20495   operand6 = operands[6];
20496   operand7 = operands[7];
20497   emit_insn (gen_rtx_SET (VOIDmode,
20498   operand4,
20499   gen_rtx (GET_CODE (operand1), GET_MODE (operand1),
20500     copy_rtx (operand4),
20501     operand5)));
20502   emit_insn (gen_rtx_SET (VOIDmode,
20503   gen_rtx_SUBREG (TImode,
20504   operand2,
20505   0),
20506   gen_rtx_AND (TImode,
20507   gen_rtx_SUBREG (TImode,
20508   copy_rtx (operand2),
20509   0),
20510   gen_rtx_SUBREG (TImode,
20511   copy_rtx (operand4),
20512   0))));
20513   emit_insn (gen_rtx_SET (VOIDmode,
20514   gen_rtx_SUBREG (TImode,
20515   copy_rtx (operand4),
20516   0),
20517   gen_rtx_AND (TImode,
20518   gen_rtx_NOT (TImode,
20519   gen_rtx_SUBREG (TImode,
20520   copy_rtx (operand4),
20521   0)),
20522   gen_rtx_SUBREG (TImode,
20523   operand3,
20524   0))));
20525   emit_insn (gen_rtx_SET (VOIDmode,
20526   gen_rtx_SUBREG (TImode,
20527   operand0,
20528   0),
20529   gen_rtx_IOR (TImode,
20530   gen_rtx_SUBREG (TImode,
20531   operand6,
20532   0),
20533   gen_rtx_SUBREG (TImode,
20534   operand7,
20535   0))));
20536   _val = get_insns ();
20537   end_sequence ();
20538   return _val;
20539 }
20540 
20541 /* ../../gcc/gcc/config/i386/i386.md:16810 */
20542 extern rtx gen_split_1445 PARAMS ((rtx *));
20543 rtx
20544 gen_split_1445 (operands)
20545       rtx *operands;
20546 {
20547   rtx operand0;
20548   rtx operand1;
20549   rtx operand2;
20550   rtx operand3;
20551   rtx operand4;
20552   rtx operand5;
20553   rtx operand6;
20554   rtx operand7;
20555   rtx _val = 0;
20556   start_sequence ();
20557 {
20558   PUT_MODE (operands[1], GET_MODE (operands[0]));
20559   if (!sse_comparison_operator (operands[1], VOIDmode)
20560       || !rtx_equal_p (operands[0], operands[4]))
20561     {
20562       rtx tmp = operands[5];
20563       operands[5] = operands[4];
20564       operands[4] = tmp;
20565       PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1])));
20566     }
20567   if (!rtx_equal_p (operands[0], operands[4]))
20568     abort ();
20569   if (const0_operand (operands[2], GET_MODE (operands[0])))
20570     {
20571       operands[7] = operands[3];
20572       operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0],
20573                0));
20574     }
20575   else
20576     {
20577       operands[7] = operands[2];
20578       operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0);
20579     }
20580 }
20581   operand0 = operands[0];
20582   operand1 = operands[1];
20583   operand2 = operands[2];
20584   operand3 = operands[3];
20585   operand4 = operands[4];
20586   operand5 = operands[5];
20587   operand6 = operands[6];
20588   operand7 = operands[7];
20589   emit_insn (gen_rtx_SET (VOIDmode,
20590   operand0,
20591   gen_rtx (GET_CODE (operand1), GET_MODE (operand1),
20592     copy_rtx (operand0),
20593     operand5)));
20594   emit_insn (gen_rtx_SET (VOIDmode,
20595   gen_rtx_SUBREG (TImode,
20596   copy_rtx (operand0),
20597   0),
20598   gen_rtx_AND (TImode,
20599   operand6,
20600   gen_rtx_SUBREG (TImode,
20601   operand7,
20602   0))));
20603   _val = get_insns ();
20604   end_sequence ();
20605   return _val;
20606 }
20607 
20608 /* ../../gcc/gcc/config/i386/i386.md:16848 */
20609 rtx
20610 gen_allocate_stack_worker (operand0)
20611      rtx operand0;
20612 {
20613   rtx _val = 0;
20614   start_sequence ();
20615   {
20616     rtx operands[1];
20617     operands[0] = operand0;
20618 {
20619   if (TARGET_64BIT)
20620     emit_insn (gen_allocate_stack_worker_rex64 (operands[0]));
20621   else
20622     emit_insn (gen_allocate_stack_worker_1 (operands[0]));
20623   DONE;
20624 }
20625     operand0 = operands[0];
20626   }
20627   emit (operand0);
20628   _val = get_insns ();
20629   end_sequence ();
20630   return _val;
20631 }
20632 
20633 /* ../../gcc/gcc/config/i386/i386.md:16879 */
20634 rtx
20635 gen_allocate_stack (operand0, operand1)
20636      rtx operand0;
20637      rtx operand1;
20638 {
20639   rtx _val = 0;
20640   start_sequence ();
20641   {
20642     rtx operands[2];
20643     operands[0] = operand0;
20644     operands[1] = operand1;
20645 {
20646 #ifdef CHECK_STACK_LIMIT
20647   if (GET_CODE (operands[1]) == CONST_INT
20648       && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
20649     emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
20650          operands[1]));
20651   else 
20652 #endif
20653     emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
20654                   operands[1])));
20655 
20656   emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
20657   DONE;
20658 }
20659     operand0 = operands[0];
20660     operand1 = operands[1];
20661   }
20662   emit (gen_rtx_PARALLEL (VOIDmode,
20663   gen_rtvec (2,
20664     gen_rtx_SET (VOIDmode,
20665   operand0,
20666   gen_rtx_MINUS (SImode,
20667   gen_rtx_REG (SImode,
20668   7),
20669   operand1)),
20670     gen_rtx_CLOBBER (VOIDmode,
20671   gen_rtx_REG (CCmode,
20672   17)))));
20673   emit (gen_rtx_PARALLEL (VOIDmode,
20674   gen_rtvec (2,
20675     gen_rtx_SET (VOIDmode,
20676   gen_rtx_REG (SImode,
20677   7),
20678   gen_rtx_MINUS (SImode,
20679   gen_rtx_REG (SImode,
20680   7),
20681   operand1)),
20682     gen_rtx_CLOBBER (VOIDmode,
20683   gen_rtx_REG (CCmode,
20684   17)))));
20685   _val = get_insns ();
20686   end_sequence ();
20687   return _val;
20688 }
20689 
20690 /* ../../gcc/gcc/config/i386/i386.md:16903 */
20691 rtx
20692 gen_builtin_setjmp_receiver (operand0)
20693      rtx operand0;
20694 {
20695   rtx _val = 0;
20696   start_sequence ();
20697   {
20698     rtx operands[1];
20699     operands[0] = operand0;
20700 {
20701   emit_insn (gen_set_got (pic_offset_table_rtx));
20702   DONE;
20703 }
20704     operand0 = operands[0];
20705   }
20706   emit_insn (gen_rtx_LABEL_REF (VOIDmode,
20707   operand0));
20708   _val = get_insns ();
20709   end_sequence ();
20710   return _val;
20711 }
20712 
20713 /* ../../gcc/gcc/config/i386/i386.md:16913 */
20714 extern rtx gen_split_1449 PARAMS ((rtx *));
20715 rtx
20716 gen_split_1449 (operands)
20717       rtx *operands;
20718 {
20719   rtx operand0;
20720   rtx operand1;
20721   rtx operand2;
20722   rtx operand3;
20723   rtx _val = 0;
20724   start_sequence ();
20725 operands[0] = gen_lowpart (SImode, operands[0]);
20726    operands[1] = gen_lowpart (SImode, operands[1]);
20727    if (GET_CODE (operands[3]) != ASHIFT)
20728      operands[2] = gen_lowpart (SImode, operands[2]);
20729    PUT_MODE (operands[3], SImode);
20730   operand0 = operands[0];
20731   operand1 = operands[1];
20732   operand2 = operands[2];
20733   operand3 = operands[3];
20734   emit (gen_rtx_PARALLEL (VOIDmode,
20735   gen_rtvec (2,
20736     gen_rtx_SET (VOIDmode,
20737   operand0,
20738   gen_rtx (GET_CODE (operand3), GET_MODE (operand3),
20739     operand1,
20740     operand2)),
20741     gen_rtx_CLOBBER (VOIDmode,
20742   gen_rtx_REG (CCmode,
20743   17)))));
20744   _val = get_insns ();
20745   end_sequence ();
20746   return _val;
20747 }
20748 
20749 /* ../../gcc/gcc/config/i386/i386.md:16939 */
20750 extern rtx gen_split_1450 PARAMS ((rtx *));
20751 rtx
20752 gen_split_1450 (operands)
20753       rtx *operands;
20754 {
20755   rtx operand0;
20756   rtx operand1;
20757   rtx operand2;
20758   rtx _val = 0;
20759   start_sequence ();
20760 operands[2]
20761      = gen_int_mode (INTVAL (operands[2])
20762          & GET_MODE_MASK (GET_MODE (operands[0])),
20763          SImode);
20764    operands[0] = gen_lowpart (SImode, operands[0]);
20765    operands[1] = gen_lowpart (SImode, operands[1]);
20766   operand0 = operands[0];
20767   operand1 = operands[1];
20768   operand2 = operands[2];
20769   emit (gen_rtx_PARALLEL (VOIDmode,
20770   gen_rtvec (2,
20771     gen_rtx_SET (VOIDmode,
20772   gen_rtx_REG (CCNOmode,
20773   17),
20774   gen_rtx_COMPARE (CCNOmode,
20775   gen_rtx_AND (SImode,
20776   operand1,
20777   operand2),
20778   const0_rtx)),
20779     gen_rtx_SET (VOIDmode,
20780   operand0,
20781   gen_rtx_AND (SImode,
20782   copy_rtx (operand1),
20783   copy_rtx (operand2))))));
20784   _val = get_insns ();
20785   end_sequence ();
20786   return _val;
20787 }
20788 
20789 /* ../../gcc/gcc/config/i386/i386.md:16968 */
20790 extern rtx gen_split_1451 PARAMS ((rtx *));
20791 rtx
20792 gen_split_1451 (operands)
20793       rtx *operands;
20794 {
20795   rtx operand0;
20796   rtx operand1;
20797   rtx _val = 0;
20798   start_sequence ();
20799 operands[1]
20800      = gen_int_mode (INTVAL (operands[1])
20801          & GET_MODE_MASK (GET_MODE (operands[0])),
20802          SImode);
20803    operands[0] = gen_lowpart (SImode, operands[0]);
20804   operand0 = operands[0];
20805   operand1 = operands[1];
20806   emit_insn (gen_rtx_SET (VOIDmode,
20807   gen_rtx_REG (CCNOmode,
20808   17),
20809   gen_rtx_COMPARE (CCNOmode,
20810   gen_rtx_AND (SImode,
20811   operand0,
20812   operand1),
20813   const0_rtx)));
20814   _val = get_insns ();
20815   end_sequence ();
20816   return _val;
20817 }
20818 
20819 /* ../../gcc/gcc/config/i386/i386.md:16987 */
20820 extern rtx gen_split_1452 PARAMS ((rtx *));
20821 rtx
20822 gen_split_1452 (operands)
20823       rtx *operands;
20824 {
20825   rtx operand0;
20826   rtx operand1;
20827   rtx _val = 0;
20828   start_sequence ();
20829 operands[0] = gen_lowpart (SImode, operands[0]);
20830    operands[1] = gen_lowpart (SImode, operands[1]);
20831   operand0 = operands[0];
20832   operand1 = operands[1];
20833   emit (gen_rtx_PARALLEL (VOIDmode,
20834   gen_rtvec (2,
20835     gen_rtx_SET (VOIDmode,
20836   operand0,
20837   gen_rtx_NEG (SImode,
20838   operand1)),
20839     gen_rtx_CLOBBER (VOIDmode,
20840   gen_rtx_REG (CCmode,
20841   17)))));
20842   _val = get_insns ();
20843   end_sequence ();
20844   return _val;
20845 }
20846 
20847 /* ../../gcc/gcc/config/i386/i386.md:17001 */
20848 extern rtx gen_split_1453 PARAMS ((rtx *));
20849 rtx
20850 gen_split_1453 (operands)
20851       rtx *operands;
20852 {
20853   rtx operand0;
20854   rtx operand1;
20855   rtx _val = 0;
20856   start_sequence ();
20857 operands[0] = gen_lowpart (SImode, operands[0]);
20858    operands[1] = gen_lowpart (SImode, operands[1]);
20859   operand0 = operands[0];
20860   operand1 = operands[1];
20861   emit_insn (gen_rtx_SET (VOIDmode,
20862   operand0,
20863   gen_rtx_NOT (SImode,
20864   operand1)));
20865   _val = get_insns ();
20866   end_sequence ();
20867   return _val;
20868 }
20869 
20870 /* ../../gcc/gcc/config/i386/i386.md:17013 */
20871 extern rtx gen_split_1454 PARAMS ((rtx *));
20872 rtx
20873 gen_split_1454 (operands)
20874       rtx *operands;
20875 {
20876   rtx operand0;
20877   rtx operand1;
20878   rtx operand2;
20879   rtx operand3;
20880   rtx _val = 0;
20881   start_sequence ();
20882 operands[0] = gen_lowpart (SImode, operands[0]);
20883    operands[2] = gen_lowpart (SImode, operands[2]);
20884    operands[3] = gen_lowpart (SImode, operands[3]);
20885   operand0 = operands[0];
20886   operand1 = operands[1];
20887   operand2 = operands[2];
20888   operand3 = operands[3];
20889   emit_insn (gen_rtx_SET (VOIDmode,
20890   operand0,
20891   gen_rtx_IF_THEN_ELSE (SImode,
20892   operand1,
20893   operand2,
20894   operand3)));
20895   _val = get_insns ();
20896   end_sequence ();
20897   return _val;
20898 }
20899 
20900 /* ../../gcc/gcc/config/i386/i386.md:17034 */
20901 extern rtx gen_peephole2_1455 PARAMS ((rtx, rtx *));
20902 rtx
20903 gen_peephole2_1455 (curr_insn, operands)
20904      rtx curr_insn ATTRIBUTE_UNUSED;
20905      rtx *operands;
20906 {
20907   rtx operand0;
20908   rtx operand1;
20909   rtx operand2;
20910   rtx _val = 0;
20911   HARD_REG_SET _regs_allocated;
20912   CLEAR_HARD_REG_SET (_regs_allocated);
20913   if ((operands[2] = peep2_find_free_register (1, 1, "r", SImode, &_regs_allocated)) == NULL_RTX)
20914     return NULL;
20915   start_sequence ();
20916 
20917   operand0 = operands[0];
20918   operand1 = operands[1];
20919   operand2 = operands[2];
20920   emit_insn (gen_rtx_SET (VOIDmode,
20921   operand2,
20922   operand1));
20923   emit_insn (gen_rtx_SET (VOIDmode,
20924   operand0,
20925   copy_rtx (operand2)));
20926   _val = get_insns ();
20927   end_sequence ();
20928   return _val;
20929 }
20930 
20931 /* ../../gcc/gcc/config/i386/i386.md:17043 */
20932 extern rtx gen_peephole2_1456 PARAMS ((rtx, rtx *));
20933 rtx
20934 gen_peephole2_1456 (curr_insn, operands)
20935      rtx curr_insn ATTRIBUTE_UNUSED;
20936      rtx *operands;
20937 {
20938   rtx operand0;
20939   rtx operand1;
20940   rtx operand2;
20941   rtx _val = 0;
20942   HARD_REG_SET _regs_allocated;
20943   CLEAR_HARD_REG_SET (_regs_allocated);
20944   if ((operands[2] = peep2_find_free_register (1, 1, "r", DImode, &_regs_allocated)) == NULL_RTX)
20945     return NULL;
20946   start_sequence ();
20947 
20948   operand0 = operands[0];
20949   operand1 = operands[1];
20950   operand2 = operands[2];
20951   emit_insn (gen_rtx_SET (VOIDmode,
20952   operand2,
20953   operand1));
20954   emit_insn (gen_rtx_SET (VOIDmode,
20955   operand0,
20956   copy_rtx (operand2)));
20957   _val = get_insns ();
20958   end_sequence ();
20959   return _val;
20960 }
20961 
20962 /* ../../gcc/gcc/config/i386/i386.md:17054 */
20963 extern rtx gen_peephole2_1457 PARAMS ((rtx, rtx *));
20964 rtx
20965 gen_peephole2_1457 (curr_insn, operands)
20966      rtx curr_insn ATTRIBUTE_UNUSED;
20967      rtx *operands;
20968 {
20969   rtx operand0;
20970   rtx operand1;
20971   rtx operand2;
20972   rtx _val = 0;
20973   HARD_REG_SET _regs_allocated;
20974   CLEAR_HARD_REG_SET (_regs_allocated);
20975   if ((operands[2] = peep2_find_free_register (1, 1, "r", SFmode, &_regs_allocated)) == NULL_RTX)
20976     return NULL;
20977   start_sequence ();
20978 
20979   operand0 = operands[0];
20980   operand1 = operands[1];
20981   operand2 = operands[2];
20982   emit_insn (gen_rtx_SET (VOIDmode,
20983   operand2,
20984   operand1));
20985   emit_insn (gen_rtx_SET (VOIDmode,
20986   operand0,
20987   copy_rtx (operand2)));
20988   _val = get_insns ();
20989   end_sequence ();
20990   return _val;
20991 }
20992 
20993 /* ../../gcc/gcc/config/i386/i386.md:17063 */
20994 extern rtx gen_peephole2_1458 PARAMS ((rtx, rtx *));
20995 rtx
20996 gen_peephole2_1458 (curr_insn, operands)
20997      rtx curr_insn ATTRIBUTE_UNUSED;
20998      rtx *operands;
20999 {
21000   rtx operand0;
21001   rtx operand1;
21002   rtx operand2;
21003   rtx _val = 0;
21004   HARD_REG_SET _regs_allocated;
21005   CLEAR_HARD_REG_SET (_regs_allocated);
21006   if ((operands[2] = peep2_find_free_register (1, 1, "r", HImode, &_regs_allocated)) == NULL_RTX)
21007     return NULL;
21008   start_sequence ();
21009 
21010   operand0 = operands[0];
21011   operand1 = operands[1];
21012   operand2 = operands[2];
21013   emit_insn (gen_rtx_SET (VOIDmode,
21014   operand2,
21015   operand1));
21016   emit_insn (gen_rtx_SET (VOIDmode,
21017   operand0,
21018   copy_rtx (operand2)));
21019   _val = get_insns ();
21020   end_sequence ();
21021   return _val;
21022 }
21023 
21024 /* ../../gcc/gcc/config/i386/i386.md:17072 */
21025 extern rtx gen_peephole2_1459 PARAMS ((rtx, rtx *));
21026 rtx
21027 gen_peephole2_1459 (curr_insn, operands)
21028      rtx curr_insn ATTRIBUTE_UNUSED;
21029      rtx *operands;
21030 {
21031   rtx operand0;
21032   rtx operand1;
21033   rtx operand2;
21034   rtx _val = 0;
21035   HARD_REG_SET _regs_allocated;
21036   CLEAR_HARD_REG_SET (_regs_allocated);
21037   if ((operands[2] = peep2_find_free_register (1, 1, "q", QImode, &_regs_allocated)) == NULL_RTX)
21038     return NULL;
21039   start_sequence ();
21040 
21041   operand0 = operands[0];
21042   operand1 = operands[1];
21043   operand2 = operands[2];
21044   emit_insn (gen_rtx_SET (VOIDmode,
21045   operand2,
21046   operand1));
21047   emit_insn (gen_rtx_SET (VOIDmode,
21048   operand0,
21049   copy_rtx (operand2)));
21050   _val = get_insns ();
21051   end_sequence ();
21052   return _val;
21053 }
21054 
21055 /* ../../gcc/gcc/config/i386/i386.md:17083 */
21056 extern rtx gen_peephole2_1460 PARAMS ((rtx, rtx *));
21057 rtx
21058 gen_peephole2_1460 (curr_insn, operands)
21059      rtx curr_insn ATTRIBUTE_UNUSED;
21060      rtx *operands;
21061 {
21062   rtx operand0;
21063   rtx operand1;
21064   rtx _val = 0;
21065   HARD_REG_SET _regs_allocated;
21066   CLEAR_HARD_REG_SET (_regs_allocated);
21067   if ((operands[1] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
21068     return NULL;
21069   start_sequence ();
21070 
21071   operand0 = operands[0];
21072   operand1 = operands[1];
21073   emit (gen_rtx_PARALLEL (VOIDmode,
21074   gen_rtvec (2,
21075     gen_rtx_SET (VOIDmode,
21076   operand1,
21077   const0_rtx),
21078     gen_rtx_CLOBBER (VOIDmode,
21079   gen_rtx_REG (CCmode,
21080   17)))));
21081   emit_insn (gen_rtx_SET (VOIDmode,
21082   operand0,
21083   copy_rtx (operand1)));
21084   _val = get_insns ();
21085   end_sequence ();
21086   return _val;
21087 }
21088 
21089 /* ../../gcc/gcc/config/i386/i386.md:17097 */
21090 extern rtx gen_peephole2_1461 PARAMS ((rtx, rtx *));
21091 rtx
21092 gen_peephole2_1461 (curr_insn, operands)
21093      rtx curr_insn ATTRIBUTE_UNUSED;
21094      rtx *operands;
21095 {
21096   rtx operand0;
21097   rtx operand1;
21098   rtx operand2;
21099   rtx _val = 0;
21100   HARD_REG_SET _regs_allocated;
21101   CLEAR_HARD_REG_SET (_regs_allocated);
21102   if ((operands[1] = peep2_find_free_register (0, 0, "r", HImode, &_regs_allocated)) == NULL_RTX)
21103     return NULL;
21104   start_sequence ();
21105 operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));
21106   operand0 = operands[0];
21107   operand1 = operands[1];
21108   operand2 = operands[2];
21109   emit (gen_rtx_PARALLEL (VOIDmode,
21110   gen_rtvec (2,
21111     gen_rtx_SET (VOIDmode,
21112   operand2,
21113   const0_rtx),
21114     gen_rtx_CLOBBER (VOIDmode,
21115   gen_rtx_REG (CCmode,
21116   17)))));
21117   emit_insn (gen_rtx_SET (VOIDmode,
21118   operand0,
21119   operand1));
21120   _val = get_insns ();
21121   end_sequence ();
21122   return _val;
21123 }
21124 
21125 /* ../../gcc/gcc/config/i386/i386.md:17111 */
21126 extern rtx gen_peephole2_1462 PARAMS ((rtx, rtx *));
21127 rtx
21128 gen_peephole2_1462 (curr_insn, operands)
21129      rtx curr_insn ATTRIBUTE_UNUSED;
21130      rtx *operands;
21131 {
21132   rtx operand0;
21133   rtx operand1;
21134   rtx operand2;
21135   rtx _val = 0;
21136   HARD_REG_SET _regs_allocated;
21137   CLEAR_HARD_REG_SET (_regs_allocated);
21138   if ((operands[1] = peep2_find_free_register (0, 0, "q", QImode, &_regs_allocated)) == NULL_RTX)
21139     return NULL;
21140   start_sequence ();
21141 operands[2] = gen_rtx_REG (SImode, true_regnum (operands[1]));
21142   operand0 = operands[0];
21143   operand1 = operands[1];
21144   operand2 = operands[2];
21145   emit (gen_rtx_PARALLEL (VOIDmode,
21146   gen_rtvec (2,
21147     gen_rtx_SET (VOIDmode,
21148   operand2,
21149   const0_rtx),
21150     gen_rtx_CLOBBER (VOIDmode,
21151   gen_rtx_REG (CCmode,
21152   17)))));
21153   emit_insn (gen_rtx_SET (VOIDmode,
21154   operand0,
21155   operand1));
21156   _val = get_insns ();
21157   end_sequence ();
21158   return _val;
21159 }
21160 
21161 /* ../../gcc/gcc/config/i386/i386.md:17125 */
21162 extern rtx gen_peephole2_1463 PARAMS ((rtx, rtx *));
21163 rtx
21164 gen_peephole2_1463 (curr_insn, operands)
21165      rtx curr_insn ATTRIBUTE_UNUSED;
21166      rtx *operands;
21167 {
21168   rtx operand0;
21169   rtx operand1;
21170   rtx operand2;
21171   rtx _val = 0;
21172   HARD_REG_SET _regs_allocated;
21173   CLEAR_HARD_REG_SET (_regs_allocated);
21174   if ((operands[2] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
21175     return NULL;
21176   start_sequence ();
21177 
21178   operand0 = operands[0];
21179   operand1 = operands[1];
21180   operand2 = operands[2];
21181   emit_insn (gen_rtx_SET (VOIDmode,
21182   operand2,
21183   operand1));
21184   emit_insn (gen_rtx_SET (VOIDmode,
21185   operand0,
21186   copy_rtx (operand2)));
21187   _val = get_insns ();
21188   end_sequence ();
21189   return _val;
21190 }
21191 
21192 /* ../../gcc/gcc/config/i386/i386.md:17136 */
21193 extern rtx gen_peephole2_1464 PARAMS ((rtx, rtx *));
21194 rtx
21195 gen_peephole2_1464 (curr_insn, operands)
21196      rtx curr_insn ATTRIBUTE_UNUSED;
21197      rtx *operands;
21198 {
21199   rtx operand0;
21200   rtx operand1;
21201   rtx operand2;
21202   rtx _val = 0;
21203   HARD_REG_SET _regs_allocated;
21204   CLEAR_HARD_REG_SET (_regs_allocated);
21205   if ((operands[2] = peep2_find_free_register (0, 0, "r", HImode, &_regs_allocated)) == NULL_RTX)
21206     return NULL;
21207   start_sequence ();
21208 
21209   operand0 = operands[0];
21210   operand1 = operands[1];
21211   operand2 = operands[2];
21212   emit_insn (gen_rtx_SET (VOIDmode,
21213   operand2,
21214   operand1));
21215   emit_insn (gen_rtx_SET (VOIDmode,
21216   operand0,
21217   copy_rtx (operand2)));
21218   _val = get_insns ();
21219   end_sequence ();
21220   return _val;
21221 }
21222 
21223 /* ../../gcc/gcc/config/i386/i386.md:17146 */
21224 extern rtx gen_peephole2_1465 PARAMS ((rtx, rtx *));
21225 rtx
21226 gen_peephole2_1465 (curr_insn, operands)
21227      rtx curr_insn ATTRIBUTE_UNUSED;
21228      rtx *operands;
21229 {
21230   rtx operand0;
21231   rtx operand1;
21232   rtx operand2;
21233   rtx _val = 0;
21234   HARD_REG_SET _regs_allocated;
21235   CLEAR_HARD_REG_SET (_regs_allocated);
21236   if ((operands[2] = peep2_find_free_register (0, 0, "q", QImode, &_regs_allocated)) == NULL_RTX)
21237     return NULL;
21238   start_sequence ();
21239 
21240   operand0 = operands[0];
21241   operand1 = operands[1];
21242   operand2 = operands[2];
21243   emit_insn (gen_rtx_SET (VOIDmode,
21244   operand2,
21245   operand1));
21246   emit_insn (gen_rtx_SET (VOIDmode,
21247   operand0,
21248   copy_rtx (operand2)));
21249   _val = get_insns ();
21250   end_sequence ();
21251   return _val;
21252 }
21253 
21254 /* ../../gcc/gcc/config/i386/i386.md:17157 */
21255 extern rtx gen_peephole2_1466 PARAMS ((rtx, rtx *));
21256 rtx
21257 gen_peephole2_1466 (curr_insn, operands)
21258      rtx curr_insn ATTRIBUTE_UNUSED;
21259      rtx *operands;
21260 {
21261   rtx operand0;
21262   rtx operand1;
21263   rtx operand2;
21264   rtx operand3;
21265   rtx _val = 0;
21266   HARD_REG_SET _regs_allocated;
21267   CLEAR_HARD_REG_SET (_regs_allocated);
21268   if ((operands[3] = peep2_find_free_register (1, 1, "r", SImode, &_regs_allocated)) == NULL_RTX)
21269     return NULL;
21270   start_sequence ();
21271 
21272   operand0 = operands[0];
21273   operand1 = operands[1];
21274   operand2 = operands[2];
21275   operand3 = operands[3];
21276   emit_insn (gen_rtx_SET (VOIDmode,
21277   operand3,
21278   operand0));
21279   emit_insn (gen_rtx_SET (VOIDmode,
21280   gen_rtx_REG (CCNOmode,
21281   17),
21282   gen_rtx_COMPARE (CCNOmode,
21283   copy_rtx (operand3),
21284   const0_rtx)));
21285   _val = get_insns ();
21286   end_sequence ();
21287   return _val;
21288 }
21289 
21290 /* ../../gcc/gcc/config/i386/i386.md:17178 */
21291 extern rtx gen_peephole2_1467 PARAMS ((rtx, rtx *));
21292 rtx
21293 gen_peephole2_1467 (curr_insn, operands)
21294      rtx curr_insn ATTRIBUTE_UNUSED;
21295      rtx *operands;
21296 {
21297   rtx operand0;
21298   rtx operand1;
21299   rtx _val = 0;
21300   HARD_REG_SET _regs_allocated;
21301   CLEAR_HARD_REG_SET (_regs_allocated);
21302   start_sequence ();
21303 
21304   operand0 = operands[0];
21305   operand1 = operands[1];
21306   emit (gen_rtx_PARALLEL (VOIDmode,
21307   gen_rtvec (2,
21308     gen_rtx_SET (VOIDmode,
21309   operand0,
21310   gen_rtx_XOR (SImode,
21311   operand1,
21312   constm1_rtx)),
21313     gen_rtx_CLOBBER (VOIDmode,
21314   gen_rtx_REG (CCmode,
21315   17)))));
21316   _val = get_insns ();
21317   end_sequence ();
21318   return _val;
21319 }
21320 
21321 /* ../../gcc/gcc/config/i386/i386.md:17192 */
21322 extern rtx gen_peephole2_1468 PARAMS ((rtx, rtx *));
21323 rtx
21324 gen_peephole2_1468 (curr_insn, operands)
21325      rtx curr_insn ATTRIBUTE_UNUSED;
21326      rtx *operands;
21327 {
21328   rtx operand0;
21329   rtx operand1;
21330   rtx _val = 0;
21331   HARD_REG_SET _regs_allocated;
21332   CLEAR_HARD_REG_SET (_regs_allocated);
21333   start_sequence ();
21334 
21335   operand0 = operands[0];
21336   operand1 = operands[1];
21337   emit (gen_rtx_PARALLEL (VOIDmode,
21338   gen_rtvec (2,
21339     gen_rtx_SET (VOIDmode,
21340   operand0,
21341   gen_rtx_XOR (HImode,
21342   operand1,
21343   constm1_rtx)),
21344     gen_rtx_CLOBBER (VOIDmode,
21345   gen_rtx_REG (CCmode,
21346   17)))));
21347   _val = get_insns ();
21348   end_sequence ();
21349   return _val;
21350 }
21351 
21352 /* ../../gcc/gcc/config/i386/i386.md:17206 */
21353 extern rtx gen_peephole2_1469 PARAMS ((rtx, rtx *));
21354 rtx
21355 gen_peephole2_1469 (curr_insn, operands)
21356      rtx curr_insn ATTRIBUTE_UNUSED;
21357      rtx *operands;
21358 {
21359   rtx operand0;
21360   rtx operand1;
21361   rtx _val = 0;
21362   HARD_REG_SET _regs_allocated;
21363   CLEAR_HARD_REG_SET (_regs_allocated);
21364   start_sequence ();
21365 
21366   operand0 = operands[0];
21367   operand1 = operands[1];
21368   emit (gen_rtx_PARALLEL (VOIDmode,
21369   gen_rtvec (2,
21370     gen_rtx_SET (VOIDmode,
21371   operand0,
21372   gen_rtx_XOR (QImode,
21373   operand1,
21374   constm1_rtx)),
21375     gen_rtx_CLOBBER (VOIDmode,
21376   gen_rtx_REG (CCmode,
21377   17)))));
21378   _val = get_insns ();
21379   end_sequence ();
21380   return _val;
21381 }
21382 
21383 /* ../../gcc/gcc/config/i386/i386.md:17227 */
21384 extern rtx gen_peephole2_1470 PARAMS ((rtx, rtx *));
21385 rtx
21386 gen_peephole2_1470 (curr_insn, operands)
21387      rtx curr_insn ATTRIBUTE_UNUSED;
21388      rtx *operands;
21389 {
21390   rtx operand0;
21391   rtx operand1;
21392   rtx _val = 0;
21393   HARD_REG_SET _regs_allocated;
21394   CLEAR_HARD_REG_SET (_regs_allocated);
21395   start_sequence ();
21396 
21397   operand0 = operands[0];
21398   operand1 = operands[1];
21399   emit (gen_rtx_PARALLEL (VOIDmode,
21400   gen_rtvec (2,
21401     gen_rtx_SET (VOIDmode,
21402   gen_rtx_REG (CCNOmode,
21403   17),
21404   gen_rtx_COMPARE (CCNOmode,
21405   gen_rtx_AND (SImode,
21406   operand0,
21407   operand1),
21408   const0_rtx)),
21409     gen_rtx_SET (VOIDmode,
21410   copy_rtx (operand0),
21411   gen_rtx_AND (SImode,
21412   copy_rtx (operand0),
21413   copy_rtx (operand1))))));
21414   _val = get_insns ();
21415   end_sequence ();
21416   return _val;
21417 }
21418 
21419 /* ../../gcc/gcc/config/i386/i386.md:17249 */
21420 extern rtx gen_peephole2_1471 PARAMS ((rtx, rtx *));
21421 rtx
21422 gen_peephole2_1471 (curr_insn, operands)
21423      rtx curr_insn ATTRIBUTE_UNUSED;
21424      rtx *operands;
21425 {
21426   rtx operand0;
21427   rtx operand1;
21428   rtx _val = 0;
21429   HARD_REG_SET _regs_allocated;
21430   CLEAR_HARD_REG_SET (_regs_allocated);
21431   start_sequence ();
21432 
21433   operand0 = operands[0];
21434   operand1 = operands[1];
21435   emit (gen_rtx_PARALLEL (VOIDmode,
21436   gen_rtvec (2,
21437     gen_rtx_SET (VOIDmode,
21438   gen_rtx_REG (CCNOmode,
21439   17),
21440   gen_rtx_COMPARE (CCNOmode,
21441   gen_rtx_AND (QImode,
21442   operand0,
21443   operand1),
21444   const0_rtx)),
21445     gen_rtx_SET (VOIDmode,
21446   copy_rtx (operand0),
21447   gen_rtx_AND (QImode,
21448   copy_rtx (operand0),
21449   copy_rtx (operand1))))));
21450   _val = get_insns ();
21451   end_sequence ();
21452   return _val;
21453 }
21454 
21455 /* ../../gcc/gcc/config/i386/i386.md:17267 */
21456 extern rtx gen_peephole2_1472 PARAMS ((rtx, rtx *));
21457 rtx
21458 gen_peephole2_1472 (curr_insn, operands)
21459      rtx curr_insn ATTRIBUTE_UNUSED;
21460      rtx *operands;
21461 {
21462   rtx operand0;
21463   rtx operand1;
21464   rtx _val = 0;
21465   HARD_REG_SET _regs_allocated;
21466   CLEAR_HARD_REG_SET (_regs_allocated);
21467   start_sequence ();
21468 
21469   operand0 = operands[0];
21470   operand1 = operands[1];
21471   emit (gen_rtx_PARALLEL (VOIDmode,
21472   gen_rtvec (2,
21473     gen_rtx_SET (VOIDmode,
21474   gen_rtx_REG (CCNOmode,
21475   17),
21476   gen_rtx_COMPARE (CCNOmode,
21477   gen_rtx_AND (SImode,
21478   gen_rtx_ZERO_EXTRACT (SImode,
21479   operand0,
21480   GEN_INT (8LL),
21481   GEN_INT (8LL)),
21482   operand1),
21483   const0_rtx)),
21484     gen_rtx_SET (VOIDmode,
21485   gen_rtx_ZERO_EXTRACT (SImode,
21486   copy_rtx (operand0),
21487   GEN_INT (8LL),
21488   GEN_INT (8LL)),
21489   gen_rtx_AND (SImode,
21490   gen_rtx_ZERO_EXTRACT (SImode,
21491   copy_rtx (operand0),
21492   GEN_INT (8LL),
21493   GEN_INT (8LL)),
21494   copy_rtx (operand1))))));
21495   _val = get_insns ();
21496   end_sequence ();
21497   return _val;
21498 }
21499 
21500 /* ../../gcc/gcc/config/i386/i386.md:17302 */
21501 extern rtx gen_peephole2_1473 PARAMS ((rtx, rtx *));
21502 rtx
21503 gen_peephole2_1473 (curr_insn, operands)
21504      rtx curr_insn ATTRIBUTE_UNUSED;
21505      rtx *operands;
21506 {
21507   rtx operand0;
21508   rtx operand1;
21509   rtx operand2;
21510   rtx operand3;
21511   rtx _val = 0;
21512   HARD_REG_SET _regs_allocated;
21513   CLEAR_HARD_REG_SET (_regs_allocated);
21514   if ((operands[2] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
21515     return NULL;
21516   start_sequence ();
21517 
21518   operand0 = operands[0];
21519   operand1 = operands[1];
21520   operand2 = operands[2];
21521   operand3 = operands[3];
21522   emit_insn (gen_rtx_SET (VOIDmode,
21523   operand2,
21524   operand1));
21525   emit (gen_rtx_PARALLEL (VOIDmode,
21526   gen_rtvec (2,
21527     gen_rtx_SET (VOIDmode,
21528   operand0,
21529   gen_rtx (GET_CODE (operand3), GET_MODE (operand3),
21530     copy_rtx (operand0),
21531     copy_rtx (operand2))),
21532     gen_rtx_CLOBBER (VOIDmode,
21533   gen_rtx_REG (CCmode,
21534   17)))));
21535   _val = get_insns ();
21536   end_sequence ();
21537   return _val;
21538 }
21539 
21540 /* ../../gcc/gcc/config/i386/i386.md:17316 */
21541 extern rtx gen_peephole2_1474 PARAMS ((rtx, rtx *));
21542 rtx
21543 gen_peephole2_1474 (curr_insn, operands)
21544      rtx curr_insn ATTRIBUTE_UNUSED;
21545      rtx *operands;
21546 {
21547   rtx operand0;
21548   rtx operand1;
21549   rtx operand2;
21550   rtx operand3;
21551   rtx _val = 0;
21552   HARD_REG_SET _regs_allocated;
21553   CLEAR_HARD_REG_SET (_regs_allocated);
21554   if ((operands[2] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
21555     return NULL;
21556   start_sequence ();
21557 
21558   operand0 = operands[0];
21559   operand1 = operands[1];
21560   operand2 = operands[2];
21561   operand3 = operands[3];
21562   emit_insn (gen_rtx_SET (VOIDmode,
21563   operand2,
21564   operand1));
21565   emit (gen_rtx_PARALLEL (VOIDmode,
21566   gen_rtvec (2,
21567     gen_rtx_SET (VOIDmode,
21568   operand0,
21569   gen_rtx (GET_CODE (operand3), GET_MODE (operand3),
21570     copy_rtx (operand2),
21571     copy_rtx (operand0))),
21572     gen_rtx_CLOBBER (VOIDmode,
21573   gen_rtx_REG (CCmode,
21574   17)))));
21575   _val = get_insns ();
21576   end_sequence ();
21577   return _val;
21578 }
21579 
21580 /* ../../gcc/gcc/config/i386/i386.md:17336 */
21581 extern rtx gen_peephole2_1475 PARAMS ((rtx, rtx *));
21582 rtx
21583 gen_peephole2_1475 (curr_insn, operands)
21584      rtx curr_insn ATTRIBUTE_UNUSED;
21585      rtx *operands;
21586 {
21587   rtx operand0;
21588   rtx operand1;
21589   rtx operand2;
21590   rtx operand3;
21591   rtx _val = 0;
21592   HARD_REG_SET _regs_allocated;
21593   CLEAR_HARD_REG_SET (_regs_allocated);
21594   if ((operands[2] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
21595     return NULL;
21596   start_sequence ();
21597 
21598   operand0 = operands[0];
21599   operand1 = operands[1];
21600   operand2 = operands[2];
21601   operand3 = operands[3];
21602   emit_insn (gen_rtx_SET (VOIDmode,
21603   operand2,
21604   operand0));
21605   emit (gen_rtx_PARALLEL (VOIDmode,
21606   gen_rtvec (2,
21607     gen_rtx_SET (VOIDmode,
21608   copy_rtx (operand2),
21609   gen_rtx (GET_CODE (operand3), GET_MODE (operand3),
21610     copy_rtx (operand2),
21611     operand1)),
21612     gen_rtx_CLOBBER (VOIDmode,
21613   gen_rtx_REG (CCmode,
21614   17)))));
21615   emit_insn (gen_rtx_SET (VOIDmode,
21616   copy_rtx (operand0),
21617   copy_rtx (operand2)));
21618   _val = get_insns ();
21619   end_sequence ();
21620   return _val;
21621 }
21622 
21623 /* ../../gcc/gcc/config/i386/i386.md:17351 */
21624 extern rtx gen_peephole2_1476 PARAMS ((rtx, rtx *));
21625 rtx
21626 gen_peephole2_1476 (curr_insn, operands)
21627      rtx curr_insn ATTRIBUTE_UNUSED;
21628      rtx *operands;
21629 {
21630   rtx operand0;
21631   rtx operand1;
21632   rtx operand2;
21633   rtx operand3;
21634   rtx _val = 0;
21635   HARD_REG_SET _regs_allocated;
21636   CLEAR_HARD_REG_SET (_regs_allocated);
21637   if ((operands[2] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
21638     return NULL;
21639   start_sequence ();
21640 
21641   operand0 = operands[0];
21642   operand1 = operands[1];
21643   operand2 = operands[2];
21644   operand3 = operands[3];
21645   emit_insn (gen_rtx_SET (VOIDmode,
21646   operand2,
21647   operand0));
21648   emit (gen_rtx_PARALLEL (VOIDmode,
21649   gen_rtvec (2,
21650     gen_rtx_SET (VOIDmode,
21651   copy_rtx (operand2),
21652   gen_rtx (GET_CODE (operand3), GET_MODE (operand3),
21653     operand1,
21654     copy_rtx (operand2))),
21655     gen_rtx_CLOBBER (VOIDmode,
21656   gen_rtx_REG (CCmode,
21657   17)))));
21658   emit_insn (gen_rtx_SET (VOIDmode,
21659   copy_rtx (operand0),
21660   copy_rtx (operand2)));
21661   _val = get_insns ();
21662   end_sequence ();
21663   return _val;
21664 }
21665 
21666 /* ../../gcc/gcc/config/i386/i386.md:17367 */
21667 extern rtx gen_peephole2_1477 PARAMS ((rtx, rtx *));
21668 rtx
21669 gen_peephole2_1477 (curr_insn, operands)
21670      rtx curr_insn ATTRIBUTE_UNUSED;
21671      rtx *operands;
21672 {
21673   rtx operand0;
21674   rtx _val = 0;
21675   HARD_REG_SET _regs_allocated;
21676   CLEAR_HARD_REG_SET (_regs_allocated);
21677   start_sequence ();
21678 operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
21679             true_regnum (operands[0]));
21680   operand0 = operands[0];
21681   emit (gen_rtx_PARALLEL (VOIDmode,
21682   gen_rtvec (2,
21683     gen_rtx_SET (VOIDmode,
21684   operand0,
21685   const0_rtx),
21686     gen_rtx_CLOBBER (VOIDmode,
21687   gen_rtx_REG (CCmode,
21688   17)))));
21689   _val = get_insns ();
21690   end_sequence ();
21691   return _val;
21692 }
21693 
21694 /* ../../gcc/gcc/config/i386/i386.md:17381 */
21695 extern rtx gen_peephole2_1478 PARAMS ((rtx, rtx *));
21696 rtx
21697 gen_peephole2_1478 (curr_insn, operands)
21698      rtx curr_insn ATTRIBUTE_UNUSED;
21699      rtx *operands;
21700 {
21701   rtx operand0;
21702   rtx _val = 0;
21703   HARD_REG_SET _regs_allocated;
21704   CLEAR_HARD_REG_SET (_regs_allocated);
21705   start_sequence ();
21706   operand0 = operands[0];
21707   emit (gen_rtx_PARALLEL (VOIDmode,
21708   gen_rtvec (2,
21709     gen_rtx_SET (VOIDmode,
21710   gen_rtx_STRICT_LOW_PART (VOIDmode,
21711   operand0),
21712   const0_rtx),
21713     gen_rtx_CLOBBER (VOIDmode,
21714   gen_rtx_REG (CCmode,
21715   17)))));
21716   _val = get_insns ();
21717   end_sequence ();
21718   return _val;
21719 }
21720 
21721 /* ../../gcc/gcc/config/i386/i386.md:17392 */
21722 extern rtx gen_peephole2_1479 PARAMS ((rtx, rtx *));
21723 rtx
21724 gen_peephole2_1479 (curr_insn, operands)
21725      rtx curr_insn ATTRIBUTE_UNUSED;
21726      rtx *operands;
21727 {
21728   rtx operand0;
21729   rtx _val = 0;
21730   HARD_REG_SET _regs_allocated;
21731   CLEAR_HARD_REG_SET (_regs_allocated);
21732   start_sequence ();
21733 operands[0] = gen_rtx_REG (GET_MODE (operands[0]) == DImode ? DImode : SImode,
21734             true_regnum (operands[0]));
21735   operand0 = operands[0];
21736   emit (gen_rtx_PARALLEL (VOIDmode,
21737   gen_rtvec (2,
21738     gen_rtx_SET (VOIDmode,
21739   operand0,
21740   constm1_rtx),
21741     gen_rtx_CLOBBER (VOIDmode,
21742   gen_rtx_REG (CCmode,
21743   17)))));
21744   _val = get_insns ();
21745   end_sequence ();
21746   return _val;
21747 }
21748 
21749 /* ../../gcc/gcc/config/i386/i386.md:17407 */
21750 extern rtx gen_peephole2_1480 PARAMS ((rtx, rtx *));
21751 rtx
21752 gen_peephole2_1480 (curr_insn, operands)
21753      rtx curr_insn ATTRIBUTE_UNUSED;
21754      rtx *operands;
21755 {
21756   rtx operand0;
21757   rtx operand1;
21758   rtx _val = 0;
21759   HARD_REG_SET _regs_allocated;
21760   CLEAR_HARD_REG_SET (_regs_allocated);
21761   start_sequence ();
21762 
21763   operand0 = operands[0];
21764   operand1 = operands[1];
21765   emit (gen_rtx_PARALLEL (VOIDmode,
21766   gen_rtvec (2,
21767     gen_rtx_SET (VOIDmode,
21768   operand0,
21769   gen_rtx_PLUS (SImode,
21770   copy_rtx (operand0),
21771   operand1)),
21772     gen_rtx_CLOBBER (VOIDmode,
21773   gen_rtx_REG (CCmode,
21774   17)))));
21775   _val = get_insns ();
21776   end_sequence ();
21777   return _val;
21778 }
21779 
21780 /* ../../gcc/gcc/config/i386/i386.md:17416 */
21781 extern rtx gen_peephole2_1481 PARAMS ((rtx, rtx *));
21782 rtx
21783 gen_peephole2_1481 (curr_insn, operands)
21784      rtx curr_insn ATTRIBUTE_UNUSED;
21785      rtx *operands;
21786 {
21787   rtx operand0;
21788   rtx operand1;
21789   rtx operand2;
21790   rtx _val = 0;
21791   HARD_REG_SET _regs_allocated;
21792   CLEAR_HARD_REG_SET (_regs_allocated);
21793   start_sequence ();
21794 operands[2] = gen_lowpart (SImode, operands[2]);
21795   operand0 = operands[0];
21796   operand1 = operands[1];
21797   operand2 = operands[2];
21798   emit (gen_rtx_PARALLEL (VOIDmode,
21799   gen_rtvec (2,
21800     gen_rtx_SET (VOIDmode,
21801   operand0,
21802   gen_rtx_PLUS (SImode,
21803   copy_rtx (operand0),
21804   operand2)),
21805     gen_rtx_CLOBBER (VOIDmode,
21806   gen_rtx_REG (CCmode,
21807   17)))));
21808   _val = get_insns ();
21809   end_sequence ();
21810   return _val;
21811 }
21812 
21813 /* ../../gcc/gcc/config/i386/i386.md:17425 */
21814 extern rtx gen_peephole2_1482 PARAMS ((rtx, rtx *));
21815 rtx
21816 gen_peephole2_1482 (curr_insn, operands)
21817      rtx curr_insn ATTRIBUTE_UNUSED;
21818      rtx *operands;
21819 {
21820   rtx operand0;
21821   rtx operand1;
21822   rtx _val = 0;
21823   HARD_REG_SET _regs_allocated;
21824   CLEAR_HARD_REG_SET (_regs_allocated);
21825   start_sequence ();
21826 
21827   operand0 = operands[0];
21828   operand1 = operands[1];
21829   emit (gen_rtx_PARALLEL (VOIDmode,
21830   gen_rtvec (2,
21831     gen_rtx_SET (VOIDmode,
21832   operand0,
21833   gen_rtx_PLUS (DImode,
21834   copy_rtx (operand0),
21835   operand1)),
21836     gen_rtx_CLOBBER (VOIDmode,
21837   gen_rtx_REG (CCmode,
21838   17)))));
21839   _val = get_insns ();
21840   end_sequence ();
21841   return _val;
21842 }
21843 
21844 /* ../../gcc/gcc/config/i386/i386.md:17434 */
21845 extern rtx gen_peephole2_1483 PARAMS ((rtx, rtx *));
21846 rtx
21847 gen_peephole2_1483 (curr_insn, operands)
21848      rtx curr_insn ATTRIBUTE_UNUSED;
21849      rtx *operands;
21850 {
21851   rtx operand0;
21852   rtx operand1;
21853   rtx operand2;
21854   rtx _val = 0;
21855   HARD_REG_SET _regs_allocated;
21856   CLEAR_HARD_REG_SET (_regs_allocated);
21857   start_sequence ();
21858 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));
21859   operand0 = operands[0];
21860   operand1 = operands[1];
21861   operand2 = operands[2];
21862   emit (gen_rtx_PARALLEL (VOIDmode,
21863   gen_rtvec (2,
21864     gen_rtx_SET (VOIDmode,
21865   operand0,
21866   gen_rtx_ASHIFT (SImode,
21867   copy_rtx (operand0),
21868   operand2)),
21869     gen_rtx_CLOBBER (VOIDmode,
21870   gen_rtx_REG (CCmode,
21871   17)))));
21872   _val = get_insns ();
21873   end_sequence ();
21874   return _val;
21875 }
21876 
21877 /* ../../gcc/gcc/config/i386/i386.md:17444 */
21878 extern rtx gen_peephole2_1484 PARAMS ((rtx, rtx *));
21879 rtx
21880 gen_peephole2_1484 (curr_insn, operands)
21881      rtx curr_insn ATTRIBUTE_UNUSED;
21882      rtx *operands;
21883 {
21884   rtx operand0;
21885   rtx operand1;
21886   rtx operand2;
21887   rtx _val = 0;
21888   HARD_REG_SET _regs_allocated;
21889   CLEAR_HARD_REG_SET (_regs_allocated);
21890   start_sequence ();
21891 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[1])));
21892   operand0 = operands[0];
21893   operand1 = operands[1];
21894   operand2 = operands[2];
21895   emit (gen_rtx_PARALLEL (VOIDmode,
21896   gen_rtvec (2,
21897     gen_rtx_SET (VOIDmode,
21898   operand0,
21899   gen_rtx_ASHIFT (DImode,
21900   copy_rtx (operand0),
21901   operand2)),
21902     gen_rtx_CLOBBER (VOIDmode,
21903   gen_rtx_REG (CCmode,
21904   17)))));
21905   _val = get_insns ();
21906   end_sequence ();
21907   return _val;
21908 }
21909 
21910 /* ../../gcc/gcc/config/i386/i386.md:17454 */
21911 extern rtx gen_peephole2_1485 PARAMS ((rtx, rtx *));
21912 rtx
21913 gen_peephole2_1485 (curr_insn, operands)
21914      rtx curr_insn ATTRIBUTE_UNUSED;
21915      rtx *operands;
21916 {
21917   rtx operand0;
21918   rtx operand1;
21919   rtx operand2;
21920   rtx _val = 0;
21921   HARD_REG_SET _regs_allocated;
21922   CLEAR_HARD_REG_SET (_regs_allocated);
21923   start_sequence ();
21924 operands[2] = GEN_INT (exact_log2 (INTVAL (operands[2])));
21925   operand0 = operands[0];
21926   operand1 = operands[1];
21927   operand2 = operands[2];
21928   emit (gen_rtx_PARALLEL (VOIDmode,
21929   gen_rtvec (2,
21930     gen_rtx_SET (VOIDmode,
21931   operand0,
21932   gen_rtx_ASHIFT (SImode,
21933   copy_rtx (operand0),
21934   operand2)),
21935     gen_rtx_CLOBBER (VOIDmode,
21936   gen_rtx_REG (CCmode,
21937   17)))));
21938   _val = get_insns ();
21939   end_sequence ();
21940   return _val;
21941 }
21942 
21943 /* ../../gcc/gcc/config/i386/i386.md:17484 */
21944 extern rtx gen_peephole2_1486 PARAMS ((rtx, rtx *));
21945 rtx
21946 gen_peephole2_1486 (curr_insn, operands)
21947      rtx curr_insn ATTRIBUTE_UNUSED;
21948      rtx *operands;
21949 {
21950   rtx operand0;
21951   rtx _val = 0;
21952   HARD_REG_SET _regs_allocated;
21953   CLEAR_HARD_REG_SET (_regs_allocated);
21954   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
21955     return NULL;
21956   start_sequence ();
21957   operand0 = operands[0];
21958   emit_insn (gen_rtx_CLOBBER (VOIDmode,
21959   operand0));
21960   emit (gen_rtx_PARALLEL (VOIDmode,
21961   gen_rtvec (2,
21962     gen_rtx_SET (VOIDmode,
21963   gen_rtx_MEM (SImode,
21964   gen_rtx_PRE_DEC (SImode,
21965   gen_rtx_REG (SImode,
21966   7))),
21967   copy_rtx (operand0)),
21968     gen_rtx_CLOBBER (VOIDmode,
21969   gen_rtx_MEM (BLKmode,
21970   gen_rtx_SCRATCH (VOIDmode))))));
21971   _val = get_insns ();
21972   end_sequence ();
21973   return _val;
21974 }
21975 
21976 /* ../../gcc/gcc/config/i386/i386.md:17494 */
21977 extern rtx gen_peephole2_1487 PARAMS ((rtx, rtx *));
21978 rtx
21979 gen_peephole2_1487 (curr_insn, operands)
21980      rtx curr_insn ATTRIBUTE_UNUSED;
21981      rtx *operands;
21982 {
21983   rtx operand0;
21984   rtx _val = 0;
21985   HARD_REG_SET _regs_allocated;
21986   CLEAR_HARD_REG_SET (_regs_allocated);
21987   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
21988     return NULL;
21989   start_sequence ();
21990   operand0 = operands[0];
21991   emit_insn (gen_rtx_CLOBBER (VOIDmode,
21992   operand0));
21993   emit_insn (gen_rtx_SET (VOIDmode,
21994   gen_rtx_MEM (SImode,
21995   gen_rtx_PRE_DEC (SImode,
21996   gen_rtx_REG (SImode,
21997   7))),
21998   copy_rtx (operand0)));
21999   emit (gen_rtx_PARALLEL (VOIDmode,
22000   gen_rtvec (2,
22001     gen_rtx_SET (VOIDmode,
22002   gen_rtx_MEM (SImode,
22003   gen_rtx_PRE_DEC (SImode,
22004   gen_rtx_REG (SImode,
22005   7))),
22006   copy_rtx (operand0)),
22007     gen_rtx_CLOBBER (VOIDmode,
22008   gen_rtx_MEM (BLKmode,
22009   gen_rtx_SCRATCH (VOIDmode))))));
22010   _val = get_insns ();
22011   end_sequence ();
22012   return _val;
22013 }
22014 
22015 /* ../../gcc/gcc/config/i386/i386.md:17506 */
22016 extern rtx gen_peephole2_1488 PARAMS ((rtx, rtx *));
22017 rtx
22018 gen_peephole2_1488 (curr_insn, operands)
22019      rtx curr_insn ATTRIBUTE_UNUSED;
22020      rtx *operands;
22021 {
22022   rtx operand0;
22023   rtx _val = 0;
22024   HARD_REG_SET _regs_allocated;
22025   CLEAR_HARD_REG_SET (_regs_allocated);
22026   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22027     return NULL;
22028   start_sequence ();
22029   operand0 = operands[0];
22030   emit_insn (gen_rtx_CLOBBER (VOIDmode,
22031   operand0));
22032   emit_insn (gen_rtx_SET (VOIDmode,
22033   gen_rtx_MEM (SImode,
22034   gen_rtx_PRE_DEC (SImode,
22035   gen_rtx_REG (SImode,
22036   7))),
22037   copy_rtx (operand0)));
22038   _val = get_insns ();
22039   end_sequence ();
22040   return _val;
22041 }
22042 
22043 /* ../../gcc/gcc/config/i386/i386.md:17514 */
22044 extern rtx gen_peephole2_1489 PARAMS ((rtx, rtx *));
22045 rtx
22046 gen_peephole2_1489 (curr_insn, operands)
22047      rtx curr_insn ATTRIBUTE_UNUSED;
22048      rtx *operands;
22049 {
22050   rtx operand0;
22051   rtx _val = 0;
22052   HARD_REG_SET _regs_allocated;
22053   CLEAR_HARD_REG_SET (_regs_allocated);
22054   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22055     return NULL;
22056   start_sequence ();
22057   operand0 = operands[0];
22058   emit_insn (gen_rtx_CLOBBER (VOIDmode,
22059   operand0));
22060   emit_insn (gen_rtx_SET (VOIDmode,
22061   gen_rtx_MEM (SImode,
22062   gen_rtx_PRE_DEC (SImode,
22063   gen_rtx_REG (SImode,
22064   7))),
22065   copy_rtx (operand0)));
22066   emit_insn (gen_rtx_SET (VOIDmode,
22067   gen_rtx_MEM (SImode,
22068   gen_rtx_PRE_DEC (SImode,
22069   gen_rtx_REG (SImode,
22070   7))),
22071   copy_rtx (operand0)));
22072   _val = get_insns ();
22073   end_sequence ();
22074   return _val;
22075 }
22076 
22077 /* ../../gcc/gcc/config/i386/i386.md:17524 */
22078 extern rtx gen_peephole2_1490 PARAMS ((rtx, rtx *));
22079 rtx
22080 gen_peephole2_1490 (curr_insn, operands)
22081      rtx curr_insn ATTRIBUTE_UNUSED;
22082      rtx *operands;
22083 {
22084   rtx operand0;
22085   rtx _val = 0;
22086   HARD_REG_SET _regs_allocated;
22087   CLEAR_HARD_REG_SET (_regs_allocated);
22088   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22089     return NULL;
22090   start_sequence ();
22091 
22092   operand0 = operands[0];
22093   emit (gen_rtx_PARALLEL (VOIDmode,
22094   gen_rtvec (3,
22095     gen_rtx_SET (VOIDmode,
22096   operand0,
22097   gen_rtx_MEM (SImode,
22098   gen_rtx_REG (SImode,
22099   7))),
22100     gen_rtx_SET (VOIDmode,
22101   gen_rtx_REG (SImode,
22102   7),
22103   gen_rtx_PLUS (SImode,
22104   gen_rtx_REG (SImode,
22105   7),
22106   GEN_INT (4LL))),
22107     gen_rtx_CLOBBER (VOIDmode,
22108   gen_rtx_MEM (BLKmode,
22109   gen_rtx_SCRATCH (VOIDmode))))));
22110   _val = get_insns ();
22111   end_sequence ();
22112   return _val;
22113 }
22114 
22115 /* ../../gcc/gcc/config/i386/i386.md:17537 */
22116 extern rtx gen_peephole2_1491 PARAMS ((rtx, rtx *));
22117 rtx
22118 gen_peephole2_1491 (curr_insn, operands)
22119      rtx curr_insn ATTRIBUTE_UNUSED;
22120      rtx *operands;
22121 {
22122   rtx operand0;
22123   rtx operand1;
22124   rtx _val = 0;
22125   HARD_REG_SET _regs_allocated;
22126   CLEAR_HARD_REG_SET (_regs_allocated);
22127   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22128     return NULL;
22129   if ((operands[1] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22130     return NULL;
22131   start_sequence ();
22132 
22133   operand0 = operands[0];
22134   operand1 = operands[1];
22135   emit (gen_rtx_PARALLEL (VOIDmode,
22136   gen_rtvec (3,
22137     gen_rtx_SET (VOIDmode,
22138   operand0,
22139   gen_rtx_MEM (SImode,
22140   gen_rtx_REG (SImode,
22141   7))),
22142     gen_rtx_SET (VOIDmode,
22143   gen_rtx_REG (SImode,
22144   7),
22145   gen_rtx_PLUS (SImode,
22146   gen_rtx_REG (SImode,
22147   7),
22148   GEN_INT (4LL))),
22149     gen_rtx_CLOBBER (VOIDmode,
22150   gen_rtx_MEM (BLKmode,
22151   gen_rtx_SCRATCH (VOIDmode))))));
22152   emit (gen_rtx_PARALLEL (VOIDmode,
22153   gen_rtvec (2,
22154     gen_rtx_SET (VOIDmode,
22155   operand1,
22156   gen_rtx_MEM (SImode,
22157   gen_rtx_REG (SImode,
22158   7))),
22159     gen_rtx_SET (VOIDmode,
22160   gen_rtx_REG (SImode,
22161   7),
22162   gen_rtx_PLUS (SImode,
22163   gen_rtx_REG (SImode,
22164   7),
22165   GEN_INT (4LL))))));
22166   _val = get_insns ();
22167   end_sequence ();
22168   return _val;
22169 }
22170 
22171 /* ../../gcc/gcc/config/i386/i386.md:17551 */
22172 extern rtx gen_peephole2_1492 PARAMS ((rtx, rtx *));
22173 rtx
22174 gen_peephole2_1492 (curr_insn, operands)
22175      rtx curr_insn ATTRIBUTE_UNUSED;
22176      rtx *operands;
22177 {
22178   rtx operand0;
22179   rtx _val = 0;
22180   HARD_REG_SET _regs_allocated;
22181   CLEAR_HARD_REG_SET (_regs_allocated);
22182   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22183     return NULL;
22184   start_sequence ();
22185 
22186   operand0 = operands[0];
22187   emit (gen_rtx_PARALLEL (VOIDmode,
22188   gen_rtvec (3,
22189     gen_rtx_SET (VOIDmode,
22190   operand0,
22191   gen_rtx_MEM (SImode,
22192   gen_rtx_REG (SImode,
22193   7))),
22194     gen_rtx_SET (VOIDmode,
22195   gen_rtx_REG (SImode,
22196   7),
22197   gen_rtx_PLUS (SImode,
22198   gen_rtx_REG (SImode,
22199   7),
22200   GEN_INT (4LL))),
22201     gen_rtx_CLOBBER (VOIDmode,
22202   gen_rtx_MEM (BLKmode,
22203   gen_rtx_SCRATCH (VOIDmode))))));
22204   emit (gen_rtx_PARALLEL (VOIDmode,
22205   gen_rtvec (2,
22206     gen_rtx_SET (VOIDmode,
22207   copy_rtx (operand0),
22208   gen_rtx_MEM (SImode,
22209   gen_rtx_REG (SImode,
22210   7))),
22211     gen_rtx_SET (VOIDmode,
22212   gen_rtx_REG (SImode,
22213   7),
22214   gen_rtx_PLUS (SImode,
22215   gen_rtx_REG (SImode,
22216   7),
22217   GEN_INT (4LL))))));
22218   _val = get_insns ();
22219   end_sequence ();
22220   return _val;
22221 }
22222 
22223 /* ../../gcc/gcc/config/i386/i386.md:17565 */
22224 extern rtx gen_peephole2_1493 PARAMS ((rtx, rtx *));
22225 rtx
22226 gen_peephole2_1493 (curr_insn, operands)
22227      rtx curr_insn ATTRIBUTE_UNUSED;
22228      rtx *operands;
22229 {
22230   rtx operand0;
22231   rtx _val = 0;
22232   HARD_REG_SET _regs_allocated;
22233   CLEAR_HARD_REG_SET (_regs_allocated);
22234   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22235     return NULL;
22236   start_sequence ();
22237 
22238   operand0 = operands[0];
22239   emit (gen_rtx_PARALLEL (VOIDmode,
22240   gen_rtvec (2,
22241     gen_rtx_SET (VOIDmode,
22242   operand0,
22243   gen_rtx_MEM (SImode,
22244   gen_rtx_REG (SImode,
22245   7))),
22246     gen_rtx_SET (VOIDmode,
22247   gen_rtx_REG (SImode,
22248   7),
22249   gen_rtx_PLUS (SImode,
22250   gen_rtx_REG (SImode,
22251   7),
22252   GEN_INT (4LL))))));
22253   _val = get_insns ();
22254   end_sequence ();
22255   return _val;
22256 }
22257 
22258 /* ../../gcc/gcc/config/i386/i386.md:17576 */
22259 extern rtx gen_peephole2_1494 PARAMS ((rtx, rtx *));
22260 rtx
22261 gen_peephole2_1494 (curr_insn, operands)
22262      rtx curr_insn ATTRIBUTE_UNUSED;
22263      rtx *operands;
22264 {
22265   rtx operand0;
22266   rtx operand1;
22267   rtx _val = 0;
22268   HARD_REG_SET _regs_allocated;
22269   CLEAR_HARD_REG_SET (_regs_allocated);
22270   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22271     return NULL;
22272   if ((operands[1] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22273     return NULL;
22274   start_sequence ();
22275 
22276   operand0 = operands[0];
22277   operand1 = operands[1];
22278   emit (gen_rtx_PARALLEL (VOIDmode,
22279   gen_rtvec (2,
22280     gen_rtx_SET (VOIDmode,
22281   operand0,
22282   gen_rtx_MEM (SImode,
22283   gen_rtx_REG (SImode,
22284   7))),
22285     gen_rtx_SET (VOIDmode,
22286   gen_rtx_REG (SImode,
22287   7),
22288   gen_rtx_PLUS (SImode,
22289   gen_rtx_REG (SImode,
22290   7),
22291   GEN_INT (4LL))))));
22292   emit (gen_rtx_PARALLEL (VOIDmode,
22293   gen_rtvec (2,
22294     gen_rtx_SET (VOIDmode,
22295   operand1,
22296   gen_rtx_MEM (SImode,
22297   gen_rtx_REG (SImode,
22298   7))),
22299     gen_rtx_SET (VOIDmode,
22300   gen_rtx_REG (SImode,
22301   7),
22302   gen_rtx_PLUS (SImode,
22303   gen_rtx_REG (SImode,
22304   7),
22305   GEN_INT (4LL))))));
22306   _val = get_insns ();
22307   end_sequence ();
22308   return _val;
22309 }
22310 
22311 /* ../../gcc/gcc/config/i386/i386.md:17588 */
22312 extern rtx gen_peephole2_1495 PARAMS ((rtx, rtx *));
22313 rtx
22314 gen_peephole2_1495 (curr_insn, operands)
22315      rtx curr_insn ATTRIBUTE_UNUSED;
22316      rtx *operands;
22317 {
22318   rtx operand0;
22319   rtx _val = 0;
22320   HARD_REG_SET _regs_allocated;
22321   CLEAR_HARD_REG_SET (_regs_allocated);
22322   if ((operands[0] = peep2_find_free_register (0, 0, "r", SImode, &_regs_allocated)) == NULL_RTX)
22323     return NULL;
22324   start_sequence ();
22325 
22326   operand0 = operands[0];
22327   emit (gen_rtx_PARALLEL (VOIDmode,
22328   gen_rtvec (2,
22329     gen_rtx_SET (VOIDmode,
22330   operand0,
22331   gen_rtx_MEM (SImode,
22332   gen_rtx_REG (SImode,
22333   7))),
22334     gen_rtx_SET (VOIDmode,
22335   gen_rtx_REG (SImode,
22336   7),
22337   gen_rtx_PLUS (SImode,
22338   gen_rtx_REG (SImode,
22339   7),
22340   GEN_INT (4LL))))));
22341   emit (gen_rtx_PARALLEL (VOIDmode,
22342   gen_rtvec (2,
22343     gen_rtx_SET (VOIDmode,
22344   copy_rtx (operand0),
22345   gen_rtx_MEM (SImode,
22346   gen_rtx_REG (SImode,
22347   7))),
22348     gen_rtx_SET (VOIDmode,
22349   gen_rtx_REG (SImode,
22350   7),
22351   gen_rtx_PLUS (SImode,
22352   gen_rtx_REG (SImode,
22353   7),
22354   GEN_INT (4LL))))));
22355   _val = get_insns ();
22356   end_sequence ();
22357   return _val;
22358 }
22359 
22360 /* ../../gcc/gcc/config/i386/i386.md:17601 */
22361 extern rtx gen_peephole2_1496 PARAMS ((rtx, rtx *));
22362 rtx
22363 gen_peephole2_1496 (curr_insn, operands)
22364      rtx curr_insn ATTRIBUTE_UNUSED;
22365      rtx *operands;
22366 {
22367   rtx operand0;
22368   rtx operand1;
22369   rtx _val = 0;
22370   HARD_REG_SET _regs_allocated;
22371   CLEAR_HARD_REG_SET (_regs_allocated);
22372   start_sequence ();
22373 
22374   operand0 = operands[0];
22375   operand1 = operands[1];
22376   emit (gen_rtx_PARALLEL (VOIDmode,
22377   gen_rtvec (2,
22378     gen_rtx_SET (VOIDmode,
22379   gen_rtx_REG (CCGCmode,
22380   17),
22381   gen_rtx_COMPARE (CCGCmode,
22382   operand0,
22383   operand1)),
22384     gen_rtx_CLOBBER (VOIDmode,
22385   copy_rtx (operand0)))));
22386   _val = get_insns ();
22387   end_sequence ();
22388   return _val;
22389 }
22390 
22391 /* ../../gcc/gcc/config/i386/i386.md:17613 */
22392 extern rtx gen_peephole2_1497 PARAMS ((rtx, rtx *));
22393 rtx
22394 gen_peephole2_1497 (curr_insn, operands)
22395      rtx curr_insn ATTRIBUTE_UNUSED;
22396      rtx *operands;
22397 {
22398   rtx operand0;
22399   rtx operand1;
22400   rtx _val = 0;
22401   HARD_REG_SET _regs_allocated;
22402   CLEAR_HARD_REG_SET (_regs_allocated);
22403   start_sequence ();
22404 
22405   operand0 = operands[0];
22406   operand1 = operands[1];
22407   emit (gen_rtx_PARALLEL (VOIDmode,
22408   gen_rtvec (2,
22409     gen_rtx_SET (VOIDmode,
22410   gen_rtx_REG (CCGCmode,
22411   17),
22412   gen_rtx_COMPARE (CCGCmode,
22413   operand0,
22414   operand1)),
22415     gen_rtx_CLOBBER (VOIDmode,
22416   copy_rtx (operand0)))));
22417   _val = get_insns ();
22418   end_sequence ();
22419   return _val;
22420 }
22421 
22422 /* ../../gcc/gcc/config/i386/i386.md:17625 */
22423 extern rtx gen_peephole2_1498 PARAMS ((rtx, rtx *));
22424 rtx
22425 gen_peephole2_1498 (curr_insn, operands)
22426      rtx curr_insn ATTRIBUTE_UNUSED;
22427      rtx *operands;
22428 {
22429   rtx operand0;
22430   rtx operand1;
22431   rtx _val = 0;
22432   HARD_REG_SET _regs_allocated;
22433   CLEAR_HARD_REG_SET (_regs_allocated);
22434   start_sequence ();
22435 
22436   operand0 = operands[0];
22437   operand1 = operands[1];
22438   emit (gen_rtx_PARALLEL (VOIDmode,
22439   gen_rtvec (2,
22440     gen_rtx_SET (VOIDmode,
22441   gen_rtx_REG (CCGCmode,
22442   17),
22443   gen_rtx_COMPARE (CCGCmode,
22444   operand0,
22445   operand1)),
22446     gen_rtx_CLOBBER (VOIDmode,
22447   copy_rtx (operand0)))));
22448   _val = get_insns ();
22449   end_sequence ();
22450   return _val;
22451 }
22452 
22453 /* ../../gcc/gcc/config/i386/i386.md:17638 */
22454 extern rtx gen_peephole2_1499 PARAMS ((rtx, rtx *));
22455 rtx
22456 gen_peephole2_1499 (curr_insn, operands)
22457      rtx curr_insn ATTRIBUTE_UNUSED;
22458      rtx *operands;
22459 {
22460   rtx operand0;
22461   rtx _val = 0;
22462   HARD_REG_SET _regs_allocated;
22463   CLEAR_HARD_REG_SET (_regs_allocated);
22464   start_sequence ();
22465 
22466   operand0 = operands[0];
22467   emit (gen_rtx_PARALLEL (VOIDmode,
22468   gen_rtvec (2,
22469     gen_rtx_SET (VOIDmode,
22470   gen_rtx_REG (CCGCmode,
22471   17),
22472   gen_rtx_COMPARE (CCGCmode,
22473   operand0,
22474   GEN_INT (128LL))),
22475     gen_rtx_CLOBBER (VOIDmode,
22476   copy_rtx (operand0)))));
22477   _val = get_insns ();
22478   end_sequence ();
22479   return _val;
22480 }
22481 
22482 /* ../../gcc/gcc/config/i386/i386.md:17650 */
22483 extern rtx gen_peephole2_1500 PARAMS ((rtx, rtx *));
22484 rtx
22485 gen_peephole2_1500 (curr_insn, operands)
22486      rtx curr_insn ATTRIBUTE_UNUSED;
22487      rtx *operands;
22488 {
22489   rtx operand0;
22490   rtx _val = 0;
22491   HARD_REG_SET _regs_allocated;
22492   CLEAR_HARD_REG_SET (_regs_allocated);
22493   start_sequence ();
22494 
22495   operand0 = operands[0];
22496   emit (gen_rtx_PARALLEL (VOIDmode,
22497   gen_rtvec (2,
22498     gen_rtx_SET (VOIDmode,
22499   gen_rtx_REG (CCGCmode,
22500   17),
22501   gen_rtx_COMPARE (CCGCmode,
22502   operand0,
22503   GEN_INT (128LL))),
22504     gen_rtx_CLOBBER (VOIDmode,
22505   copy_rtx (operand0)))));
22506   _val = get_insns ();
22507   end_sequence ();
22508   return _val;
22509 }
22510 
22511 /* ../../gcc/gcc/config/i386/i386.md:17662 */
22512 extern rtx gen_peephole2_1501 PARAMS ((rtx, rtx *));
22513 rtx
22514 gen_peephole2_1501 (curr_insn, operands)
22515      rtx curr_insn ATTRIBUTE_UNUSED;
22516      rtx *operands;
22517 {
22518   rtx operand0;
22519   rtx _val = 0;
22520   HARD_REG_SET _regs_allocated;
22521   CLEAR_HARD_REG_SET (_regs_allocated);
22522   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22523     return NULL;
22524   start_sequence ();
22525   operand0 = operands[0];
22526   emit_insn (gen_rtx_CLOBBER (VOIDmode,
22527   operand0));
22528   emit (gen_rtx_PARALLEL (VOIDmode,
22529   gen_rtvec (2,
22530     gen_rtx_SET (VOIDmode,
22531   gen_rtx_MEM (DImode,
22532   gen_rtx_PRE_DEC (DImode,
22533   gen_rtx_REG (DImode,
22534   7))),
22535   copy_rtx (operand0)),
22536     gen_rtx_CLOBBER (VOIDmode,
22537   gen_rtx_MEM (BLKmode,
22538   gen_rtx_SCRATCH (VOIDmode))))));
22539   _val = get_insns ();
22540   end_sequence ();
22541   return _val;
22542 }
22543 
22544 /* ../../gcc/gcc/config/i386/i386.md:17672 */
22545 extern rtx gen_peephole2_1502 PARAMS ((rtx, rtx *));
22546 rtx
22547 gen_peephole2_1502 (curr_insn, operands)
22548      rtx curr_insn ATTRIBUTE_UNUSED;
22549      rtx *operands;
22550 {
22551   rtx operand0;
22552   rtx _val = 0;
22553   HARD_REG_SET _regs_allocated;
22554   CLEAR_HARD_REG_SET (_regs_allocated);
22555   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22556     return NULL;
22557   start_sequence ();
22558   operand0 = operands[0];
22559   emit_insn (gen_rtx_CLOBBER (VOIDmode,
22560   operand0));
22561   emit_insn (gen_rtx_SET (VOIDmode,
22562   gen_rtx_MEM (DImode,
22563   gen_rtx_PRE_DEC (DImode,
22564   gen_rtx_REG (DImode,
22565   7))),
22566   copy_rtx (operand0)));
22567   emit (gen_rtx_PARALLEL (VOIDmode,
22568   gen_rtvec (2,
22569     gen_rtx_SET (VOIDmode,
22570   gen_rtx_MEM (DImode,
22571   gen_rtx_PRE_DEC (DImode,
22572   gen_rtx_REG (DImode,
22573   7))),
22574   copy_rtx (operand0)),
22575     gen_rtx_CLOBBER (VOIDmode,
22576   gen_rtx_MEM (BLKmode,
22577   gen_rtx_SCRATCH (VOIDmode))))));
22578   _val = get_insns ();
22579   end_sequence ();
22580   return _val;
22581 }
22582 
22583 /* ../../gcc/gcc/config/i386/i386.md:17684 */
22584 extern rtx gen_peephole2_1503 PARAMS ((rtx, rtx *));
22585 rtx
22586 gen_peephole2_1503 (curr_insn, operands)
22587      rtx curr_insn ATTRIBUTE_UNUSED;
22588      rtx *operands;
22589 {
22590   rtx operand0;
22591   rtx _val = 0;
22592   HARD_REG_SET _regs_allocated;
22593   CLEAR_HARD_REG_SET (_regs_allocated);
22594   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22595     return NULL;
22596   start_sequence ();
22597   operand0 = operands[0];
22598   emit_insn (gen_rtx_CLOBBER (VOIDmode,
22599   operand0));
22600   emit_insn (gen_rtx_SET (VOIDmode,
22601   gen_rtx_MEM (DImode,
22602   gen_rtx_PRE_DEC (DImode,
22603   gen_rtx_REG (DImode,
22604   7))),
22605   copy_rtx (operand0)));
22606   _val = get_insns ();
22607   end_sequence ();
22608   return _val;
22609 }
22610 
22611 /* ../../gcc/gcc/config/i386/i386.md:17692 */
22612 extern rtx gen_peephole2_1504 PARAMS ((rtx, rtx *));
22613 rtx
22614 gen_peephole2_1504 (curr_insn, operands)
22615      rtx curr_insn ATTRIBUTE_UNUSED;
22616      rtx *operands;
22617 {
22618   rtx operand0;
22619   rtx _val = 0;
22620   HARD_REG_SET _regs_allocated;
22621   CLEAR_HARD_REG_SET (_regs_allocated);
22622   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22623     return NULL;
22624   start_sequence ();
22625   operand0 = operands[0];
22626   emit_insn (gen_rtx_CLOBBER (VOIDmode,
22627   operand0));
22628   emit_insn (gen_rtx_SET (VOIDmode,
22629   gen_rtx_MEM (DImode,
22630   gen_rtx_PRE_DEC (DImode,
22631   gen_rtx_REG (DImode,
22632   7))),
22633   copy_rtx (operand0)));
22634   emit_insn (gen_rtx_SET (VOIDmode,
22635   gen_rtx_MEM (DImode,
22636   gen_rtx_PRE_DEC (DImode,
22637   gen_rtx_REG (DImode,
22638   7))),
22639   copy_rtx (operand0)));
22640   _val = get_insns ();
22641   end_sequence ();
22642   return _val;
22643 }
22644 
22645 /* ../../gcc/gcc/config/i386/i386.md:17702 */
22646 extern rtx gen_peephole2_1505 PARAMS ((rtx, rtx *));
22647 rtx
22648 gen_peephole2_1505 (curr_insn, operands)
22649      rtx curr_insn ATTRIBUTE_UNUSED;
22650      rtx *operands;
22651 {
22652   rtx operand0;
22653   rtx _val = 0;
22654   HARD_REG_SET _regs_allocated;
22655   CLEAR_HARD_REG_SET (_regs_allocated);
22656   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22657     return NULL;
22658   start_sequence ();
22659 
22660   operand0 = operands[0];
22661   emit (gen_rtx_PARALLEL (VOIDmode,
22662   gen_rtvec (3,
22663     gen_rtx_SET (VOIDmode,
22664   operand0,
22665   gen_rtx_MEM (DImode,
22666   gen_rtx_REG (DImode,
22667   7))),
22668     gen_rtx_SET (VOIDmode,
22669   gen_rtx_REG (DImode,
22670   7),
22671   gen_rtx_PLUS (DImode,
22672   gen_rtx_REG (DImode,
22673   7),
22674   GEN_INT (8LL))),
22675     gen_rtx_CLOBBER (VOIDmode,
22676   gen_rtx_MEM (BLKmode,
22677   gen_rtx_SCRATCH (VOIDmode))))));
22678   _val = get_insns ();
22679   end_sequence ();
22680   return _val;
22681 }
22682 
22683 /* ../../gcc/gcc/config/i386/i386.md:17715 */
22684 extern rtx gen_peephole2_1506 PARAMS ((rtx, rtx *));
22685 rtx
22686 gen_peephole2_1506 (curr_insn, operands)
22687      rtx curr_insn ATTRIBUTE_UNUSED;
22688      rtx *operands;
22689 {
22690   rtx operand0;
22691   rtx operand1;
22692   rtx _val = 0;
22693   HARD_REG_SET _regs_allocated;
22694   CLEAR_HARD_REG_SET (_regs_allocated);
22695   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22696     return NULL;
22697   if ((operands[1] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22698     return NULL;
22699   start_sequence ();
22700 
22701   operand0 = operands[0];
22702   operand1 = operands[1];
22703   emit (gen_rtx_PARALLEL (VOIDmode,
22704   gen_rtvec (3,
22705     gen_rtx_SET (VOIDmode,
22706   operand0,
22707   gen_rtx_MEM (DImode,
22708   gen_rtx_REG (DImode,
22709   7))),
22710     gen_rtx_SET (VOIDmode,
22711   gen_rtx_REG (DImode,
22712   7),
22713   gen_rtx_PLUS (DImode,
22714   gen_rtx_REG (DImode,
22715   7),
22716   GEN_INT (8LL))),
22717     gen_rtx_CLOBBER (VOIDmode,
22718   gen_rtx_MEM (BLKmode,
22719   gen_rtx_SCRATCH (VOIDmode))))));
22720   emit (gen_rtx_PARALLEL (VOIDmode,
22721   gen_rtvec (2,
22722     gen_rtx_SET (VOIDmode,
22723   operand1,
22724   gen_rtx_MEM (DImode,
22725   gen_rtx_REG (DImode,
22726   7))),
22727     gen_rtx_SET (VOIDmode,
22728   gen_rtx_REG (DImode,
22729   7),
22730   gen_rtx_PLUS (DImode,
22731   gen_rtx_REG (DImode,
22732   7),
22733   GEN_INT (8LL))))));
22734   _val = get_insns ();
22735   end_sequence ();
22736   return _val;
22737 }
22738 
22739 /* ../../gcc/gcc/config/i386/i386.md:17729 */
22740 extern rtx gen_peephole2_1507 PARAMS ((rtx, rtx *));
22741 rtx
22742 gen_peephole2_1507 (curr_insn, operands)
22743      rtx curr_insn ATTRIBUTE_UNUSED;
22744      rtx *operands;
22745 {
22746   rtx operand0;
22747   rtx _val = 0;
22748   HARD_REG_SET _regs_allocated;
22749   CLEAR_HARD_REG_SET (_regs_allocated);
22750   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22751     return NULL;
22752   start_sequence ();
22753 
22754   operand0 = operands[0];
22755   emit (gen_rtx_PARALLEL (VOIDmode,
22756   gen_rtvec (3,
22757     gen_rtx_SET (VOIDmode,
22758   operand0,
22759   gen_rtx_MEM (DImode,
22760   gen_rtx_REG (DImode,
22761   7))),
22762     gen_rtx_SET (VOIDmode,
22763   gen_rtx_REG (DImode,
22764   7),
22765   gen_rtx_PLUS (DImode,
22766   gen_rtx_REG (DImode,
22767   7),
22768   GEN_INT (8LL))),
22769     gen_rtx_CLOBBER (VOIDmode,
22770   gen_rtx_MEM (BLKmode,
22771   gen_rtx_SCRATCH (VOIDmode))))));
22772   emit (gen_rtx_PARALLEL (VOIDmode,
22773   gen_rtvec (2,
22774     gen_rtx_SET (VOIDmode,
22775   copy_rtx (operand0),
22776   gen_rtx_MEM (DImode,
22777   gen_rtx_REG (DImode,
22778   7))),
22779     gen_rtx_SET (VOIDmode,
22780   gen_rtx_REG (DImode,
22781   7),
22782   gen_rtx_PLUS (DImode,
22783   gen_rtx_REG (DImode,
22784   7),
22785   GEN_INT (8LL))))));
22786   _val = get_insns ();
22787   end_sequence ();
22788   return _val;
22789 }
22790 
22791 /* ../../gcc/gcc/config/i386/i386.md:17743 */
22792 extern rtx gen_peephole2_1508 PARAMS ((rtx, rtx *));
22793 rtx
22794 gen_peephole2_1508 (curr_insn, operands)
22795      rtx curr_insn ATTRIBUTE_UNUSED;
22796      rtx *operands;
22797 {
22798   rtx operand0;
22799   rtx _val = 0;
22800   HARD_REG_SET _regs_allocated;
22801   CLEAR_HARD_REG_SET (_regs_allocated);
22802   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22803     return NULL;
22804   start_sequence ();
22805 
22806   operand0 = operands[0];
22807   emit (gen_rtx_PARALLEL (VOIDmode,
22808   gen_rtvec (2,
22809     gen_rtx_SET (VOIDmode,
22810   operand0,
22811   gen_rtx_MEM (DImode,
22812   gen_rtx_REG (DImode,
22813   7))),
22814     gen_rtx_SET (VOIDmode,
22815   gen_rtx_REG (DImode,
22816   7),
22817   gen_rtx_PLUS (DImode,
22818   gen_rtx_REG (DImode,
22819   7),
22820   GEN_INT (8LL))))));
22821   _val = get_insns ();
22822   end_sequence ();
22823   return _val;
22824 }
22825 
22826 /* ../../gcc/gcc/config/i386/i386.md:17754 */
22827 extern rtx gen_peephole2_1509 PARAMS ((rtx, rtx *));
22828 rtx
22829 gen_peephole2_1509 (curr_insn, operands)
22830      rtx curr_insn ATTRIBUTE_UNUSED;
22831      rtx *operands;
22832 {
22833   rtx operand0;
22834   rtx operand1;
22835   rtx _val = 0;
22836   HARD_REG_SET _regs_allocated;
22837   CLEAR_HARD_REG_SET (_regs_allocated);
22838   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22839     return NULL;
22840   if ((operands[1] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22841     return NULL;
22842   start_sequence ();
22843 
22844   operand0 = operands[0];
22845   operand1 = operands[1];
22846   emit (gen_rtx_PARALLEL (VOIDmode,
22847   gen_rtvec (2,
22848     gen_rtx_SET (VOIDmode,
22849   operand0,
22850   gen_rtx_MEM (DImode,
22851   gen_rtx_REG (DImode,
22852   7))),
22853     gen_rtx_SET (VOIDmode,
22854   gen_rtx_REG (DImode,
22855   7),
22856   gen_rtx_PLUS (DImode,
22857   gen_rtx_REG (DImode,
22858   7),
22859   GEN_INT (8LL))))));
22860   emit (gen_rtx_PARALLEL (VOIDmode,
22861   gen_rtvec (2,
22862     gen_rtx_SET (VOIDmode,
22863   operand1,
22864   gen_rtx_MEM (DImode,
22865   gen_rtx_REG (DImode,
22866   7))),
22867     gen_rtx_SET (VOIDmode,
22868   gen_rtx_REG (DImode,
22869   7),
22870   gen_rtx_PLUS (DImode,
22871   gen_rtx_REG (DImode,
22872   7),
22873   GEN_INT (8LL))))));
22874   _val = get_insns ();
22875   end_sequence ();
22876   return _val;
22877 }
22878 
22879 /* ../../gcc/gcc/config/i386/i386.md:17766 */
22880 extern rtx gen_peephole2_1510 PARAMS ((rtx, rtx *));
22881 rtx
22882 gen_peephole2_1510 (curr_insn, operands)
22883      rtx curr_insn ATTRIBUTE_UNUSED;
22884      rtx *operands;
22885 {
22886   rtx operand0;
22887   rtx _val = 0;
22888   HARD_REG_SET _regs_allocated;
22889   CLEAR_HARD_REG_SET (_regs_allocated);
22890   if ((operands[0] = peep2_find_free_register (0, 0, "r", DImode, &_regs_allocated)) == NULL_RTX)
22891     return NULL;
22892   start_sequence ();
22893 
22894   operand0 = operands[0];
22895   emit (gen_rtx_PARALLEL (VOIDmode,
22896   gen_rtvec (2,
22897     gen_rtx_SET (VOIDmode,
22898   operand0,
22899   gen_rtx_MEM (DImode,
22900   gen_rtx_REG (DImode,
22901   7))),
22902     gen_rtx_SET (VOIDmode,
22903   gen_rtx_REG (DImode,
22904   7),
22905   gen_rtx_PLUS (DImode,
22906   gen_rtx_REG (DImode,
22907   7),
22908   GEN_INT (8LL))))));
22909   emit (gen_rtx_PARALLEL (VOIDmode,
22910   gen_rtvec (2,
22911     gen_rtx_SET (VOIDmode,
22912   copy_rtx (operand0),
22913   gen_rtx_MEM (DImode,
22914   gen_rtx_REG (DImode,
22915   7))),
22916     gen_rtx_SET (VOIDmode,
22917   gen_rtx_REG (DImode,
22918   7),
22919   gen_rtx_PLUS (DImode,
22920   gen_rtx_REG (DImode,
22921   7),
22922   GEN_INT (8LL))))));
22923   _val = get_insns ();
22924   end_sequence ();
22925   return _val;
22926 }
22927 
22928 /* ../../gcc/gcc/config/i386/i386.md:17905 */
22929 rtx
22930 gen_conditional_trap (operand0, operand1)
22931      rtx operand0;
22932      rtx operand1;
22933 {
22934   rtx operand2;
22935   rtx _val = 0;
22936   start_sequence ();
22937   {
22938     rtx operands[3];
22939     operands[0] = operand0;
22940     operands[1] = operand1;
22941 {
22942   emit_insn (gen_rtx_TRAP_IF (VOIDmode,
22943             ix86_expand_compare (GET_CODE (operands[0]),
22944                NULL, NULL),
22945             operands[1]));
22946   DONE;
22947 }
22948     operand0 = operands[0];
22949     operand1 = operands[1];
22950     operand2 = operands[2];
22951   }
22952   emit_insn (gen_rtx_TRAP_IF (VOIDmode,
22953   gen_rtx (GET_CODE (operand0), VOIDmode,
22954     operand2,
22955     const0_rtx),
22956   operand1));
22957   _val = get_insns ();
22958   end_sequence ();
22959   return _val;
22960 }
22961 
22962 /* ../../gcc/gcc/config/i386/i386.md:18019 */
22963 rtx
22964 gen_movti (operand0, operand1)
22965      rtx operand0;
22966      rtx operand1;
22967 {
22968   rtx _val = 0;
22969   start_sequence ();
22970   {
22971     rtx operands[2];
22972     operands[0] = operand0;
22973     operands[1] = operand1;
22974 {
22975   if (TARGET_64BIT)
22976     ix86_expand_move (TImode, operands);
22977   else
22978     ix86_expand_vector_move (TImode, operands);
22979   DONE;
22980 }
22981     operand0 = operands[0];
22982     operand1 = operands[1];
22983   }
22984   emit_insn (gen_rtx_SET (VOIDmode,
22985   operand0,
22986   operand1));
22987   _val = get_insns ();
22988   end_sequence ();
22989   return _val;
22990 }
22991 
22992 /* ../../gcc/gcc/config/i386/i386.md:18067 */
22993 rtx
22994 gen_movv2df (operand0, operand1)
22995      rtx operand0;
22996      rtx operand1;
22997 {
22998   rtx _val = 0;
22999   start_sequence ();
23000   {
23001     rtx operands[2];
23002     operands[0] = operand0;
23003     operands[1] = operand1;
23004 {
23005   ix86_expand_vector_move (V2DFmode, operands);
23006   DONE;
23007 }
23008     operand0 = operands[0];
23009     operand1 = operands[1];
23010   }
23011   emit_insn (gen_rtx_SET (VOIDmode,
23012   operand0,
23013   operand1));
23014   _val = get_insns ();
23015   end_sequence ();
23016   return _val;
23017 }
23018 
23019 /* ../../gcc/gcc/config/i386/i386.md:18076 */
23020 rtx
23021 gen_movv8hi (operand0, operand1)
23022      rtx operand0;
23023      rtx operand1;
23024 {
23025   rtx _val = 0;
23026   start_sequence ();
23027   {
23028     rtx operands[2];
23029     operands[0] = operand0;
23030     operands[1] = operand1;
23031 {
23032   ix86_expand_vector_move (V8HImode, operands);
23033   DONE;
23034 }
23035     operand0 = operands[0];
23036     operand1 = operands[1];
23037   }
23038   emit_insn (gen_rtx_SET (VOIDmode,
23039   operand0,
23040   operand1));
23041   _val = get_insns ();
23042   end_sequence ();
23043   return _val;
23044 }
23045 
23046 /* ../../gcc/gcc/config/i386/i386.md:18085 */
23047 rtx
23048 gen_movv16qi (operand0, operand1)
23049      rtx operand0;
23050      rtx operand1;
23051 {
23052   rtx _val = 0;
23053   start_sequence ();
23054   {
23055     rtx operands[2];
23056     operands[0] = operand0;
23057     operands[1] = operand1;
23058 {
23059   ix86_expand_vector_move (V16QImode, operands);
23060   DONE;
23061 }
23062     operand0 = operands[0];
23063     operand1 = operands[1];
23064   }
23065   emit_insn (gen_rtx_SET (VOIDmode,
23066   operand0,
23067   operand1));
23068   _val = get_insns ();
23069   end_sequence ();
23070   return _val;
23071 }
23072 
23073 /* ../../gcc/gcc/config/i386/i386.md:18094 */
23074 rtx
23075 gen_movv4sf (operand0, operand1)
23076      rtx operand0;
23077      rtx operand1;
23078 {
23079   rtx _val = 0;
23080   start_sequence ();
23081   {
23082     rtx operands[2];
23083     operands[0] = operand0;
23084     operands[1] = operand1;
23085 {
23086   ix86_expand_vector_move (V4SFmode, operands);
23087   DONE;
23088 }
23089     operand0 = operands[0];
23090     operand1 = operands[1];
23091   }
23092   emit_insn (gen_rtx_SET (VOIDmode,
23093   operand0,
23094   operand1));
23095   _val = get_insns ();
23096   end_sequence ();
23097   return _val;
23098 }
23099 
23100 /* ../../gcc/gcc/config/i386/i386.md:18103 */
23101 rtx
23102 gen_movv4si (operand0, operand1)
23103      rtx operand0;
23104      rtx operand1;
23105 {
23106   rtx _val = 0;
23107   start_sequence ();
23108   {
23109     rtx operands[2];
23110     operands[0] = operand0;
23111     operands[1] = operand1;
23112 {
23113   ix86_expand_vector_move (V4SImode, operands);
23114   DONE;
23115 }
23116     operand0 = operands[0];
23117     operand1 = operands[1];
23118   }
23119   emit_insn (gen_rtx_SET (VOIDmode,
23120   operand0,
23121   operand1));
23122   _val = get_insns ();
23123   end_sequence ();
23124   return _val;
23125 }
23126 
23127 /* ../../gcc/gcc/config/i386/i386.md:18112 */
23128 rtx
23129 gen_movv2di (operand0, operand1)
23130      rtx operand0;
23131      rtx operand1;
23132 {
23133   rtx _val = 0;
23134   start_sequence ();
23135   {
23136     rtx operands[2];
23137     operands[0] = operand0;
23138     operands[1] = operand1;
23139 {
23140   ix86_expand_vector_move (V2DImode, operands);
23141   DONE;
23142 }
23143     operand0 = operands[0];
23144     operand1 = operands[1];
23145   }
23146   emit_insn (gen_rtx_SET (VOIDmode,
23147   operand0,
23148   operand1));
23149   _val = get_insns ();
23150   end_sequence ();
23151   return _val;
23152 }
23153 
23154 /* ../../gcc/gcc/config/i386/i386.md:18121 */
23155 rtx
23156 gen_movv2si (operand0, operand1)
23157      rtx operand0;
23158      rtx operand1;
23159 {
23160   rtx _val = 0;
23161   start_sequence ();
23162   {
23163     rtx operands[2];
23164     operands[0] = operand0;
23165     operands[1] = operand1;
23166 {
23167   ix86_expand_vector_move (V2SImode, operands);
23168   DONE;
23169 }
23170     operand0 = operands[0];
23171     operand1 = operands[1];
23172   }
23173   emit_insn (gen_rtx_SET (VOIDmode,
23174   operand0,
23175   operand1));
23176   _val = get_insns ();
23177   end_sequence ();
23178   return _val;
23179 }
23180 
23181 /* ../../gcc/gcc/config/i386/i386.md:18130 */
23182 rtx
23183 gen_movv4hi (operand0, operand1)
23184      rtx operand0;
23185      rtx operand1;
23186 {
23187   rtx _val = 0;
23188   start_sequence ();
23189   {
23190     rtx operands[2];
23191     operands[0] = operand0;
23192     operands[1] = operand1;
23193 {
23194   ix86_expand_vector_move (V4HImode, operands);
23195   DONE;
23196 }
23197     operand0 = operands[0];
23198     operand1 = operands[1];
23199   }
23200   emit_insn (gen_rtx_SET (VOIDmode,
23201   operand0,
23202   operand1));
23203   _val = get_insns ();
23204   end_sequence ();
23205   return _val;
23206 }
23207 
23208 /* ../../gcc/gcc/config/i386/i386.md:18139 */
23209 rtx
23210 gen_movv8qi (operand0, operand1)
23211      rtx operand0;
23212      rtx operand1;
23213 {
23214   rtx _val = 0;
23215   start_sequence ();
23216   {
23217     rtx operands[2];
23218     operands[0] = operand0;
23219     operands[1] = operand1;
23220 {
23221   ix86_expand_vector_move (V8QImode, operands);
23222   DONE;
23223 }
23224     operand0 = operands[0];
23225     operand1 = operands[1];
23226   }
23227   emit_insn (gen_rtx_SET (VOIDmode,
23228   operand0,
23229   operand1));
23230   _val = get_insns ();
23231   end_sequence ();
23232   return _val;
23233 }
23234 
23235 /* ../../gcc/gcc/config/i386/i386.md:18148 */
23236 rtx
23237 gen_movv2sf (operand0, operand1)
23238      rtx operand0;
23239      rtx operand1;
23240 {
23241   rtx _val = 0;
23242   start_sequence ();
23243   {
23244     rtx operands[2];
23245     operands[0] = operand0;
23246     operands[1] = operand1;
23247 {
23248   ix86_expand_vector_move (V2SFmode, operands);
23249   DONE;
23250 }
23251     operand0 = operands[0];
23252     operand1 = operands[1];
23253   }
23254   emit_insn (gen_rtx_SET (VOIDmode,
23255   operand0,
23256   operand1));
23257   _val = get_insns ();
23258   end_sequence ();
23259   return _val;
23260 }
23261 
23262 /* ../../gcc/gcc/config/i386/i386.md:18217 */
23263 extern rtx gen_split_1523 PARAMS ((rtx *));
23264 rtx
23265 gen_split_1523 (operands)
23266       rtx *operands;
23267 {
23268   rtx operand0;
23269   rtx operand1;
23270   rtx operand2;
23271   rtx operand3;
23272   rtx _val = 0;
23273   start_sequence ();
23274 operands[2] = change_address (operands[0], GET_MODE (operands[0]),
23275          stack_pointer_rtx);
23276    operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));
23277   operand0 = operands[0];
23278   operand1 = operands[1];
23279   operand2 = operands[2];
23280   operand3 = operands[3];
23281   emit_insn (gen_rtx_SET (VOIDmode,
23282   gen_rtx_REG (SImode,
23283   7),
23284   gen_rtx_PLUS (SImode,
23285   gen_rtx_REG (SImode,
23286   7),
23287   operand3)));
23288   emit_insn (gen_rtx_SET (VOIDmode,
23289   operand2,
23290   operand1));
23291   _val = get_insns ();
23292   end_sequence ();
23293   return _val;
23294 }
23295 
23296 /* ../../gcc/gcc/config/i386/i386.md:18228 */
23297 extern rtx gen_split_1524 PARAMS ((rtx *));
23298 rtx
23299 gen_split_1524 (operands)
23300       rtx *operands;
23301 {
23302   rtx operand0;
23303   rtx operand1;
23304   rtx operand2;
23305   rtx operand3;
23306   rtx _val = 0;
23307   start_sequence ();
23308 operands[2] = change_address (operands[0], GET_MODE (operands[0]),
23309          stack_pointer_rtx);
23310    operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));
23311   operand0 = operands[0];
23312   operand1 = operands[1];
23313   operand2 = operands[2];
23314   operand3 = operands[3];
23315   emit_insn (gen_rtx_SET (VOIDmode,
23316   gen_rtx_REG (DImode,
23317   7),
23318   gen_rtx_PLUS (DImode,
23319   gen_rtx_REG (DImode,
23320   7),
23321   operand3)));
23322   emit_insn (gen_rtx_SET (VOIDmode,
23323   operand2,
23324   operand1));
23325   _val = get_insns ();
23326   end_sequence ();
23327   return _val;
23328 }
23329 
23330 /* ../../gcc/gcc/config/i386/i386.md:18240 */
23331 extern rtx gen_split_1525 PARAMS ((rtx *));
23332 rtx
23333 gen_split_1525 (operands)
23334       rtx *operands;
23335 {
23336   rtx operand0;
23337   rtx operand1;
23338   rtx _val = 0;
23339   start_sequence ();
23340 
23341   operand0 = operands[0];
23342   operand1 = operands[1];
23343   emit_insn (gen_rtx_SET (VOIDmode,
23344   gen_rtx_REG (SImode,
23345   7),
23346   gen_rtx_PLUS (SImode,
23347   gen_rtx_REG (SImode,
23348   7),
23349   GEN_INT (-16LL))));
23350   emit_insn (gen_rtx_SET (VOIDmode,
23351   gen_rtx_MEM (TImode,
23352   gen_rtx_REG (SImode,
23353   7)),
23354   operand1));
23355   _val = get_insns ();
23356   end_sequence ();
23357   return _val;
23358 }
23359 
23360 /* ../../gcc/gcc/config/i386/i386.md:18251 */
23361 extern rtx gen_split_1526 PARAMS ((rtx *));
23362 rtx
23363 gen_split_1526 (operands)
23364       rtx *operands;
23365 {
23366   rtx operand0;
23367   rtx operand1;
23368   rtx _val = 0;
23369   start_sequence ();
23370 
23371   operand0 = operands[0];
23372   operand1 = operands[1];
23373   emit_insn (gen_rtx_SET (VOIDmode,
23374   gen_rtx_REG (SImode,
23375   7),
23376   gen_rtx_PLUS (SImode,
23377   gen_rtx_REG (SImode,
23378   7),
23379   GEN_INT (-16LL))));
23380   emit_insn (gen_rtx_SET (VOIDmode,
23381   gen_rtx_MEM (V2DFmode,
23382   gen_rtx_REG (SImode,
23383   7)),
23384   operand1));
23385   _val = get_insns ();
23386   end_sequence ();
23387   return _val;
23388 }
23389 
23390 /* ../../gcc/gcc/config/i386/i386.md:18262 */
23391 extern rtx gen_split_1527 PARAMS ((rtx *));
23392 rtx
23393 gen_split_1527 (operands)
23394       rtx *operands;
23395 {
23396   rtx operand0;
23397   rtx operand1;
23398   rtx _val = 0;
23399   start_sequence ();
23400 
23401   operand0 = operands[0];
23402   operand1 = operands[1];
23403   emit_insn (gen_rtx_SET (VOIDmode,
23404   gen_rtx_REG (SImode,
23405   7),
23406   gen_rtx_PLUS (SImode,
23407   gen_rtx_REG (SImode,
23408   7),
23409   GEN_INT (-16LL))));
23410   emit_insn (gen_rtx_SET (VOIDmode,
23411   gen_rtx_MEM (V2DImode,
23412   gen_rtx_REG (SImode,
23413   7)),
23414   operand1));
23415   _val = get_insns ();
23416   end_sequence ();
23417   return _val;
23418 }
23419 
23420 /* ../../gcc/gcc/config/i386/i386.md:18273 */
23421 extern rtx gen_split_1528 PARAMS ((rtx *));
23422 rtx
23423 gen_split_1528 (operands)
23424       rtx *operands;
23425 {
23426   rtx operand0;
23427   rtx operand1;
23428   rtx _val = 0;
23429   start_sequence ();
23430 
23431   operand0 = operands[0];
23432   operand1 = operands[1];
23433   emit_insn (gen_rtx_SET (VOIDmode,
23434   gen_rtx_REG (SImode,
23435   7),
23436   gen_rtx_PLUS (SImode,
23437   gen_rtx_REG (SImode,
23438   7),
23439   GEN_INT (-16LL))));
23440   emit_insn (gen_rtx_SET (VOIDmode,
23441   gen_rtx_MEM (V8HImode,
23442   gen_rtx_REG (SImode,
23443   7)),
23444   operand1));
23445   _val = get_insns ();
23446   end_sequence ();
23447   return _val;
23448 }
23449 
23450 /* ../../gcc/gcc/config/i386/i386.md:18284 */
23451 extern rtx gen_split_1529 PARAMS ((rtx *));
23452 rtx
23453 gen_split_1529 (operands)
23454       rtx *operands;
23455 {
23456   rtx operand0;
23457   rtx operand1;
23458   rtx _val = 0;
23459   start_sequence ();
23460 
23461   operand0 = operands[0];
23462   operand1 = operands[1];
23463   emit_insn (gen_rtx_SET (VOIDmode,
23464   gen_rtx_REG (SImode,
23465   7),
23466   gen_rtx_PLUS (SImode,
23467   gen_rtx_REG (SImode,
23468   7),
23469   GEN_INT (-16LL))));
23470   emit_insn (gen_rtx_SET (VOIDmode,
23471   gen_rtx_MEM (V16QImode,
23472   gen_rtx_REG (SImode,
23473   7)),
23474   operand1));
23475   _val = get_insns ();
23476   end_sequence ();
23477   return _val;
23478 }
23479 
23480 /* ../../gcc/gcc/config/i386/i386.md:18295 */
23481 extern rtx gen_split_1530 PARAMS ((rtx *));
23482 rtx
23483 gen_split_1530 (operands)
23484       rtx *operands;
23485 {
23486   rtx operand0;
23487   rtx operand1;
23488   rtx _val = 0;
23489   start_sequence ();
23490 
23491   operand0 = operands[0];
23492   operand1 = operands[1];
23493   emit_insn (gen_rtx_SET (VOIDmode,
23494   gen_rtx_REG (SImode,
23495   7),
23496   gen_rtx_PLUS (SImode,
23497   gen_rtx_REG (SImode,
23498   7),
23499   GEN_INT (-16LL))));
23500   emit_insn (gen_rtx_SET (VOIDmode,
23501   gen_rtx_MEM (V4SFmode,
23502   gen_rtx_REG (SImode,
23503   7)),
23504   operand1));
23505   _val = get_insns ();
23506   end_sequence ();
23507   return _val;
23508 }
23509 
23510 /* ../../gcc/gcc/config/i386/i386.md:18306 */
23511 extern rtx gen_split_1531 PARAMS ((rtx *));
23512 rtx
23513 gen_split_1531 (operands)
23514       rtx *operands;
23515 {
23516   rtx operand0;
23517   rtx operand1;
23518   rtx _val = 0;
23519   start_sequence ();
23520 
23521   operand0 = operands[0];
23522   operand1 = operands[1];
23523   emit_insn (gen_rtx_SET (VOIDmode,
23524   gen_rtx_REG (SImode,
23525   7),
23526   gen_rtx_PLUS (SImode,
23527   gen_rtx_REG (SImode,
23528   7),
23529   GEN_INT (-16LL))));
23530   emit_insn (gen_rtx_SET (VOIDmode,
23531   gen_rtx_MEM (V4SImode,
23532   gen_rtx_REG (SImode,
23533   7)),
23534   operand1));
23535   _val = get_insns ();
23536   end_sequence ();
23537   return _val;
23538 }
23539 
23540 /* ../../gcc/gcc/config/i386/i386.md:18317 */
23541 extern rtx gen_split_1532 PARAMS ((rtx *));
23542 rtx
23543 gen_split_1532 (operands)
23544       rtx *operands;
23545 {
23546   rtx operand0;
23547   rtx operand1;
23548   rtx _val = 0;
23549   start_sequence ();
23550 
23551   operand0 = operands[0];
23552   operand1 = operands[1];
23553   emit_insn (gen_rtx_SET (VOIDmode,
23554   gen_rtx_REG (SImode,
23555   7),
23556   gen_rtx_PLUS (SImode,
23557   gen_rtx_REG (SImode,
23558   7),
23559   GEN_INT (-8LL))));
23560   emit_insn (gen_rtx_SET (VOIDmode,
23561   gen_rtx_MEM (V2SImode,
23562   gen_rtx_REG (SImode,
23563   7)),
23564   operand1));
23565   _val = get_insns ();
23566   end_sequence ();
23567   return _val;
23568 }
23569 
23570 /* ../../gcc/gcc/config/i386/i386.md:18328 */
23571 extern rtx gen_split_1533 PARAMS ((rtx *));
23572 rtx
23573 gen_split_1533 (operands)
23574       rtx *operands;
23575 {
23576   rtx operand0;
23577   rtx operand1;
23578   rtx _val = 0;
23579   start_sequence ();
23580 
23581   operand0 = operands[0];
23582   operand1 = operands[1];
23583   emit_insn (gen_rtx_SET (VOIDmode,
23584   gen_rtx_REG (SImode,
23585   7),
23586   gen_rtx_PLUS (SImode,
23587   gen_rtx_REG (SImode,
23588   7),
23589   GEN_INT (-8LL))));
23590   emit_insn (gen_rtx_SET (VOIDmode,
23591   gen_rtx_MEM (V4HImode,
23592   gen_rtx_REG (SImode,
23593   7)),
23594   operand1));
23595   _val = get_insns ();
23596   end_sequence ();
23597   return _val;
23598 }
23599 
23600 /* ../../gcc/gcc/config/i386/i386.md:18339 */
23601 extern rtx gen_split_1534 PARAMS ((rtx *));
23602 rtx
23603 gen_split_1534 (operands)
23604       rtx *operands;
23605 {
23606   rtx operand0;
23607   rtx operand1;
23608   rtx _val = 0;
23609   start_sequence ();
23610 
23611   operand0 = operands[0];
23612   operand1 = operands[1];
23613   emit_insn (gen_rtx_SET (VOIDmode,
23614   gen_rtx_REG (SImode,
23615   7),
23616   gen_rtx_PLUS (SImode,
23617   gen_rtx_REG (SImode,
23618   7),
23619   GEN_INT (-8LL))));
23620   emit_insn (gen_rtx_SET (VOIDmode,
23621   gen_rtx_MEM (V8QImode,
23622   gen_rtx_REG (SImode,
23623   7)),
23624   operand1));
23625   _val = get_insns ();
23626   end_sequence ();
23627   return _val;
23628 }
23629 
23630 /* ../../gcc/gcc/config/i386/i386.md:18350 */
23631 extern rtx gen_split_1535 PARAMS ((rtx *));
23632 rtx
23633 gen_split_1535 (operands)
23634       rtx *operands;
23635 {
23636   rtx operand0;
23637   rtx operand1;
23638   rtx _val = 0;
23639   start_sequence ();
23640 
23641   operand0 = operands[0];
23642   operand1 = operands[1];
23643   emit_insn (gen_rtx_SET (VOIDmode,
23644   gen_rtx_REG (SImode,
23645   7),
23646   gen_rtx_PLUS (SImode,
23647   gen_rtx_REG (SImode,
23648   7),
23649   GEN_INT (-8LL))));
23650   emit_insn (gen_rtx_SET (VOIDmode,
23651   gen_rtx_MEM (V2SFmode,
23652   gen_rtx_REG (SImode,
23653   7)),
23654   operand1));
23655   _val = get_insns ();
23656   end_sequence ();
23657   return _val;
23658 }
23659 
23660 /* ../../gcc/gcc/config/i386/i386.md:18387 */
23661 extern rtx gen_split_1536 PARAMS ((rtx *));
23662 rtx
23663 gen_split_1536 (operands)
23664       rtx *operands ATTRIBUTE_UNUSED;
23665 {
23666   rtx _val = 0;
23667   start_sequence ();
23668 ix86_split_long_move (operands); DONE;
23669   emit_insn (const0_rtx);
23670   _val = get_insns ();
23671   end_sequence ();
23672   return _val;
23673 }
23674 
23675 /* ../../gcc/gcc/config/i386/i386.md:18397 */
23676 rtx
23677 gen_sse_movaps (operand0, operand1)
23678      rtx operand0;
23679      rtx operand1;
23680 {
23681   rtx _val = 0;
23682   start_sequence ();
23683   {
23684     rtx operands[2];
23685     operands[0] = operand0;
23686     operands[1] = operand1;
23687 {
23688   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
23689     {
23690       rtx tmp = gen_reg_rtx (V4SFmode);
23691       emit_insn (gen_sse_movaps (tmp, operands[1]));
23692       emit_move_insn (operands[0], tmp);
23693       DONE;
23694     }
23695 }
23696     operand0 = operands[0];
23697     operand1 = operands[1];
23698   }
23699   emit_insn (gen_rtx_SET (VOIDmode,
23700   operand0,
23701   gen_rtx_UNSPEC (V4SFmode,
23702   gen_rtvec (1,
23703     operand1),
23704   38)));
23705   _val = get_insns ();
23706   end_sequence ();
23707   return _val;
23708 }
23709 
23710 /* ../../gcc/gcc/config/i386/i386.md:18422 */
23711 rtx
23712 gen_sse_movups (operand0, operand1)
23713      rtx operand0;
23714      rtx operand1;
23715 {
23716   rtx _val = 0;
23717   start_sequence ();
23718   {
23719     rtx operands[2];
23720     operands[0] = operand0;
23721     operands[1] = operand1;
23722 {
23723   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
23724     {
23725       rtx tmp = gen_reg_rtx (V4SFmode);
23726       emit_insn (gen_sse_movups (tmp, operands[1]));
23727       emit_move_insn (operands[0], tmp);
23728       DONE;
23729     }
23730 }
23731     operand0 = operands[0];
23732     operand1 = operands[1];
23733   }
23734   emit_insn (gen_rtx_SET (VOIDmode,
23735   operand0,
23736   gen_rtx_UNSPEC (V4SFmode,
23737   gen_rtvec (1,
23738     operand1),
23739   39)));
23740   _val = get_insns ();
23741   end_sequence ();
23742   return _val;
23743 }
23744 
23745 /* ../../gcc/gcc/config/i386/i386.md:18562 */
23746 rtx
23747 gen_sse_loadss (operand0, operand1)
23748      rtx operand0;
23749      rtx operand1;
23750 {
23751   rtx _val = 0;
23752   start_sequence ();
23753   {
23754     rtx operands[2];
23755     operands[0] = operand0;
23756     operands[1] = operand1;
23757 {
23758   emit_insn (gen_sse_loadss_1 (operands[0], operands[1],
23759              CONST0_RTX (V4SFmode)));
23760   DONE;
23761 }
23762     operand0 = operands[0];
23763     operand1 = operands[1];
23764   }
23765   emit (operand0);
23766   emit (operand1);
23767   _val = get_insns ();
23768   end_sequence ();
23769   return _val;
23770 }
23771 
23772 /* ../../gcc/gcc/config/i386/i386.md:18798 */
23773 rtx
23774 gen_sse_andv4sf3 (operand0, operand1, operand2)
23775      rtx operand0;
23776      rtx operand1;
23777      rtx operand2;
23778 {
23779   return gen_rtx_SET (VOIDmode,
23780   gen_rtx_SUBREG (TImode,
23781   operand0,
23782   0),
23783   gen_rtx_AND (TImode,
23784   gen_rtx_SUBREG (TImode,
23785   operand1,
23786   0),
23787   gen_rtx_SUBREG (TImode,
23788   operand2,
23789   0)));
23790 }
23791 
23792 /* ../../gcc/gcc/config/i386/i386.md:18825 */
23793 rtx
23794 gen_sse_nandv4sf3 (operand0, operand1, operand2)
23795      rtx operand0;
23796      rtx operand1;
23797      rtx operand2;
23798 {
23799   return gen_rtx_SET (VOIDmode,
23800   gen_rtx_SUBREG (TImode,
23801   operand0,
23802   0),
23803   gen_rtx_AND (TImode,
23804   gen_rtx_NOT (TImode,
23805   gen_rtx_SUBREG (TImode,
23806   operand1,
23807   0)),
23808   gen_rtx_SUBREG (TImode,
23809   operand2,
23810   0)));
23811 }
23812 
23813 /* ../../gcc/gcc/config/i386/i386.md:18850 */
23814 rtx
23815 gen_sse_iorv4sf3 (operand0, operand1, operand2)
23816      rtx operand0;
23817      rtx operand1;
23818      rtx operand2;
23819 {
23820   return gen_rtx_SET (VOIDmode,
23821   gen_rtx_SUBREG (TImode,
23822   operand0,
23823   0),
23824   gen_rtx_IOR (TImode,
23825   gen_rtx_SUBREG (TImode,
23826   operand1,
23827   0),
23828   gen_rtx_SUBREG (TImode,
23829   operand2,
23830   0)));
23831 }
23832 
23833 /* ../../gcc/gcc/config/i386/i386.md:18877 */
23834 rtx
23835 gen_sse_xorv4sf3 (operand0, operand1, operand2)
23836      rtx operand0;
23837      rtx operand1;
23838      rtx operand2;
23839 {
23840   return gen_rtx_SET (VOIDmode,
23841   gen_rtx_SUBREG (TImode,
23842   operand0,
23843   0),
23844   gen_rtx_XOR (TImode,
23845   gen_rtx_SUBREG (TImode,
23846   operand1,
23847   0),
23848   gen_rtx_SUBREG (TImode,
23849   operand2,
23850   0)));
23851 }
23852 
23853 /* ../../gcc/gcc/config/i386/i386.md:18907 */
23854 rtx
23855 gen_sse2_andv2df3 (operand0, operand1, operand2)
23856      rtx operand0;
23857      rtx operand1;
23858      rtx operand2;
23859 {
23860   return gen_rtx_SET (VOIDmode,
23861   gen_rtx_SUBREG (TImode,
23862   operand0,
23863   0),
23864   gen_rtx_AND (TImode,
23865   gen_rtx_SUBREG (TImode,
23866   operand1,
23867   0),
23868   gen_rtx_SUBREG (TImode,
23869   operand2,
23870   0)));
23871 }
23872 
23873 /* ../../gcc/gcc/config/i386/i386.md:18934 */
23874 rtx
23875 gen_sse2_nandv2df3 (operand0, operand1, operand2)
23876      rtx operand0;
23877      rtx operand1;
23878      rtx operand2;
23879 {
23880   return gen_rtx_SET (VOIDmode,
23881   gen_rtx_SUBREG (TImode,
23882   operand0,
23883   0),
23884   gen_rtx_AND (TImode,
23885   gen_rtx_NOT (TImode,
23886   gen_rtx_SUBREG (TImode,
23887   operand1,
23888   0)),
23889   gen_rtx_SUBREG (TImode,
23890   operand2,
23891   0)));
23892 }
23893 
23894 /* ../../gcc/gcc/config/i386/i386.md:18959 */
23895 rtx
23896 gen_sse2_iorv2df3 (operand0, operand1, operand2)
23897      rtx operand0;
23898      rtx operand1;
23899      rtx operand2;
23900 {
23901   return gen_rtx_SET (VOIDmode,
23902   gen_rtx_SUBREG (TImode,
23903   operand0,
23904   0),
23905   gen_rtx_IOR (TImode,
23906   gen_rtx_SUBREG (TImode,
23907   operand1,
23908   0),
23909   gen_rtx_SUBREG (TImode,
23910   operand2,
23911   0)));
23912 }
23913 
23914 /* ../../gcc/gcc/config/i386/i386.md:18986 */
23915 rtx
23916 gen_sse2_xorv2df3 (operand0, operand1, operand2)
23917      rtx operand0;
23918      rtx operand1;
23919      rtx operand2;
23920 {
23921   return gen_rtx_SET (VOIDmode,
23922   gen_rtx_SUBREG (TImode,
23923   operand0,
23924   0),
23925   gen_rtx_XOR (TImode,
23926   gen_rtx_SUBREG (TImode,
23927   operand1,
23928   0),
23929   gen_rtx_SUBREG (TImode,
23930   operand2,
23931   0)));
23932 }
23933 
23934 /* ../../gcc/gcc/config/i386/i386.md:20119 */
23935 rtx
23936 gen_sfence ()
23937 {
23938   rtx operand0;
23939   rtx _val = 0;
23940   start_sequence ();
23941   {
23942     rtx operands[1];
23943 {
23944   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
23945   MEM_VOLATILE_P (operands[0]) = 1;
23946 }
23947     operand0 = operands[0];
23948   }
23949   emit_insn (gen_rtx_SET (VOIDmode,
23950   operand0,
23951   gen_rtx_UNSPEC (BLKmode,
23952   gen_rtvec (1,
23953     operand0),
23954   44)));
23955   _val = get_insns ();
23956   end_sequence ();
23957   return _val;
23958 }
23959 
23960 /* ../../gcc/gcc/config/i386/i386.md:20136 */
23961 rtx
23962 gen_sse_prologue_save (operand0, operand1, operand2, operand3)
23963      rtx operand0;
23964      rtx operand1;
23965      rtx operand2;
23966      rtx operand3;
23967 {
23968   return gen_rtx_PARALLEL (VOIDmode,
23969   gen_rtvec (4,
23970     gen_rtx_SET (VOIDmode,
23971   operand0,
23972   gen_rtx_UNSPEC (BLKmode,
23973   gen_rtvec (8,
23974     gen_rtx_REG (DImode,
23975   21),
23976     gen_rtx_REG (DImode,
23977   22),
23978     gen_rtx_REG (DImode,
23979   23),
23980     gen_rtx_REG (DImode,
23981   24),
23982     gen_rtx_REG (DImode,
23983   25),
23984     gen_rtx_REG (DImode,
23985   26),
23986     gen_rtx_REG (DImode,
23987   27),
23988     gen_rtx_REG (DImode,
23989   28)),
23990   13)),
23991     gen_rtx_USE (VOIDmode,
23992   operand1),
23993     gen_rtx_USE (VOIDmode,
23994   operand2),
23995     gen_rtx_USE (VOIDmode,
23996   gen_rtx_LABEL_REF (DImode,
23997   operand3))));
23998 }
23999 
24000 /* ../../gcc/gcc/config/i386/i386.md:20502 */
24001 rtx
24002 gen_prefetch (operand0, operand1, operand2)
24003      rtx operand0;
24004      rtx operand1;
24005      rtx operand2;
24006 {
24007   rtx _val = 0;
24008   start_sequence ();
24009   {
24010     rtx operands[3];
24011     operands[0] = operand0;
24012     operands[1] = operand1;
24013     operands[2] = operand2;
24014 {
24015   int rw = INTVAL (operands[1]);
24016   int locality = INTVAL (operands[2]);
24017 
24018   if (rw != 0 && rw != 1)
24019     abort ();
24020   if (locality < 0 || locality > 3)
24021     abort ();
24022   if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
24023     abort ();
24024 
24025   /* Use 3dNOW prefetch in case we are asking for write prefetch not
24026      suported by SSE counterpart or the SSE prefetch is not available
24027      (K6 machines).  Otherwise use SSE prefetch as it allows specifying
24028      of locality.  */
24029   if (TARGET_3DNOW && (!TARGET_PREFETCH_SSE || rw))
24030     operands[2] = GEN_INT (3);
24031   else
24032     operands[1] = const0_rtx;
24033 }
24034     operand0 = operands[0];
24035     operand1 = operands[1];
24036     operand2 = operands[2];
24037   }
24038   emit_insn (gen_rtx_PREFETCH (VOIDmode,
24039   operand0,
24040   operand1,
24041   operand2));
24042   _val = get_insns ();
24043   end_sequence ();
24044   return _val;
24045 }
24046 
24047 /* ../../gcc/gcc/config/i386/i386.md:22070 */
24048 rtx
24049 gen_sse2_loadsd (operand0, operand1)
24050      rtx operand0;
24051      rtx operand1;
24052 {
24053   rtx _val = 0;
24054   start_sequence ();
24055   {
24056     rtx operands[2];
24057     operands[0] = operand0;
24058     operands[1] = operand1;
24059 {
24060   emit_insn (gen_sse2_loadsd_1 (operands[0], operands[1],
24061               CONST0_RTX (V2DFmode)));
24062   DONE;
24063 }
24064     operand0 = operands[0];
24065     operand1 = operands[1];
24066   }
24067   emit (operand0);
24068   emit (operand1);
24069   _val = get_insns ();
24070   end_sequence ();
24071   return _val;
24072 }
24073 
24074 /* ../../gcc/gcc/config/i386/i386.md:22132 */
24075 rtx
24076 gen_sse2_mfence ()
24077 {
24078   rtx operand0;
24079   rtx _val = 0;
24080   start_sequence ();
24081   {
24082     rtx operands[1];
24083 {
24084   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
24085   MEM_VOLATILE_P (operands[0]) = 1;
24086 }
24087     operand0 = operands[0];
24088   }
24089   emit_insn (gen_rtx_SET (VOIDmode,
24090   operand0,
24091   gen_rtx_UNSPEC (BLKmode,
24092   gen_rtvec (1,
24093     operand0),
24094   59)));
24095   _val = get_insns ();
24096   end_sequence ();
24097   return _val;
24098 }
24099 
24100 /* ../../gcc/gcc/config/i386/i386.md:22149 */
24101 rtx
24102 gen_sse2_lfence ()
24103 {
24104   rtx operand0;
24105   rtx _val = 0;
24106   start_sequence ();
24107   {
24108     rtx operands[1];
24109 {
24110   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
24111   MEM_VOLATILE_P (operands[0]) = 1;
24112 }
24113     operand0 = operands[0];
24114   }
24115   emit_insn (gen_rtx_SET (VOIDmode,
24116   operand0,
24117   gen_rtx_UNSPEC (BLKmode,
24118   gen_rtvec (1,
24119     operand0),
24120   60)));
24121   _val = get_insns ();
24122   end_sequence ();
24123   return _val;
24124 }
24125 
24126 
24127 
24128 void
24129 add_clobbers (pattern, insn_code_number)
24130      rtx pattern ATTRIBUTE_UNUSED;
24131      int insn_code_number;
24132 {
24133   switch (insn_code_number)
24134     {
24135     case 864:
24136     case 850:
24137       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24138   gen_rtx_REG (XFmode,
24139   8));
24140       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24141   gen_rtx_REG (XFmode,
24142   9));
24143       XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
24144   gen_rtx_REG (XFmode,
24145   10));
24146       XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
24147   gen_rtx_REG (XFmode,
24148   11));
24149       XVECEXP (pattern, 0, 5) = gen_rtx_CLOBBER (VOIDmode,
24150   gen_rtx_REG (XFmode,
24151   12));
24152       XVECEXP (pattern, 0, 6) = gen_rtx_CLOBBER (VOIDmode,
24153   gen_rtx_REG (XFmode,
24154   13));
24155       XVECEXP (pattern, 0, 7) = gen_rtx_CLOBBER (VOIDmode,
24156   gen_rtx_REG (XFmode,
24157   14));
24158       XVECEXP (pattern, 0, 8) = gen_rtx_CLOBBER (VOIDmode,
24159   gen_rtx_REG (XFmode,
24160   15));
24161       XVECEXP (pattern, 0, 9) = gen_rtx_CLOBBER (VOIDmode,
24162   gen_rtx_REG (DImode,
24163   29));
24164       XVECEXP (pattern, 0, 10) = gen_rtx_CLOBBER (VOIDmode,
24165   gen_rtx_REG (DImode,
24166   30));
24167       XVECEXP (pattern, 0, 11) = gen_rtx_CLOBBER (VOIDmode,
24168   gen_rtx_REG (DImode,
24169   31));
24170       XVECEXP (pattern, 0, 12) = gen_rtx_CLOBBER (VOIDmode,
24171   gen_rtx_REG (DImode,
24172   32));
24173       XVECEXP (pattern, 0, 13) = gen_rtx_CLOBBER (VOIDmode,
24174   gen_rtx_REG (DImode,
24175   33));
24176       XVECEXP (pattern, 0, 14) = gen_rtx_CLOBBER (VOIDmode,
24177   gen_rtx_REG (DImode,
24178   34));
24179       XVECEXP (pattern, 0, 15) = gen_rtx_CLOBBER (VOIDmode,
24180   gen_rtx_REG (DImode,
24181   35));
24182       XVECEXP (pattern, 0, 16) = gen_rtx_CLOBBER (VOIDmode,
24183   gen_rtx_REG (DImode,
24184   36));
24185       break;
24186 
24187     case 663:
24188     case 662:
24189       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24190   gen_rtx_SCRATCH (DFmode));
24191       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24192   gen_rtx_REG (CCmode,
24193   17));
24194       break;
24195 
24196     case 661:
24197     case 660:
24198       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24199   gen_rtx_SCRATCH (SFmode));
24200       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24201   gen_rtx_REG (CCmode,
24202   17));
24203       break;
24204 
24205     case 543:
24206     case 541:
24207     case 540:
24208     case 538:
24209     case 537:
24210       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24211   gen_rtx_SCRATCH (SImode));
24212       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24213   gen_rtx_SCRATCH (SImode));
24214       XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
24215   gen_rtx_REG (CCmode,
24216   17));
24217       break;
24218 
24219     case 520:
24220       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24221   gen_rtx_SCRATCH (SImode));
24222       XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
24223   gen_rtx_REG (CCmode,
24224   17));
24225       break;
24226 
24227     case 514:
24228     case 513:
24229     case 512:
24230     case 511:
24231       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24232   gen_rtx_REG (CCFPmode,
24233   18));
24234       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24235   gen_rtx_REG (CCFPmode,
24236   17));
24237       XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
24238   gen_rtx_SCRATCH (HImode));
24239       break;
24240 
24241     case 510:
24242     case 509:
24243     case 508:
24244     case 507:
24245     case 506:
24246     case 505:
24247       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24248   gen_rtx_REG (CCFPmode,
24249   18));
24250       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24251   gen_rtx_REG (CCFPmode,
24252   17));
24253       break;
24254 
24255     case 673:
24256     case 672:
24257     case 635:
24258     case 634:
24259     case 275:
24260     case 274:
24261     case 272:
24262     case 269:
24263     case 266:
24264       XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
24265   gen_rtx_REG (CCmode,
24266   17));
24267       break;
24268 
24269     case 384:
24270     case 383:
24271     case 380:
24272     case 365:
24273     case 364:
24274     case 361:
24275     case 273:
24276     case 271:
24277     case 270:
24278     case 268:
24279     case 267:
24280     case 265:
24281     case 264:
24282       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24283   gen_rtx_REG (CCmode,
24284   17));
24285       break;
24286 
24287     case 455:
24288     case 428:
24289     case 410:
24290     case 261:
24291     case 260:
24292     case 258:
24293     case 257:
24294       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24295   gen_rtx_SCRATCH (SImode));
24296       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24297   gen_rtx_REG (CCmode,
24298   17));
24299       break;
24300 
24301     case 259:
24302     case 256:
24303       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24304   gen_rtx_SCRATCH (DImode));
24305       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24306   gen_rtx_REG (CCmode,
24307   17));
24308       break;
24309 
24310     case 346:
24311     case 320:
24312     case 221:
24313     case 220:
24314     case 219:
24315       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24316   gen_rtx_SCRATCH (QImode));
24317       break;
24318 
24319     case 337:
24320     case 315:
24321     case 214:
24322     case 213:
24323     case 212:
24324       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24325   gen_rtx_SCRATCH (HImode));
24326       break;
24327 
24328     case 334:
24329     case 312:
24330     case 208:
24331     case 207:
24332     case 205:
24333       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24334   gen_rtx_SCRATCH (SImode));
24335       break;
24336 
24337     case 327:
24338     case 305:
24339     case 200:
24340     case 199:
24341     case 198:
24342       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24343   gen_rtx_SCRATCH (DImode));
24344       break;
24345 
24346     case 148:
24347       XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
24348   gen_rtx_SCRATCH (DFmode));
24349       break;
24350 
24351     case 147:
24352       XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
24353   gen_rtx_SCRATCH (DFmode));
24354       break;
24355 
24356     case 118:
24357       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24358   gen_rtx_REG (CCmode,
24359   17));
24360       XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
24361   gen_rtx_SCRATCH (SImode));
24362       break;
24363 
24364     case 656:
24365     case 655:
24366     case 653:
24367     case 652:
24368     case 650:
24369     case 649:
24370     case 647:
24371     case 646:
24372     case 638:
24373     case 636:
24374     case 547:
24375     case 546:
24376     case 531:
24377     case 498:
24378     case 497:
24379     case 496:
24380     case 495:
24381     case 494:
24382     case 493:
24383     case 492:
24384     case 491:
24385     case 490:
24386     case 489:
24387     case 488:
24388     case 487:
24389     case 486:
24390     case 485:
24391     case 484:
24392     case 483:
24393     case 482:
24394     case 481:
24395     case 480:
24396     case 479:
24397     case 478:
24398     case 477:
24399     case 476:
24400     case 475:
24401     case 472:
24402     case 471:
24403     case 470:
24404     case 469:
24405     case 466:
24406     case 465:
24407     case 460:
24408     case 459:
24409     case 458:
24410     case 457:
24411     case 456:
24412     case 452:
24413     case 451:
24414     case 448:
24415     case 447:
24416     case 446:
24417     case 445:
24418     case 442:
24419     case 441:
24420     case 436:
24421     case 435:
24422     case 434:
24423     case 433:
24424     case 432:
24425     case 431:
24426     case 430:
24427     case 429:
24428     case 425:
24429     case 424:
24430     case 423:
24431     case 421:
24432     case 420:
24433     case 418:
24434     case 417:
24435     case 414:
24436     case 413:
24437     case 412:
24438     case 411:
24439     case 408:
24440     case 388:
24441     case 387:
24442     case 386:
24443     case 385:
24444     case 382:
24445     case 381:
24446     case 379:
24447     case 369:
24448     case 368:
24449     case 367:
24450     case 366:
24451     case 363:
24452     case 362:
24453     case 360:
24454     case 358:
24455     case 356:
24456     case 353:
24457     case 352:
24458     case 350:
24459     case 349:
24460     case 343:
24461     case 342:
24462     case 341:
24463     case 340:
24464     case 339:
24465     case 338:
24466     case 335:
24467     case 330:
24468     case 329:
24469     case 328:
24470     case 325:
24471     case 324:
24472     case 323:
24473     case 322:
24474     case 321:
24475     case 317:
24476     case 316:
24477     case 313:
24478     case 308:
24479     case 307:
24480     case 306:
24481     case 303:
24482     case 302:
24483     case 301:
24484     case 300:
24485     case 298:
24486     case 295:
24487     case 294:
24488     case 292:
24489     case 289:
24490     case 288:
24491     case 286:
24492     case 263:
24493     case 262:
24494     case 255:
24495     case 254:
24496     case 253:
24497     case 252:
24498     case 251:
24499     case 250:
24500     case 249:
24501     case 248:
24502     case 247:
24503     case 246:
24504     case 245:
24505     case 242:
24506     case 241:
24507     case 238:
24508     case 233:
24509     case 232:
24510     case 231:
24511     case 230:
24512     case 227:
24513     case 226:
24514     case 225:
24515     case 224:
24516     case 223:
24517     case 222:
24518     case 217:
24519     case 216:
24520     case 215:
24521     case 210:
24522     case 209:
24523     case 202:
24524     case 201:
24525     case 196:
24526     case 183:
24527     case 182:
24528     case 180:
24529     case 179:
24530     case 114:
24531     case 112:
24532     case 111:
24533     case 109:
24534     case 108:
24535     case 106:
24536     case 81:
24537     case 80:
24538     case 62:
24539     case 56:
24540     case 43:
24541     case 42:
24542       XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
24543   gen_rtx_REG (CCmode,
24544   17));
24545       break;
24546 
24547     default:
24548       abort ();
24549     }
24550 }
24551 
24552 
24553 int
24554 added_clobbers_hard_reg_p (insn_code_number)
24555      int insn_code_number;
24556 {
24557   switch (insn_code_number)
24558     {
24559     case 346:
24560     case 320:
24561     case 221:
24562     case 220:
24563     case 219:
24564     case 337:
24565     case 315:
24566     case 214:
24567     case 213:
24568     case 212:
24569     case 334:
24570     case 312:
24571     case 208:
24572     case 207:
24573     case 205:
24574     case 327:
24575     case 305:
24576     case 200:
24577     case 199:
24578     case 198:
24579     case 148:
24580     case 147:
24581       return 0;
24582 
24583     case 864:
24584     case 850:
24585     case 663:
24586     case 662:
24587     case 661:
24588     case 660:
24589     case 543:
24590     case 541:
24591     case 540:
24592     case 538:
24593     case 537:
24594     case 520:
24595     case 514:
24596     case 513:
24597     case 512:
24598     case 511:
24599     case 510:
24600     case 509:
24601     case 508:
24602     case 507:
24603     case 506:
24604     case 505:
24605     case 673:
24606     case 672:
24607     case 635:
24608     case 634:
24609     case 275:
24610     case 274:
24611     case 272:
24612     case 269:
24613     case 266:
24614     case 384:
24615     case 383:
24616     case 380:
24617     case 365:
24618     case 364:
24619     case 361:
24620     case 273:
24621     case 271:
24622     case 270:
24623     case 268:
24624     case 267:
24625     case 265:
24626     case 264:
24627     case 455:
24628     case 428:
24629     case 410:
24630     case 261:
24631     case 260:
24632     case 258:
24633     case 257:
24634     case 259:
24635     case 256:
24636     case 118:
24637     case 656:
24638     case 655:
24639     case 653:
24640     case 652:
24641     case 650:
24642     case 649:
24643     case 647:
24644     case 646:
24645     case 638:
24646     case 636:
24647     case 547:
24648     case 546:
24649     case 531:
24650     case 498:
24651     case 497:
24652     case 496:
24653     case 495:
24654     case 494:
24655     case 493:
24656     case 492:
24657     case 491:
24658     case 490:
24659     case 489:
24660     case 488:
24661     case 487:
24662     case 486:
24663     case 485:
24664     case 484:
24665     case 483:
24666     case 482:
24667     case 481:
24668     case 480:
24669     case 479:
24670     case 478:
24671     case 477:
24672     case 476:
24673     case 475:
24674     case 472:
24675     case 471:
24676     case 470:
24677     case 469:
24678     case 466:
24679     case 465:
24680     case 460:
24681     case 459:
24682     case 458:
24683     case 457:
24684     case 456:
24685     case 452:
24686     case 451:
24687     case 448:
24688     case 447:
24689     case 446:
24690     case 445:
24691     case 442:
24692     case 441:
24693     case 436:
24694     case 435:
24695     case 434:
24696     case 433:
24697     case 432:
24698     case 431:
24699     case 430:
24700     case 429:
24701     case 425:
24702     case 424:
24703     case 423:
24704     case 421:
24705     case 420:
24706     case 418:
24707     case 417:
24708     case 414:
24709     case 413:
24710     case 412:
24711     case 411:
24712     case 408:
24713     case 388:
24714     case 387:
24715     case 386:
24716     case 385:
24717     case 382:
24718     case 381:
24719     case 379:
24720     case 369:
24721     case 368:
24722     case 367:
24723     case 366:
24724     case 363:
24725     case 362:
24726     case 360:
24727     case 358:
24728     case 356:
24729     case 353:
24730     case 352:
24731     case 350:
24732     case 349:
24733     case 343:
24734     case 342:
24735     case 341:
24736     case 340:
24737     case 339:
24738     case 338:
24739     case 335:
24740     case 330:
24741     case 329:
24742     case 328:
24743     case 325:
24744     case 324:
24745     case 323:
24746     case 322:
24747     case 321:
24748     case 317:
24749     case 316:
24750     case 313:
24751     case 308:
24752     case 307:
24753     case 306:
24754     case 303:
24755     case 302:
24756     case 301:
24757     case 300:
24758     case 298:
24759     case 295:
24760     case 294:
24761     case 292:
24762     case 289:
24763     case 288:
24764     case 286:
24765     case 263:
24766     case 262:
24767     case 255:
24768     case 254:
24769     case 253:
24770     case 252:
24771     case 251:
24772     case 250:
24773     case 249:
24774     case 248:
24775     case 247:
24776     case 246:
24777     case 245:
24778     case 242:
24779     case 241:
24780     case 238:
24781     case 233:
24782     case 232:
24783     case 231:
24784     case 230:
24785     case 227:
24786     case 226:
24787     case 225:
24788     case 224:
24789     case 223:
24790     case 222:
24791     case 217:
24792     case 216:
24793     case 215:
24794     case 210:
24795     case 209:
24796     case 202:
24797     case 201:
24798     case 196:
24799     case 183:
24800     case 182:
24801     case 180:
24802     case 179:
24803     case 114:
24804     case 112:
24805     case 111:
24806     case 109:
24807     case 108:
24808     case 106:
24809     case 81:
24810     case 80:
24811     case 62:
24812     case 56:
24813     case 43:
24814     case 42:
24815       return 1;
24816 
24817     default:
24818       abort ();
24819     }
24820 }