osprey-gcc-4.2.0/gcc/config/rs6000/rs6000.c

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/* Subroutines used for code generation on IBM RS/6000.
   Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
   Free Software Foundation, Inc.
   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)

   This file is part of GCC.

   GCC is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published
   by the Free Software Foundation; either version 2, or (at your
   option) any later version.

   GCC is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
   License for more details.

   You should have received a copy of the GNU General Public License
   along with GCC; see the file COPYING.  If not, write to the
   Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "rtl.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "real.h"
#include "insn-config.h"
#include "conditions.h"
#include "insn-attr.h"
#include "flags.h"
#include "recog.h"
#include "obstack.h"
#include "tree.h"
#include "expr.h"
#include "optabs.h"
#include "except.h"
#include "function.h"
#include "output.h"
#include "basic-block.h"
#include "integrate.h"
#include "toplev.h"
#include "ggc.h"
#include "hashtab.h"
#include "tm_p.h"
#include "target.h"
#include "target-def.h"
#include "langhooks.h"
#include "reload.h"
#include "cfglayout.h"
#include "sched-int.h"
#include "tree-gimple.h"
#include "intl.h"
#include "params.h"
#include "tm-constrs.h"
#if TARGET_XCOFF
#include "xcoffout.h"  /* get declarations of xcoff_*_section_name */
#endif
#if TARGET_MACHO
#include "gstab.h"  /* for N_SLINE */
#endif

#ifndef TARGET_NO_PROTOTYPE
#define TARGET_NO_PROTOTYPE 0
#endif

#define min(A,B)  ((A) < (B) ? (A) : (B))
#define max(A,B)  ((A) > (B) ? (A) : (B))

/* Structure used to define the rs6000 stack */
typedef struct rs6000_stack {
  int first_gp_reg_save;  /* first callee saved GP register used */
  int first_fp_reg_save;  /* first callee saved FP register used */
  int first_altivec_reg_save; /* first callee saved AltiVec register used */
  int lr_save_p;    /* true if the link reg needs to be saved */
  int cr_save_p;    /* true if the CR reg needs to be saved */
  unsigned int vrsave_mask; /* mask of vec registers to save */
  int push_p;     /* true if we need to allocate stack space */
  int calls_p;      /* true if the function makes any calls */
  int world_save_p;   /* true if we're saving *everything*:
           r13-r31, cr, f14-f31, vrsave, v20-v31  */
  enum rs6000_abi abi;    /* which ABI to use */
  int gp_save_offset;   /* offset to save GP regs from initial SP */
  int fp_save_offset;   /* offset to save FP regs from initial SP */
  int altivec_save_offset;  /* offset to save AltiVec regs from initial SP */
  int lr_save_offset;   /* offset to save LR from initial SP */
  int cr_save_offset;   /* offset to save CR from initial SP */
  int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
  int spe_gp_save_offset; /* offset to save spe 64-bit gprs  */
  int varargs_save_offset;  /* offset to save the varargs registers */
  int ehrd_offset;    /* offset to EH return data */
  int reg_size;     /* register size (4 or 8) */
  HOST_WIDE_INT vars_size;  /* variable save area size */
  int parm_size;    /* outgoing parameter size */
  int save_size;    /* save area size */
  int fixed_size;   /* fixed size of stack frame */
  int gp_size;      /* size of saved GP registers */
  int fp_size;      /* size of saved FP registers */
  int altivec_size;   /* size of saved AltiVec registers */
  int cr_size;      /* size to hold CR if not in save_size */
  int vrsave_size;    /* size to hold VRSAVE if not in save_size */
  int altivec_padding_size; /* size of altivec alignment padding if
           not in save_size */
  int spe_gp_size;    /* size of 64-bit GPR save size for SPE */
  int spe_padding_size;
  HOST_WIDE_INT total_size; /* total bytes allocated for stack */
  int spe_64bit_regs_used;
} rs6000_stack_t;

/* A C structure for machine-specific, per-function data.
   This is added to the cfun structure.  */
typedef struct machine_function GTY(())
{
  /* Flags if __builtin_return_address (n) with n >= 1 was used.  */
  int ra_needs_full_frame;
  /* Some local-dynamic symbol.  */
  const char *some_ld_name;
  /* Whether the instruction chain has been scanned already.  */
  int insn_chain_scanned_p;
  /* Flags if __builtin_return_address (0) was used.  */
  int ra_need_lr;
  /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
     varargs save area.  */
  HOST_WIDE_INT varargs_save_offset;
} machine_function;

/* Target cpu type */

enum processor_type rs6000_cpu;
struct rs6000_cpu_select rs6000_select[3] =
{
  /* switch   name,     tune  arch */
  { (const char *)0,  "--with-cpu=",    1,  1 },
  { (const char *)0,  "-mcpu=",   1,  1 },
  { (const char *)0,  "-mtune=",    1,  0 },
};

/* Always emit branch hint bits.  */
static GTY(()) bool rs6000_always_hint;

/* Schedule instructions for group formation.  */
static GTY(()) bool rs6000_sched_groups;

/* Support for -msched-costly-dep option.  */
const char *rs6000_sched_costly_dep_str;
enum rs6000_dependence_cost rs6000_sched_costly_dep;

/* Support for -minsert-sched-nops option.  */
const char *rs6000_sched_insert_nops_str;
enum rs6000_nop_insertion rs6000_sched_insert_nops;

/* Support targetm.vectorize.builtin_mask_for_load.  */
static GTY(()) tree altivec_builtin_mask_for_load;

/* Size of long double.  */
int rs6000_long_double_type_size;

/* IEEE quad extended precision long double. */
int rs6000_ieeequad;

/* Whether -mabi=altivec has appeared.  */
int rs6000_altivec_abi;

/* Nonzero if we want SPE ABI extensions.  */
int rs6000_spe_abi;

/* Nonzero if floating point operations are done in the GPRs.  */
int rs6000_float_gprs = 0;

/* Nonzero if we want Darwin's struct-by-value-in-regs ABI.  */
int rs6000_darwin64_abi;

/* Set to nonzero once AIX common-mode calls have been defined.  */
static GTY(()) int common_mode_defined;

/* Save information from a "cmpxx" operation until the branch or scc is
   emitted.  */
rtx rs6000_compare_op0, rs6000_compare_op1;
int rs6000_compare_fp_p;

/* Label number of label created for -mrelocatable, to call to so we can
   get the address of the GOT section */
int rs6000_pic_labelno;

#ifdef USING_ELFOS_H
/* Which abi to adhere to */
const char *rs6000_abi_name;

/* Semantics of the small data area */
enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;

/* Which small data model to use */
const char *rs6000_sdata_name = (char *)0;

/* Counter for labels which are to be placed in .fixup.  */
int fixuplabelno = 0;
#endif

/* Bit size of immediate TLS offsets and string from which it is decoded.  */
int rs6000_tls_size = 32;
const char *rs6000_tls_size_string;

/* ABI enumeration available for subtarget to use.  */
enum rs6000_abi rs6000_current_abi;

/* Whether to use variant of AIX ABI for PowerPC64 Linux.  */
int dot_symbols;

/* Debug flags */
const char *rs6000_debug_name;
int rs6000_debug_stack;   /* debug stack applications */
int rs6000_debug_arg;   /* debug argument handling */

/* Value is TRUE if register/mode pair is acceptable.  */
bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];

/* Built in types.  */

tree rs6000_builtin_types[RS6000_BTI_MAX];
tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];

const char *rs6000_traceback_name;
static enum {
  traceback_default = 0,
  traceback_none,
  traceback_part,
  traceback_full
} rs6000_traceback;

/* Flag to say the TOC is initialized */
int toc_initialized;
char toc_label_name[10];

static GTY(()) section *read_only_data_section;
static GTY(()) section *private_data_section;
static GTY(()) section *read_only_private_data_section;
static GTY(()) section *sdata2_section;
static GTY(()) section *toc_section;

/* Control alignment for fields within structures.  */
/* String from -malign-XXXXX.  */
int rs6000_alignment_flags;

/* True for any options that were explicitly set.  */
struct {
  bool aix_struct_ret;    /* True if -maix-struct-ret was used.  */
  bool alignment;   /* True if -malign- was used.  */
  bool abi;     /* True if -mabi=spe/nospe was used.  */
  bool spe;     /* True if -mspe= was used.  */
  bool float_gprs;    /* True if -mfloat-gprs= was used.  */
  bool isel;      /* True if -misel was used. */
  bool long_double;         /* True if -mlong-double- was used.  */
  bool ieee;      /* True if -mabi=ieee/ibmlongdouble used.  */
} rs6000_explicit_options;

struct builtin_description
{
  /* mask is not const because we're going to alter it below.  This
     nonsense will go away when we rewrite the -march infrastructure
     to give us more target flag bits.  */
  unsigned int mask;
  const enum insn_code icode;
  const char *const name;
  const enum rs6000_builtins code;
};

/* Target cpu costs.  */

struct processor_costs {
  const int mulsi;    /* cost of SImode multiplication.  */
  const int mulsi_const;  /* cost of SImode multiplication by constant.  */
  const int mulsi_const9; /* cost of SImode mult by short constant.  */
  const int muldi;    /* cost of DImode multiplication.  */
  const int divsi;    /* cost of SImode division.  */
  const int divdi;    /* cost of DImode division.  */
  const int fp;     /* cost of simple SFmode and DFmode insns.  */
  const int dmul;   /* cost of DFmode multiplication (and fmadd).  */
  const int sdiv;   /* cost of SFmode division (fdivs).  */
  const int ddiv;   /* cost of DFmode division (fdiv).  */
};

const struct processor_costs *rs6000_cost;

/* Processor costs (relative to an add) */

/* Instruction size costs on 32bit processors.  */
static const
struct processor_costs size32_cost = {
  COSTS_N_INSNS (1),    /* mulsi */
  COSTS_N_INSNS (1),    /* mulsi_const */
  COSTS_N_INSNS (1),    /* mulsi_const9 */
  COSTS_N_INSNS (1),    /* muldi */
  COSTS_N_INSNS (1),    /* divsi */
  COSTS_N_INSNS (1),    /* divdi */
  COSTS_N_INSNS (1),    /* fp */
  COSTS_N_INSNS (1),    /* dmul */
  COSTS_N_INSNS (1),    /* sdiv */
  COSTS_N_INSNS (1),    /* ddiv */
};

/* Instruction size costs on 64bit processors.  */
static const
struct processor_costs size64_cost = {
  COSTS_N_INSNS (1),    /* mulsi */
  COSTS_N_INSNS (1),    /* mulsi_const */
  COSTS_N_INSNS (1),    /* mulsi_const9 */
  COSTS_N_INSNS (1),    /* muldi */
  COSTS_N_INSNS (1),    /* divsi */
  COSTS_N_INSNS (1),    /* divdi */
  COSTS_N_INSNS (1),    /* fp */
  COSTS_N_INSNS (1),    /* dmul */
  COSTS_N_INSNS (1),    /* sdiv */
  COSTS_N_INSNS (1),    /* ddiv */
};

/* Instruction costs on RIOS1 processors.  */
static const
struct processor_costs rios1_cost = {
  COSTS_N_INSNS (5),    /* mulsi */
  COSTS_N_INSNS (4),    /* mulsi_const */
  COSTS_N_INSNS (3),    /* mulsi_const9 */
  COSTS_N_INSNS (5),    /* muldi */
  COSTS_N_INSNS (19),   /* divsi */
  COSTS_N_INSNS (19),   /* divdi */
  COSTS_N_INSNS (2),    /* fp */
  COSTS_N_INSNS (2),    /* dmul */
  COSTS_N_INSNS (19),   /* sdiv */
  COSTS_N_INSNS (19),   /* ddiv */
};

/* Instruction costs on RIOS2 processors.  */
static const
struct processor_costs rios2_cost = {
  COSTS_N_INSNS (2),    /* mulsi */
  COSTS_N_INSNS (2),    /* mulsi_const */
  COSTS_N_INSNS (2),    /* mulsi_const9 */
  COSTS_N_INSNS (2),    /* muldi */
  COSTS_N_INSNS (13),   /* divsi */
  COSTS_N_INSNS (13),   /* divdi */
  COSTS_N_INSNS (2),    /* fp */
  COSTS_N_INSNS (2),    /* dmul */
  COSTS_N_INSNS (17),   /* sdiv */
  COSTS_N_INSNS (17),   /* ddiv */
};

/* Instruction costs on RS64A processors.  */
static const
struct processor_costs rs64a_cost = {
  COSTS_N_INSNS (20),   /* mulsi */
  COSTS_N_INSNS (12),   /* mulsi_const */
  COSTS_N_INSNS (8),    /* mulsi_const9 */
  COSTS_N_INSNS (34),   /* muldi */
  COSTS_N_INSNS (65),   /* divsi */
  COSTS_N_INSNS (67),   /* divdi */
  COSTS_N_INSNS (4),    /* fp */
  COSTS_N_INSNS (4),    /* dmul */
  COSTS_N_INSNS (31),   /* sdiv */
  COSTS_N_INSNS (31),   /* ddiv */
};

/* Instruction costs on MPCCORE processors.  */
static const
struct processor_costs mpccore_cost = {
  COSTS_N_INSNS (2),    /* mulsi */
  COSTS_N_INSNS (2),    /* mulsi_const */
  COSTS_N_INSNS (2),    /* mulsi_const9 */
  COSTS_N_INSNS (2),    /* muldi */
  COSTS_N_INSNS (6),    /* divsi */
  COSTS_N_INSNS (6),    /* divdi */
  COSTS_N_INSNS (4),    /* fp */
  COSTS_N_INSNS (5),    /* dmul */
  COSTS_N_INSNS (10),   /* sdiv */
  COSTS_N_INSNS (17),   /* ddiv */
};

/* Instruction costs on PPC403 processors.  */
static const
struct processor_costs ppc403_cost = {
  COSTS_N_INSNS (4),    /* mulsi */
  COSTS_N_INSNS (4),    /* mulsi_const */
  COSTS_N_INSNS (4),    /* mulsi_const9 */
  COSTS_N_INSNS (4),    /* muldi */
  COSTS_N_INSNS (33),   /* divsi */
  COSTS_N_INSNS (33),   /* divdi */
  COSTS_N_INSNS (11),   /* fp */
  COSTS_N_INSNS (11),   /* dmul */
  COSTS_N_INSNS (11),   /* sdiv */
  COSTS_N_INSNS (11),   /* ddiv */
};

/* Instruction costs on PPC405 processors.  */
static const
struct processor_costs ppc405_cost = {
  COSTS_N_INSNS (5),    /* mulsi */
  COSTS_N_INSNS (4),    /* mulsi_const */
  COSTS_N_INSNS (3),    /* mulsi_const9 */
  COSTS_N_INSNS (5),    /* muldi */
  COSTS_N_INSNS (35),   /* divsi */
  COSTS_N_INSNS (35),   /* divdi */
  COSTS_N_INSNS (11),   /* fp */
  COSTS_N_INSNS (11),   /* dmul */
  COSTS_N_INSNS (11),   /* sdiv */
  COSTS_N_INSNS (11),   /* ddiv */
};

/* Instruction costs on PPC440 processors.  */
static const
struct processor_costs ppc440_cost = {
  COSTS_N_INSNS (3),    /* mulsi */
  COSTS_N_INSNS (2),    /* mulsi_const */
  COSTS_N_INSNS (2),    /* mulsi_const9 */
  COSTS_N_INSNS (3),    /* muldi */
  COSTS_N_INSNS (34),   /* divsi */
  COSTS_N_INSNS (34),   /* divdi */
  COSTS_N_INSNS (5),    /* fp */
  COSTS_N_INSNS (5),    /* dmul */
  COSTS_N_INSNS (19),   /* sdiv */
  COSTS_N_INSNS (33),   /* ddiv */
};

/* Instruction costs on PPC601 processors.  */
static const
struct processor_costs ppc601_cost = {
  COSTS_N_INSNS (5),    /* mulsi */
  COSTS_N_INSNS (5),    /* mulsi_const */
  COSTS_N_INSNS (5),    /* mulsi_const9 */
  COSTS_N_INSNS (5),    /* muldi */
  COSTS_N_INSNS (36),   /* divsi */
  COSTS_N_INSNS (36),   /* divdi */
  COSTS_N_INSNS (4),    /* fp */
  COSTS_N_INSNS (5),    /* dmul */
  COSTS_N_INSNS (17),   /* sdiv */
  COSTS_N_INSNS (31),   /* ddiv */
};

/* Instruction costs on PPC603 processors.  */
static const
struct processor_costs ppc603_cost = {
  COSTS_N_INSNS (5),    /* mulsi */
  COSTS_N_INSNS (3),    /* mulsi_const */
  COSTS_N_INSNS (2),    /* mulsi_const9 */
  COSTS_N_INSNS (5),    /* muldi */
  COSTS_N_INSNS (37),   /* divsi */
  COSTS_N_INSNS (37),   /* divdi */
  COSTS_N_INSNS (3),    /* fp */
  COSTS_N_INSNS (4),    /* dmul */
  COSTS_N_INSNS (18),   /* sdiv */
  COSTS_N_INSNS (33),   /* ddiv */
};

/* Instruction costs on PPC604 processors.  */
static const
struct processor_costs ppc604_cost = {
  COSTS_N_INSNS (4),    /* mulsi */
  COSTS_N_INSNS (4),    /* mulsi_const */
  COSTS_N_INSNS (4),    /* mulsi_const9 */
  COSTS_N_INSNS (4),    /* muldi */
  COSTS_N_INSNS (20),   /* divsi */
  COSTS_N_INSNS (20),   /* divdi */
  COSTS_N_INSNS (3),    /* fp */
  COSTS_N_INSNS (3),    /* dmul */
  COSTS_N_INSNS (18),   /* sdiv */
  COSTS_N_INSNS (32),   /* ddiv */
};

/* Instruction costs on PPC604e processors.  */
static const
struct processor_costs ppc604e_cost = {
  COSTS_N_INSNS (2),    /* mulsi */
  COSTS_N_INSNS (2),    /* mulsi_const */
  COSTS_N_INSNS (2),    /* mulsi_const9 */
  COSTS_N_INSNS (2),    /* muldi */
  COSTS_N_INSNS (20),   /* divsi */
  COSTS_N_INSNS (20),   /* divdi */
  COSTS_N_INSNS (3),    /* fp */
  COSTS_N_INSNS (3),    /* dmul */
  COSTS_N_INSNS (18),   /* sdiv */
  COSTS_N_INSNS (32),   /* ddiv */
};

/* Instruction costs on PPC620 processors.  */
static const
struct processor_costs ppc620_cost = {
  COSTS_N_INSNS (5),    /* mulsi */
  COSTS_N_INSNS (4),    /* mulsi_const */
  COSTS_N_INSNS (3),    /* mulsi_const9 */
  COSTS_N_INSNS (7),    /* muldi */
  COSTS_N_INSNS (21),   /* divsi */
  COSTS_N_INSNS (37),   /* divdi */
  COSTS_N_INSNS (3),    /* fp */
  COSTS_N_INSNS (3),    /* dmul */
  COSTS_N_INSNS (18),   /* sdiv */
  COSTS_N_INSNS (32),   /* ddiv */
};

/* Instruction costs on PPC630 processors.  */
static const
struct processor_costs ppc630_cost = {
  COSTS_N_INSNS (5),    /* mulsi */
  COSTS_N_INSNS (4),    /* mulsi_const */
  COSTS_N_INSNS (3),    /* mulsi_const9 */
  COSTS_N_INSNS (7),    /* muldi */
  COSTS_N_INSNS (21),   /* divsi */
  COSTS_N_INSNS (37),   /* divdi */
  COSTS_N_INSNS (3),    /* fp */
  COSTS_N_INSNS (3),    /* dmul */
  COSTS_N_INSNS (17),   /* sdiv */
  COSTS_N_INSNS (21),   /* ddiv */
};

/* Instruction costs on PPC750 and PPC7400 processors.  */
static const
struct processor_costs ppc750_cost = {
  COSTS_N_INSNS (5),    /* mulsi */
  COSTS_N_INSNS (3),    /* mulsi_const */
  COSTS_N_INSNS (2),    /* mulsi_const9 */
  COSTS_N_INSNS (5),    /* muldi */
  COSTS_N_INSNS (17),   /* divsi */
  COSTS_N_INSNS (17),   /* divdi */
  COSTS_N_INSNS (3),    /* fp */
  COSTS_N_INSNS (3),    /* dmul */
  COSTS_N_INSNS (17),   /* sdiv */
  COSTS_N_INSNS (31),   /* ddiv */
};

/* Instruction costs on PPC7450 processors.  */
static const
struct processor_costs ppc7450_cost = {
  COSTS_N_INSNS (4),    /* mulsi */
  COSTS_N_INSNS (3),    /* mulsi_const */
  COSTS_N_INSNS (3),    /* mulsi_const9 */
  COSTS_N_INSNS (4),    /* muldi */
  COSTS_N_INSNS (23),   /* divsi */
  COSTS_N_INSNS (23),   /* divdi */
  COSTS_N_INSNS (5),    /* fp */
  COSTS_N_INSNS (5),    /* dmul */
  COSTS_N_INSNS (21),   /* sdiv */
  COSTS_N_INSNS (35),   /* ddiv */
};

/* Instruction costs on PPC8540 processors.  */
static const
struct processor_costs ppc8540_cost = {
  COSTS_N_INSNS (4),    /* mulsi */
  COSTS_N_INSNS (4),    /* mulsi_const */
  COSTS_N_INSNS (4),    /* mulsi_const9 */
  COSTS_N_INSNS (4),    /* muldi */
  COSTS_N_INSNS (19),   /* divsi */
  COSTS_N_INSNS (19),   /* divdi */
  COSTS_N_INSNS (4),    /* fp */
  COSTS_N_INSNS (4),    /* dmul */
  COSTS_N_INSNS (29),   /* sdiv */
  COSTS_N_INSNS (29),   /* ddiv */
};

/* Instruction costs on POWER4 and POWER5 processors.  */
static const
struct processor_costs power4_cost = {
  COSTS_N_INSNS (3),    /* mulsi */
  COSTS_N_INSNS (2),    /* mulsi_const */
  COSTS_N_INSNS (2),    /* mulsi_const9 */
  COSTS_N_INSNS (4),    /* muldi */
  COSTS_N_INSNS (18),   /* divsi */
  COSTS_N_INSNS (34),   /* divdi */
  COSTS_N_INSNS (3),    /* fp */
  COSTS_N_INSNS (3),    /* dmul */
  COSTS_N_INSNS (17),   /* sdiv */
  COSTS_N_INSNS (17),   /* ddiv */
};


static bool rs6000_function_ok_for_sibcall (tree, tree);
static const char *rs6000_invalid_within_doloop (rtx);
static rtx rs6000_generate_compare (enum rtx_code);
static void rs6000_maybe_dead (rtx);
static void rs6000_emit_stack_tie (void);
static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
static rtx spe_synthesize_frame_save (rtx);
static bool spe_func_has_64bit_regs_p (void);
static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
           int, HOST_WIDE_INT);
static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
static unsigned rs6000_hash_constant (rtx);
static unsigned toc_hash_function (const void *);
static int toc_hash_eq (const void *, const void *);
static int constant_pool_expr_1 (rtx, int *, int *);
static bool constant_pool_expr_p (rtx);
static bool legitimate_small_data_p (enum machine_mode, rtx);
static bool legitimate_indexed_address_p (rtx, int);
static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
static struct machine_function * rs6000_init_machine_status (void);
static bool rs6000_assemble_integer (rtx, unsigned int, int);
static bool no_global_regs_above (int);
#ifdef HAVE_GAS_HIDDEN
static void rs6000_assemble_visibility (tree, int);
#endif
static int rs6000_ra_ever_killed (void);
static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
static bool rs6000_ms_bitfield_layout_p (tree);
static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
static const char *rs6000_mangle_fundamental_type (tree);
extern const struct attribute_spec rs6000_attribute_table[];
static void rs6000_set_default_type_attributes (tree);
static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
            tree);
static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
static bool rs6000_return_in_memory (tree, tree);
static void rs6000_file_start (void);
#if TARGET_ELF
static int rs6000_elf_reloc_rw_mask (void);
static void rs6000_elf_asm_out_constructor (rtx, int);
static void rs6000_elf_asm_out_destructor (rtx, int);
static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
static void rs6000_elf_asm_init_sections (void);
static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
                 unsigned HOST_WIDE_INT);
static void rs6000_elf_encode_section_info (tree, rtx, int)
     ATTRIBUTE_UNUSED;
#endif
static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
#if TARGET_XCOFF
static void rs6000_xcoff_asm_output_anchor (rtx);
static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
static void rs6000_xcoff_asm_init_sections (void);
static int rs6000_xcoff_reloc_rw_mask (void);
static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
static section *rs6000_xcoff_select_section (tree, int,
               unsigned HOST_WIDE_INT);
static void rs6000_xcoff_unique_section (tree, int);
static section *rs6000_xcoff_select_rtx_section
  (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
static const char * rs6000_xcoff_strip_name_encoding (const char *);
static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
static void rs6000_xcoff_file_start (void);
static void rs6000_xcoff_file_end (void);
#endif
static int rs6000_variable_issue (FILE *, int, rtx, int);
static bool rs6000_rtx_costs (rtx, int, int, int *);
static int rs6000_adjust_cost (rtx, rtx, rtx, int);
static bool is_microcoded_insn (rtx);
static int is_dispatch_slot_restricted (rtx);
static bool is_cracked_insn (rtx);
static bool is_branch_slot_insn (rtx);
static int rs6000_adjust_priority (rtx, int);
static int rs6000_issue_rate (void);
static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
static rtx get_next_active_insn (rtx, rtx);
static bool insn_terminates_group_p (rtx , enum group_termination);
static bool is_costly_group (rtx *, rtx);
static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
static int redefine_groups (FILE *, int, rtx, rtx);
static int pad_groups (FILE *, int, rtx, rtx);
static void rs6000_sched_finish (FILE *, int);
static int rs6000_use_sched_lookahead (void);
static tree rs6000_builtin_mask_for_load (void);

static void def_builtin (int, const char *, tree, int);
static void rs6000_init_builtins (void);
static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
static void altivec_init_builtins (void);
static void rs6000_common_init_builtins (void);
static void rs6000_init_libfuncs (void);

static void enable_mask_for_builtins (struct builtin_description *, int,
              enum rs6000_builtins,
              enum rs6000_builtins);
static tree build_opaque_vector_type (tree, int);
static void spe_init_builtins (void);
static rtx spe_expand_builtin (tree, rtx, bool *);
static rtx spe_expand_stv_builtin (enum insn_code, tree);
static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
static rs6000_stack_t *rs6000_stack_info (void);
static void debug_stack_info (rs6000_stack_t *);

static rtx altivec_expand_builtin (tree, rtx, bool *);
static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
static rtx altivec_expand_st_builtin (tree, rtx, bool *);
static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
static rtx altivec_expand_predicate_builtin (enum insn_code,
               const char *, tree, rtx);
static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
static rtx altivec_expand_stv_builtin (enum insn_code, tree);
static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
static rtx altivec_expand_vec_set_builtin (tree);
static rtx altivec_expand_vec_ext_builtin (tree, rtx);
static int get_element_number (tree, tree);
static bool rs6000_handle_option (size_t, const char *, int);
static void rs6000_parse_tls_size_option (void);
static void rs6000_parse_yes_no_option (const char *, const char *, int *);
static int first_altivec_reg_to_save (void);
static unsigned int compute_vrsave_mask (void);
static void compute_save_world_info (rs6000_stack_t *info_ptr);
static void is_altivec_return_reg (rtx, void *);
static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
int easy_vector_constant (rtx, enum machine_mode);
static bool rs6000_is_opaque_type (tree);
static rtx rs6000_dwarf_register_span (rtx);
static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
static rtx rs6000_tls_get_addr (void);
static rtx rs6000_got_sym (void);
static int rs6000_tls_symbol_ref_1 (rtx *, void *);
static const char *rs6000_get_some_local_dynamic_name (void);
static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
static rtx rs6000_complex_function_value (enum machine_mode);
static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
            enum machine_mode, tree);
static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
                  HOST_WIDE_INT);
static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
              tree, HOST_WIDE_INT);
static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
                HOST_WIDE_INT,
                rtx[], int *);
static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
                 tree, HOST_WIDE_INT,
                 rtx[], int *);
static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
static void setup_incoming_varargs (CUMULATIVE_ARGS *,
            enum machine_mode, tree,
            int *, int);
static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
              tree, bool);
static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
             tree, bool);
static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
#if TARGET_MACHO
static void macho_branch_islands (void);
static int no_previous_def (tree function_name);
static tree get_prev_label (tree function_name);
static void rs6000_darwin_file_start (void);
#endif

static tree rs6000_build_builtin_va_list (void);
static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
static bool rs6000_scalar_mode_supported_p (enum machine_mode);
static bool rs6000_vector_mode_supported_p (enum machine_mode);
static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
           enum machine_mode);
static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
               enum machine_mode);
static int get_vsel_insn (enum machine_mode);
static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
static tree rs6000_stack_protect_fail (void);

const int INSN_NOT_AVAILABLE = -1;
static enum machine_mode rs6000_eh_return_filter_mode (void);

/* Hash table stuff for keeping track of TOC entries.  */

struct toc_hash_struct GTY(())
{
  /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
     ASM_OUTPUT_SPECIAL_POOL_ENTRY_P.  */
  rtx key;
  enum machine_mode key_mode;
  int labelno;
};

static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;

/* Default register names.  */
char rs6000_reg_names[][8] =
{
      "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
      "8",  "9", "10", "11", "12", "13", "14", "15",
     "16", "17", "18", "19", "20", "21", "22", "23",
     "24", "25", "26", "27", "28", "29", "30", "31",
      "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
      "8",  "9", "10", "11", "12", "13", "14", "15",
     "16", "17", "18", "19", "20", "21", "22", "23",
     "24", "25", "26", "27", "28", "29", "30", "31",
     "mq", "lr", "ctr","ap",
      "0",  "1",  "2",  "3",  "4",  "5",  "6",  "7",
      "xer",
      /* AltiVec registers.  */
      "0",  "1",  "2",  "3",  "4",  "5",  "6", "7",
      "8",  "9",  "10", "11", "12", "13", "14", "15",
      "16", "17", "18", "19", "20", "21", "22", "23",
      "24", "25", "26", "27", "28", "29", "30", "31",
      "vrsave", "vscr",
      /* SPE registers.  */
      "spe_acc", "spefscr",
      /* Soft frame pointer.  */
      "sfp"
};

#ifdef TARGET_REGNAMES
static const char alt_reg_names[][8] =
{
   "%r0",   "%r1",  "%r2",  "%r3",  "%r4",  "%r5",  "%r6",  "%r7",
   "%r8",   "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
  "%r16",  "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
  "%r24",  "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
   "%f0",   "%f1",  "%f2",  "%f3",  "%f4",  "%f5",  "%f6",  "%f7",
   "%f8",   "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
  "%f16",  "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
  "%f24",  "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
    "mq",    "lr",  "ctr",   "ap",
  "%cr0",  "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
   "xer",
  /* AltiVec registers.  */
   "%v0",  "%v1",  "%v2",  "%v3",  "%v4",  "%v5",  "%v6", "%v7",
   "%v8",  "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
  "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
  "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
  "vrsave", "vscr",
  /* SPE registers.  */
  "spe_acc", "spefscr",
  /* Soft frame pointer.  */
  "sfp"
};
#endif

#ifndef MASK_STRICT_ALIGN
#define MASK_STRICT_ALIGN 0
#endif
#ifndef TARGET_PROFILE_KERNEL
#define TARGET_PROFILE_KERNEL 0
#endif

/* The VRSAVE bitmask puts bit %v0 as the most significant bit.  */
#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))

/* Initialize the GCC target structure.  */
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes

#undef TARGET_ASM_ALIGNED_DI_OP
#define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP

/* Default unaligned ops are only provided for ELF.  Find the ops needed
   for non-ELF systems.  */
#ifndef OBJECT_FORMAT_ELF
#if TARGET_XCOFF
/* For XCOFF.  rs6000_assemble_integer will handle unaligned DIs on
   64-bit targets.  */
#undef TARGET_ASM_UNALIGNED_HI_OP
#define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
#undef TARGET_ASM_UNALIGNED_SI_OP
#define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
#else
/* For Darwin.  */
#undef TARGET_ASM_UNALIGNED_HI_OP
#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
#undef TARGET_ASM_UNALIGNED_SI_OP
#define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
#undef TARGET_ASM_ALIGNED_DI_OP
#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
#endif
#endif

/* This hook deals with fixups for relocatable code and DI-mode objects
   in 64-bit code.  */
#undef TARGET_ASM_INTEGER
#define TARGET_ASM_INTEGER rs6000_assemble_integer

#ifdef HAVE_GAS_HIDDEN
#undef TARGET_ASM_ASSEMBLE_VISIBILITY
#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
#endif

#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS HAVE_AS_TLS

#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p

#undef TARGET_ASM_FUNCTION_PROLOGUE
#define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
#undef TARGET_ASM_FUNCTION_EPILOGUE
#define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue

#undef  TARGET_SCHED_VARIABLE_ISSUE
#define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue

#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
#undef TARGET_SCHED_ADJUST_PRIORITY
#define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
#undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
#define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
#undef TARGET_SCHED_FINISH
#define TARGET_SCHED_FINISH rs6000_sched_finish

#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead

#undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
#define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load

#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS rs6000_init_builtins

#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN rs6000_expand_builtin

#undef TARGET_MANGLE_FUNDAMENTAL_TYPE
#define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type

#undef TARGET_INIT_LIBFUNCS
#define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs

#if TARGET_MACHO
#undef TARGET_BINDS_LOCAL_P
#define TARGET_BINDS_LOCAL_P darwin_binds_local_p
#endif

#undef TARGET_MS_BITFIELD_LAYOUT_P
#define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p

#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk

#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true

#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall

#undef TARGET_INVALID_WITHIN_DOLOOP
#define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop

#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS rs6000_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST hook_int_rtx_0

#undef TARGET_VECTOR_OPAQUE_P
#define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type

#undef TARGET_DWARF_REGISTER_SPAN
#define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span

/* On rs6000, function arguments are promoted, as are function return
   values.  */
#undef TARGET_PROMOTE_FUNCTION_ARGS
#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
#undef TARGET_PROMOTE_FUNCTION_RETURN
#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true

#undef TARGET_RETURN_IN_MEMORY
#define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory

#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs

/* Always strict argument naming on rs6000.  */
#undef TARGET_STRICT_ARGUMENT_NAMING
#define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
#undef TARGET_SPLIT_COMPLEX_ARG
#define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
#undef TARGET_ARG_PARTIAL_BYTES
#define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes

#undef TARGET_BUILD_BUILTIN_VA_LIST
#define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list

#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg

#undef TARGET_EH_RETURN_FILTER_MODE
#define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode

#undef TARGET_SCALAR_MODE_SUPPORTED_P
#define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p

#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p

#undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
#define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn

#undef TARGET_HANDLE_OPTION
#define TARGET_HANDLE_OPTION rs6000_handle_option

#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS \
  (TARGET_DEFAULT)

#undef TARGET_STACK_PROTECT_FAIL
#define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail

/* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
   The PowerPC architecture requires only weak consistency among
   processors--that is, memory accesses between processors need not be
   sequentially consistent and memory accesses among processors can occur
   in any order. The ability to order memory accesses weakly provides
   opportunities for more efficient use of the system bus. Unless a
   dependency exists, the 604e allows read operations to precede store
   operations.  */
#undef TARGET_RELAXED_ORDERING
#define TARGET_RELAXED_ORDERING true

#ifdef HAVE_AS_TLS
#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
#define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
#endif

/* Use a 32-bit anchor range.  This leads to sequences like:

  addis tmp,anchor,high
  add dest,tmp,low

   where tmp itself acts as an anchor, and can be shared between
   accesses to the same 64k page.  */
#undef TARGET_MIN_ANCHOR_OFFSET
#define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
#undef TARGET_MAX_ANCHOR_OFFSET
#define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
#define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p

struct gcc_target targetm = TARGET_INITIALIZER;


/* Value is 1 if hard register REGNO can hold a value of machine-mode
   MODE.  */
static int
rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
{
  /* The GPRs can hold any mode, but values bigger than one register
     cannot go past R31.  */
  if (INT_REGNO_P (regno))
    return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);

  /* The float registers can only hold floating modes and DImode.
     This also excludes decimal float modes.  */
  if (FP_REGNO_P (regno))
    return
      (SCALAR_FLOAT_MODE_P (mode)
       && !DECIMAL_FLOAT_MODE_P (mode)
       && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
      || (GET_MODE_CLASS (mode) == MODE_INT
    && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);

  /* The CR register can only hold CC modes.  */
  if (CR_REGNO_P (regno))
    return GET_MODE_CLASS (mode) == MODE_CC;

  if (XER_REGNO_P (regno))
    return mode == PSImode;

  /* AltiVec only in AldyVec registers.  */
  if (ALTIVEC_REGNO_P (regno))
    return ALTIVEC_VECTOR_MODE (mode);

  /* ...but GPRs can hold SIMD data on the SPE in one register.  */
  if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
    return 1;

  /* We cannot put TImode anywhere except general register and it must be
     able to fit within the register set.  */

  return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
}

/* Initialize rs6000_hard_regno_mode_ok_p table.  */
static void
rs6000_init_hard_regno_mode_ok (void)
{
  int r, m;

  for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
    for (m = 0; m < NUM_MACHINE_MODES; ++m)
      if (rs6000_hard_regno_mode_ok (r, m))
  rs6000_hard_regno_mode_ok_p[m][r] = true;
}

/* If not otherwise specified by a target, make 'long double' equivalent to
   'double'.  */

#ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
#define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
#endif

/* Override command line options.  Mostly we process the processor
   type and sometimes adjust other TARGET_ options.  */

void
rs6000_override_options (const char *default_cpu)
{
  size_t i, j;
  struct rs6000_cpu_select *ptr;
  int set_masks;

  /* Simplifications for entries below.  */

  enum {
    POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
    POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
  };

  /* This table occasionally claims that a processor does not support
     a particular feature even though it does, but the feature is slower
     than the alternative.  Thus, it shouldn't be relied on as a
     complete description of the processor's support.

     Please keep this list in order, and don't forget to update the
     documentation in invoke.texi when adding a new processor or
     flag.  */
  static struct ptt
    {
      const char *const name;   /* Canonical processor name.  */
      const enum processor_type processor; /* Processor type enum value.  */
      const int target_enable;  /* Target flags to enable.  */
    } const processor_target_table[]
      = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
   {"403", PROCESSOR_PPC403,
    POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
   {"405", PROCESSOR_PPC405,
    POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
   {"405fp", PROCESSOR_PPC405,
    POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
   {"440", PROCESSOR_PPC440,
    POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
   {"440fp", PROCESSOR_PPC440,
    POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
   {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
   {"601", PROCESSOR_PPC601,
    MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
   {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
   {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
   {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
   {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
   {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
   {"620", PROCESSOR_PPC620,
    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
   {"630", PROCESSOR_PPC630,
    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
   {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
   {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
   {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
   {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
   {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
   {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
   {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
   {"8540", PROCESSOR_PPC8540,
    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
   /* 8548 has a dummy entry for now.  */
   {"8548", PROCESSOR_PPC8540,
    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
   {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
   {"970", PROCESSOR_POWER4,
    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
   {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
   {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
   {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
   {"G4",  PROCESSOR_PPC7450, POWERPC_7400_MASK},
   {"G5", PROCESSOR_POWER4,
    POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
   {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
   {"power2", PROCESSOR_POWER,
    MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
   {"power3", PROCESSOR_PPC630,
    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
   {"power4", PROCESSOR_POWER4,
    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
   {"power5", PROCESSOR_POWER5,
    POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
    | MASK_MFCRF | MASK_POPCNTB},
   {"power5+", PROCESSOR_POWER5,
    POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
    | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
   {"power6", PROCESSOR_POWER5,
    POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
    | MASK_FPRND},
   {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
   {"powerpc64", PROCESSOR_POWERPC64,
    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
   {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
   {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
   {"rios2", PROCESSOR_RIOS2,
    MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
   {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
   {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
   {"rs64", PROCESSOR_RS64A,
    POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
      };

  const size_t ptt_size = ARRAY_SIZE (processor_target_table);

  /* Some OSs don't support saving the high part of 64-bit registers on
     context switch.  Other OSs don't support saving Altivec registers.
     On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
     settings; if the user wants either, the user must explicitly specify
     them and we won't interfere with the user's specification.  */

  enum {
    POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
    POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
         | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
         | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
         | MASK_DLMZB)
  };

  rs6000_init_hard_regno_mode_ok ();

  set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
#ifdef OS_MISSING_POWERPC64
  if (OS_MISSING_POWERPC64)
    set_masks &= ~MASK_POWERPC64;
#endif
#ifdef OS_MISSING_ALTIVEC
  if (OS_MISSING_ALTIVEC)
    set_masks &= ~MASK_ALTIVEC;
#endif

  /* Don't override by the processor default if given explicitly.  */
  set_masks &= ~target_flags_explicit;

  /* Identify the processor type.  */
  rs6000_select[0].string = default_cpu;
  rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;

  for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
    {
      ptr = &rs6000_select[i];
      if (ptr->string != (char *)0 && ptr->string[0] != '\0')
  {
    for (j = 0; j < ptt_size; j++)
      if (! strcmp (ptr->string, processor_target_table[j].name))
        {
    if (ptr->set_tune_p)
      rs6000_cpu = processor_target_table[j].processor;

    if (ptr->set_arch_p)
      {
        target_flags &= ~set_masks;
        target_flags |= (processor_target_table[j].target_enable
             & set_masks);
      }
    break;
        }

    if (j == ptt_size)
      error ("bad value (%s) for %s switch", ptr->string, ptr->name);
  }
    }

  if (TARGET_E500)
    rs6000_isel = 1;

  /* If we are optimizing big endian systems for space, use the load/store
     multiple and string instructions.  */
  if (BYTES_BIG_ENDIAN && optimize_size)
    target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);

  /* Don't allow -mmultiple or -mstring on little endian systems
     unless the cpu is a 750, because the hardware doesn't support the
     instructions used in little endian mode, and causes an alignment
     trap.  The 750 does not cause an alignment trap (except when the
     target is unaligned).  */

  if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
    {
      if (TARGET_MULTIPLE)
  {
    target_flags &= ~MASK_MULTIPLE;
    if ((target_flags_explicit & MASK_MULTIPLE) != 0)
      warning (0, "-mmultiple is not supported on little endian systems");
  }

      if (TARGET_STRING)
  {
    target_flags &= ~MASK_STRING;
    if ((target_flags_explicit & MASK_STRING) != 0)
      warning (0, "-mstring is not supported on little endian systems");
  }
    }

  /* Set debug flags */
  if (rs6000_debug_name)
    {
      if (! strcmp (rs6000_debug_name, "all"))
  rs6000_debug_stack = rs6000_debug_arg = 1;
      else if (! strcmp (rs6000_debug_name, "stack"))
  rs6000_debug_stack = 1;
      else if (! strcmp (rs6000_debug_name, "arg"))
  rs6000_debug_arg = 1;
      else
  error ("unknown -mdebug-%s switch", rs6000_debug_name);
    }

  if (rs6000_traceback_name)
    {
      if (! strncmp (rs6000_traceback_name, "full", 4))
  rs6000_traceback = traceback_full;
      else if (! strncmp (rs6000_traceback_name, "part", 4))
  rs6000_traceback = traceback_part;
      else if (! strncmp (rs6000_traceback_name, "no", 2))
  rs6000_traceback = traceback_none;
      else
  error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
         rs6000_traceback_name);
    }

  if (!rs6000_explicit_options.long_double)
    rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;

#ifndef POWERPC_LINUX
  if (!rs6000_explicit_options.ieee)
    rs6000_ieeequad = 1;
#endif

  /* Set Altivec ABI as default for powerpc64 linux.  */
  if (TARGET_ELF && TARGET_64BIT)
    {
      rs6000_altivec_abi = 1;
      TARGET_ALTIVEC_VRSAVE = 1;
    }

  /* Set the Darwin64 ABI as default for 64-bit Darwin.  */
  if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
    {
      rs6000_darwin64_abi = 1;
#if TARGET_MACHO
      darwin_one_byte_bool = 1;
#endif
      /* Default to natural alignment, for better performance.  */
      rs6000_alignment_flags = MASK_ALIGN_NATURAL;
    }

  /* Place FP constants in the constant pool instead of TOC
     if section anchors enabled.  */
  if (flag_section_anchors)
    TARGET_NO_FP_IN_TOC = 1;

  /* Handle -mtls-size option.  */
  rs6000_parse_tls_size_option ();

#ifdef SUBTARGET_OVERRIDE_OPTIONS
  SUBTARGET_OVERRIDE_OPTIONS;
#endif
#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
  SUBSUBTARGET_OVERRIDE_OPTIONS;
#endif
#ifdef SUB3TARGET_OVERRIDE_OPTIONS
  SUB3TARGET_OVERRIDE_OPTIONS;
#endif

  if (TARGET_E500)
    {
      if (TARGET_ALTIVEC)
  error ("AltiVec and E500 instructions cannot coexist");

      /* The e500 does not have string instructions, and we set
   MASK_STRING above when optimizing for size.  */
      if ((target_flags & MASK_STRING) != 0)
  target_flags = target_flags & ~MASK_STRING;
    }
  else if (rs6000_select[1].string != NULL)
    {
      /* For the powerpc-eabispe configuration, we set all these by
   default, so let's unset them if we manually set another
   CPU that is not the E500.  */
      if (!rs6000_explicit_options.abi)
  rs6000_spe_abi = 0;
      if (!rs6000_explicit_options.spe)
  rs6000_spe = 0;
      if (!rs6000_explicit_options.float_gprs)
  rs6000_float_gprs = 0;
      if (!rs6000_explicit_options.isel)
  rs6000_isel = 0;
      if (!rs6000_explicit_options.long_double)
  rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
    }

  rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
      && rs6000_cpu != PROCESSOR_POWER5);
  rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
       || rs6000_cpu == PROCESSOR_POWER5);

  rs6000_sched_restricted_insns_priority
    = (rs6000_sched_groups ? 1 : 0);

  /* Handle -msched-costly-dep option.  */
  rs6000_sched_costly_dep
    = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);

  if (rs6000_sched_costly_dep_str)
    {
      if (! strcmp (rs6000_sched_costly_dep_str, "no"))
  rs6000_sched_costly_dep = no_dep_costly;
      else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
  rs6000_sched_costly_dep = all_deps_costly;
      else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
  rs6000_sched_costly_dep = true_store_to_load_dep_costly;
      else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
  rs6000_sched_costly_dep = store_to_load_dep_costly;
      else
  rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
    }

  /* Handle -minsert-sched-nops option.  */
  rs6000_sched_insert_nops
    = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);

  if (rs6000_sched_insert_nops_str)
    {
      if (! strcmp (rs6000_sched_insert_nops_str, "no"))
  rs6000_sched_insert_nops = sched_finish_none;
      else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
  rs6000_sched_insert_nops = sched_finish_pad_groups;
      else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
  rs6000_sched_insert_nops = sched_finish_regroup_exact;
      else
  rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
    }

#ifdef TARGET_REGNAMES
  /* If the user desires alternate register names, copy in the
     alternate names now.  */
  if (TARGET_REGNAMES)
    memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
#endif

  /* Set aix_struct_return last, after the ABI is determined.
     If -maix-struct-return or -msvr4-struct-return was explicitly
     used, don't override with the ABI default.  */
  if (!rs6000_explicit_options.aix_struct_ret)
    aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);

  if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
    REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;

  if (TARGET_TOC)
    ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);

  /* We can only guarantee the availability of DI pseudo-ops when
     assembling for 64-bit targets.  */
  if (!TARGET_64BIT)
    {
      targetm.asm_out.aligned_op.di = NULL;
      targetm.asm_out.unaligned_op.di = NULL;
    }

  /* Set branch target alignment, if not optimizing for size.  */
  if (!optimize_size)
    {
      if (rs6000_sched_groups)
  {
    if (align_functions <= 0)
      align_functions = 16;
    if (align_jumps <= 0)
      align_jumps = 16;
    if (align_loops <= 0)
      align_loops = 16;
  }
      if (align_jumps_max_skip <= 0)
  align_jumps_max_skip = 15;
      if (align_loops_max_skip <= 0)
  align_loops_max_skip = 15;
    }

  /* Arrange to save and restore machine status around nested functions.  */
  init_machine_status = rs6000_init_machine_status;

  /* We should always be splitting complex arguments, but we can't break
     Linux and Darwin ABIs at the moment.  For now, only AIX is fixed.  */
  if (DEFAULT_ABI != ABI_AIX)
    targetm.calls.split_complex_arg = NULL;

  /* Initialize rs6000_cost with the appropriate target costs.  */
  if (optimize_size)
    rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
  else
    switch (rs6000_cpu)
      {
      case PROCESSOR_RIOS1:
  rs6000_cost = &rios1_cost;
  break;

      case PROCESSOR_RIOS2:
  rs6000_cost = &rios2_cost;
  break;

      case PROCESSOR_RS64A:
  rs6000_cost = &rs64a_cost;
  break;

      case PROCESSOR_MPCCORE:
  rs6000_cost = &mpccore_cost;
  break;

      case PROCESSOR_PPC403:
  rs6000_cost = &ppc403_cost;
  break;

      case PROCESSOR_PPC405:
  rs6000_cost = &ppc405_cost;
  break;

      case PROCESSOR_PPC440:
  rs6000_cost = &ppc440_cost;
  break;

      case PROCESSOR_PPC601:
  rs6000_cost = &ppc601_cost;
  break;

      case PROCESSOR_PPC603:
  rs6000_cost = &ppc603_cost;
  break;

      case PROCESSOR_PPC604:
  rs6000_cost = &ppc604_cost;
  break;

      case PROCESSOR_PPC604e:
  rs6000_cost = &ppc604e_cost;
  break;

      case PROCESSOR_PPC620:
  rs6000_cost = &ppc620_cost;
  break;

      case PROCESSOR_PPC630:
  rs6000_cost = &ppc630_cost;
  break;

      case PROCESSOR_PPC750:
      case PROCESSOR_PPC7400:
  rs6000_cost = &ppc750_cost;
  break;

      case PROCESSOR_PPC7450:
  rs6000_cost = &ppc7450_cost;
  break;

      case PROCESSOR_PPC8540:
  rs6000_cost = &ppc8540_cost;
  break;

      case PROCESSOR_POWER4:
      case PROCESSOR_POWER5:
  rs6000_cost = &power4_cost;
  break;

      default:
  gcc_unreachable ();
      }
}

/* Implement targetm.vectorize.builtin_mask_for_load.  */
static tree
rs6000_builtin_mask_for_load (void)
{
  if (TARGET_ALTIVEC)
    return altivec_builtin_mask_for_load;
  else
    return 0;
}

/* Handle generic options of the form -mfoo=yes/no.
   NAME is the option name.
   VALUE is the option value.
   FLAG is the pointer to the flag where to store a 1 or 0, depending on
   whether the option value is 'yes' or 'no' respectively.  */
static void
rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
{
  if (value == 0)
    return;
  else if (!strcmp (value, "yes"))
    *flag = 1;
  else if (!strcmp (value, "no"))
    *flag = 0;
  else
    error ("unknown -m%s= option specified: '%s'", name, value);
}

/* Validate and record the size specified with the -mtls-size option.  */

static void
rs6000_parse_tls_size_option (void)
{
  if (rs6000_tls_size_string == 0)
    return;
  else if (strcmp (rs6000_tls_size_string, "16") == 0)
    rs6000_tls_size = 16;
  else if (strcmp (rs6000_tls_size_string, "32") == 0)
    rs6000_tls_size = 32;
  else if (strcmp (rs6000_tls_size_string, "64") == 0)
    rs6000_tls_size = 64;
  else
    error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
}

void
optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
{
  if (DEFAULT_ABI == ABI_DARWIN)
    /* The Darwin libraries never set errno, so we might as well
       avoid calling them when that's the only reason we would.  */
    flag_errno_math = 0;

  /* Double growth factor to counter reduced min jump length.  */
  set_param_value ("max-grow-copy-bb-insns", 16);

  /* Enable section anchors by default.
     Skip section anchors for Objective C and Objective C++
     until front-ends fixed.  */
  if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
    flag_section_anchors = 1;
}

/* Implement TARGET_HANDLE_OPTION.  */

static bool
rs6000_handle_option (size_t code, const char *arg, int value)
{
  switch (code)
    {
    case OPT_mno_power:
      target_flags &= ~(MASK_POWER | MASK_POWER2
      | MASK_MULTIPLE | MASK_STRING);
      target_flags_explicit |= (MASK_POWER | MASK_POWER2
        | MASK_MULTIPLE | MASK_STRING);
      break;
    case OPT_mno_powerpc:
      target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
      | MASK_PPC_GFXOPT | MASK_POWERPC64);
      target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
        | MASK_PPC_GFXOPT | MASK_POWERPC64);
      break;
    case OPT_mfull_toc:
      target_flags &= ~MASK_MINIMAL_TOC;
      TARGET_NO_FP_IN_TOC = 0;
      TARGET_NO_SUM_IN_TOC = 0;
      target_flags_explicit |= MASK_MINIMAL_TOC;
#ifdef TARGET_USES_SYSV4_OPT
      /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
   just the same as -mminimal-toc.  */
      target_flags |= MASK_MINIMAL_TOC;
      target_flags_explicit |= MASK_MINIMAL_TOC;
#endif
      break;

#ifdef TARGET_USES_SYSV4_OPT
    case OPT_mtoc:
      /* Make -mtoc behave like -mminimal-toc.  */
      target_flags |= MASK_MINIMAL_TOC;
      target_flags_explicit |= MASK_MINIMAL_TOC;
      break;
#endif

#ifdef TARGET_USES_AIX64_OPT
    case OPT_maix64:
#else
    case OPT_m64:
#endif
      target_flags |= MASK_POWERPC64 | MASK_POWERPC;
      target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
      target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
      break;

#ifdef TARGET_USES_AIX64_OPT
    case OPT_maix32:
#else
    case OPT_m32:
#endif
      target_flags &= ~MASK_POWERPC64;
      target_flags_explicit |= MASK_POWERPC64;
      break;

    case OPT_minsert_sched_nops_:
      rs6000_sched_insert_nops_str = arg;
      break;

    case OPT_mminimal_toc:
      if (value == 1)
  {
    TARGET_NO_FP_IN_TOC = 0;
    TARGET_NO_SUM_IN_TOC = 0;
  }
      break;

    case OPT_mpower:
      if (value == 1)
  {
    target_flags |= (MASK_MULTIPLE | MASK_STRING);
    target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
  }
      break;

    case OPT_mpower2:
      if (value == 1)
  {
    target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
    target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
  }
      break;

    case OPT_mpowerpc_gpopt:
    case OPT_mpowerpc_gfxopt:
      if (value == 1)
  {
    target_flags |= MASK_POWERPC;
    target_flags_explicit |= MASK_POWERPC;
  }
      break;

    case OPT_maix_struct_return:
    case OPT_msvr4_struct_return:
      rs6000_explicit_options.aix_struct_ret = true;
      break;

    case OPT_mvrsave_:
      rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
      break;

    case OPT_misel_:
      rs6000_explicit_options.isel = true;
      rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
      break;

    case OPT_mspe_:
      rs6000_explicit_options.spe = true;
      rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
      /* No SPE means 64-bit long doubles, even if an E500.  */
      if (!rs6000_spe)
  rs6000_long_double_type_size = 64;
      break;

    case OPT_mdebug_:
      rs6000_debug_name = arg;
      break;

#ifdef TARGET_USES_SYSV4_OPT
    case OPT_mcall_:
      rs6000_abi_name = arg;
      break;

    case OPT_msdata_:
      rs6000_sdata_name = arg;
      break;

    case OPT_mtls_size_:
      rs6000_tls_size_string = arg;
      break;

    case OPT_mrelocatable:
      if (value == 1)
  {
    target_flags |= MASK_MINIMAL_TOC;
    target_flags_explicit |= MASK_MINIMAL_TOC;
    TARGET_NO_FP_IN_TOC = 1;
  }
      break;

    case OPT_mrelocatable_lib:
      if (value == 1)
  {
    target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
    target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
    TARGET_NO_FP_IN_TOC = 1;
  }
      else
  {
    target_flags &= ~MASK_RELOCATABLE;
    target_flags_explicit |= MASK_RELOCATABLE;
  }
      break;
#endif

    case OPT_mabi_:
      if (!strcmp (arg, "altivec"))
  {
    rs6000_explicit_options.abi = true;
    rs6000_altivec_abi = 1;
    rs6000_spe_abi = 0;
  }
      else if (! strcmp (arg, "no-altivec"))
  {
    /* ??? Don't set rs6000_explicit_options.abi here, to allow
       the default for rs6000_spe_abi to be chosen later.  */
    rs6000_altivec_abi = 0;
  }
      else if (! strcmp (arg, "spe"))
  {
    rs6000_explicit_options.abi = true;
    rs6000_spe_abi = 1;
    rs6000_altivec_abi = 0;
    if (!TARGET_SPE_ABI)
      error ("not configured for ABI: '%s'", arg);
  }
      else if (! strcmp (arg, "no-spe"))
  {
    rs6000_explicit_options.abi = true;
    rs6000_spe_abi = 0;
  }

      /* These are here for testing during development only, do not
   document in the manual please.  */
      else if (! strcmp (arg, "d64"))
  {
    rs6000_darwin64_abi = 1;
    warning (0, "Using darwin64 ABI");
  }
      else if (! strcmp (arg, "d32"))
  {
    rs6000_darwin64_abi = 0;
    warning (0, "Using old darwin ABI");
  }

      else if (! strcmp (arg, "ibmlongdouble"))
  {
    rs6000_explicit_options.ieee = true;
    rs6000_ieeequad = 0;
    warning (0, "Using IBM extended precision long double");
  }
      else if (! strcmp (arg, "ieeelongdouble"))
  {
    rs6000_explicit_options.ieee = true;
    rs6000_ieeequad = 1;
    warning (0, "Using IEEE extended precision long double");
  }

      else
  {
    error ("unknown ABI specified: '%s'", arg);
    return false;
  }
      break;

    case OPT_mcpu_:
      rs6000_select[1].string = arg;
      break;

    case OPT_mtune_:
      rs6000_select[2].string = arg;
      break;

    case OPT_mtraceback_:
      rs6000_traceback_name = arg;
      break;

    case OPT_mfloat_gprs_:
      rs6000_explicit_options.float_gprs = true;
      if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
  rs6000_float_gprs = 1;
      else if (! strcmp (arg, "double"))
  rs6000_float_gprs = 2;
      else if (! strcmp (arg, "no"))
  rs6000_float_gprs = 0;
      else
  {
    error ("invalid option for -mfloat-gprs: '%s'", arg);
    return false;
  }
      break;

    case OPT_mlong_double_:
      rs6000_explicit_options.long_double = true;
      rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
      if (value != 64 && value != 128)
  {
    error ("Unknown switch -mlong-double-%s", arg);
    rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
    return false;
  }
      else
  rs6000_long_double_type_size = value;
      break;

    case OPT_msched_costly_dep_:
      rs6000_sched_costly_dep_str = arg;
      break;

    case OPT_malign_:
      rs6000_explicit_options.alignment = true;
      if (! strcmp (arg, "power"))
  {
    /* On 64-bit Darwin, power alignment is ABI-incompatible with
       some C library functions, so warn about it. The flag may be
       useful for performance studies from time to time though, so
       don't disable it entirely.  */
    if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
      warning (0, "-malign-power is not supported for 64-bit Darwin;"
         " it is incompatible with the installed C and C++ libraries");
    rs6000_alignment_flags = MASK_ALIGN_POWER;
  }
      else if (! strcmp (arg, "natural"))
  rs6000_alignment_flags = MASK_ALIGN_NATURAL;
      else
  {
    error ("unknown -malign-XXXXX option specified: '%s'", arg);
    return false;
  }
      break;
    }
  return true;
}

/* Do anything needed at the start of the asm file.  */

static void
rs6000_file_start (void)
{
  size_t i;
  char buffer[80];
  const char *start = buffer;
  struct rs6000_cpu_select *ptr;
  const char *default_cpu = TARGET_CPU_DEFAULT;
  FILE *file = asm_out_file;

  default_file_start ();

#ifdef TARGET_BI_ARCH
  if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
    default_cpu = 0;
#endif

  if (flag_verbose_asm)
    {
      sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
      rs6000_select[0].string = default_cpu;

      for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
  {
    ptr = &rs6000_select[i];
    if (ptr->string != (char *)0 && ptr->string[0] != '\0')
      {
        fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
        start = "";
      }
  }

      if (PPC405_ERRATUM77)
  {
    fprintf (file, "%s PPC405CR_ERRATUM77", start);
    start = "";
  }

#ifdef USING_ELFOS_H
      switch (rs6000_sdata)
  {
  case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
  case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
  case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
  case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
  }

      if (rs6000_sdata && g_switch_value)
  {
    fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
       g_switch_value);
    start = "";
  }
#endif

      if (*start == '\0')
  putc ('\n', file);
    }

  if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
    {
      switch_to_section (toc_section);
      switch_to_section (text_section);
    }
}


/* Return nonzero if this function is known to have a null epilogue.  */

int
direct_return (void)
{
  if (reload_completed)
    {
      rs6000_stack_t *info = rs6000_stack_info ();

      if (info->first_gp_reg_save == 32
    && info->first_fp_reg_save == 64
    && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
    && ! info->lr_save_p
    && ! info->cr_save_p
    && info->vrsave_mask == 0
    && ! info->push_p)
  return 1;
    }

  return 0;
}

/* Return the number of instructions it takes to form a constant in an
   integer register.  */

int
num_insns_constant_wide (HOST_WIDE_INT value)
{
  /* signed constant loadable with {cal|addi} */
  if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
    return 1;

  /* constant loadable with {cau|addis} */
  else if ((value & 0xffff) == 0
     && (value >> 31 == -1 || value >> 31 == 0))
    return 1;

#if HOST_BITS_PER_WIDE_INT == 64
  else if (TARGET_POWERPC64)
    {
      HOST_WIDE_INT low  = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
      HOST_WIDE_INT high = value >> 31;

      if (high == 0 || high == -1)
  return 2;

      high >>= 1;

      if (low == 0)
  return num_insns_constant_wide (high) + 1;
      else
  return (num_insns_constant_wide (high)
    + num_insns_constant_wide (low) + 1);
    }
#endif

  else
    return 2;
}

int
num_insns_constant (rtx op, enum machine_mode mode)
{
  HOST_WIDE_INT low, high;

  switch (GET_CODE (op))
    {
    case CONST_INT:
#if HOST_BITS_PER_WIDE_INT == 64
      if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
    && mask64_operand (op, mode))
  return 2;
      else
#endif
  return num_insns_constant_wide (INTVAL (op));

      case CONST_DOUBLE:
  if (mode == SFmode)
    {
      long l;
      REAL_VALUE_TYPE rv;

      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
      REAL_VALUE_TO_TARGET_SINGLE (rv, l);
      return num_insns_constant_wide ((HOST_WIDE_INT) l);
    }

  if (mode == VOIDmode || mode == DImode)
    {
      high = CONST_DOUBLE_HIGH (op);
      low  = CONST_DOUBLE_LOW (op);
    }
  else
    {
      long l[2];
      REAL_VALUE_TYPE rv;

      REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
      REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
      high = l[WORDS_BIG_ENDIAN == 0];
      low  = l[WORDS_BIG_ENDIAN != 0];
    }

  if (TARGET_32BIT)
    return (num_insns_constant_wide (low)
      + num_insns_constant_wide (high));
  else
    {
      if ((high == 0 && low >= 0)
    || (high == -1 && low < 0))
        return num_insns_constant_wide (low);

      else if (mask64_operand (op, mode))
        return 2;

      else if (low == 0)
        return num_insns_constant_wide (high) + 1;

      else
        return (num_insns_constant_wide (high)
          + num_insns_constant_wide (low) + 1);
    }

    default:
      gcc_unreachable ();
    }
}

/* Interpret element ELT of the CONST_VECTOR OP as an integer value.
   If the mode of OP is MODE_VECTOR_INT, this simply returns the
   corresponding element of the vector, but for V4SFmode and V2SFmode,
   the corresponding "float" is interpreted as an SImode integer.  */

static HOST_WIDE_INT
const_vector_elt_as_int (rtx op, unsigned int elt)
{
  rtx tmp = CONST_VECTOR_ELT (op, elt);
  if (GET_MODE (op) == V4SFmode
      || GET_MODE (op) == V2SFmode)
    tmp = gen_lowpart (SImode, tmp);
  return INTVAL (tmp);
}

/* Return true if OP can be synthesized with a particular vspltisb, vspltish
   or vspltisw instruction.  OP is a CONST_VECTOR.  Which instruction is used
   depends on STEP and COPIES, one of which will be 1.  If COPIES > 1,
   all items are set to the same value and contain COPIES replicas of the
   vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
   operand and the others are set to the value of the operand's msb.  */

static bool
vspltis_constant (rtx op, unsigned step, unsigned copies)
{
  enum machine_mode mode = GET_MODE (op);
  enum machine_mode inner = GET_MODE_INNER (mode);

  unsigned i;
  unsigned nunits = GET_MODE_NUNITS (mode);
  unsigned bitsize = GET_MODE_BITSIZE (inner);
  unsigned mask = GET_MODE_MASK (inner);

  HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
  HOST_WIDE_INT splat_val = val;
  HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;

  /* Construct the value to be splatted, if possible.  If not, return 0.  */
  for (i = 2; i <= copies; i *= 2)
    {
      HOST_WIDE_INT small_val;
      bitsize /= 2;
      small_val = splat_val >> bitsize;
      mask >>= bitsize;
      if (splat_val != ((small_val << bitsize) | (small_val & mask)))
  return false;
      splat_val = small_val;
    }

  /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw].  */
  if (EASY_VECTOR_15 (splat_val))
    ;

  /* Also check if we can splat, and then add the result to itself.  Do so if
     the value is positive, of if the splat instruction is using OP's mode;
     for splat_val < 0, the splat and the add should use the same mode.  */
  else if (EASY_VECTOR_15_ADD_SELF (splat_val)
           && (splat_val >= 0 || (step == 1 && copies == 1)))
    ;

  else
    return false;

  /* Check if VAL is present in every STEP-th element, and the
     other elements are filled with its most significant bit.  */
  for (i = 0; i < nunits - 1; ++i)
    {
      HOST_WIDE_INT desired_val;
      if (((i + 1) & (step - 1)) == 0)
  desired_val = val;
      else
  desired_val = msb_val;

      if (desired_val != const_vector_elt_as_int (op, i))
  return false;
    }

  return true;
}


/* Return true if OP is of the given MODE and can be synthesized
   with a vspltisb, vspltish or vspltisw.  */

bool
easy_altivec_constant (rtx op, enum machine_mode mode)
{
  unsigned step, copies;

  if (mode == VOIDmode)
    mode = GET_MODE (op);
  else if (mode != GET_MODE (op))
    return false;

  /* Start with a vspltisw.  */
  step = GET_MODE_NUNITS (mode) / 4;
  copies = 1;

  if (vspltis_constant (op, step, copies))
    return true;

  /* Then try with a vspltish.  */
  if (step == 1)
    copies <<= 1;
  else
    step >>= 1;

  if (vspltis_constant (op, step, copies))
    return true;

  /* And finally a vspltisb.  */
  if (step == 1)
    copies <<= 1;
  else
    step >>= 1;

  if (vspltis_constant (op, step, copies))
    return true;

  return false;
}

/* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
   result is OP.  Abort if it is not possible.  */

rtx
gen_easy_altivec_constant (rtx op)
{
  enum machine_mode mode = GET_MODE (op);
  int nunits = GET_MODE_NUNITS (mode);
  rtx last = CONST_VECTOR_ELT (op, nunits - 1);
  unsigned step = nunits / 4;
  unsigned copies = 1;

  /* Start with a vspltisw.  */
  if (vspltis_constant (op, step, copies))
    return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));

  /* Then try with a vspltish.  */
  if (step == 1)
    copies <<= 1;
  else
    step >>= 1;

  if (vspltis_constant (op, step, copies))
    return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));

  /* And finally a vspltisb.  */
  if (step == 1)
    copies <<= 1;
  else
    step >>= 1;

  if (vspltis_constant (op, step, copies))
    return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));

  gcc_unreachable ();
}

const char *
output_vec_const_move (rtx *operands)
{
  int cst, cst2;
  enum machine_mode mode;
  rtx dest, vec;

  dest = operands[0];
  vec = operands[1];
  mode = GET_MODE (dest);

  if (TARGET_ALTIVEC)
    {
      rtx splat_vec;
      if (zero_constant (vec, mode))
  return "vxor %0,%0,%0";

      splat_vec = gen_easy_altivec_constant (vec);
      gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
      operands[1] = XEXP (splat_vec, 0);
      if (!EASY_VECTOR_15 (INTVAL (operands[1])))
  return "#";

      switch (GET_MODE (splat_vec))
  {
  case V4SImode:
    return "vspltisw %0,%1";

  case V8HImode:
    return "vspltish %0,%1";

  case V16QImode:
    return "vspltisb %0,%1";

  default:
    gcc_unreachable ();
  }
    }

  gcc_assert (TARGET_SPE);

  /* Vector constant 0 is handled as a splitter of V2SI, and in the
     pattern of V1DI, V4HI, and V2SF.

     FIXME: We should probably return # and add post reload
     splitters for these, but this way is so easy ;-).  */
  cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
  cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
  operands[1] = CONST_VECTOR_ELT (vec, 0);
  operands[2] = CONST_VECTOR_ELT (vec, 1);
  if (cst == cst2)
    return "li %0,%1\n\tevmergelo %0,%0,%0";
  else
    return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
}

/* Initialize vector TARGET to VALS.  */

void
rs6000_expand_vector_init (rtx target, rtx vals)
{
  enum machine_mode mode = GET_MODE (target);
  enum machine_mode inner_mode = GET_MODE_INNER (mode);
  int n_elts = GET_MODE_NUNITS (mode);
  int n_var = 0, one_var = -1;
  bool all_same = true, all_const_zero = true;
  rtx x, mem;
  int i;

  for (i = 0; i < n_elts; ++i)
    {
      x = XVECEXP (vals, 0, i);
      if (!CONSTANT_P (x))
  ++n_var, one_var = i;
      else if (x != CONST0_RTX (inner_mode))
  all_const_zero = false;

      if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
  all_same = false;
    }

  if (n_var == 0)
    {
      if (mode != V4SFmode && all_const_zero)
  {
    /* Zero register.  */
    emit_insn (gen_rtx_SET (VOIDmode, target,
          gen_rtx_XOR (mode, target, target)));
    return;
  }
      else if (mode != V4SFmode && easy_vector_constant (vals, mode))
  {
    /* Splat immediate.  */
    emit_insn (gen_rtx_SET (VOIDmode, target, vals));
    return;
  }
      else if (all_same)
  ; /* Splat vector element.  */
      else
  {
    /* Load from constant pool.  */
    emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
    return;
  }
    }

  /* Store value to stack temp.  Load vector element.  Splat.  */
  if (all_same)
    {
      mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
      emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
          XVECEXP (vals, 0, 0));
      x = gen_rtx_UNSPEC (VOIDmode,
        gen_rtvec (1, const0_rtx), UNSPEC_LVE);
      emit_insn (gen_rtx_PARALLEL (VOIDmode,
           gen_rtvec (2,
                gen_rtx_SET (VOIDmode,
                 target, mem),
                x)));
      x = gen_rtx_VEC_SELECT (inner_mode, target,
            gen_rtx_PARALLEL (VOIDmode,
            gen_rtvec (1, const0_rtx)));
      emit_insn (gen_rtx_SET (VOIDmode, target,
            gen_rtx_VEC_DUPLICATE (mode, x)));
      return;
    }

  /* One field is non-constant.  Load constant then overwrite
     varying field.  */
  if (n_var == 1)
    {
      rtx copy = copy_rtx (vals);

      /* Load constant part of vector, substitute neighboring value for
   varying element.  */
      XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
      rs6000_expand_vector_init (target, copy);

      /* Insert variable.  */
      rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
      return;
    }

  /* Construct the vector in memory one field at a time
     and load the whole vector.  */
  mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
  for (i = 0; i < n_elts; i++)
    emit_move_insn (adjust_address_nv (mem, inner_mode,
            i * GET_MODE_SIZE (inner_mode)),
        XVECEXP (vals, 0, i));
  emit_move_insn (target, mem);
}

/* Set field ELT of TARGET to VAL.  */

void
rs6000_expand_vector_set (rtx target, rtx val, int elt)
{
  enum machine_mode mode = GET_MODE (target);
  enum machine_mode inner_mode = GET_MODE_INNER (mode);
  rtx reg = gen_reg_rtx (mode);
  rtx mask, mem, x;
  int width = GET_MODE_SIZE (inner_mode);
  int i;

  /* Load single variable value.  */
  mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
  emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
  x = gen_rtx_UNSPEC (VOIDmode,
          gen_rtvec (1, const0_rtx), UNSPEC_LVE);
  emit_insn (gen_rtx_PARALLEL (VOIDmode,
             gen_rtvec (2,
            gen_rtx_SET (VOIDmode,
                   reg, mem),
            x)));

  /* Linear sequence.  */
  mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
  for (i = 0; i < 16; ++i)
    XVECEXP (mask, 0, i) = GEN_INT (i);

  /* Set permute mask to insert element into target.  */
  for (i = 0; i < width; ++i)
    XVECEXP (mask, 0, elt*width + i)
      = GEN_INT (i + 0x10);
  x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
  x = gen_rtx_UNSPEC (mode,
          gen_rtvec (3, target, reg,
         force_reg (V16QImode, x)),
          UNSPEC_VPERM);
  emit_insn (gen_rtx_SET (VOIDmode, target, x));
}

/* Extract field ELT from VEC into TARGET.  */

void
rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
{
  enum machine_mode mode = GET_MODE (vec);
  enum machine_mode inner_mode = GET_MODE_INNER (mode);
  rtx mem, x;

  /* Allocate mode-sized buffer.  */
  mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);

  /* Add offset to field within buffer matching vector element.  */
  mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));

  /* Store single field into mode-sized buffer.  */
  x = gen_rtx_UNSPEC (VOIDmode,
          gen_rtvec (1, const0_rtx), UNSPEC_STVE);
  emit_insn (gen_rtx_PARALLEL (VOIDmode,
             gen_rtvec (2,
            gen_rtx_SET (VOIDmode,
                   mem, vec),
            x)));
  emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
}

/* Generates shifts and masks for a pair of rldicl or rldicr insns to
   implement ANDing by the mask IN.  */
void
build_mask64_2_operands (rtx in, rtx *out)
{
#if HOST_BITS_PER_WIDE_INT >= 64
  unsigned HOST_WIDE_INT c, lsb, m1, m2;
  int shift;

  gcc_assert (GET_CODE (in) == CONST_INT);

  c = INTVAL (in);
  if (c & 1)
    {
      /* Assume c initially something like 0x00fff000000fffff.  The idea
   is to rotate the word so that the middle ^^^^^^ group of zeros
   is at the MS end and can be cleared with an rldicl mask.  We then
   rotate back and clear off the MS    ^^ group of zeros with a
   second rldicl.  */
      c = ~c;     /*   c == 0xff000ffffff00000 */
      lsb = c & -c;   /* lsb == 0x0000000000100000 */
      m1 = -lsb;    /*  m1 == 0xfffffffffff00000 */
      c = ~c;     /*   c == 0x00fff000000fffff */
      c &= -lsb;    /*   c == 0x00fff00000000000 */
      lsb = c & -c;   /* lsb == 0x0000100000000000 */
      c = ~c;     /*   c == 0xff000fffffffffff */
      c &= -lsb;    /*   c == 0xff00000000000000 */
      shift = 0;
      while ((lsb >>= 1) != 0)
  shift++;    /* shift == 44 on exit from loop */
      m1 <<= 64 - shift;  /*  m1 == 0xffffff0000000000 */
      m1 = ~m1;     /*  m1 == 0x000000ffffffffff */
      m2 = ~c;      /*  m2 == 0x00ffffffffffffff */
    }
  else
    {
      /* Assume c initially something like 0xff000f0000000000.  The idea
   is to rotate the word so that the     ^^^  middle group of zeros
   is at the LS end and can be cleared with an rldicr mask.  We then
   rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
   a second rldicr.  */
      lsb = c & -c;   /* lsb == 0x0000010000000000 */
      m2 = -lsb;    /*  m2 == 0xffffff0000000000 */
      c = ~c;     /*   c == 0x00fff0ffffffffff */
      c &= -lsb;    /*   c == 0x00fff00000000000 */
      lsb = c & -c;   /* lsb == 0x0000100000000000 */
      c = ~c;     /*   c == 0xff000fffffffffff */
      c &= -lsb;    /*   c == 0xff00000000000000 */
      shift = 0;
      while ((lsb >>= 1) != 0)
  shift++;    /* shift == 44 on exit from loop */
      m1 = ~c;      /*  m1 == 0x00ffffffffffffff */
      m1 >>= shift;   /*  m1 == 0x0000000000000fff */
      m1 = ~m1;     /*  m1 == 0xfffffffffffff000 */
    }

  /* Note that when we only have two 0->1 and 1->0 transitions, one of the
     masks will be all 1's.  We are guaranteed more than one transition.  */
  out[0] = GEN_INT (64 - shift);
  out[1] = GEN_INT (m1);
  out[2] = GEN_INT (shift);
  out[3] = GEN_INT (m2);
#else
  (void)in;
  (void)out;
  gcc_unreachable ();
#endif
}

/* Return TRUE if OP is an invalid SUBREG operation on the e500.  */

bool
invalid_e500_subreg (rtx op, enum machine_mode mode)
{
  if (TARGET_E500_DOUBLE)
    {
      /* Reject (subreg:SI (reg:DF)).  */
      if (GET_CODE (op) == SUBREG
    && mode == SImode
    && REG_P (SUBREG_REG (op))
    && GET_MODE (SUBREG_REG (op)) == DFmode)
  return true;

      /* Reject (subreg:DF (reg:DI)).  */
      if (GET_CODE (op) == SUBREG
    && mode == DFmode
    && REG_P (SUBREG_REG (op))
    && GET_MODE (SUBREG_REG (op)) == DImode)
  return true;
    }

  if (TARGET_SPE
      && GET_CODE (op) == SUBREG
      && mode == SImode
      && REG_P (SUBREG_REG (op))
      && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
    return true;

  return false;
}

/* Darwin, AIX increases natural record alignment to doubleword if the first
   field is an FP double while the FP fields remain word aligned.  */

unsigned int
rs6000_special_round_type_align (tree type, unsigned int computed,
         unsigned int specified)
{
  unsigned int align = MAX (computed, specified);
  tree field = TYPE_FIELDS (type);

  /* Skip all non field decls */
  while (field != NULL && TREE_CODE (field) != FIELD_DECL)
    field = TREE_CHAIN (field);

  if (field != NULL && field != type)
    {
      type = TREE_TYPE (field);
      while (TREE_CODE (type) == ARRAY_TYPE)
  type = TREE_TYPE (type);

      if (type != error_mark_node && TYPE_MODE (type) == DFmode)
  align = MAX (align, 64);
    }

  return align;
}

/* Return 1 for an operand in small memory on V.4/eabi.  */

int
small_data_operand (rtx op ATTRIBUTE_UNUSED,
        enum machine_mode mode ATTRIBUTE_UNUSED)
{
#if TARGET_ELF
  rtx sym_ref;

  if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
    return 0;

  if (DEFAULT_ABI != ABI_V4)
    return 0;

  if (GET_CODE (op) == SYMBOL_REF)
    sym_ref = op;

  else if (GET_CODE (op) != CONST
     || GET_CODE (XEXP (op, 0)) != PLUS
     || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
     || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
    return 0;

  else
    {
      rtx sum = XEXP (op, 0);
      HOST_WIDE_INT summand;

      /* We have to be careful here, because it is the referenced address
   that must be 32k from _SDA_BASE_, not just the symbol.  */
      summand = INTVAL (XEXP (sum, 1));
      if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
  return 0;

      sym_ref = XEXP (sum, 0);
    }

  return SYMBOL_REF_SMALL_P (sym_ref);
#else
  return 0;
#endif
}

/* Return true if either operand is a general purpose register.  */

bool
gpr_or_gpr_p (rtx op0, rtx op1)
{
  return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
    || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
}


/* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address.  */

static int
constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
{
  switch (GET_CODE (op))
    {
    case SYMBOL_REF:
      if (RS6000_SYMBOL_REF_TLS_P (op))
  return 0;
      else if (CONSTANT_POOL_ADDRESS_P (op))
  {
    if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
      {
        *have_sym = 1;
        return 1;
      }
    else
      return 0;
  }
      else if (! strcmp (XSTR (op, 0), toc_label_name))
  {
    *have_toc = 1;
    return 1;
  }
      else
  return 0;
    case PLUS:
    case MINUS:
      return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
        && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
    case CONST:
      return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
    case CONST_INT:
      return 1;
    default:
      return 0;
    }
}

static bool
constant_pool_expr_p (rtx op)
{
  int have_sym = 0;
  int have_toc = 0;
  return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
}

bool
toc_relative_expr_p (rtx op)
{
  int have_sym = 0;
  int have_toc = 0;
  return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
}

bool
legitimate_constant_pool_address_p (rtx x)
{
  return (TARGET_TOC
    && GET_CODE (x) == PLUS
    && GET_CODE (XEXP (x, 0)) == REG
    && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
    && constant_pool_expr_p (XEXP (x, 1)));
}

static bool
legitimate_small_data_p (enum machine_mode mode, rtx x)
{
  return (DEFAULT_ABI == ABI_V4
    && !flag_pic && !TARGET_TOC
    && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
    && small_data_operand (x, mode));
}

/* SPE offset addressing is limited to 5-bits worth of double words.  */
#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)

bool
rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
{
  unsigned HOST_WIDE_INT offset, extra;

  if (GET_CODE (x) != PLUS)
    return false;
  if (GET_CODE (XEXP (x, 0)) != REG)
    return false;
  if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
    return false;
  if (legitimate_constant_pool_address_p (x))
    return true;
  if (GET_CODE (XEXP (x, 1)) != CONST_INT)
    return false;

  offset = INTVAL (XEXP (x, 1));
  extra = 0;
  switch (mode)
    {
    case V16QImode:
    case V8HImode:
    case V4SFmode:
    case V4SImode:
      /* AltiVec vector modes.  Only reg+reg addressing is valid and
   constant offset zero should not occur due to canonicalization.
   Allow any offset when not strict before reload.  */
      return !strict;

    case V4HImode:
    case V2SImode:
    case V1DImode:
    case V2SFmode:
      /* SPE vector modes.  */
      return SPE_CONST_OFFSET_OK (offset);

    case DFmode:
      if (TARGET_E500_DOUBLE)
  return SPE_CONST_OFFSET_OK (offset);

    case DImode:
      /* On e500v2, we may have:

     (subreg:DF (mem:DI (plus (reg) (const_int))) 0).

         Which gets addressed with evldd instructions.  */
      if (TARGET_E500_DOUBLE)
  return SPE_CONST_OFFSET_OK (offset);

      if (mode == DFmode || !TARGET_POWERPC64)
  extra = 4;
      else if (offset & 3)
  return false;
      break;

    case TFmode:
    case TImode:
      if (mode == TFmode || !TARGET_POWERPC64)
  extra = 12;
      else if (offset & 3)
  return false;
      else
  extra = 8;
      break;

    default:
      break;
    }

  offset += 0x8000;
  return (offset < 0x10000) && (offset + extra < 0x10000);
}

static bool
legitimate_indexed_address_p (rtx x, int strict)
{
  rtx op0, op1;

  if (GET_CODE (x) != PLUS)
    return false;

  op0 = XEXP (x, 0);
  op1 = XEXP (x, 1);

  /* Recognize the rtl generated by reload which we know will later be
     replaced with proper base and index regs.  */
  if (!strict
      && reload_in_progress
      && (REG_P (op0) || GET_CODE (op0) == PLUS)
      && REG_P (op1))
    return true;

  return (REG_P (op0) && REG_P (op1)
    && ((INT_REG_OK_FOR_BASE_P (op0, strict)
         && INT_REG_OK_FOR_INDEX_P (op1, strict))
        || (INT_REG_OK_FOR_BASE_P (op1, strict)
      && INT_REG_OK_FOR_INDEX_P (op0, strict))));
}

inline bool
legitimate_indirect_address_p (rtx x, int strict)
{
  return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
}

bool
macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
{
  if (!TARGET_MACHO || !flag_pic
      || mode != SImode || GET_CODE (x) != MEM)
    return false;
  x = XEXP (x, 0);

  if (GET_CODE (x) != LO_SUM)
    return false;
  if (GET_CODE (XEXP (x, 0)) != REG)
    return false;
  if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
    return false;
  x = XEXP (x, 1);

  return CONSTANT_P (x);
}

static bool
legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
{
  if (GET_CODE (x) != LO_SUM)
    return false;
  if (GET_CODE (XEXP (x, 0)) != REG)
    return false;
  if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
    return false;
  /* Restrict addressing for DI because of our SUBREG hackery.  */
  if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
    return false;
  x = XEXP (x, 1);

  if (TARGET_ELF || TARGET_MACHO)
    {
      if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
  return false;
      if (TARGET_TOC)
  return false;
      if (GET_MODE_NUNITS (mode) != 1)
  return false;
      if (GET_MODE_BITSIZE (mode) > 64
    || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
        && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
  return false;

      return CONSTANT_P (x);
    }

  return false;
}


/* Try machine-dependent ways of modifying an illegitimate address
   to be legitimate.  If we find one, return the new, valid address.
   This is used from only one place: `memory_address' in explow.c.

   OLDX is the address as it was before break_out_memory_refs was
   called.  In some cases it is useful to look at this to decide what
   needs to be done.

   MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.

   It is always safe for this function to do nothing.  It exists to
   recognize opportunities to optimize the output.

   On RS/6000, first check for the sum of a register with a constant
   integer that is out of range.  If so, generate code to add the
   constant with the low-order 16 bits masked to the register and force
   this result into another register (this can be done with `cau').
   Then generate an address of REG+(CONST&0xffff), allowing for the
   possibility of bit 16 being a one.

   Then check for the sum of a register and something not constant, try to
   load the other things into a register and return the sum.  */

rtx
rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
         enum machine_mode mode)
{
  if (GET_CODE (x) == SYMBOL_REF)
    {
      enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
      if (model != 0)
  return rs6000_legitimize_tls_address (x, model);
    }

  if (GET_CODE (x) == PLUS
      && GET_CODE (XEXP (x, 0)) == REG
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
    {
      HOST_WIDE_INT high_int, low_int;
      rtx sum;
      low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
      high_int = INTVAL (XEXP (x, 1)) - low_int;
      sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
           GEN_INT (high_int)), 0);
      return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
    }
  else if (GET_CODE (x) == PLUS
     && GET_CODE (XEXP (x, 0)) == REG
     && GET_CODE (XEXP (x, 1)) != CONST_INT
     && GET_MODE_NUNITS (mode) == 1
     && ((TARGET_HARD_FLOAT && TARGET_FPRS)
         || TARGET_POWERPC64
         || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
       && mode != TFmode))
     && (TARGET_POWERPC64 || mode != DImode)
     && mode != TImode)
    {
      return gen_rtx_PLUS (Pmode, XEXP (x, 0),
         force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
    }
  else if (ALTIVEC_VECTOR_MODE (mode))
    {
      rtx reg;

      /* Make sure both operands are registers.  */
      if (GET_CODE (x) == PLUS)
  return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
           force_reg (Pmode, XEXP (x, 1)));

      reg = force_reg (Pmode, x);
      return reg;
    }
  else if (SPE_VECTOR_MODE (mode)
     || (TARGET_E500_DOUBLE && (mode == DFmode
              || mode == DImode)))
    {
      if (mode == DImode)
  return NULL_RTX;
      /* We accept [reg + reg] and [reg + OFFSET].  */

      if (GET_CODE (x) == PLUS)
  {
    rtx op1 = XEXP (x, 0);
    rtx op2 = XEXP (x, 1);

    op1 = force_reg (Pmode, op1);

    if (GET_CODE (op2) != REG
        && (GET_CODE (op2) != CONST_INT
      || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
      op2 = force_reg (Pmode, op2);

    return gen_rtx_PLUS (Pmode, op1, op2);
  }

      return force_reg (Pmode, x);
    }
  else if (TARGET_ELF
     && TARGET_32BIT
     && TARGET_NO_TOC
     && ! flag_pic
     && GET_CODE (x) != CONST_INT
     && GET_CODE (x) != CONST_DOUBLE
     && CONSTANT_P (x)
     && GET_MODE_NUNITS (mode) == 1
     && (GET_MODE_BITSIZE (mode) <= 32
         || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
    {
      rtx reg = gen_reg_rtx (Pmode);
      emit_insn (gen_elf_high (reg, x));
      return gen_rtx_LO_SUM (Pmode, reg, x);
    }
  else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
     && ! flag_pic
#if TARGET_MACHO
     && ! MACHO_DYNAMIC_NO_PIC_P
#endif
     && GET_CODE (x) != CONST_INT
     && GET_CODE (x) != CONST_DOUBLE
     && CONSTANT_P (x)
     && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
     && mode != DImode
     && mode != TImode)
    {
      rtx reg = gen_reg_rtx (Pmode);
      emit_insn (gen_macho_high (reg, x));
      return gen_rtx_LO_SUM (Pmode, reg, x);
    }
  else if (TARGET_TOC
     && constant_pool_expr_p (x)
     && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
    {
      return create_TOC_reference (x);
    }
  else
    return NULL_RTX;
}

/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
   We need to emit DTP-relative relocations.  */

static void
rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
{
  switch (size)
    {
    case 4:
      fputs ("\t.long\t", file);
      break;
    case 8:
      fputs (DOUBLE_INT_ASM_OP, file);
      break;
    default:
      gcc_unreachable ();
    }
  output_addr_const (file, x);
  fputs ("@dtprel+0x8000", file);
}

/* Construct the SYMBOL_REF for the tls_get_addr function.  */

static GTY(()) rtx rs6000_tls_symbol;
static rtx
rs6000_tls_get_addr (void)
{
  if (!rs6000_tls_symbol)
    rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");

  return rs6000_tls_symbol;
}

/* Construct the SYMBOL_REF for TLS GOT references.  */

static GTY(()) rtx rs6000_got_symbol;
static rtx
rs6000_got_sym (void)
{
  if (!rs6000_got_symbol)
    {
      rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
      SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
      SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
    }

  return rs6000_got_symbol;
}

/* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
   this (thread-local) address.  */

static rtx
rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
{
  rtx dest, insn;

  dest = gen_reg_rtx (Pmode);
  if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
    {
      rtx tlsreg;

      if (TARGET_64BIT)
  {
    tlsreg = gen_rtx_REG (Pmode, 13);
    insn = gen_tls_tprel_64 (dest, tlsreg, addr);
  }
      else
  {
    tlsreg = gen_rtx_REG (Pmode, 2);
    insn = gen_tls_tprel_32 (dest, tlsreg, addr);
  }
      emit_insn (insn);
    }
  else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
    {
      rtx tlsreg, tmp;

      tmp = gen_reg_rtx (Pmode);
      if (TARGET_64BIT)
  {
    tlsreg = gen_rtx_REG (Pmode, 13);
    insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
  }
      else
  {
    tlsreg = gen_rtx_REG (Pmode, 2);
    insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
  }
      emit_insn (insn);
      if (TARGET_64BIT)
  insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
      else
  insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
      emit_insn (insn);
    }
  else
    {
      rtx r3, got, tga, tmp1, tmp2, eqv;

      /* We currently use relocations like @got@tlsgd for tls, which
   means the linker will handle allocation of tls entries, placing
   them in the .got section.  So use a pointer to the .got section,
   not one to secondary TOC sections used by 64-bit -mminimal-toc,
   or to secondary GOT sections used by 32-bit -fPIC.  */
      if (TARGET_64BIT)
  got = gen_rtx_REG (Pmode, 2);
      else
  {
    if (flag_pic == 1)
      got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
    else
      {
        rtx gsym = rs6000_got_sym ();
        got = gen_reg_rtx (Pmode);
        if (flag_pic == 0)
    rs6000_emit_move (got, gsym, Pmode);
        else
    {
      rtx tempLR, tmp3, mem;
      rtx first, last;

      tempLR = gen_reg_rtx (Pmode);
      tmp1 = gen_reg_rtx (Pmode);
      tmp2 = gen_reg_rtx (Pmode);
      tmp3 = gen_reg_rtx (Pmode);
      mem = gen_const_mem (Pmode, tmp1);

      first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
      emit_move_insn (tmp1, tempLR);
      emit_move_insn (tmp2, mem);
      emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
      last = emit_move_insn (got, tmp3);
      REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
              REG_NOTES (last));
      REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
               REG_NOTES (first));
      REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
              REG_NOTES (last));
    }
      }
  }

      if (model == TLS_MODEL_GLOBAL_DYNAMIC)
  {
    r3 = gen_rtx_REG (Pmode, 3);
    if (TARGET_64BIT)
      insn = gen_tls_gd_64 (r3, got, addr);
    else
      insn = gen_tls_gd_32 (r3, got, addr);
    start_sequence ();
    emit_insn (insn);
    tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
    insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
    insn = emit_call_insn (insn);
    CONST_OR_PURE_CALL_P (insn) = 1;
    use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
    insn = get_insns ();
    end_sequence ();
    emit_libcall_block (insn, dest, r3, addr);
  }
      else if (model == TLS_MODEL_LOCAL_DYNAMIC)
  {
    r3 = gen_rtx_REG (Pmode, 3);
    if (TARGET_64BIT)
      insn = gen_tls_ld_64 (r3, got);
    else
      insn = gen_tls_ld_32 (r3, got);
    start_sequence ();
    emit_insn (insn);
    tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
    insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
    insn = emit_call_insn (insn);
    CONST_OR_PURE_CALL_P (insn) = 1;
    use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
    insn = get_insns ();
    end_sequence ();
    tmp1 = gen_reg_rtx (Pmode);
    eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
        UNSPEC_TLSLD);
    emit_libcall_block (insn, tmp1, r3, eqv);
    if (rs6000_tls_size == 16)
      {
        if (TARGET_64BIT)
    insn = gen_tls_dtprel_64 (dest, tmp1, addr);
        else
    insn = gen_tls_dtprel_32 (dest, tmp1, addr);
      }
    else if (rs6000_tls_size == 32)
      {
        tmp2 = gen_reg_rtx (Pmode);
        if (TARGET_64BIT)
    insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
        else
    insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
        emit_insn (insn);
        if (TARGET_64BIT)
    insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
        else
    insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
      }
    else
      {
        tmp2 = gen_reg_rtx (Pmode);
        if (TARGET_64BIT)
    insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
        else
    insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
        emit_insn (insn);
        insn = gen_rtx_SET (Pmode, dest,
          gen_rtx_PLUS (Pmode, tmp2, tmp1));
      }
    emit_insn (insn);
  }
      else
  {
    /* IE, or 64 bit offset LE.  */
    tmp2 = gen_reg_rtx (Pmode);
    if (TARGET_64BIT)
      insn = gen_tls_got_tprel_64 (tmp2, got, addr);
    else
      insn = gen_tls_got_tprel_32 (tmp2, got, addr);
    emit_insn (insn);
    if (TARGET_64BIT)
      insn = gen_tls_tls_64 (dest, tmp2, addr);
    else
      insn = gen_tls_tls_32 (dest, tmp2, addr);
    emit_insn (insn);
  }
    }

  return dest;
}

/* Return 1 if X contains a thread-local symbol.  */

bool
rs6000_tls_referenced_p (rtx x)
{
  if (! TARGET_HAVE_TLS)
    return false;

  return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
}

/* Return 1 if *X is a thread-local symbol.  This is the same as
   rs6000_tls_symbol_ref except for the type of the unused argument.  */

static int
rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
{
  return RS6000_SYMBOL_REF_TLS_P (*x);
}

/* The convention appears to be to define this wherever it is used.
   With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
   is now used here.  */
#ifndef REG_MODE_OK_FOR_BASE_P
#define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
#endif

/* Our implementation of LEGITIMIZE_RELOAD_ADDRESS.  Returns a value to
   replace the input X, or the original X if no replacement is called for.
   The output parameter *WIN is 1 if the calling macro should goto WIN,
   0 if it should not.

   For RS/6000, we wish to handle large displacements off a base
   register by splitting the addend across an addiu/addis and the mem insn.
   This cuts number of extra insns needed from 3 to 1.

   On Darwin, we use this to generate code for floating point constants.
   A movsf_low is generated so we wind up with 2 instructions rather than 3.
   The Darwin code is inside #if TARGET_MACHO because only then is
   machopic_function_base_name() defined.  */
rtx
rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
          int opnum, int type,
          int ind_levels ATTRIBUTE_UNUSED, int *win)
{
  /* We must recognize output that we have already generated ourselves.  */
  if (GET_CODE (x) == PLUS
      && GET_CODE (XEXP (x, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
      && GET_CODE (XEXP (x, 1)) == CONST_INT)
    {
      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
       BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
       opnum, (enum reload_type)type);
      *win = 1;
      return x;
    }

#if TARGET_MACHO
  if (DEFAULT_ABI == ABI_DARWIN && flag_pic
      && GET_CODE (x) == LO_SUM
      && GET_CODE (XEXP (x, 0)) == PLUS
      && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
      && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
      && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
      && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
      && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
      && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
      && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
    {
      /* Result of previous invocation of this function on Darwin
   floating point constant.  */
      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
       BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
       opnum, (enum reload_type)type);
      *win = 1;
      return x;
    }
#endif

  /* Force ld/std non-word aligned offset into base register by wrapping
     in offset 0.  */
  if (GET_CODE (x) == PLUS
      && GET_CODE (XEXP (x, 0)) == REG
      && REGNO (XEXP (x, 0)) < 32
      && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && (INTVAL (XEXP (x, 1)) & 3) != 0
      && !ALTIVEC_VECTOR_MODE (mode)
      && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
      && TARGET_POWERPC64)
    {
      x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
       BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
       opnum, (enum reload_type) type);
      *win = 1;
      return x;
    }

  if (GET_CODE (x) == PLUS
      && GET_CODE (XEXP (x, 0)) == REG
      && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
      && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && !SPE_VECTOR_MODE (mode)
      && !(TARGET_E500_DOUBLE && (mode == DFmode
          || mode == DImode))
      && !ALTIVEC_VECTOR_MODE (mode))
    {
      HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
      HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
      HOST_WIDE_INT high
  = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;

      /* Check for 32-bit overflow.  */
      if (high + low != val)
  {
    *win = 0;
    return x;
  }

      /* Reload the high part into a base reg; leave the low part
   in the mem directly.  */

      x = gen_rtx_PLUS (GET_MODE (x),
      gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
              GEN_INT (high)),
      GEN_INT (low));

      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
       BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
       opnum, (enum reload_type)type);
      *win = 1;
      return x;
    }

  if (GET_CODE (x) == SYMBOL_REF
      && !ALTIVEC_VECTOR_MODE (mode)
      && !SPE_VECTOR_MODE (mode)
#if TARGET_MACHO
      && DEFAULT_ABI == ABI_DARWIN
      && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
#else
      && DEFAULT_ABI == ABI_V4
      && !flag_pic
#endif
      /* Don't do this for TFmode, since the result isn't offsettable.
   The same goes for DImode without 64-bit gprs and DFmode
   without fprs.  */
      && mode != TFmode
      && (mode != DImode || TARGET_POWERPC64)
      && (mode != DFmode || TARGET_POWERPC64
    || (TARGET_FPRS && TARGET_HARD_FLOAT)))
    {
#if TARGET_MACHO
      if (flag_pic)
  {
    rtx offset = gen_rtx_CONST (Pmode,
       gen_rtx_MINUS (Pmode, x,
          machopic_function_base_sym ()));
    x = gen_rtx_LO_SUM (GET_MODE (x),
    gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
      gen_rtx_HIGH (Pmode, offset)), offset);
  }
      else
#endif
  x = gen_rtx_LO_SUM (GET_MODE (x),
        gen_rtx_HIGH (Pmode, x), x);

      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
       BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
       opnum, (enum reload_type)type);
      *win = 1;
      return x;
    }

  /* Reload an offset address wrapped by an AND that represents the
     masking of the lower bits.  Strip the outer AND and let reload
     convert the offset address into an indirect address.  */
  if (TARGET_ALTIVEC
      && ALTIVEC_VECTOR_MODE (mode)
      && GET_CODE (x) == AND
      && GET_CODE (XEXP (x, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && INTVAL (XEXP (x, 1)) == -16)
    {
      x = XEXP (x, 0);
      *win = 1;
      return x;
    }

  if (TARGET_TOC
      && constant_pool_expr_p (x)
      && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
    {
      x = create_TOC_reference (x);
      *win = 1;
      return x;
    }
  *win = 0;
  return x;
}

/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
   that is a valid memory address for an instruction.
   The MODE argument is the machine mode for the MEM expression
   that wants to use this address.

   On the RS/6000, there are four valid address: a SYMBOL_REF that
   refers to a constant pool entry of an address (or the sum of it
   plus a constant), a short (16-bit signed) constant plus a register,
   the sum of two registers, or a register indirect, possibly with an
   auto-increment.  For DFmode and DImode with a constant plus register,
   we must ensure that both words are addressable or PowerPC64 with offset
   word aligned.

   For modes spanning multiple registers (DFmode in 32-bit GPRs,
   32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
   adjacent memory cells are accessed by adding word-sized offsets
   during assembly output.  */
int
rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
{
  /* If this is an unaligned stvx/ldvx type address, discard the outer AND.  */
  if (TARGET_ALTIVEC
      && ALTIVEC_VECTOR_MODE (mode)
      && GET_CODE (x) == AND
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && INTVAL (XEXP (x, 1)) == -16)
    x = XEXP (x, 0);

  if (RS6000_SYMBOL_REF_TLS_P (x))
    return 0;
  if (legitimate_indirect_address_p (x, reg_ok_strict))
    return 1;
  if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
      && !ALTIVEC_VECTOR_MODE (mode)
      && !SPE_VECTOR_MODE (mode)
      && mode != TFmode
      /* Restrict addressing for DI because of our SUBREG hackery.  */
      && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
      && TARGET_UPDATE
      && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
    return 1;
  if (legitimate_small_data_p (mode, x))
    return 1;
  if (legitimate_constant_pool_address_p (x))
    return 1;
  /* If not REG_OK_STRICT (before reload) let pass any stack offset.  */
  if (! reg_ok_strict
      && GET_CODE (x) == PLUS
      && GET_CODE (XEXP (x, 0)) == REG
      && (XEXP (x, 0) == virtual_stack_vars_rtx
    || XEXP (x, 0) == arg_pointer_rtx)
      && GET_CODE (XEXP (x, 1)) == CONST_INT)
    return 1;
  if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
    return 1;
  if (mode != TImode
      && mode != TFmode
      && ((TARGET_HARD_FLOAT && TARGET_FPRS)
    || TARGET_POWERPC64
    || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
      && (TARGET_POWERPC64 || mode != DImode)
      && legitimate_indexed_address_p (x, reg_ok_strict))
    return 1;
  if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
    return 1;
  return 0;
}

/* Go to LABEL if ADDR (a legitimate address expression)
   has an effect that depends on the machine mode it is used for.

   On the RS/6000 this is true of all integral offsets (since AltiVec
   modes don't allow them) or is a pre-increment or decrement.

   ??? Except that due to conceptual problems in offsettable_address_p
   we can't really report the problems of integral offsets.  So leave
   this assuming that the adjustable offset must be valid for the
   sub-words of a TFmode operand, which is what we had before.  */

bool
rs6000_mode_dependent_address (rtx addr)
{
  switch (GET_CODE (addr))
    {
    case PLUS:
      if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
  {
    unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
    return val + 12 + 0x8000 >= 0x10000;
  }
      break;

    case LO_SUM:
      return true;

    case PRE_INC:
    case PRE_DEC:
      return TARGET_UPDATE;

    default:
      break;
    }

  return false;
}

/* More elaborate version of recog's offsettable_memref_p predicate
   that works around the ??? note of rs6000_mode_dependent_address.
   In particular it accepts

     (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))

   in 32-bit mode, that the recog predicate rejects.  */

bool
rs6000_offsettable_memref_p (rtx op)
{
  if (!MEM_P (op))
    return false;

  /* First mimic offsettable_memref_p.  */
  if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
    return true;

  /* offsettable_address_p invokes rs6000_mode_dependent_address, but
     the latter predicate knows nothing about the mode of the memory
     reference and, therefore, assumes that it is the largest supported
     mode (TFmode).  As a consequence, legitimate offsettable memory
     references are rejected.  rs6000_legitimate_offset_address_p contains
     the correct logic for the PLUS case of rs6000_mode_dependent_address.  */
  return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
}

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   For the SPE, GPRs are 64 bits but only 32 bits are visible in
   scalar instructions.  The upper 32 bits are only available to the
   SIMD instructions.

   POWER and PowerPC GPRs hold 32 bits worth;
   PowerPC64 GPRs and FPRs point register holds 64 bits worth.  */

int
rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
{
  if (FP_REGNO_P (regno))
    return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;

  if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
    return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;

  if (ALTIVEC_REGNO_P (regno))
    return
      (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;

  /* The value returned for SCmode in the E500 double case is 2 for
     ABI compatibility; storing an SCmode value in a single register
     would require function_arg and rs6000_spe_function_arg to handle
     SCmode so as to pass the value correctly in a pair of
     registers.  */
  if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
    return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;

  return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
}

/* Change register usage conditional on target flags.  */
void
rs6000_conditional_register_usage (void)
{
  int i;

  /* Set MQ register fixed (already call_used) if not POWER
     architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
     be allocated.  */
  if (! TARGET_POWER)
    fixed_regs[64] = 1;

  /* 64-bit AIX and Linux reserve GPR13 for thread-private data.  */
  if (TARGET_64BIT)
    fixed_regs[13] = call_used_regs[13]
      = call_really_used_regs[13] = 1;

  /* Conditionally disable FPRs.  */
  if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
    for (i = 32; i < 64; i++)
      fixed_regs[i] = call_used_regs[i]
  = call_really_used_regs[i] = 1;

  /* The TOC register is not killed across calls in a way that is
     visible to the compiler.  */
  if (DEFAULT_ABI == ABI_AIX)
    call_really_used_regs[2] = 0;

  if (DEFAULT_ABI == ABI_V4
      && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
      && flag_pic == 2)
    fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;

  if (DEFAULT_ABI == ABI_V4
      && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
      && flag_pic == 1)
    fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
      = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
      = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;

  if (DEFAULT_ABI == ABI_DARWIN
      && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
      fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
      = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
      = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;

  if (TARGET_TOC && TARGET_MINIMAL_TOC)
    fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
      = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;

  if (TARGET_ALTIVEC)
    global_regs[VSCR_REGNO] = 1;

  if (TARGET_SPE)
    {
      global_regs[SPEFSCR_REGNO] = 1;
      fixed_regs[FIXED_SCRATCH]
  = call_used_regs[FIXED_SCRATCH]
  = call_really_used_regs[FIXED_SCRATCH] = 1;
    }

  if (! TARGET_ALTIVEC)
    {
      for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
  fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
      call_really_used_regs[VRSAVE_REGNO] = 1;
    }

  if (TARGET_ALTIVEC_ABI)
    for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
      call_used_regs[i] = call_really_used_regs[i] = 1;
}

/* Try to output insns to set TARGET equal to the constant C if it can
   be done in less than N insns.  Do all computations in MODE.
   Returns the place where the output has been placed if it can be
   done and the insns have been emitted.  If it would take more than N
   insns, zero is returned and no insns and emitted.  */

rtx
rs6000_emit_set_const (rtx dest, enum machine_mode mode,
           rtx source, int n ATTRIBUTE_UNUSED)
{
  rtx result, insn, set;
  HOST_WIDE_INT c0, c1;

  switch (mode)
    {
      case  QImode:
    case HImode:
      if (dest == NULL)
  dest = gen_reg_rtx (mode);
      emit_insn (gen_rtx_SET (VOIDmode, dest, source));
      return dest;

    case SImode:
      result = no_new_pseudos ? dest : gen_reg_rtx (SImode);

      emit_insn (gen_rtx_SET (VOIDmode, result,
            GEN_INT (INTVAL (source)
               & (~ (HOST_WIDE_INT) 0xffff))));
      emit_insn (gen_rtx_SET (VOIDmode, dest,
            gen_rtx_IOR (SImode, result,
             GEN_INT (INTVAL (source) & 0xffff))));
      result = dest;
      break;

    case DImode:
      switch (GET_CODE (source))
  {
  case CONST_INT:
    c0 = INTVAL (source);
    c1 = -(c0 < 0);
    break;

  case CONST_DOUBLE:
#if HOST_BITS_PER_WIDE_INT >= 64
    c0 = CONST_DOUBLE_LOW (source);
    c1 = -(c0 < 0);
#else
    c0 = CONST_DOUBLE_LOW (source);
    c1 = CONST_DOUBLE_HIGH (source);
#endif
    break;

  default:
    gcc_unreachable ();
  }

      result = rs6000_emit_set_long_const (dest, c0, c1);
      break;

    default:
      gcc_unreachable ();
    }

  insn = get_last_insn ();
  set = single_set (insn);
  if (! CONSTANT_P (SET_SRC (set)))
    set_unique_reg_note (insn, REG_EQUAL, source);

  return result;
}

/* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
   fall back to a straight forward decomposition.  We do this to avoid
   exponential run times encountered when looking for longer sequences
   with rs6000_emit_set_const.  */
static rtx
rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
{
  if (!TARGET_POWERPC64)
    {
      rtx operand1, operand2;

      operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
          DImode);
      operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
          DImode);
      emit_move_insn (operand1, GEN_INT (c1));
      emit_move_insn (operand2, GEN_INT (c2));
    }
  else
    {
      HOST_WIDE_INT ud1, ud2, ud3, ud4;

      ud1 = c1 & 0xffff;
      ud2 = (c1 & 0xffff0000) >> 16;
#if HOST_BITS_PER_WIDE_INT >= 64
      c2 = c1 >> 32;
#endif
      ud3 = c2 & 0xffff;
      ud4 = (c2 & 0xffff0000) >> 16;

      if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
    || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
  {
    if (ud1 & 0x8000)
      emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) -  0x8000)));
    else
      emit_move_insn (dest, GEN_INT (ud1));
  }

      else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
         || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
  {
    if (ud2 & 0x8000)
      emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
             - 0x80000000));
    else
      emit_move_insn (dest, GEN_INT (ud2 << 16));
    if (ud1 != 0)
      emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
  }
      else if ((ud4 == 0xffff && (ud3 & 0x8000))
         || (ud4 == 0 && ! (ud3 & 0x8000)))
  {
    if (ud3 & 0x8000)
      emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
             - 0x80000000));
    else
      emit_move_insn (dest, GEN_INT (ud3 << 16));

    if (ud2 != 0)
      emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
    emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
    if (ud1 != 0)
      emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
  }
      else
  {
    if (ud4 & 0x8000)
      emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
             - 0x80000000));
    else
      emit_move_insn (dest, GEN_INT (ud4 << 16));

    if (ud3 != 0)
      emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));

    emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
    if (ud2 != 0)
      emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
                 GEN_INT (ud2 << 16)));
    if (ud1 != 0)
      emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
  }
    }
  return dest;
}

/* Helper for the following.  Get rid of [r+r] memory refs
   in cases where it won't work (TImode, TFmode).  */

static void
rs6000_eliminate_indexed_memrefs (rtx operands[2])
{
  if (GET_CODE (operands[0]) == MEM
      && GET_CODE (XEXP (operands[0], 0)) != REG
      && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
      && ! reload_in_progress)
    operands[0]
      = replace_equiv_address (operands[0],
             copy_addr_to_reg (XEXP (operands[0], 0)));

  if (GET_CODE (operands[1]) == MEM
      && GET_CODE (XEXP (operands[1], 0)) != REG
      && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
      && ! reload_in_progress)
    operands[1]
      = replace_equiv_address (operands[1],
             copy_addr_to_reg (XEXP (operands[1], 0)));
}

/* Emit a move from SOURCE to DEST in mode MODE.  */
void
rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
{
  rtx operands[2];
  operands[0] = dest;
  operands[1] = source;

  /* Sanity checks.  Check that we get CONST_DOUBLE only when we should.  */
  if (GET_CODE (operands[1]) == CONST_DOUBLE
      && ! FLOAT_MODE_P (mode)
      && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
    {
      /* FIXME.  This should never happen.  */
      /* Since it seems that it does, do the safe thing and convert
   to a CONST_INT.  */
      operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
    }
  gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
        || FLOAT_MODE_P (mode)
        || ((CONST_DOUBLE_HIGH (operands[1]) != 0
       || CONST_DOUBLE_LOW (operands[1]) < 0)
      && (CONST_DOUBLE_HIGH (operands[1]) != -1
          || CONST_DOUBLE_LOW (operands[1]) >= 0)));

  /* Check if GCC is setting up a block move that will end up using FP
     registers as temporaries.  We must make sure this is acceptable.  */
  if (GET_CODE (operands[0]) == MEM
      && GET_CODE (operands[1]) == MEM
      && mode == DImode
      && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
    || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
      && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
              ? 32 : MEM_ALIGN (operands[0])))
      || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
                 ? 32
                 : MEM_ALIGN (operands[1]))))
      && ! MEM_VOLATILE_P (operands [0])
      && ! MEM_VOLATILE_P (operands [1]))
    {
      emit_move_insn (adjust_address (operands[0], SImode, 0),
          adjust_address (operands[1], SImode, 0));
      emit_move_insn (adjust_address (operands[0], SImode, 4),
          adjust_address (operands[1], SImode, 4));
      return;
    }

  if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
      && !gpc_reg_operand (operands[1], mode))
    operands[1] = force_reg (mode, operands[1]);

  if (mode == SFmode && ! TARGET_POWERPC
      && TARGET_HARD_FLOAT && TARGET_FPRS
      && GET_CODE (operands[0]) == MEM)
    {
      int regnum;

      if (reload_in_progress || reload_completed)
  regnum = true_regnum (operands[1]);
      else if (GET_CODE (operands[1]) == REG)
  regnum = REGNO (operands[1]);
      else
  regnum = -1;

      /* If operands[1] is a register, on POWER it may have
   double-precision data in it, so truncate it to single
   precision.  */
      if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
  {
    rtx newreg;
    newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
    emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
    operands[1] = newreg;
  }
    }

  /* Recognize the case where operand[1] is a reference to thread-local
     data and load its address to a register.  */
  if (rs6000_tls_referenced_p (operands[1]))
    {
      enum tls_model model;
      rtx tmp = operands[1];
      rtx addend = NULL;

      if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
  {
          addend = XEXP (XEXP (tmp, 0), 1);
    tmp = XEXP (XEXP (tmp, 0), 0);
  }

      gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
      model = SYMBOL_REF_TLS_MODEL (tmp);
      gcc_assert (model != 0);

      tmp = rs6000_legitimize_tls_address (tmp, model);
      if (addend)
  {
    tmp = gen_rtx_PLUS (mode, tmp, addend);
    tmp = force_operand (tmp, operands[0]);
  }
      operands[1] = tmp;
    }

  /* Handle the case where reload calls us with an invalid address.  */
  if (reload_in_progress && mode == Pmode
      && (! general_operand (operands[1], mode)
    || ! nonimmediate_operand (operands[0], mode)))
    goto emit_set;

  /* 128-bit constant floating-point values on Darwin should really be
     loaded as two parts.  */
  if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
      && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
    {
      /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
   know how to get a DFmode SUBREG of a TFmode.  */
      rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
      simplify_gen_subreg (DImode, operands[1], mode, 0),
      DImode);
      rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
               GET_MODE_SIZE (DImode)),
      simplify_gen_subreg (DImode, operands[1], mode,
               GET_MODE_SIZE (DImode)),
      DImode);
      return;
    }

  /* FIXME:  In the long term, this switch statement should go away
     and be replaced by a sequence of tests based on things like
     mode == Pmode.  */
  switch (mode)
    {
    case HImode:
    case QImode:
      if (CONSTANT_P (operands[1])
    && GET_CODE (operands[1]) != CONST_INT)
  operands[1] = force_const_mem (mode, operands[1]);
      break;

    case TFmode:
      rs6000_eliminate_indexed_memrefs (operands);
      /* fall through */

    case DFmode:
    case SFmode:
      if (CONSTANT_P (operands[1])
    && ! easy_fp_constant (operands[1], mode))
  operands[1] = force_const_mem (mode, operands[1]);
      break;

    case V16QImode:
    case V8HImode:
    case V4SFmode:
    case V4SImode:
    case V4HImode:
    case V2SFmode:
    case V2SImode:
    case V1DImode:
      if (CONSTANT_P (operands[1])
    && !easy_vector_constant (operands[1], mode))
  operands[1] = force_const_mem (mode, operands[1]);
      break;

    case SImode:
    case DImode:
      /* Use default pattern for address of ELF small data */
      if (TARGET_ELF
    && mode == Pmode
    && DEFAULT_ABI == ABI_V4
    && (GET_CODE (operands[1]) == SYMBOL_REF
        || GET_CODE (operands[1]) == CONST)
    && small_data_operand (operands[1], mode))
  {
    emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
    return;
  }

      if (DEFAULT_ABI == ABI_V4
    && mode == Pmode && mode == SImode
    && flag_pic == 1 && got_operand (operands[1], mode))
  {
    emit_insn (gen_movsi_got (operands[0], operands[1]));
    return;
  }

      if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
    && TARGET_NO_TOC
    && ! flag_pic
    && mode == Pmode
    && CONSTANT_P (operands[1])
    && GET_CODE (operands[1]) != HIGH
    && GET_CODE (operands[1]) != CONST_INT)
  {
    rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));

    /* If this is a function address on -mcall-aixdesc,
       convert it to the address of the descriptor.  */
    if (DEFAULT_ABI == ABI_AIX
        && GET_CODE (operands[1]) == SYMBOL_REF
        && XSTR (operands[1], 0)[0] == '.')
      {
        const char *name = XSTR (operands[1], 0);
        rtx new_ref;
        while (*name == '.')
    name++;
        new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
        CONSTANT_POOL_ADDRESS_P (new_ref)
    = CONSTANT_POOL_ADDRESS_P (operands[1]);
        SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
        SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
        SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
        operands[1] = new_ref;
      }

    if (DEFAULT_ABI == ABI_DARWIN)
      {
#if TARGET_MACHO
        if (MACHO_DYNAMIC_NO_PIC_P)
    {
      /* Take care of any required data indirection.  */
      operands[1] = rs6000_machopic_legitimize_pic_address (
          operands[1], mode, operands[0]);
      if (operands[0] != operands[1])
        emit_insn (gen_rtx_SET (VOIDmode,
              operands[0], operands[1]));
      return;
    }
#endif
        emit_insn (gen_macho_high (target, operands[1]));
        emit_insn (gen_macho_low (operands[0], target, operands[1]));
        return;
      }

    emit_insn (gen_elf_high (target, operands[1]));
    emit_insn (gen_elf_low (operands[0], target, operands[1]));
    return;
  }

      /* If this is a SYMBOL_REF that refers to a constant pool entry,
   and we have put it in the TOC, we just need to make a TOC-relative
   reference to it.  */
      if (TARGET_TOC
    && GET_CODE (operands[1]) == SYMBOL_REF
    && constant_pool_expr_p (operands[1])
    && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
                get_pool_mode (operands[1])))
  {
    operands[1] = create_TOC_reference (operands[1]);
  }
      else if (mode == Pmode
         && CONSTANT_P (operands[1])
         && ((GET_CODE (operands[1]) != CONST_INT
        && ! easy_fp_constant (operands[1], mode))
       || (GET_CODE (operands[1]) == CONST_INT
           && num_insns_constant (operands[1], mode) > 2)
       || (GET_CODE (operands[0]) == REG
           && FP_REGNO_P (REGNO (operands[0]))))
         && GET_CODE (operands[1]) != HIGH
         && ! legitimate_constant_pool_address_p (operands[1])
         && ! toc_relative_expr_p (operands[1]))
  {
    /* Emit a USE operation so that the constant isn't deleted if
       expensive optimizations are turned on because nobody
       references it.  This should only be done for operands that
       contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
       This should not be done for operands that contain LABEL_REFs.
       For now, we just handle the obvious case.  */
    if (GET_CODE (operands[1]) != LABEL_REF)
      emit_insn (gen_rtx_USE (VOIDmode, operands[1]));

#if TARGET_MACHO
    /* Darwin uses a special PIC legitimizer.  */
    if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
      {
        operands[1] =
    rs6000_machopic_legitimize_pic_address (operands[1], mode,
              operands[0]);
        if (operands[0] != operands[1])
    emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
        return;
      }
#endif

    /* If we are to limit the number of things we put in the TOC and
       this is a symbol plus a constant we can add in one insn,
       just put the symbol in the TOC and add the constant.  Don't do
       this if reload is in progress.  */
    if (GET_CODE (operands[1]) == CONST
        && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
        && GET_CODE (XEXP (operands[1], 0)) == PLUS
        && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
        && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
      || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
        && ! side_effects_p (operands[0]))
      {
        rtx sym =
    force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
        rtx other = XEXP (XEXP (operands[1], 0), 1);

        sym = force_reg (mode, sym);
        if (mode == SImode)
    emit_insn (gen_addsi3 (operands[0], sym, other));
        else
    emit_insn (gen_adddi3 (operands[0], sym, other));
        return;
      }

    operands[1] = force_const_mem (mode, operands[1]);

    if (TARGET_TOC
        && constant_pool_expr_p (XEXP (operands[1], 0))
        && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
      get_pool_constant (XEXP (operands[1], 0)),
      get_pool_mode (XEXP (operands[1], 0))))
      {
        operands[1]
    = gen_const_mem (mode,
         create_TOC_reference (XEXP (operands[1], 0)));
        set_mem_alias_set (operands[1], get_TOC_alias_set ());
      }
  }
      break;

    case TImode:
      rs6000_eliminate_indexed_memrefs (operands);

      if (TARGET_POWER)
  {
    emit_insn (gen_rtx_PARALLEL (VOIDmode,
           gen_rtvec (2,
          gen_rtx_SET (VOIDmode,
                 operands[0], operands[1]),
          gen_rtx_CLOBBER (VOIDmode,
               gen_rtx_SCRATCH (SImode)))));
    return;
  }
      break;

    default:
      gcc_unreachable ();
    }

  /* Above, we may have called force_const_mem which may have returned
     an invalid address.  If we can, fix this up; otherwise, reload will
     have to deal with it.  */
  if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
    operands[1] = validize_mem (operands[1]);

 emit_set:
  emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
}

/* Nonzero if we can use a floating-point register to pass this arg.  */
#define USE_FP_FOR_ARG_P(CUM,MODE,TYPE)   \
  (SCALAR_FLOAT_MODE_P (MODE)     \
   && !DECIMAL_FLOAT_MODE_P (MODE)    \
   && (CUM)->fregno <= FP_ARG_MAX_REG   \
   && TARGET_HARD_FLOAT && TARGET_FPRS)

/* Nonzero if we can use an AltiVec register to pass this arg.  */
#define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED)  \
  (ALTIVEC_VECTOR_MODE (MODE)       \
   && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG    \
   && TARGET_ALTIVEC_ABI        \
   && (NAMED))

/* Return a nonzero value to say to return the function value in
   memory, just as large structures are always returned.  TYPE will be
   the data type of the value, and FNTYPE will be the type of the
   function doing the returning, or @code{NULL} for libcalls.

   The AIX ABI for the RS/6000 specifies that all structures are
   returned in memory.  The Darwin ABI does the same.  The SVR4 ABI
   specifies that structures <= 8 bytes are returned in r3/r4, but a
   draft put them in memory, and GCC used to implement the draft
   instead of the final standard.  Therefore, aix_struct_return
   controls this instead of DEFAULT_ABI; V.4 targets needing backward
   compatibility can change DRAFT_V4_STRUCT_RET to override the
   default, and -m switches get the final word.  See
   rs6000_override_options for more details.

   The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
   long double support is enabled.  These values are returned in memory.

   int_size_in_bytes returns -1 for variable size objects, which go in
   memory always.  The cast to unsigned makes -1 > 8.  */

static bool
rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
{
  /* In the darwin64 abi, try to use registers for larger structs
     if possible.  */
  if (rs6000_darwin64_abi
      && TREE_CODE (type) == RECORD_TYPE
      && int_size_in_bytes (type) > 0)
    {
      CUMULATIVE_ARGS valcum;
      rtx valret;

      valcum.words = 0;
      valcum.fregno = FP_ARG_MIN_REG;
      valcum.vregno = ALTIVEC_ARG_MIN_REG;
      /* Do a trial code generation as if this were going to be passed
   as an argument; if any part goes in memory, we return NULL.  */
      valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
      if (valret)
  return false;
      /* Otherwise fall through to more conventional ABI rules.  */
    }

  if (AGGREGATE_TYPE_P (type)
      && (aix_struct_return
    || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
    return true;

  /* Allow -maltivec -mabi=no-altivec without warning.  Altivec vector
     modes only exist for GCC vector types if -maltivec.  */
  if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
      && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
    return false;

  /* Return synthetic vectors in memory.  */
  if (TREE_CODE (type) == VECTOR_TYPE
      && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
    {
      static bool warned_for_return_big_vectors = false;
      if (!warned_for_return_big_vectors)
  {
    warning (0, "GCC vector returned by reference: "
       "non-standard ABI extension with no compatibility guarantee");
    warned_for_return_big_vectors = true;
  }
      return true;
    }

  if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
    return true;

  return false;
}

/* Initialize a variable CUM of type CUMULATIVE_ARGS
   for a call to a function whose data type is FNTYPE.
   For a library call, FNTYPE is 0.

   For incoming args we set the number of arguments in the prototype large
   so we never return a PARALLEL.  */

void
init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
          rtx libname ATTRIBUTE_UNUSED, int incoming,
          int libcall, int n_named_args)
{
  static CUMULATIVE_ARGS zero_cumulative;

  *cum = zero_cumulative;
  cum->words = 0;
  cum->fregno = FP_ARG_MIN_REG;
  cum->vregno = ALTIVEC_ARG_MIN_REG;
  cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
  cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
          ? CALL_LIBCALL : CALL_NORMAL);
  cum->sysv_gregno = GP_ARG_MIN_REG;
  cum->stdarg = fntype
    && (TYPE_ARG_TYPES (fntype) != 0
  && (TREE_VALUE (tree_last  (TYPE_ARG_TYPES (fntype)))
      != void_type_node));

  cum->nargs_prototype = 0;
  if (incoming || cum->prototype)
    cum->nargs_prototype = n_named_args;

  /* Check for a longcall attribute.  */
  if ((!fntype && rs6000_default_long_calls)
      || (fntype
    && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
    && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
    cum->call_cookie |= CALL_LONG;

  if (TARGET_DEBUG_ARG)
    {
      fprintf (stderr, "\ninit_cumulative_args:");
      if (fntype)
  {
    tree ret_type = TREE_TYPE (fntype);
    fprintf (stderr, " ret code = %s,",
       tree_code_name[ (int)TREE_CODE (ret_type) ]);
  }

      if (cum->call_cookie & CALL_LONG)
  fprintf (stderr, " longcall,");

      fprintf (stderr, " proto = %d, nargs = %d\n",
         cum->prototype, cum->nargs_prototype);
    }

  if (fntype
      && !TARGET_ALTIVEC
      && TARGET_ALTIVEC_ABI
      && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
    {
      error ("cannot return value in vector register because"
       " altivec instructions are disabled, use -maltivec"
       " to enable them");
    }
}

/* Return true if TYPE must be passed on the stack and not in registers.  */

static bool
rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
{
  if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
    return must_pass_in_stack_var_size (mode, type);
  else
    return must_pass_in_stack_var_size_or_pad (mode, type);
}

/* If defined, a C expression which determines whether, and in which
   direction, to pad out an argument with extra space.  The value
   should be of type `enum direction': either `upward' to pad above
   the argument, `downward' to pad below, or `none' to inhibit
   padding.

   For the AIX ABI structs are always stored left shifted in their
   argument slot.  */

enum direction
function_arg_padding (enum machine_mode mode, tree type)
{
#ifndef AGGREGATE_PADDING_FIXED
#define AGGREGATE_PADDING_FIXED 0
#endif
#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
#define AGGREGATES_PAD_UPWARD_ALWAYS 0
#endif

  if (!AGGREGATE_PADDING_FIXED)
    {
      /* GCC used to pass structures of the same size as integer types as
   if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
   i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
   passed padded downward, except that -mstrict-align further
   muddied the water in that multi-component structures of 2 and 4
   bytes in size were passed padded upward.

   The following arranges for best compatibility with previous
   versions of gcc, but removes the -mstrict-align dependency.  */
      if (BYTES_BIG_ENDIAN)
  {
    HOST_WIDE_INT size = 0;

    if (mode == BLKmode)
      {
        if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
    size = int_size_in_bytes (type);
      }
    else
      size = GET_MODE_SIZE (mode);

    if (size == 1 || size == 2 || size == 4)
      return downward;
  }
      return upward;
    }

  if (AGGREGATES_PAD_UPWARD_ALWAYS)
    {
      if (type != 0 && AGGREGATE_TYPE_P (type))
  return upward;
    }

  /* Fall back to the default.  */
  return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
}

/* If defined, a C expression that gives the alignment boundary, in bits,
   of an argument with the specified mode and type.  If it is not defined,
   PARM_BOUNDARY is used for all arguments.

   V.4 wants long longs and doubles to be double word aligned.  Just
   testing the mode size is a boneheaded way to do this as it means
   that other types such as complex int are also double word aligned.
   However, we're stuck with this because changing the ABI might break
   existing library interfaces.

   Doubleword align SPE vectors.
   Quadword align Altivec vectors.
   Quadword align large synthetic vector types.   */

int
function_arg_boundary (enum machine_mode mode, tree type)
{
  if (DEFAULT_ABI == ABI_V4
      && (GET_MODE_SIZE (mode) == 8
    || (TARGET_HARD_FLOAT
        && TARGET_FPRS
        && mode == TFmode)))
    return 64;
  else if (SPE_VECTOR_MODE (mode)
     || (type && TREE_CODE (type) == VECTOR_TYPE
         && int_size_in_bytes (type) >= 8
         && int_size_in_bytes (type) < 16))
    return 64;
  else if (ALTIVEC_VECTOR_MODE (mode)
     || (type && TREE_CODE (type) == VECTOR_TYPE
         && int_size_in_bytes (type) >= 16))
    return 128;
  else if (rs6000_darwin64_abi && mode == BLKmode
     && type && TYPE_ALIGN (type) > 64)
    return 128;
  else
    return PARM_BOUNDARY;
}

/* For a function parm of MODE and TYPE, return the starting word in
   the parameter area.  NWORDS of the parameter area are already used.  */

static unsigned int
rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
{
  unsigned int align;
  unsigned int parm_offset;

  align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
  parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
  return nwords + (-(parm_offset + nwords) & align);
}

/* Compute the size (in words) of a function argument.  */

static unsigned long
rs6000_arg_size (enum machine_mode mode, tree type)
{
  unsigned long size;

  if (mode != BLKmode)
    size = GET_MODE_SIZE (mode);
  else
    size = int_size_in_bytes (type);

  if (TARGET_32BIT)
    return (size + 3) >> 2;
  else
    return (size + 7) >> 3;
}

/* Use this to flush pending int fields.  */

static void
rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
            HOST_WIDE_INT bitpos)
{
  unsigned int startbit, endbit;
  int intregs, intoffset;
  enum machine_mode mode;

  if (cum->intoffset == -1)
    return;

  intoffset = cum->intoffset;
  cum->intoffset = -1;

  if (intoffset % BITS_PER_WORD != 0)
    {
      mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
          MODE_INT, 0);
      if (mode == BLKmode)
  {
    /* We couldn't find an appropriate mode, which happens,
       e.g., in packed structs when there are 3 bytes to load.
       Back intoffset back to the beginning of the word in this
       case.  */
    intoffset = intoffset & -BITS_PER_WORD;
  }
    }

  startbit = intoffset & -BITS_PER_WORD;
  endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
  intregs = (endbit - startbit) / BITS_PER_WORD;
  cum->words += intregs;
}

/* The darwin64 ABI calls for us to recurse down through structs,
   looking for elements passed in registers.  Unfortunately, we have
   to track int register count here also because of misalignments
   in powerpc alignment mode.  */

static void
rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
              tree type,
              HOST_WIDE_INT startbitpos)
{
  tree f;

  for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
    if (TREE_CODE (f) == FIELD_DECL)
      {
  HOST_WIDE_INT bitpos = startbitpos;
  tree ftype = TREE_TYPE (f);
  enum machine_mode mode;
  if (ftype == error_mark_node)
    continue;
  mode = TYPE_MODE (ftype);

  if (DECL_SIZE (f) != 0
      && host_integerp (bit_position (f), 1))
    bitpos += int_bit_position (f);

  /* ??? FIXME: else assume zero offset.  */

  if (TREE_CODE (ftype) == RECORD_TYPE)
    rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
  else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
    {
      rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
      cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
      cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
    }
  else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
    {
      rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
      cum->vregno++;
      cum->words += 2;
    }
  else if (cum->intoffset == -1)
    cum->intoffset = bitpos;
      }
}

/* Update the data in CUM to advance over an argument
   of mode MODE and data type TYPE.
   (TYPE is null for libcalls where that information may not be available.)

   Note that for args passed by reference, function_arg will be called
   with MODE and TYPE set to that of the pointer to the arg, not the arg
   itself.  */

void
function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
          tree type, int named, int depth)
{
  int size;

  /* Only tick off an argument if we're not recursing.  */
  if (depth == 0)
    cum->nargs_prototype--;

  if (TARGET_ALTIVEC_ABI
      && (ALTIVEC_VECTOR_MODE (mode)
    || (type && TREE_CODE (type) == VECTOR_TYPE
        && int_size_in_bytes (type) == 16)))
    {
      bool stack = false;

      if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
  {
    cum->vregno++;
    if (!TARGET_ALTIVEC)
      error ("cannot pass argument in vector register because"
       " altivec instructions are disabled, use -maltivec"
       " to enable them");

    /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
       even if it is going to be passed in a vector register.
       Darwin does the same for variable-argument functions.  */
    if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
        || (cum->stdarg && DEFAULT_ABI != ABI_V4))
      stack = true;
  }
      else
  stack = true;

      if (stack)
  {
    int align;

    /* Vector parameters must be 16-byte aligned.  This places
       them at 2 mod 4 in terms of words in 32-bit mode, since
       the parameter save area starts at offset 24 from the
       stack.  In 64-bit mode, they just have to start on an
       even word, since the parameter save area is 16-byte
       aligned.  Space for GPRs is reserved even if the argument
       will be passed in memory.  */
    if (TARGET_32BIT)
      align = (2 - cum->words) & 3;
    else
      align = cum->words & 1;
    cum->words += align + rs6000_arg_size (mode, type);

    if (TARGET_DEBUG_ARG)
      {
        fprintf (stderr, "function_adv: words = %2d, align=%d, ",
           cum->words, align);
        fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
           cum->nargs_prototype, cum->prototype,
           GET_MODE_NAME (mode));
      }
  }
    }
  else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
     && !cum->stdarg
     && cum->sysv_gregno <= GP_ARG_MAX_REG)
    cum->sysv_gregno++;

  else if (rs6000_darwin64_abi
     && mode == BLKmode
         && TREE_CODE (type) == RECORD_TYPE
     && (size = int_size_in_bytes (type)) > 0)
    {
      /* Variable sized types have size == -1 and are
   treated as if consisting entirely of ints.
   Pad to 16 byte boundary if needed.  */
      if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
    && (cum->words % 2) != 0)
  cum->words++;
      /* For varargs, we can just go up by the size of the struct. */
      if (!named)
  cum->words += (size + 7) / 8;
      else
  {
    /* It is tempting to say int register count just goes up by
       sizeof(type)/8, but this is wrong in a case such as
       { int; double; int; } [powerpc alignment].  We have to
       grovel through the fields for these too.  */
    cum->intoffset = 0;
    rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
    rs6000_darwin64_record_arg_advance_flush (cum,
                size * BITS_PER_UNIT);
  }
    }
  else if (DEFAULT_ABI == ABI_V4)
    {
      if (TARGET_HARD_FLOAT && TARGET_FPRS
    && (mode == SFmode || mode == DFmode
        || (mode == TFmode && !TARGET_IEEEQUAD)))
  {
    if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
      cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
    else
      {
        cum->fregno = FP_ARG_V4_MAX_REG + 1;
        if (mode == DFmode || mode == TFmode)
    cum->words += cum->words & 1;
        cum->words += rs6000_arg_size (mode, type);
      }
  }
      else
  {
    int n_words = rs6000_arg_size (mode, type);
    int gregno = cum->sysv_gregno;

    /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
       (r7,r8) or (r9,r10).  As does any other 2 word item such
       as complex int due to a historical mistake.  */
    if (n_words == 2)
      gregno += (1 - gregno) & 1;

    /* Multi-reg args are not split between registers and stack.  */
    if (gregno + n_words - 1 > GP_ARG_MAX_REG)
      {
        /* Long long and SPE vectors are aligned on the stack.
     So are other 2 word items such as complex int due to
     a historical mistake.  */
        if (n_words == 2)
    cum->words += cum->words & 1;
        cum->words += n_words;
      }

    /* Note: continuing to accumulate gregno past when we've started
       spilling to the stack indicates the fact that we've started
       spilling to the stack to expand_builtin_saveregs.  */
    cum->sysv_gregno = gregno + n_words;
  }

      if (TARGET_DEBUG_ARG)
  {
    fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
       cum->words, cum->fregno);
    fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
       cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
    fprintf (stderr, "mode = %4s, named = %d\n",
       GET_MODE_NAME (mode), named);
  }
    }
  else
    {
      int n_words = rs6000_arg_size (mode, type);
      int start_words = cum->words;
      int align_words = rs6000_parm_start (mode, type, start_words);

      cum->words = align_words + n_words;

      if (SCALAR_FLOAT_MODE_P (mode)
    && !DECIMAL_FLOAT_MODE_P (mode)
    && TARGET_HARD_FLOAT && TARGET_FPRS)
  cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;

      if (TARGET_DEBUG_ARG)
  {
    fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
       cum->words, cum->fregno);
    fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
       cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
    fprintf (stderr, "named = %d, align = %d, depth = %d\n",
       named, align_words - start_words, depth);
  }
    }
}

static rtx
spe_build_register_parallel (enum machine_mode mode, int gregno)
{
  rtx r1, r3;

  switch (mode)
    {
    case DFmode:
      r1 = gen_rtx_REG (DImode, gregno);
      r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
      return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));

    case DCmode:
      r1 = gen_rtx_REG (DImode, gregno);
      r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
      r3 = gen_rtx_REG (DImode, gregno + 2);
      r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
      return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));

    default:
      gcc_unreachable ();
    }
}

/* Determine where to put a SIMD argument on the SPE.  */
static rtx
rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
       tree type)
{
  int gregno = cum->sysv_gregno;

  /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
     are passed and returned in a pair of GPRs for ABI compatibility.  */
  if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
    {
      int n_words = rs6000_arg_size (mode, type);

      /* Doubles go in an odd/even register pair (r5/r6, etc).  */
      if (mode == DFmode)
  gregno += (1 - gregno) & 1;

      /* Multi-reg args are not split between registers and stack.  */
      if (gregno + n_words - 1 > GP_ARG_MAX_REG)
  return NULL_RTX;

      return spe_build_register_parallel (mode, gregno);
    }
  if (cum->stdarg)
    {
      int n_words = rs6000_arg_size (mode, type);

      /* SPE vectors are put in odd registers.  */
      if (n_words == 2 && (gregno & 1) == 0)
  gregno += 1;

      if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
  {
    rtx r1, r2;
    enum machine_mode m = SImode;

    r1 = gen_rtx_REG (m, gregno);
    r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
    r2 = gen_rtx_REG (m, gregno + 1);
    r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
    return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
  }
      else
  return NULL_RTX;
    }
  else
    {
      if (gregno <= GP_ARG_MAX_REG)
  return gen_rtx_REG (mode, gregno);
      else
  return NULL_RTX;
    }
}

/* A subroutine of rs6000_darwin64_record_arg.  Assign the bits of the
   structure between cum->intoffset and bitpos to integer registers.  */

static void
rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
          HOST_WIDE_INT bitpos, rtx rvec[], int *k)
{
  enum machine_mode mode;
  unsigned int regno;
  unsigned int startbit, endbit;
  int this_regno, intregs, intoffset;
  rtx reg;

  if (cum->intoffset == -1)
    return;

  intoffset = cum->intoffset;
  cum->intoffset = -1;

  /* If this is the trailing part of a word, try to only load that
     much into the register.  Otherwise load the whole register.  Note
     that in the latter case we may pick up unwanted bits.  It's not a
     problem at the moment but may wish to revisit.  */

  if (intoffset % BITS_PER_WORD != 0)
    {
      mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
        MODE_INT, 0);
      if (mode == BLKmode)
  {
    /* We couldn't find an appropriate mode, which happens,
       e.g., in packed structs when there are 3 bytes to load.
       Back intoffset back to the beginning of the word in this
       case.  */
   intoffset = intoffset & -BITS_PER_WORD;
   mode = word_mode;
  }
    }
  else
    mode = word_mode;

  startbit = intoffset & -BITS_PER_WORD;
  endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
  intregs = (endbit - startbit) / BITS_PER_WORD;
  this_regno = cum->words + intoffset / BITS_PER_WORD;

  if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
    cum->use_stack = 1;

  intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
  if (intregs <= 0)
    return;

  intoffset /= BITS_PER_UNIT;
  do
    {
      regno = GP_ARG_MIN_REG + this_regno;
      reg = gen_rtx_REG (mode, regno);
      rvec[(*k)++] =
  gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));

      this_regno += 1;
      intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
      mode = word_mode;
      intregs -= 1;
    }
  while (intregs > 0);
}

/* Recursive workhorse for the following.  */

static void
rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
            HOST_WIDE_INT startbitpos, rtx rvec[],
            int *k)
{
  tree f;

  for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
    if (TREE_CODE (f) == FIELD_DECL)
      {
  HOST_WIDE_INT bitpos = startbitpos;
  tree ftype = TREE_TYPE (f);
  enum machine_mode mode;
  if (ftype == error_mark_node)
    continue;
  mode = TYPE_MODE (ftype);

  if (DECL_SIZE (f) != 0
      && host_integerp (bit_position (f), 1))
    bitpos += int_bit_position (f);

  /* ??? FIXME: else assume zero offset.  */

  if (TREE_CODE (ftype) == RECORD_TYPE)
    rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
  else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
    {
#if 0
      switch (mode)
        {
        case SCmode: mode = SFmode; break;
        case DCmode: mode = DFmode; break;
        case TCmode: mode = TFmode; break;
        default: break;
        }
#endif
      rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
      rvec[(*k)++]
        = gen_rtx_EXPR_LIST (VOIDmode,
           gen_rtx_REG (mode, cum->fregno++),
           GEN_INT (bitpos / BITS_PER_UNIT));
      if (mode == TFmode)
        cum->fregno++;
    }
  else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
    {
      rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
      rvec[(*k)++]
        = gen_rtx_EXPR_LIST (VOIDmode,
           gen_rtx_REG (mode, cum->vregno++),
           GEN_INT (bitpos / BITS_PER_UNIT));
    }
  else if (cum->intoffset == -1)
    cum->intoffset = bitpos;
      }
}

/* For the darwin64 ABI, we want to construct a PARALLEL consisting of
   the register(s) to be used for each field and subfield of a struct
   being passed by value, along with the offset of where the
   register's value may be found in the block.  FP fields go in FP
   register, vector fields go in vector registers, and everything
   else goes in int registers, packed as in memory.

   This code is also used for function return values.  RETVAL indicates
   whether this is the case.

   Much of this is taken from the SPARC V9 port, which has a similar
   calling convention.  */

static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
          int named, bool retval)
{
  rtx rvec[FIRST_PSEUDO_REGISTER];
  int k = 1, kbase = 1;
  HOST_WIDE_INT typesize = int_size_in_bytes (type);
  /* This is a copy; modifications are not visible to our caller.  */
  CUMULATIVE_ARGS copy_cum = *orig_cum;
  CUMULATIVE_ARGS *cum = &copy_cum;

  /* Pad to 16 byte boundary if needed.  */
  if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
      && (cum->words % 2) != 0)
    cum->words++;

  cum->intoffset = 0;
  cum->use_stack = 0;
  cum->named = named;

  /* Put entries into rvec[] for individual FP and vector fields, and
     for the chunks of memory that go in int regs.  Note we start at
     element 1; 0 is reserved for an indication of using memory, and
     may or may not be filled in below. */
  rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
  rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);

  /* If any part of the struct went on the stack put all of it there.
     This hack is because the generic code for
     FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
     parts of the struct are not at the beginning.  */
  if (cum->use_stack)
    {
      if (retval)
  return NULL_RTX;    /* doesn't go in registers at all */
      kbase = 0;
      rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
    }
  if (k > 1 || cum->use_stack)
    return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
  else
    return NULL_RTX;
}

/* Determine where to place an argument in 64-bit mode with 32-bit ABI.  */

static rtx
rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
{
  int n_units;
  int i, k;
  rtx rvec[GP_ARG_NUM_REG + 1];

  if (align_words >= GP_ARG_NUM_REG)
    return NULL_RTX;

  n_units = rs6000_arg_size (mode, type);

  /* Optimize the simple case where the arg fits in one gpr, except in
     the case of BLKmode due to assign_parms assuming that registers are
     BITS_PER_WORD wide.  */
  if (n_units == 0
      || (n_units == 1 && mode != BLKmode))
    return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);

  k = 0;
  if (align_words + n_units > GP_ARG_NUM_REG)
    /* Not all of the arg fits in gprs.  Say that it goes in memory too,
       using a magic NULL_RTX component.
       This is not strictly correct.  Only some of the arg belongs in
       memory, not all of it.  However, the normal scheme using
       function_arg_partial_nregs can result in unusual subregs, eg.
       (subreg:SI (reg:DF) 4), which are not handled well.  The code to
       store the whole arg to memory is often more efficient than code
       to store pieces, and we know that space is available in the right
       place for the whole arg.  */
    rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);

  i = 0;
  do
    {
      rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
      rtx off = GEN_INT (i++ * 4);
      rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
    }
  while (++align_words < GP_ARG_NUM_REG && --n_units != 0);

  return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
}

/* Determine where to put an argument to a function.
   Value is zero to push the argument on the stack,
   or a hard register in which to store the argument.

   MODE is the argument's machine mode.
   TYPE is the data type of the argument (as a tree).
    This is null for libcalls where that information may
    not be available.
   CUM is a variable of type CUMULATIVE_ARGS which gives info about
    the preceding args and about the function being called.  It is
    not modified in this routine.
   NAMED is nonzero if this argument is a named parameter
    (otherwise it is an extra parameter matching an ellipsis).

   On RS/6000 the first eight words of non-FP are normally in registers
   and the rest are pushed.  Under AIX, the first 13 FP args are in registers.
   Under V.4, the first 8 FP args are in registers.

   If this is floating-point and no prototype is specified, we use
   both an FP and integer register (or possibly FP reg and stack).  Library
   functions (when CALL_LIBCALL is set) always have the proper types for args,
   so we can pass the FP value just in one register.  emit_library_function
   doesn't support PARALLEL anyway.

   Note that for args passed by reference, function_arg will be called
   with MODE and TYPE set to that of the pointer to the arg, not the arg
   itself.  */

rtx
function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
        tree type, int named)
{
  enum rs6000_abi abi = DEFAULT_ABI;

  /* Return a marker to indicate whether CR1 needs to set or clear the
     bit that V.4 uses to say fp args were passed in registers.
     Assume that we don't need the marker for software floating point,
     or compiler generated library calls.  */
  if (mode == VOIDmode)
    {
      if (abi == ABI_V4
    && (cum->call_cookie & CALL_LIBCALL) == 0
    && (cum->stdarg
        || (cum->nargs_prototype < 0
      && (cum->prototype || TARGET_NO_PROTOTYPE))))
  {
    /* For the SPE, we need to crxor CR6 always.  */
    if (TARGET_SPE_ABI)
      return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
    else if (TARGET_HARD_FLOAT && TARGET_FPRS)
      return GEN_INT (cum->call_cookie
          | ((cum->fregno == FP_ARG_MIN_REG)
             ? CALL_V4_SET_FP_ARGS
             : CALL_V4_CLEAR_FP_ARGS));
  }

      return GEN_INT (cum->call_cookie);
    }

  if (rs6000_darwin64_abi && mode == BLKmode
      && TREE_CODE (type) == RECORD_TYPE)
    {
      rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
      if (rslt != NULL_RTX)
  return rslt;
      /* Else fall through to usual handling.  */
    }

  if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
    if (TARGET_64BIT && ! cum->prototype)
      {
  /* Vector parameters get passed in vector register
     and also in GPRs or memory, in absence of prototype.  */
  int align_words;
  rtx slot;
  align_words = (cum->words + 1) & ~1;

  if (align_words >= GP_ARG_NUM_REG)
    {
      slot = NULL_RTX;
    }
  else
    {
      slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
    }
  return gen_rtx_PARALLEL (mode,
     gen_rtvec (2,
          gen_rtx_EXPR_LIST (VOIDmode,
                 slot, const0_rtx),
          gen_rtx_EXPR_LIST (VOIDmode,
                 gen_rtx_REG (mode, cum->vregno),
                 const0_rtx)));
      }
    else
      return gen_rtx_REG (mode, cum->vregno);
  else if (TARGET_ALTIVEC_ABI
     && (ALTIVEC_VECTOR_MODE (mode)
         || (type && TREE_CODE (type) == VECTOR_TYPE
       && int_size_in_bytes (type) == 16)))
    {
      if (named || abi == ABI_V4)
  return NULL_RTX;
      else
  {
    /* Vector parameters to varargs functions under AIX or Darwin
       get passed in memory and possibly also in GPRs.  */
    int align, align_words, n_words;
    enum machine_mode part_mode;

    /* Vector parameters must be 16-byte aligned.  This places them at
       2 mod 4 in terms of words in 32-bit mode, since the parameter
       save area starts at offset 24 from the stack.  In 64-bit mode,
       they just have to start on an even word, since the parameter
       save area is 16-byte aligned.  */
    if (TARGET_32BIT)
      align = (2 - cum->words) & 3;
    else
      align = cum->words & 1;
    align_words = cum->words + align;

    /* Out of registers?  Memory, then.  */
    if (align_words >= GP_ARG_NUM_REG)
      return NULL_RTX;

    if (TARGET_32BIT && TARGET_POWERPC64)
      return rs6000_mixed_function_arg (mode, type, align_words);

    /* The vector value goes in GPRs.  Only the part of the
       value in GPRs is reported here.  */
    part_mode = mode;
    n_words = rs6000_arg_size (mode, type);
    if (align_words + n_words > GP_ARG_NUM_REG)
      /* Fortunately, there are only two possibilities, the value
         is either wholly in GPRs or half in GPRs and half not.  */
      part_mode = DImode;

    return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
  }
    }
  else if (TARGET_SPE_ABI && TARGET_SPE
     && (SPE_VECTOR_MODE (mode)
         || (TARGET_E500_DOUBLE && (mode == DFmode
            || mode == DCmode))))
    return rs6000_spe_function_arg (cum, mode, type);

  else if (abi == ABI_V4)
    {
      if (TARGET_HARD_FLOAT && TARGET_FPRS
    && (mode == SFmode || mode == DFmode
        || (mode == TFmode && !TARGET_IEEEQUAD)))
  {
    if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
      return gen_rtx_REG (mode, cum->fregno);
    else
      return NULL_RTX;
  }
      else
  {
    int n_words = rs6000_arg_size (mode, type);
    int gregno = cum->sysv_gregno;

    /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
       (r7,r8) or (r9,r10).  As does any other 2 word item such
       as complex int due to a historical mistake.  */
    if (n_words == 2)
      gregno += (1 - gregno) & 1;

    /* Multi-reg args are not split between registers and stack.  */
    if (gregno + n_words - 1 > GP_ARG_MAX_REG)
      return NULL_RTX;

    if (TARGET_32BIT && TARGET_POWERPC64)
      return rs6000_mixed_function_arg (mode, type,
                gregno - GP_ARG_MIN_REG);
    return gen_rtx_REG (mode, gregno);
  }
    }
  else
    {
      int align_words = rs6000_parm_start (mode, type, cum->words);

      if (USE_FP_FOR_ARG_P (cum, mode, type))
  {
    rtx rvec[GP_ARG_NUM_REG + 1];
    rtx r;
    int k;
    bool needs_psave;
    enum machine_mode fmode = mode;
    unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;

    if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
      {
        /* Currently, we only ever need one reg here because complex
     doubles are split.  */
        gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);

        /* Long double split over regs and memory.  */
        fmode = DFmode;
      }

    /* Do we also need to pass this arg in the parameter save
       area?  */
    needs_psave = (type
       && (cum->nargs_prototype <= 0
           || (DEFAULT_ABI == ABI_AIX
         && TARGET_XL_COMPAT
         && align_words >= GP_ARG_NUM_REG)));

    if (!needs_psave && mode == fmode)
      return gen_rtx_REG (fmode, cum->fregno);

    k = 0;
    if (needs_psave)
      {
        /* Describe the part that goes in gprs or the stack.
     This piece must come first, before the fprs.  */
        if (align_words < GP_ARG_NUM_REG)
    {
      unsigned long n_words = rs6000_arg_size (mode, type);

      if (align_words + n_words > GP_ARG_NUM_REG
          || (TARGET_32BIT && TARGET_POWERPC64))
        {
          /* If this is partially on the stack, then we only
       include the portion actually in registers here.  */
          enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
          rtx off;
          int i = 0;
          if (align_words + n_words > GP_ARG_NUM_REG)
      /* Not all of the arg fits in gprs.  Say that it
         goes in memory too, using a magic NULL_RTX
         component.  Also see comment in
         rs6000_mixed_function_arg for why the normal
         function_arg_partial_nregs scheme doesn't work
         in this case. */
      rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
                   const0_rtx);
          do
      {
        r = gen_rtx_REG (rmode,
             GP_ARG_MIN_REG + align_words);
        off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
        rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
      }
          while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
        }
      else
        {
          /* The whole arg fits in gprs.  */
          r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
          rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
        }
    }
        else
    /* It's entirely in memory.  */
    rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
      }

    /* Describe where this piece goes in the fprs.  */
    r = gen_rtx_REG (fmode, cum->fregno);
    rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);

    return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
  }
      else if (align_words < GP_ARG_NUM_REG)
  {
    if (TARGET_32BIT && TARGET_POWERPC64)
      return rs6000_mixed_function_arg (mode, type, align_words);

    if (mode == BLKmode)
      mode = Pmode;

    return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
  }
      else
  return NULL_RTX;
    }
}

/* For an arg passed partly in registers and partly in memory, this is
   the number of bytes passed in registers.  For args passed entirely in
   registers or entirely in memory, zero.  When an arg is described by a
   PARALLEL, perhaps using more than one register type, this function
   returns the number of bytes used by the first element of the PARALLEL.  */

static int
rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
        tree type, bool named)
{
  int ret = 0;
  int align_words;

  if (DEFAULT_ABI == ABI_V4)
    return 0;

  if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
      && cum->nargs_prototype >= 0)
    return 0;

  /* In this complicated case we just disable the partial_nregs code.  */
  if (rs6000_darwin64_abi && mode == BLKmode
      && TREE_CODE (type) == RECORD_TYPE
      && int_size_in_bytes (type) > 0)
    return 0;

  align_words = rs6000_parm_start (mode, type, cum->words);

  if (USE_FP_FOR_ARG_P (cum, mode, type))
    {
      /* If we are passing this arg in the fixed parameter save area
   (gprs or memory) as well as fprs, then this function should
   return the number of partial bytes passed in the parameter
   save area rather than partial bytes passed in fprs.  */
      if (type
    && (cum->nargs_prototype <= 0
        || (DEFAULT_ABI == ABI_AIX
      && TARGET_XL_COMPAT
      && align_words >= GP_ARG_NUM_REG)))
  return 0;
      else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
         > FP_ARG_MAX_REG + 1)
  ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
      else if (cum->nargs_prototype >= 0)
  return 0;
    }

  if (align_words < GP_ARG_NUM_REG
      && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
    ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);

  if (ret != 0 && TARGET_DEBUG_ARG)
    fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);

  return ret;
}

/* A C expression that indicates when an argument must be passed by
   reference.  If nonzero for an argument, a copy of that argument is
   made in memory and a pointer to the argument is passed instead of
   the argument itself.  The pointer is passed in whatever way is
   appropriate for passing a pointer to that type.

   Under V.4, aggregates and long double are passed by reference.

   As an extension to all 32-bit ABIs, AltiVec vectors are passed by
   reference unless the AltiVec vector extension ABI is in force.

   As an extension to all ABIs, variable sized types are passed by
   reference.  */

static bool
rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
        enum machine_mode mode, tree type,
        bool named ATTRIBUTE_UNUSED)
{
  if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
    {
      if (TARGET_DEBUG_ARG)
  fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
      return 1;
    }

  if (!type)
    return 0;

  if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
    {
      if (TARGET_DEBUG_ARG)
  fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
      return 1;
    }

  if (int_size_in_bytes (type) < 0)
    {
      if (TARGET_DEBUG_ARG)
  fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
      return 1;
    }

  /* Allow -maltivec -mabi=no-altivec without warning.  Altivec vector
     modes only exist for GCC vector types if -maltivec.  */
  if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
    {
      if (TARGET_DEBUG_ARG)
  fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
      return 1;
    }

  /* Pass synthetic vectors in memory.  */
  if (TREE_CODE (type) == VECTOR_TYPE
      && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
    {
      static bool warned_for_pass_big_vectors = false;
      if (TARGET_DEBUG_ARG)
  fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
      if (!warned_for_pass_big_vectors)
  {
    warning (0, "GCC vector passed by reference: "
       "non-standard ABI extension with no compatibility guarantee");
    warned_for_pass_big_vectors = true;
  }
      return 1;
    }

  return 0;
}

static void
rs6000_move_block_from_reg (int regno, rtx x, int nregs)
{
  int i;
  enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;

  if (nregs == 0)
    return;

  for (i = 0; i < nregs; i++)
    {
      rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
      if (reload_completed)
  {
    if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
      tem = NULL_RTX;
    else
      tem = simplify_gen_subreg (reg_mode, x, BLKmode,
               i * GET_MODE_SIZE (reg_mode));
  }
      else
  tem = replace_equiv_address (tem, XEXP (tem, 0));

      gcc_assert (tem);

      emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
    }
}

/* Perform any needed actions needed for a function that is receiving a
   variable number of arguments.

   CUM is as above.

   MODE and TYPE are the mode and type of the current parameter.

   PRETEND_SIZE is a variable that should be set to the amount of stack
   that must be pushed by the prolog to pretend that our caller pushed
   it.

   Normally, this macro will push all remaining incoming registers on the
   stack and set PRETEND_SIZE to the length of the registers pushed.  */

static void
setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
      tree type, int *pretend_size ATTRIBUTE_UNUSED,
      int no_rtl)
{
  CUMULATIVE_ARGS next_cum;
  int reg_size = TARGET_32BIT ? 4 : 8;
  rtx save_area = NULL_RTX, mem;
  int first_reg_offset, set;

  /* Skip the last named argument.  */
  next_cum = *cum;
  function_arg_advance (&next_cum, mode, type, 1, 0);

  if (DEFAULT_ABI == ABI_V4)
    {
      first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;

      if (! no_rtl)
  {
    int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
    HOST_WIDE_INT offset = 0;

    /* Try to optimize the size of the varargs save area.
       The ABI requires that ap.reg_save_area is doubleword
       aligned, but we don't need to allocate space for all
       the bytes, only those to which we actually will save
       anything.  */
    if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
      gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
    if (TARGET_HARD_FLOAT && TARGET_FPRS
        && next_cum.fregno <= FP_ARG_V4_MAX_REG
        && cfun->va_list_fpr_size)
      {
        if (gpr_reg_num)
    fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
         * UNITS_PER_FP_WORD;
        if (cfun->va_list_fpr_size
      < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
    fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
        else
    fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
          * UNITS_PER_FP_WORD;
      }
    if (gpr_reg_num)
      {
        offset = -((first_reg_offset * reg_size) & ~7);
        if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
    {
      gpr_reg_num = cfun->va_list_gpr_size;
      if (reg_size == 4 && (first_reg_offset & 1))
        gpr_reg_num++;
    }
        gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
      }
    else if (fpr_size)
      offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
           * UNITS_PER_FP_WORD
         - (int) (GP_ARG_NUM_REG * reg_size);

    if (gpr_size + fpr_size)
      {
        rtx reg_save_area
    = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
        gcc_assert (GET_CODE (reg_save_area) == MEM);
        reg_save_area = XEXP (reg_save_area, 0);
        if (GET_CODE (reg_save_area) == PLUS)
    {
      gcc_assert (XEXP (reg_save_area, 0)
            == virtual_stack_vars_rtx);
      gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
      offset += INTVAL (XEXP (reg_save_area, 1));
    }
        else
    gcc_assert (reg_save_area == virtual_stack_vars_rtx);
      }

    cfun->machine->varargs_save_offset = offset;
    save_area = plus_constant (virtual_stack_vars_rtx, offset);
  }
    }
  else
    {
      first_reg_offset = next_cum.words;
      save_area = virtual_incoming_args_rtx;

      if (targetm.calls.must_pass_in_stack (mode, type))
  first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
    }

  set = get_varargs_alias_set ();
  if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
      && cfun->va_list_gpr_size)
    {
      int nregs = GP_ARG_NUM_REG - first_reg_offset;

      if (va_list_gpr_counter_field)
  {
    /* V4 va_list_gpr_size counts number of registers needed.  */
    if (nregs > cfun->va_list_gpr_size)
      nregs = cfun->va_list_gpr_size;
  }
      else
  {
    /* char * va_list instead counts number of bytes needed.  */
    if (nregs > cfun->va_list_gpr_size / reg_size)
      nregs = cfun->va_list_gpr_size / reg_size;
  }

      mem = gen_rtx_MEM (BLKmode,
       plus_constant (save_area,
          first_reg_offset * reg_size));
      MEM_NOTRAP_P (mem) = 1;
      set_mem_alias_set (mem, set);
      set_mem_align (mem, BITS_PER_WORD);

      rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
          nregs);
    }

  /* Save FP registers if needed.  */
  if (DEFAULT_ABI == ABI_V4
      && TARGET_HARD_FLOAT && TARGET_FPRS
      && ! no_rtl
      && next_cum.fregno <= FP_ARG_V4_MAX_REG
      && cfun->va_list_fpr_size)
    {
      int fregno = next_cum.fregno, nregs;
      rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
      rtx lab = gen_label_rtx ();
      int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
                 * UNITS_PER_FP_WORD);

      emit_jump_insn
  (gen_rtx_SET (VOIDmode,
          pc_rtx,
          gen_rtx_IF_THEN_ELSE (VOIDmode,
              gen_rtx_NE (VOIDmode, cr1,
              const0_rtx),
              gen_rtx_LABEL_REF (VOIDmode, lab),
              pc_rtx)));

      for (nregs = 0;
     fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
     fregno++, off += UNITS_PER_FP_WORD, nregs++)
  {
    mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
    MEM_NOTRAP_P (mem) = 1;
    set_mem_alias_set (mem, set);
    set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
    emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
  }

      emit_label (lab);
    }
}

/* Create the va_list data type.  */

static tree
rs6000_build_builtin_va_list (void)
{
  tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;

  /* For AIX, prefer 'char *' because that's what the system
     header files like.  */
  if (DEFAULT_ABI != ABI_V4)
    return build_pointer_type (char_type_node);

  record = (*lang_hooks.types.make_type) (RECORD_TYPE);
  type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);

  f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
          unsigned_char_type_node);
  f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
          unsigned_char_type_node);
  /* Give the two bytes of padding a name, so that -Wpadded won't warn on
     every user file.  */
  f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
          short_unsigned_type_node);
  f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
          ptr_type_node);
  f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
          ptr_type_node);

  va_list_gpr_counter_field = f_gpr;
  va_list_fpr_counter_field = f_fpr;

  DECL_FIELD_CONTEXT (f_gpr) = record;
  DECL_FIELD_CONTEXT (f_fpr) = record;
  DECL_FIELD_CONTEXT (f_res) = record;
  DECL_FIELD_CONTEXT (f_ovf) = record;
  DECL_FIELD_CONTEXT (f_sav) = record;

  TREE_CHAIN (record) = type_decl;
  TYPE_NAME (record) = type_decl;
  TYPE_FIELDS (record) = f_gpr;
  TREE_CHAIN (f_gpr) = f_fpr;
  TREE_CHAIN (f_fpr) = f_res;
  TREE_CHAIN (f_res) = f_ovf;
  TREE_CHAIN (f_ovf) = f_sav;

  layout_type (record);

  /* The correct type is an array type of one element.  */
  return build_array_type (record, build_index_type (size_zero_node));
}

/* Implement va_start.  */

void
rs6000_va_start (tree valist, rtx nextarg)
{
  HOST_WIDE_INT words, n_gpr, n_fpr;
  tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
  tree gpr, fpr, ovf, sav, t;

  /* Only SVR4 needs something special.  */
  if (DEFAULT_ABI != ABI_V4)
    {
      std_expand_builtin_va_start (valist, nextarg);
      return;
    }

  f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
  f_fpr = TREE_CHAIN (f_gpr);
  f_res = TREE_CHAIN (f_fpr);
  f_ovf = TREE_CHAIN (f_res);
  f_sav = TREE_CHAIN (f_ovf);

  valist = build_va_arg_indirect_ref (valist);
  gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
  fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
  ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
  sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);

  /* Count number of gp and fp argument registers used.  */
  words = current_function_args_info.words;
  n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
         GP_ARG_NUM_REG);
  n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
         FP_ARG_NUM_REG);

  if (TARGET_DEBUG_ARG)
    fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
       HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
       words, n_gpr, n_fpr);

  if (cfun->va_list_gpr_size)
    {
      t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
      build_int_cst (NULL_TREE, n_gpr));
      TREE_SIDE_EFFECTS (t) = 1;
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
    }

  if (cfun->va_list_fpr_size)
    {
      t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
      build_int_cst (NULL_TREE, n_fpr));
      TREE_SIDE_EFFECTS (t) = 1;
      expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
    }

  /* Find the overflow area.  */
  t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
  if (words != 0)
    t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
          build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
  t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
  TREE_SIDE_EFFECTS (t) = 1;
  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);

  /* If there were no va_arg invocations, don't set up the register
     save area.  */
  if (!cfun->va_list_gpr_size
      && !cfun->va_list_fpr_size
      && n_gpr < GP_ARG_NUM_REG
      && n_fpr < FP_ARG_V4_MAX_REG)
    return;

  /* Find the register save area.  */
  t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
  if (cfun->machine->varargs_save_offset)
    t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
          build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
  t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
  TREE_SIDE_EFFECTS (t) = 1;
  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}

/* Implement va_arg.  */

tree
rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
{
  tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
  tree gpr, fpr, ovf, sav, reg, t, u;
  int size, rsize, n_reg, sav_ofs, sav_scale;
  tree lab_false, lab_over, addr;
  int align;
  tree ptrtype = build_pointer_type (type);

  if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
    {
      t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
      return build_va_arg_indirect_ref (t);
    }

  if (DEFAULT_ABI != ABI_V4)
    {
      if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
  {
    tree elem_type = TREE_TYPE (type);
    enum machine_mode elem_mode = TYPE_MODE (elem_type);
    int elem_size = GET_MODE_SIZE (elem_mode);

    if (elem_size < UNITS_PER_WORD)
      {
        tree real_part, imag_part;
        tree post = NULL_TREE;

        real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
              &post);
        /* Copy the value into a temporary, lest the formal temporary
     be reused out from under us.  */
        real_part = get_initialized_tmp_var (real_part, pre_p, &post);
        append_to_statement_list (post, pre_p);

        imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
              post_p);

        return build2 (COMPLEX_EXPR, type, real_part, imag_part);
      }
  }

      return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
    }

  f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
  f_fpr = TREE_CHAIN (f_gpr);
  f_res = TREE_CHAIN (f_fpr);
  f_ovf = TREE_CHAIN (f_res);
  f_sav = TREE_CHAIN (f_ovf);

  valist = build_va_arg_indirect_ref (valist);
  gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
  fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
  ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
  sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);

  size = int_size_in_bytes (type);
  rsize = (size + 3) / 4;
  align = 1;

  if (TARGET_HARD_FLOAT && TARGET_FPRS
      && (TYPE_MODE (type) == SFmode
    || TYPE_MODE (type) == DFmode
    || TYPE_MODE (type) == TFmode))
    {
      /* FP args go in FP registers, if present.  */
      reg = fpr;
      n_reg = (size + 7) / 8;
      sav_ofs = 8*4;
      sav_scale = 8;
      if (TYPE_MODE (type) != SFmode)
  align = 8;
    }
  else
    {
      /* Otherwise into GP registers.  */
      reg = gpr;
      n_reg = rsize;
      sav_ofs = 0;
      sav_scale = 4;
      if (n_reg == 2)
  align = 8;
    }

  /* Pull the value out of the saved registers....  */

  lab_over = NULL;
  addr = create_tmp_var (ptr_type_node, "addr");
  DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();

  /*  AltiVec vectors never go in registers when -mabi=altivec.  */
  if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
    align = 16;
  else
    {
      lab_false = create_artificial_label ();
      lab_over = create_artificial_label ();

      /* Long long and SPE vectors are aligned in the registers.
   As are any other 2 gpr item such as complex int due to a
   historical mistake.  */
      u = reg;
      if (n_reg == 2 && reg == gpr)
  {
    u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
         size_int (n_reg - 1));
    u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
  }

      t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
      t = build2 (GE_EXPR, boolean_type_node, u, t);
      u = build1 (GOTO_EXPR, void_type_node, lab_false);
      t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
      gimplify_and_add (t, pre_p);

      t = sav;
      if (sav_ofs)
  t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));

      u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
      u = build1 (CONVERT_EXPR, integer_type_node, u);
      u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
      t = build2 (PLUS_EXPR, ptr_type_node, t, u);

      t = build2 (MODIFY_EXPR, void_type_node, addr, t);
      gimplify_and_add (t, pre_p);

      t = build1 (GOTO_EXPR, void_type_node, lab_over);
      gimplify_and_add (t, pre_p);

      t = build1 (LABEL_EXPR, void_type_node, lab_false);
      append_to_statement_list (t, pre_p);

      if ((n_reg == 2 && reg != gpr) || n_reg > 2)
  {
    /* Ensure that we don't find any more args in regs.
       Alignment has taken care of the n_reg == 2 gpr case.  */
    t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
    gimplify_and_add (t, pre_p);
  }
    }

  /* ... otherwise out of the overflow area.  */

  /* Care for on-stack alignment if needed.  */
  t = ovf;
  if (align != 1)
    {
      t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
      t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
      build_int_cst (NULL_TREE, -align));
    }
  gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);

  u = build2 (MODIFY_EXPR, void_type_node, addr, t);
  gimplify_and_add (u, pre_p);

  t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
  t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
  gimplify_and_add (t, pre_p);

  if (lab_over)
    {
      t = build1 (LABEL_EXPR, void_type_node, lab_over);
      append_to_statement_list (t, pre_p);
    }

  if (STRICT_ALIGNMENT
      && (TYPE_ALIGN (type)
    > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
    {
      /* The value (of type complex double, for example) may not be
   aligned in memory in the saved registers, so copy via a
   temporary.  (This is the same code as used for SPARC.)  */
      tree tmp = create_tmp_var (type, "va_arg_tmp");
      tree dest_addr = build_fold_addr_expr (tmp);

      tree copy = build_function_call_expr
  (implicit_built_in_decls[BUILT_IN_MEMCPY],
   tree_cons (NULL_TREE, dest_addr,
        tree_cons (NULL_TREE, addr,
             tree_cons (NULL_TREE, size_int (rsize * 4),
            NULL_TREE))));

      gimplify_and_add (copy, pre_p);
      addr = dest_addr;
    }

  addr = fold_convert (ptrtype, addr);
  return build_va_arg_indirect_ref (addr);
}

/* Builtins.  */

static void
def_builtin (int mask, const char *name, tree type, int code)
{
  if (mask & target_flags)
    {
      if (rs6000_builtin_decls[code])
  abort ();

      rs6000_builtin_decls[code] =
        lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
             NULL, NULL_TREE);
    }
}

/* Simple ternary operations: VECd = foo (VECa, VECb, VECc).  */

static const struct builtin_description bdesc_3arg[] =
{
  { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },

  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
};

/* DST operations: void foo (void *, const int, const char).  */

static const struct builtin_description bdesc_dst[] =
{
  { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
  { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
  { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
  { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },

  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
};

/* Simple binary operations: VECc = foo (VECa, VECb).  */

static struct builtin_description bdesc_2arg[] =
{
  { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
  { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
  { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
  { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
  { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
  { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
  { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
  { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
  { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
  { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
  { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
  { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
  { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
  { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
  { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
  { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
  { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
  { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
  { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
  { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
  { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
  { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
  { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
  { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
  { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
  { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
  { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
  { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
  { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
  { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
  { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
  { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
  { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
  { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
  { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
  { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
  { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
  { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },

  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
  { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro",