Open64: osprey/be/cg/NVISA/vector_loadstore.cxx Source File

00001 /*
00002  *  Copyright 2005-2008 NVIDIA Corporation.  All rights reserved.
00003  *
00004  *  This program is free software; you can redistribute it and/or modify it
00005  *  under the terms of version 2 of the GNU General Public License as
00006  *  published by the Free Software Foundation.
00007  *
00008  *  This program is distributed in the hope that it would be useful, but
00009  *  WITHOUT ANY WARRANTY; without even the implied warranty of
00010  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
00011  *
00012  *  Further, this software is distributed without any warranty that it is
00013  *  free of the rightful claim of any third person regarding infringement
00014  *  or the like.  Any license provided herein, whether implied or
00015  *  otherwise, applies only to this software file.  Patent licenses, if
00016  *  any, provided herein do not apply to combinations of this program with
00017  *  other software, or any other product whatsoever.
00018  *
00019  *  You should have received a copy of the GNU General Public License along
00020  *  with this program; if not, write the Free Software Foundation, Inc., 59
00021  *  Temple Place - Suite 330, Boston MA 02111-1307, USA.
00022  */
00023 // Merge contiguous global memory accesses into vector accesses.
00024 // We only merge accesses within a BB.
00025 // To handle multiple interleaved accesses,
00026 // we keep a dynamic list of vectors we are working on.
00027 
00028 #include <list>
00029 #include <map>
00030 #include "defs.h"
00031 #include "tracing.h"
00032 #include "mempool.h"
00033 #include "bb.h"
00034 #include "op.h"
00035 #include "tn.h"
00036 #include "vector_loadstore.h"
00037 #include "whirl2ops.h"
00038 
00039 static BOOL tracing = FALSE;
00040 static INT num_vectors = 0;
00041 static std::map<TOP, TOP> V2InstructionMap;
00042 static std::map<TOP, TOP> V4InstructionMap;
00043 
00044 static void Create_VInstruction_Maps(void)
00045 {
00046   V2InstructionMap[TOP_ld_qualifier_space_s8_r] = TOP_ld_qualifier_global_v2_s8_r;
00047   V2InstructionMap[TOP_ld_qualifier_space_u8_r] = TOP_ld_qualifier_global_v2_u8_r;
00048   V2InstructionMap[TOP_ld_qualifier_space_s8_b32_r] = TOP_ld_qualifier_global_v2_s8_b32_r;
00049   V2InstructionMap[TOP_ld_qualifier_space_u8_b32_r] = TOP_ld_qualifier_global_v2_u8_b32_r;
00050   V2InstructionMap[TOP_ld_qualifier_space_s16_r] = TOP_ld_qualifier_global_v2_s16_r;
00051   V2InstructionMap[TOP_ld_qualifier_space_u16_r] = TOP_ld_qualifier_global_v2_u16_r;
00052   V2InstructionMap[TOP_ld_qualifier_space_s16_b32_r] = TOP_ld_qualifier_global_v2_s16_b32_r;
00053   V2InstructionMap[TOP_ld_qualifier_space_u16_b32_r] = TOP_ld_qualifier_global_v2_u16_b32_r;
00054   V2InstructionMap[TOP_ld_qualifier_space_s32_r] = TOP_ld_qualifier_global_v2_s32_r;
00055   V2InstructionMap[TOP_ld_qualifier_space_u32_r] = TOP_ld_qualifier_global_v2_u32_r;
00056   V2InstructionMap[TOP_ld_qualifier_space_s64_r] = TOP_ld_qualifier_global_v2_s64_r;
00057   V2InstructionMap[TOP_ld_qualifier_space_u64_r] = TOP_ld_qualifier_global_v2_u64_r;
00058   V2InstructionMap[TOP_ld_qualifier_space_f32_r] = TOP_ld_qualifier_global_v2_f32_r;
00059   V2InstructionMap[TOP_ld_qualifier_space_f64_r] = TOP_ld_qualifier_global_v2_f64_r;
00060   V2InstructionMap[TOP_st_qualifier_space_s8_r] = TOP_st_qualifier_global_v2_s8_r;
00061   V2InstructionMap[TOP_st_qualifier_space_u8_r] = TOP_st_qualifier_global_v2_u8_r;
00062   V2InstructionMap[TOP_st_qualifier_space_s8_b32_r] = TOP_st_qualifier_global_v2_s8_b32_r;
00063   V2InstructionMap[TOP_st_qualifier_space_u8_b32_r] = TOP_st_qualifier_global_v2_u8_b32_r;
00064   V2InstructionMap[TOP_st_qualifier_space_s16_r] = TOP_st_qualifier_global_v2_s16_r;
00065   V2InstructionMap[TOP_st_qualifier_space_u16_r] = TOP_st_qualifier_global_v2_u16_r;
00066   V2InstructionMap[TOP_st_qualifier_space_s16_b32_r] = TOP_st_qualifier_global_v2_s16_b32_r;
00067   V2InstructionMap[TOP_st_qualifier_space_u16_b32_r] = TOP_st_qualifier_global_v2_u16_b32_r;
00068   V2InstructionMap[TOP_st_qualifier_space_s32_r] = TOP_st_qualifier_global_v2_s32_r;
00069   V2InstructionMap[TOP_st_qualifier_space_u32_r] = TOP_st_qualifier_global_v2_u32_r;
00070   V2InstructionMap[TOP_st_qualifier_space_s64_r] = TOP_st_qualifier_global_v2_s64_r;
00071   V2InstructionMap[TOP_st_qualifier_space_u64_r] = TOP_st_qualifier_global_v2_u64_r;
00072   V2InstructionMap[TOP_st_qualifier_space_f32_r] = TOP_st_qualifier_global_v2_f32_r;
00073   V2InstructionMap[TOP_st_qualifier_space_f64_r] = TOP_st_qualifier_global_v2_f64_r;
00074   V2InstructionMap[TOP_ld_qualifier_space_s8_a64_r] = TOP_ld_qualifier_global_v2_s8_a64_r;
00075   V2InstructionMap[TOP_ld_qualifier_space_u8_a64_r] = TOP_ld_qualifier_global_v2_u8_a64_r;
00076   V2InstructionMap[TOP_ld_qualifier_space_s8_b32_a64_r] = TOP_ld_qualifier_global_v2_s8_b32_a64_r;
00077   V2InstructionMap[TOP_ld_qualifier_space_u8_b32_a64_r] = TOP_ld_qualifier_global_v2_u8_b32_a64_r;
00078   V2InstructionMap[TOP_ld_qualifier_space_s16_a64_r] = TOP_ld_qualifier_global_v2_s16_a64_r;
00079   V2InstructionMap[TOP_ld_qualifier_space_u16_a64_r] = TOP_ld_qualifier_global_v2_u16_a64_r;
00080   V2InstructionMap[TOP_ld_qualifier_space_s16_b32_a64_r] = TOP_ld_qualifier_global_v2_s16_b32_a64_r;
00081   V2InstructionMap[TOP_ld_qualifier_space_u16_b32_a64_r] = TOP_ld_qualifier_global_v2_u16_b32_a64_r;
00082   V2InstructionMap[TOP_ld_qualifier_space_s32_a64_r] = TOP_ld_qualifier_global_v2_s32_a64_r;
00083   V2InstructionMap[TOP_ld_qualifier_space_u32_a64_r] = TOP_ld_qualifier_global_v2_u32_a64_r;
00084   V2InstructionMap[TOP_ld_qualifier_space_s64_a64_r] = TOP_ld_qualifier_global_v2_s64_a64_r;
00085   V2InstructionMap[TOP_ld_qualifier_space_u64_a64_r] = TOP_ld_qualifier_global_v2_u64_a64_r;
00086   V2InstructionMap[TOP_ld_qualifier_space_f32_a64_r] = TOP_ld_qualifier_global_v2_f32_a64_r;
00087   V2InstructionMap[TOP_ld_qualifier_space_f64_a64_r] = TOP_ld_qualifier_global_v2_f64_a64_r;
00088   V2InstructionMap[TOP_st_qualifier_space_s8_a64_r] = TOP_st_qualifier_global_v2_s8_a64_r;
00089   V2InstructionMap[TOP_st_qualifier_space_u8_a64_r] = TOP_st_qualifier_global_v2_u8_a64_r;
00090   V2InstructionMap[TOP_st_qualifier_space_s8_b32_a64_r] = TOP_st_qualifier_global_v2_s8_b32_a64_r;
00091   V2InstructionMap[TOP_st_qualifier_space_u8_b32_a64_r] = TOP_st_qualifier_global_v2_u8_b32_a64_r;
00092   V2InstructionMap[TOP_st_qualifier_space_s16_a64_r] = TOP_st_qualifier_global_v2_s16_a64_r;
00093   V2InstructionMap[TOP_st_qualifier_space_u16_a64_r] = TOP_st_qualifier_global_v2_u16_a64_r;
00094   V2InstructionMap[TOP_st_qualifier_space_s16_b32_a64_r] = TOP_st_qualifier_global_v2_s16_b32_a64_r;
00095   V2InstructionMap[TOP_st_qualifier_space_u16_b32_a64_r] = TOP_st_qualifier_global_v2_u16_b32_a64_r;
00096   V2InstructionMap[TOP_st_qualifier_space_s32_a64_r] = TOP_st_qualifier_global_v2_s32_a64_r;
00097   V2InstructionMap[TOP_st_qualifier_space_u32_a64_r] = TOP_st_qualifier_global_v2_u32_a64_r;
00098   V2InstructionMap[TOP_st_qualifier_space_s64_a64_r] = TOP_st_qualifier_global_v2_s64_a64_r;
00099   V2InstructionMap[TOP_st_qualifier_space_u64_a64_r] = TOP_st_qualifier_global_v2_u64_a64_r;
00100   V2InstructionMap[TOP_st_qualifier_space_f32_a64_r] = TOP_st_qualifier_global_v2_f32_a64_r;
00101   V2InstructionMap[TOP_st_qualifier_space_f64_a64_r] = TOP_st_qualifier_global_v2_f64_a64_r;
00102   V2InstructionMap[TOP_ld_qualifier_space_s8_o] = TOP_ld_qualifier_global_v2_s8_o;
00103   V2InstructionMap[TOP_ld_qualifier_space_u8_o] = TOP_ld_qualifier_global_v2_u8_o;
00104   V2InstructionMap[TOP_ld_qualifier_space_s8_b32_o] = TOP_ld_qualifier_global_v2_s8_b32_o;
00105   V2InstructionMap[TOP_ld_qualifier_space_u8_b32_o] = TOP_ld_qualifier_global_v2_u8_b32_o;
00106   V2InstructionMap[TOP_ld_qualifier_space_s16_o] = TOP_ld_qualifier_global_v2_s16_o;
00107   V2InstructionMap[TOP_ld_qualifier_space_u16_o] = TOP_ld_qualifier_global_v2_u16_o;
00108   V2InstructionMap[TOP_ld_qualifier_space_s16_b32_o] = TOP_ld_qualifier_global_v2_s16_b32_o;
00109   V2InstructionMap[TOP_ld_qualifier_space_u16_b32_o] = TOP_ld_qualifier_global_v2_u16_b32_o;
00110   V2InstructionMap[TOP_ld_qualifier_space_s32_o] = TOP_ld_qualifier_global_v2_s32_o;
00111   V2InstructionMap[TOP_ld_qualifier_space_u32_o] = TOP_ld_qualifier_global_v2_u32_o;
00112   V2InstructionMap[TOP_ld_qualifier_space_s64_o] = TOP_ld_qualifier_global_v2_s64_o;
00113   V2InstructionMap[TOP_ld_qualifier_space_u64_o] = TOP_ld_qualifier_global_v2_u64_o;
00114   V2InstructionMap[TOP_ld_qualifier_space_f32_o] = TOP_ld_qualifier_global_v2_f32_o;
00115   V2InstructionMap[TOP_ld_qualifier_space_f64_o] = TOP_ld_qualifier_global_v2_f64_o;
00116   V2InstructionMap[TOP_st_qualifier_space_s8_o] = TOP_st_qualifier_global_v2_s8_o;
00117   V2InstructionMap[TOP_st_qualifier_space_u8_o] = TOP_st_qualifier_global_v2_u8_o;
00118   V2InstructionMap[TOP_st_qualifier_space_s8_b32_o] = TOP_st_qualifier_global_v2_s8_b32_o;
00119   V2InstructionMap[TOP_st_qualifier_space_u8_b32_o] = TOP_st_qualifier_global_v2_u8_b32_o;
00120   V2InstructionMap[TOP_st_qualifier_space_s16_o] = TOP_st_qualifier_global_v2_s16_o;
00121   V2InstructionMap[TOP_st_qualifier_space_u16_o] = TOP_st_qualifier_global_v2_u16_o;
00122   V2InstructionMap[TOP_st_qualifier_space_s16_b32_o] = TOP_st_qualifier_global_v2_s16_b32_o;
00123   V2InstructionMap[TOP_st_qualifier_space_u16_b32_o] = TOP_st_qualifier_global_v2_u16_b32_o;
00124   V2InstructionMap[TOP_st_qualifier_space_s32_o] = TOP_st_qualifier_global_v2_s32_o;
00125   V2InstructionMap[TOP_st_qualifier_space_u32_o] = TOP_st_qualifier_global_v2_u32_o;
00126   V2InstructionMap[TOP_st_qualifier_space_s64_o] = TOP_st_qualifier_global_v2_s64_o;
00127   V2InstructionMap[TOP_st_qualifier_space_u64_o] = TOP_st_qualifier_global_v2_u64_o;
00128   V2InstructionMap[TOP_st_qualifier_space_f32_o] = TOP_st_qualifier_global_v2_f32_o;
00129   V2InstructionMap[TOP_st_qualifier_space_f64_o] = TOP_st_qualifier_global_v2_f64_o;
00130   V2InstructionMap[TOP_ld_qualifier_space_s8_a64_o] = TOP_ld_qualifier_global_v2_s8_a64_o;
00131   V2InstructionMap[TOP_ld_qualifier_space_u8_a64_o] = TOP_ld_qualifier_global_v2_u8_a64_o;
00132   V2InstructionMap[TOP_ld_qualifier_space_s8_b32_a64_o] = TOP_ld_qualifier_global_v2_s8_b32_a64_o;
00133   V2InstructionMap[TOP_ld_qualifier_space_u8_b32_a64_o] = TOP_ld_qualifier_global_v2_u8_b32_a64_o;
00134   V2InstructionMap[TOP_ld_qualifier_space_s16_a64_o] = TOP_ld_qualifier_global_v2_s16_a64_o;
00135   V2InstructionMap[TOP_ld_qualifier_space_u16_a64_o] = TOP_ld_qualifier_global_v2_u16_a64_o;
00136   V2InstructionMap[TOP_ld_qualifier_space_s16_b32_a64_o] = TOP_ld_qualifier_global_v2_s16_b32_a64_o;
00137   V2InstructionMap[TOP_ld_qualifier_space_u16_b32_a64_o] = TOP_ld_qualifier_global_v2_u16_b32_a64_o;
00138   V2InstructionMap[TOP_ld_qualifier_space_s32_a64_o] = TOP_ld_qualifier_global_v2_s32_a64_o;
00139   V2InstructionMap[TOP_ld_qualifier_space_u32_a64_o] = TOP_ld_qualifier_global_v2_u32_a64_o;
00140   V2InstructionMap[TOP_ld_qualifier_space_s64_a64_o] = TOP_ld_qualifier_global_v2_s64_a64_o;
00141   V2InstructionMap[TOP_ld_qualifier_space_u64_a64_o] = TOP_ld_qualifier_global_v2_u64_a64_o;
00142   V2InstructionMap[TOP_ld_qualifier_space_f32_a64_o] = TOP_ld_qualifier_global_v2_f32_a64_o;
00143   V2InstructionMap[TOP_ld_qualifier_space_f64_a64_o] = TOP_ld_qualifier_global_v2_f64_a64_o;
00144   V2InstructionMap[TOP_st_qualifier_space_s8_a64_o] = TOP_st_qualifier_global_v2_s8_a64_o;
00145   V2InstructionMap[TOP_st_qualifier_space_u8_a64_o] = TOP_st_qualifier_global_v2_u8_a64_o;
00146   V2InstructionMap[TOP_st_qualifier_space_s8_b32_a64_o] = TOP_st_qualifier_global_v2_s8_b32_a64_o;
00147   V2InstructionMap[TOP_st_qualifier_space_u8_b32_a64_o] = TOP_st_qualifier_global_v2_u8_b32_a64_o;
00148   V2InstructionMap[TOP_st_qualifier_space_s16_a64_o] = TOP_st_qualifier_global_v2_s16_a64_o;
00149   V2InstructionMap[TOP_st_qualifier_space_u16_a64_o] = TOP_st_qualifier_global_v2_u16_a64_o;
00150   V2InstructionMap[TOP_st_qualifier_space_s16_b32_a64_o] = TOP_st_qualifier_global_v2_s16_b32_a64_o;
00151   V2InstructionMap[TOP_st_qualifier_space_u16_b32_a64_o] = TOP_st_qualifier_global_v2_u16_b32_a64_o;
00152   V2InstructionMap[TOP_st_qualifier_space_s32_a64_o] = TOP_st_qualifier_global_v2_s32_a64_o;
00153   V2InstructionMap[TOP_st_qualifier_space_u32_a64_o] = TOP_st_qualifier_global_v2_u32_a64_o;
00154   V2InstructionMap[TOP_st_qualifier_space_s64_a64_o] = TOP_st_qualifier_global_v2_s64_a64_o;
00155   V2InstructionMap[TOP_st_qualifier_space_u64_a64_o] = TOP_st_qualifier_global_v2_u64_a64_o;
00156   V2InstructionMap[TOP_st_qualifier_space_f32_a64_o] = TOP_st_qualifier_global_v2_f32_a64_o;
00157   V2InstructionMap[TOP_st_qualifier_space_f64_a64_o] = TOP_st_qualifier_global_v2_f64_a64_o;
00158 
00159   V4InstructionMap[TOP_ld_qualifier_space_s8_r] = TOP_ld_qualifier_global_v4_s8_r;
00160   V4InstructionMap[TOP_ld_qualifier_space_u8_r] = TOP_ld_qualifier_global_v4_u8_r;
00161   V4InstructionMap[TOP_ld_qualifier_space_s8_b32_r] = TOP_ld_qualifier_global_v4_s8_b32_r;
00162   V4InstructionMap[TOP_ld_qualifier_space_u8_b32_r] = TOP_ld_qualifier_global_v4_u8_b32_r;
00163   V4InstructionMap[TOP_ld_qualifier_space_s16_r] = TOP_ld_qualifier_global_v4_s16_r;
00164   V4InstructionMap[TOP_ld_qualifier_space_u16_r] = TOP_ld_qualifier_global_v4_u16_r;
00165   V4InstructionMap[TOP_ld_qualifier_space_s16_b32_r] = TOP_ld_qualifier_global_v4_s16_b32_r;
00166   V4InstructionMap[TOP_ld_qualifier_space_u16_b32_r] = TOP_ld_qualifier_global_v4_u16_b32_r;
00167   V4InstructionMap[TOP_ld_qualifier_space_s32_r] = TOP_ld_qualifier_global_v4_s32_r;
00168   V4InstructionMap[TOP_ld_qualifier_space_u32_r] = TOP_ld_qualifier_global_v4_u32_r;
00169   V4InstructionMap[TOP_ld_qualifier_space_f32_r] = TOP_ld_qualifier_global_v4_f32_r;
00170   V4InstructionMap[TOP_st_qualifier_space_s8_r] = TOP_st_qualifier_global_v4_s8_r;
00171   V4InstructionMap[TOP_st_qualifier_space_u8_r] = TOP_st_qualifier_global_v4_u8_r;
00172   V4InstructionMap[TOP_st_qualifier_space_s8_b32_r] = TOP_st_qualifier_global_v4_s8_b32_r;
00173   V4InstructionMap[TOP_st_qualifier_space_u8_b32_r] = TOP_st_qualifier_global_v4_u8_b32_r;
00174   V4InstructionMap[TOP_st_qualifier_space_s16_r] = TOP_st_qualifier_global_v4_s16_r;
00175   V4InstructionMap[TOP_st_qualifier_space_u16_r] = TOP_st_qualifier_global_v4_u16_r;
00176   V4InstructionMap[TOP_st_qualifier_space_s16_b32_r] = TOP_st_qualifier_global_v4_s16_b32_r;
00177   V4InstructionMap[TOP_st_qualifier_space_u16_b32_r] = TOP_st_qualifier_global_v4_u16_b32_r;
00178   V4InstructionMap[TOP_st_qualifier_space_s32_r] = TOP_st_qualifier_global_v4_s32_r;
00179   V4InstructionMap[TOP_st_qualifier_space_u32_r] = TOP_st_qualifier_global_v4_u32_r;
00180   V4InstructionMap[TOP_st_qualifier_space_f32_r] = TOP_st_qualifier_global_v4_f32_r;
00181   V4InstructionMap[TOP_ld_qualifier_space_s8_a64_r] = TOP_ld_qualifier_global_v4_s8_a64_r;
00182   V4InstructionMap[TOP_ld_qualifier_space_u8_a64_r] = TOP_ld_qualifier_global_v4_u8_a64_r;
00183   V4InstructionMap[TOP_ld_qualifier_space_s8_b32_a64_r] = TOP_ld_qualifier_global_v4_s8_b32_a64_r;
00184   V4InstructionMap[TOP_ld_qualifier_space_u8_b32_a64_r] = TOP_ld_qualifier_global_v4_u8_b32_a64_r;
00185   V4InstructionMap[TOP_ld_qualifier_space_s16_a64_r] = TOP_ld_qualifier_global_v4_s16_a64_r;
00186   V4InstructionMap[TOP_ld_qualifier_space_u16_a64_r] = TOP_ld_qualifier_global_v4_u16_a64_r;
00187   V4InstructionMap[TOP_ld_qualifier_space_s16_b32_a64_r] = TOP_ld_qualifier_global_v4_s16_b32_a64_r;
00188   V4InstructionMap[TOP_ld_qualifier_space_u16_b32_a64_r] = TOP_ld_qualifier_global_v4_u16_b32_a64_r;
00189   V4InstructionMap[TOP_ld_qualifier_space_s32_a64_r] = TOP_ld_qualifier_global_v4_s32_a64_r;
00190   V4InstructionMap[TOP_ld_qualifier_space_u32_a64_r] = TOP_ld_qualifier_global_v4_u32_a64_r;
00191   V4InstructionMap[TOP_ld_qualifier_space_f32_a64_r] = TOP_ld_qualifier_global_v4_f32_a64_r;
00192   V4InstructionMap[TOP_st_qualifier_space_s8_a64_r] = TOP_st_qualifier_global_v4_s8_a64_r;
00193   V4InstructionMap[TOP_st_qualifier_space_u8_a64_r] = TOP_st_qualifier_global_v4_u8_a64_r;
00194   V4InstructionMap[TOP_st_qualifier_space_s8_b32_a64_r] = TOP_st_qualifier_global_v4_s8_b32_a64_r;
00195   V4InstructionMap[TOP_st_qualifier_space_u8_b32_a64_r] = TOP_st_qualifier_global_v4_u8_b32_a64_r;
00196   V4InstructionMap[TOP_st_qualifier_space_s16_a64_r] = TOP_st_qualifier_global_v4_s16_a64_r;
00197   V4InstructionMap[TOP_st_qualifier_space_u16_a64_r] = TOP_st_qualifier_global_v4_u16_a64_r;
00198   V4InstructionMap[TOP_st_qualifier_space_s16_b32_a64_r] = TOP_st_qualifier_global_v4_s16_b32_a64_r;
00199   V4InstructionMap[TOP_st_qualifier_space_u16_b32_a64_r] = TOP_st_qualifier_global_v4_u16_b32_a64_r;
00200   V4InstructionMap[TOP_st_qualifier_space_s32_a64_r] = TOP_st_qualifier_global_v4_s32_a64_r;
00201   V4InstructionMap[TOP_st_qualifier_space_u32_a64_r] = TOP_st_qualifier_global_v4_u32_a64_r;
00202   V4InstructionMap[TOP_st_qualifier_space_f32_a64_r] = TOP_st_qualifier_global_v4_f32_a64_r;
00203   V4InstructionMap[TOP_ld_qualifier_space_s8_o] = TOP_ld_qualifier_global_v4_s8_o;
00204   V4InstructionMap[TOP_ld_qualifier_space_u8_o] = TOP_ld_qualifier_global_v4_u8_o;
00205   V4InstructionMap[TOP_ld_qualifier_space_s8_b32_o] = TOP_ld_qualifier_global_v4_s8_b32_o;
00206   V4InstructionMap[TOP_ld_qualifier_space_u8_b32_o] = TOP_ld_qualifier_global_v4_u8_b32_o;
00207   V4InstructionMap[TOP_ld_qualifier_space_s16_o] = TOP_ld_qualifier_global_v4_s16_o;
00208   V4InstructionMap[TOP_ld_qualifier_space_u16_o] = TOP_ld_qualifier_global_v4_u16_o;
00209   V4InstructionMap[TOP_ld_qualifier_space_s16_b32_o] = TOP_ld_qualifier_global_v4_s16_b32_o;
00210   V4InstructionMap[TOP_ld_qualifier_space_u16_b32_o] = TOP_ld_qualifier_global_v4_u16_b32_o;
00211   V4InstructionMap[TOP_ld_qualifier_space_s32_o] = TOP_ld_qualifier_global_v4_s32_o;
00212   V4InstructionMap[TOP_ld_qualifier_space_u32_o] = TOP_ld_qualifier_global_v4_u32_o;
00213   V4InstructionMap[TOP_ld_qualifier_space_f32_o] = TOP_ld_qualifier_global_v4_f32_o;
00214   V4InstructionMap[TOP_st_qualifier_space_s8_o] = TOP_st_qualifier_global_v4_s8_o;
00215   V4InstructionMap[TOP_st_qualifier_space_u8_o] = TOP_st_qualifier_global_v4_u8_o;
00216   V4InstructionMap[TOP_st_qualifier_space_s8_b32_o] = TOP_st_qualifier_global_v4_s8_b32_o;
00217   V4InstructionMap[TOP_st_qualifier_space_u8_b32_o] = TOP_st_qualifier_global_v4_u8_b32_o;
00218   V4InstructionMap[TOP_st_qualifier_space_s16_o] = TOP_st_qualifier_global_v4_s16_o;
00219   V4InstructionMap[TOP_st_qualifier_space_u16_o] = TOP_st_qualifier_global_v4_u16_o;
00220   V4InstructionMap[TOP_st_qualifier_space_s16_b32_o] = TOP_st_qualifier_global_v4_s16_b32_o;
00221   V4InstructionMap[TOP_st_qualifier_space_u16_b32_o] = TOP_st_qualifier_global_v4_u16_b32_o;
00222   V4InstructionMap[TOP_st_qualifier_space_s32_o] = TOP_st_qualifier_global_v4_s32_o;
00223   V4InstructionMap[TOP_st_qualifier_space_u32_o] = TOP_st_qualifier_global_v4_u32_o;
00224   V4InstructionMap[TOP_st_qualifier_space_f32_o] = TOP_st_qualifier_global_v4_f32_o;
00225   V4InstructionMap[TOP_ld_qualifier_space_s8_a64_o] = TOP_ld_qualifier_global_v4_s8_a64_o;
00226   V4InstructionMap[TOP_ld_qualifier_space_u8_a64_o] = TOP_ld_qualifier_global_v4_u8_a64_o;
00227   V4InstructionMap[TOP_ld_qualifier_space_s8_b32_a64_o] = TOP_ld_qualifier_global_v4_s8_b32_a64_o;
00228   V4InstructionMap[TOP_ld_qualifier_space_u8_b32_a64_o] = TOP_ld_qualifier_global_v4_u8_b32_a64_o;
00229   V4InstructionMap[TOP_ld_qualifier_space_s16_a64_o] = TOP_ld_qualifier_global_v4_s16_a64_o;
00230   V4InstructionMap[TOP_ld_qualifier_space_u16_a64_o] = TOP_ld_qualifier_global_v4_u16_a64_o;
00231   V4InstructionMap[TOP_ld_qualifier_space_s16_b32_a64_o] = TOP_ld_qualifier_global_v4_s16_b32_a64_o;
00232   V4InstructionMap[TOP_ld_qualifier_space_u16_b32_a64_o] = TOP_ld_qualifier_global_v4_u16_b32_a64_o;
00233   V4InstructionMap[TOP_ld_qualifier_space_s32_a64_o] = TOP_ld_qualifier_global_v4_s32_a64_o;
00234   V4InstructionMap[TOP_ld_qualifier_space_u32_a64_o] = TOP_ld_qualifier_global_v4_u32_a64_o;
00235   V4InstructionMap[TOP_ld_qualifier_space_f32_a64_o] = TOP_ld_qualifier_global_v4_f32_a64_o;
00236   V4InstructionMap[TOP_st_qualifier_space_s8_a64_o] = TOP_st_qualifier_global_v4_s8_a64_o;
00237   V4InstructionMap[TOP_st_qualifier_space_u8_a64_o] = TOP_st_qualifier_global_v4_u8_a64_o;
00238   V4InstructionMap[TOP_st_qualifier_space_s8_b32_a64_o] = TOP_st_qualifier_global_v4_s8_b32_a64_o;
00239   V4InstructionMap[TOP_st_qualifier_space_u8_b32_a64_o] = TOP_st_qualifier_global_v4_u8_b32_a64_o;
00240   V4InstructionMap[TOP_st_qualifier_space_s16_a64_o] = TOP_st_qualifier_global_v4_s16_a64_o;
00241   V4InstructionMap[TOP_st_qualifier_space_u16_a64_o] = TOP_st_qualifier_global_v4_u16_a64_o;
00242   V4InstructionMap[TOP_st_qualifier_space_s16_b32_a64_o] = TOP_st_qualifier_global_v4_s16_b32_a64_o;
00243   V4InstructionMap[TOP_st_qualifier_space_u16_b32_a64_o] = TOP_st_qualifier_global_v4_u16_b32_a64_o;
00244   V4InstructionMap[TOP_st_qualifier_space_s32_a64_o] = TOP_st_qualifier_global_v4_s32_a64_o;
00245   V4InstructionMap[TOP_st_qualifier_space_u32_a64_o] = TOP_st_qualifier_global_v4_u32_a64_o;
00246   V4InstructionMap[TOP_st_qualifier_space_f32_a64_o] = TOP_st_qualifier_global_v4_f32_a64_o;
00247 }
00248 
00249 typedef struct {
00250   OP* op[4];
00251   INT index; // index of last vector, -1 if none
00252 } vector_info_t;
00253 
00254 static void
00255 Print_Vector (vector_info_t *v)
00256 {
00257   INT i;
00258   fprintf(TFile, "vector has %d ops:\n", v->index);
00259   for (i = 0; i <= v->index; ++i)
00260     Print_OP_No_SrcLine(v->op[i]);
00261 }
00262 
00263 inline void Clear_Vector (vector_info_t *v)
00264 {
00265   v->index = -1;
00266 }
00267 
00268 inline BOOL Vector_Is_Empty (vector_info_t *v)
00269 {
00270   return (v->index == -1);
00271 }
00272 
00273 inline void Start_Vector (vector_info_t *v, OP *op)
00274 {
00275   v->op[0] = op;
00276   v->index = 0;
00277 }
00278 
00279 inline BOOL
00280 Vector_Is_Load (vector_info_t *v)
00281 {
00282   return OP_load(v->op[0]);
00283 }
00284 
00285 inline BOOL
00286 Vector_Is_Store (vector_info_t *v)
00287 {
00288   return OP_store(v->op[0]);
00289 }
00290 
00291 inline TN*
00292 OP_Qualifier_TN (OP *op)
00293 {
00294   return OP_opnd(op,0);
00295 }
00296 inline TN*
00297 OP_Space_TN (OP *op)
00298 {
00299   return OP_opnd(op,1);
00300 }
00301 inline TN*
00302 OP_Base_TN (OP *op)
00303 {
00304   return OP_opnd(op,OP_find_opnd_use(op,OU_base));
00305 }
00306 inline TN*
00307 OP_Offset_TN (OP *op)
00308 {
00309   return OP_opnd(op,OP_find_opnd_use(op,OU_offset));
00310 }
00311 inline TN*
00312 OP_Storeval_TN (OP *op)
00313 {
00314   return OP_opnd(op,OP_find_opnd_use(op,OU_storeval));
00315 }
00316 inline TN*
00317 Vector_Base_TN (vector_info_t *v)
00318 {
00319   return OP_Base_TN(v->op[0]);
00320 }
00321 
00322 inline TN*
00323 Vector_Offset_TN (vector_info_t *v, INT index)
00324 {
00325   return OP_Offset_TN(v->op[index]);
00326 }
00327 inline INT
00328 Vector_Offset_Value (vector_info_t *v, INT index)
00329 {
00330   return TN_value(Vector_Offset_TN(v,index));
00331 }
00332 inline TN*
00333 Vector_Storeval_TN (vector_info_t *v, INT index)
00334 {
00335   return OP_Storeval_TN(v->op[index]);
00336 }
00337 
00338 inline void Add_To_Vector (vector_info_t *v, OP *op)
00339 {
00340   Is_True(v->index < 3, ("no room in vector"));
00341   v->index++;
00342   if (TN_value(OP_Offset_TN(op)) > TN_value(Vector_Offset_TN(v,v->index-1)) ) {
00343       // put at end of vector
00344       v->op[v->index] = op;
00345   } else {
00346       // want vectors in ascending order, so find where to put op
00347       for (INT j = 0; j < v->index; ++j) {
00348         if (TN_value(OP_Offset_TN(op)) < TN_value(Vector_Offset_TN(v,j))) {
00349     // put at beginning of vector, so shift everything over
00350     for (INT i = v->index; i > j; --i)
00351       v->op[i] = v->op[i-1];
00352     v->op[j] = op;
00353     break; // stop after inserting else will duplicate
00354         }
00355       }
00356   }
00357 }
00358 
00359 static TOP Choose_Vector_Opcode (vector_info_t *v)
00360 {
00361   TOP opc;
00362   switch (v->index) {
00363   case 1:
00364     opc = V2InstructionMap[OP_code(v->op[0])];
00365     return (opc != 0 ? opc : TOP_UNDEFINED);
00366   case 3:
00367     opc = V4InstructionMap[OP_code(v->op[0])];
00368     return (opc != 0 ? opc : TOP_UNDEFINED);
00369   default:
00370     return TOP_UNDEFINED;
00371   }
00372 }
00373 
00374 // return size in bytes
00375 static INT
00376 Sizeof_Load_Store (OP *op)
00377 {
00378     if (TOP_is_memory_8bit(OP_code(op)))
00379   return 1;
00380     else if (TOP_is_memory_16bit(OP_code(op)))
00381   return 2;
00382     else if (TOP_is_memory_32bit(OP_code(op)))
00383   return 4;
00384     else if (TOP_is_memory_64bit(OP_code(op)))
00385   return 8;
00386     else 
00387   return 0;
00388 }
00389 
00390 // return 0 if no gaps, else return index of gap;
00391 // search for gaps between start and end.
00392 inline INT Find_Gap_In_Vector (vector_info_t *v, INT start, INT end)
00393 {
00394   INT step_size = Sizeof_Load_Store(v->op[0]);
00395   INT i = start;
00396   while (i < end) {
00397     if (Vector_Offset_Value(v,i+1) 
00398      != Vector_Offset_Value(v,i) + step_size)
00399       return i+1;
00400     ++i;
00401   }
00402   return 0; // no gaps
00403 }
00404 
00405 static ST *
00406 Get_Vector_Symbol (vector_info_t *v)
00407 {
00408   TN *base_tn = Vector_Base_TN(v);
00409   if (TN_is_symbol(base_tn)) {
00410     // if directly accessing a symbol, use that info
00411     return TN_var(base_tn);
00412   }
00413   return NULL;
00414 }
00415 
00416 static TY_IDX 
00417 Get_Vector_Type (vector_info_t *v)
00418 {
00419   WN *wn = Get_WN_From_Memory_OP(v->op[0]);
00420   TY_IDX ty = WN_ty(wn);
00421   ST *st = Get_Vector_Symbol(v);
00422   if (st) {
00423     // if directly accessing a symbol, use that info
00424     ty = ST_type(st);
00425   }
00426   if (TY_kind(ty) == KIND_POINTER) {
00427     ty = TY_pointed(ty);
00428   }
00429   return ty;
00430 }
00431 
00432 static BOOL Vector_Is_Possible (vector_info_t *v)
00433 {
00434   if (v->index < 1)
00435     return FALSE; // no vector
00436   // Vector must be properly aligned.
00437   // Delay align check till now because might have gathered
00438   // pieces in unaligned order.
00439   ST *st = Get_Vector_Symbol(v);
00440   TY_IDX ty = Get_Vector_Type(v);
00441   INT step_size = Sizeof_Load_Store(v->op[0]);
00442   INT min_alignment;
00443         if (v->index == 1) {
00444     // must be double aligned
00445     min_alignment = 2 * step_size;
00446   } else {
00447     // want quad aligned
00448     min_alignment = 4 * step_size;
00449   }
00450   if (TY_align(ty) < min_alignment 
00451     && (min_alignment % TY_align(ty)) == 0
00452     && st != NULL) 
00453   {
00454     // first try to increase alignment so we can use v2 or v4;
00455     // can only do this if accessing a symbol
00456     DevWarn("increase alignment to %d", min_alignment);
00457     FmtAssert(TY_kind(ST_type(st)) != KIND_POINTER,
00458       ("reached pointer type in vectors"));
00459     Set_TY_align(ty, min_alignment);
00460     Set_ST_type(st, ty);
00461     if (Has_Base_Block(st)) {
00462       Set_STB_align(ST_base(st), 
00463         MAX (STB_align(ST_base(st)), min_alignment));
00464     }
00465         }
00466 
00467   switch (v->index) {
00468   case 1:
00469     // must be double aligned
00470     if ((Vector_Offset_Value(v,0) % min_alignment) != 0)
00471       return FALSE;
00472     if ((TY_align(ty) % min_alignment) != 0)
00473       return FALSE;
00474     // check that no gaps left in vector
00475     if (Find_Gap_In_Vector (v, 0, 1) != 0)
00476       return FALSE;
00477     break;
00478   case 2:
00479     // No real advantage to emitting v3,
00480     // since hw doesn't do 12-byte accesses.
00481     // Instead, try to do v4 if aligned load,
00482     // or v2 of first or last two accesses.
00483                 if ((TY_align(ty) % min_alignment) == 0 && Vector_Is_Load(v)) {
00484                     // try to change to v4
00485                     INT i = Find_Gap_In_Vector(v,0,2);
00486                     if (i == 0) {
00487                         // no gap, add to beginning or end 
00488                         if ((Vector_Offset_Value(v,0) % min_alignment) == 0)
00489                             i = 3; // add to end
00490                         else if (((Vector_Offset_Value(v,0)-step_size) % min_alignment) == 0)
00491                             i = 0; // add to beginning
00492                         else
00493                             i = -1; // cannot safely add
00494                     }
00495                     if (i != -1) {
00496                         DevWarn("v3 is aligned as v4, add sink at %d", i);
00497                         // create dummy op with unused dest, new offset
00498                         OP *new_op = Dup_OP(v->op[0]);
00499                         Copy_WN_For_Memory_OP (new_op, v->op[0]);
00500                         Set_OP_result(new_op,0, Unused_TN(
00501                           TN_register_class(OP_result(v->op[0],0))));
00502                         if (i > 0) {
00503                           Set_OP_opnd(new_op, 
00504                             OP_find_opnd_use(new_op,OU_offset),
00505                             Gen_Literal_TN(
00506                               Vector_Offset_Value(v,i-1) + step_size,4));
00507                         } else {
00508                           Set_OP_opnd(new_op, 
00509                             OP_find_opnd_use(new_op,OU_offset),
00510                             Gen_Literal_TN(
00511                               Vector_Offset_Value(v,0) - step_size,4));
00512                         }
00513                         BB_Insert_Op_After (OP_bb(v->op[0]), v->op[0], new_op);
00514                         Add_To_Vector (v, new_op);
00515                         if (!Vector_Is_Possible(v)) { 
00516                           // if still not a vector, need to remove sink op
00517                           // that we temporarily added.
00518                           BB_Remove_Op (OP_bb(v->op[0]), new_op);
00519                           return FALSE;
00520                         } else {
00521                           return TRUE;
00522                         }
00523                     }
00524                 }
00525     min_alignment = 2 * step_size;
00526     if ((TY_align(ty) % min_alignment) != 0)
00527       return FALSE;
00528     if (((Vector_Offset_Value(v,0) % min_alignment) == 0) 
00529       // if 0,2,3 then want to use last 2
00530       && (Vector_Offset_Value(v,1) 
00531        == Vector_Offset_Value(v,0) + step_size))
00532     {
00533       v->index = 1; // will ignore 3rd op
00534     }
00535     else if ((Vector_Offset_Value(v,1) % min_alignment) == 0) {
00536       // will ignore 1st op, so shift ops over
00537       v->op[0] = v->op[1];
00538       v->op[1] = v->op[2];
00539       v->index = 1; 
00540     }
00541     else
00542       return FALSE;
00543     // check that no gaps left in vector
00544     if (Find_Gap_In_Vector (v, 0, 1) != 0)
00545       return FALSE;
00546     break;
00547   case 3:
00548     // must be quad aligned
00549     if ((Vector_Offset_Value(v,0) % min_alignment) != 0)
00550       return FALSE;
00551     if ((TY_align(ty) % min_alignment) != 0)
00552       return FALSE;
00553     // check that no gaps left in vector
00554     if (Find_Gap_In_Vector (v, 0, 3) != 0)
00555       return FALSE;
00556     break;
00557   default: // e.g. -1
00558     return FALSE;
00559   }
00560   TOP opc = Choose_Vector_Opcode (v);
00561   if (opc == TOP_UNDEFINED) {
00562     DevWarn("TBD: vector for %s", TOP_Name(OP_code(v->op[0])));
00563     return FALSE;
00564   }
00565   return TRUE;
00566 }
00567 
00568 static OP*
00569 Earliest_Vector_Op (vector_info_t *v)
00570 {
00571   OP *first_op = v->op[0];
00572   for (INT i = 1; i <= v->index; ++i) {
00573     if (OP_Precedes(v->op[i], first_op))
00574       first_op = v->op[i];
00575   }
00576   return first_op;
00577 }
00578 
00579 static OP*
00580 Latest_Vector_Op (vector_info_t *v)
00581 {
00582   OP *last_op = v->op[v->index];
00583   for (INT i = 0; i < v->index; ++i) {
00584     if (OP_Precedes(last_op, v->op[i]))
00585       last_op = v->op[i];
00586   }
00587   return last_op;
00588 }
00589 
00590 static void Emit_Vector (vector_info_t *v)
00591 {
00592   OP *vop;
00593   TOP opc = Choose_Vector_Opcode (v);
00594   BB *bb = OP_bb(v->op[0]);
00595     if (tracing) fprintf(TFile, "emit vector: %s\n", TOP_Name(opc));
00596   ++num_vectors;
00597 
00598   if (Vector_Is_Load(v)) {
00599     switch (v->index) {
00600     case 1:
00601     vop = Mk_OP (opc, 
00602       OP_result(v->op[0],0), OP_result(v->op[1],0),
00603       OP_Qualifier_TN(v->op[0]),
00604       Vector_Base_TN(v), Vector_Offset_TN(v,0));
00605     break;
00606     case 2:
00607     vop = Mk_OP (opc, 
00608       OP_result(v->op[0],0), OP_result(v->op[1],0),
00609       OP_result(v->op[2],0),
00610       OP_Qualifier_TN(v->op[0]),
00611       Vector_Base_TN(v), Vector_Offset_TN(v,0));
00612     break;
00613     case 3:
00614     vop = Mk_OP (opc, 
00615       OP_result(v->op[0],0), OP_result(v->op[1],0),
00616       OP_result(v->op[2],0), OP_result(v->op[3],0),
00617       OP_Qualifier_TN(v->op[0]),
00618       Vector_Base_TN(v), Vector_Offset_TN(v,0));
00619     break;
00620     default:
00621     FmtAssert(FALSE, ("unexpected"));
00622     }
00623     // emit new vector op before first load op
00624     BB_Insert_Op_Before (bb, Earliest_Vector_Op(v), vop);
00625   }
00626 
00627   else {  // store
00628     switch (v->index) {
00629     case 1:
00630     vop = Mk_OP (opc, OP_Qualifier_TN(v->op[0]),
00631       Vector_Base_TN(v), Vector_Offset_TN(v,0),
00632       Vector_Storeval_TN(v,0), Vector_Storeval_TN(v,1) );
00633     break;
00634     case 2:
00635     vop = Mk_OP (opc, OP_Qualifier_TN(v->op[0]),
00636       Vector_Base_TN(v), Vector_Offset_TN(v,0),
00637       Vector_Storeval_TN(v,0), Vector_Storeval_TN(v,1),
00638       Vector_Storeval_TN(v,2) );
00639     break;
00640     case 3:
00641     vop = Mk_OP (opc, OP_Qualifier_TN(v->op[0]),
00642       Vector_Base_TN(v), Vector_Offset_TN(v,0),
00643       Vector_Storeval_TN(v,0), Vector_Storeval_TN(v,1),
00644       Vector_Storeval_TN(v,2), Vector_Storeval_TN(v,3) );
00645     break;
00646     default:
00647     FmtAssert(FALSE, ("unexpected"));
00648     }
00649     // emit new vector op after last store op
00650     BB_Insert_Op_After (bb, Latest_Vector_Op(v), vop);
00651   }
00652 
00653   // remove each old op
00654   for (INT i=0; i <= v->index; ++i) {
00655     BB_Remove_Op (bb, v->op[i]);
00656   }
00657 }
00658 
00659 static BOOL
00660 Vector_Can_Add_Op (vector_info_t *v, OP *op)
00661 {
00662   if (Vector_Is_Empty(v)) return FALSE;
00663   if (v->index == 3) return FALSE; // vector is full
00664   // for several of these checks, can just check against
00665   // first op in vector, since all vector ops should be same
00666   if (OP_load(op) != OP_load(v->op[0]))
00667     return FALSE; // not both load or both store
00668   if (OP_Base_TN(op) != Vector_Base_TN(v))
00669     return FALSE; // base is different 
00670   if (! TN_has_value(OP_Offset_TN(op)))
00671     return FALSE; // no immediate offset?
00672   if (! TN_has_value(Vector_Offset_TN(v,0)))
00673     return FALSE; // no immediate offset?
00674   if (OP_Qualifier_TN(op) != OP_Qualifier_TN(v->op[0]))
00675     return FALSE; // volatile-ness must be same
00676 
00677         if (TOP_is_fp_loadstore(OP_code(op)) 
00678     != TOP_is_fp_loadstore(OP_code(v->op[0])) )
00679   {
00680     return FALSE; // types don't match
00681   }
00682   // check that values are in same register type
00683   // (e.g. if have 16bit values in 16 and 32 bit registers).
00684   if (Vector_Is_Load(v)) {
00685       if (TN_register_class(OP_result(op,0)) 
00686        != TN_register_class(OP_result(v->op[0],0)) )
00687     return FALSE;
00688   }
00689   else { // store
00690       if (TN_register_class(OP_Storeval_TN(op)) 
00691        != TN_register_class(Vector_Storeval_TN(v,0)) )
00692     return FALSE;
00693   }
00694 
00695         if (Vector_Is_Load(v)) {
00696     // vector load inserted at first load, 
00697     // so check if result of load is used between loads
00698     // E.g. load d=r1,0
00699     //  op =d2
00700     //  load d2=r1,4
00701     // So search intervening instructions for use.
00702     // Also search for intervening store to address we are loading from.
00703     OP *opi; // intervening op
00704       for (INT i = 0; i < OP_results(op); i++) {
00705       if (!TN_is_register(OP_result(op,i)))
00706     continue;
00707       for (opi = Earliest_Vector_Op(v); opi != op; opi = OP_next(opi)) {
00708     if (OP_Refs_TN(opi, OP_result(op,i))) {
00709             if (tracing) fprintf(TFile, "load used in-between\n");
00710             return FALSE; // used in-between
00711     }
00712     else if (OP_store(opi)
00713       && OP_Base_TN(opi) == OP_Base_TN(op)
00714       && TN_value(OP_Offset_TN(opi)) == TN_value(OP_Offset_TN(op)))
00715     {
00716             if (tracing) {
00717       fprintf(TFile, "store in-between\n");
00718           Print_OP_No_SrcLine(opi);
00719           Print_OP_No_SrcLine(op);
00720       Print_Vector(v);
00721       }
00722             return FALSE; // store in-between
00723     }
00724     else if (TOP_is_v2_store(OP_code(opi))
00725       && OP_Base_TN(opi) == OP_Base_TN(op)
00726       && TN_value(OP_Offset_TN(op)) >= TN_value(OP_Offset_TN(opi))
00727       && TN_value(OP_Offset_TN(op)) <= 
00728         TN_value(OP_Offset_TN(opi)) + Sizeof_Load_Store(opi))
00729     {
00730             if (tracing) {
00731       fprintf(TFile, "v2 store in-between\n");
00732           Print_OP_No_SrcLine(opi);
00733           Print_OP_No_SrcLine(op);
00734       Print_Vector(v);
00735       }
00736             return FALSE; // store in-between
00737     }
00738     else if (TOP_is_v4_store(OP_code(opi))
00739       && OP_Base_TN(opi) == OP_Base_TN(op)
00740       && TN_value(OP_Offset_TN(op)) >= TN_value(OP_Offset_TN(opi))
00741       && TN_value(OP_Offset_TN(op)) <= 
00742         TN_value(OP_Offset_TN(opi)) + 3*Sizeof_Load_Store(opi))
00743     {
00744             if (tracing) {
00745       fprintf(TFile, "v4 store in-between\n");
00746           Print_OP_No_SrcLine(opi);
00747           Print_OP_No_SrcLine(op);
00748       Print_Vector(v);
00749       }
00750             return FALSE; // store in-between
00751     }
00752       }
00753     }
00754         }
00755 
00756   INT step_size = Sizeof_Load_Store(v->op[0]);
00757   if (Sizeof_Load_Store(op) != step_size)
00758     return FALSE; // sizes don't match
00759 
00760   // check for case of double-aligned but 4 in a row;
00761   // in that case want to create 2 vectors of 2 elements each.
00762   ST *st = Get_Vector_Symbol(v);
00763   TY_IDX ty = Get_Vector_Type(v);
00764         INT max_vector_elements = 4;
00765         if (st == NULL // no info so can't change alignment
00766     && (TY_align(ty) % (4 * step_size)) != 0  // not quad aligned
00767     && (TY_align(ty) % (2 * step_size)) == 0) // double aligned
00768   {
00769     if (tracing) fprintf(TFile, "stop at 2 elements\n");
00770     max_vector_elements = 2;
00771   }
00772 
00773   // now check that offset fits in vector sequence
00774   INT op_offset = TN_value(OP_Offset_TN(op));
00775   INT op0_offset = TN_value(Vector_Offset_TN(v,0));
00776   INT field_id = WN_field_id(Get_WN_From_Memory_OP(op));
00777   INT field0_id = WN_field_id(Get_WN_From_Memory_OP(v->op[0]));
00778         TY_IDX struct_ty = WN_ty(Get_WN_From_Memory_OP(op));
00779   if (TY_kind(struct_ty) == KIND_POINTER)
00780         struct_ty = TY_pointed(struct_ty);
00781   INT num_elements = TY_size(struct_ty) / step_size;
00782 
00783         // check that offset not already in vector
00784         for (INT i=0; i <= v->index; ++i) {
00785           if (TN_value(Vector_Offset_TN(v,i)) == op_offset) {
00786             return FALSE;
00787           }
00788         }
00789   // if have field_id info, 
00790   // then offset should match field_id position
00791   // (might go in middle of sequence if saw 0,8,4 as offsets)
00792   if (field_id != 0 && field0_id != 0 && field_id != field0_id) {
00793     if ((abs(field_id-field0_id) < num_elements)
00794       && ((field_id-field0_id) == ((op_offset-op0_offset) / step_size)))
00795     return TRUE;
00796     else
00797     return FALSE;
00798   }
00799   // no field_id info, so just see if offset fits at beginning or end
00800   // With arrays of structs could end up with offsets that are too far
00801   // apart, so check total distance too.
00802   INT distance1, distance2;
00803   distance1 = op0_offset - op_offset;
00804   distance2 = op_offset - TN_value(Vector_Offset_TN(v,v->index));
00805   if (distance1 == step_size 
00806           && abs(distance2) < step_size * max_vector_elements)
00807   {
00808     return TRUE;  // fits at beginning of vector
00809   }
00810   if (distance2 == step_size 
00811     && abs(distance1) < step_size * max_vector_elements)
00812   {
00813     return TRUE;  // fits at end of vector
00814   }
00815   
00816     if (tracing) fprintf(TFile, "vector doesn't fit\n");
00817   return FALSE; // doesn't fit?
00818 }
00819 
00820 static inline BOOL Is_Potential_Load_Or_Store (OP *op)
00821 {
00822   if (OP_load(op) || OP_store(op)) {
00823     if (TN_enum(OP_Space_TN(op)) == ECV_space_global) {
00824       if (Get_WN_From_Memory_OP(op)) {  // if no wn then no alignment info
00825   // only handle _r and _o forms that have offsets
00826   if (OP_find_opnd_use(op,OU_offset) != -1)
00827           return TRUE;
00828       }
00829     }
00830   }
00831   return FALSE;
00832 }
00833 
00834 // Want to merge loads that have intervening instructions
00835 // when regs not redefined by instructions.
00836 static BOOL
00837 OP_Interferes_With_Vector (OP *op, vector_info_t *v)
00838 {
00839   INT i, j, k;
00840   if (Vector_Is_Empty(v))
00841   return FALSE;
00842 
00843   if (OP_store(op) && Vector_Is_Store(v)) {
00844     if (TN_enum(OP_Space_TN(op)) == ECV_space_global) {
00845       if (OP_Base_TN(op) == Vector_Base_TN(v)) {
00846         // check that offset not already in vector
00847         for (INT i=0; i <= v->index; ++i) {
00848           if (TN_value(Vector_Offset_TN(v,i)) == TN_value(OP_Offset_TN(op))) {
00849         if (tracing) {
00850     fprintf(TFile, "store redefines vector value\n");
00851         Print_OP_No_SrcLine(op);
00852         Print_Vector(v);
00853       }
00854             return TRUE;
00855           }
00856         }
00857       }
00858     }
00859   }
00860 
00861   // check if base is redefined
00862   for (i = 0; i < OP_results(op); i++) {
00863       if (OP_result(op,i) == Vector_Base_TN(v)) {
00864     if (tracing) fprintf(TFile, "redefines base\n");
00865   return TRUE;  // redefines base
00866       }
00867   }
00868 
00869   if (Vector_Is_Store(v)) {
00870   // vector store inserted at last store, 
00871   // so check if opnds of stores are redefined
00872   // E.g. store d=r1,0
00873   //  mov r1=
00874   //  store d2=r1,4
00875     for (i = 0; i < OP_results(op); i++) {
00876       if (!TN_is_register(OP_result(op,i)))
00877     continue;
00878       for (j = 0; j <= v->index; ++j) {
00879       for (k = 0; k < OP_opnds(v->op[j]); k++) {
00880       if (OP_result(op,i) == OP_opnd(v->op[j],k)) {
00881         if (tracing) fprintf(TFile, "store redefined (%d,%d,%d)\n", i,j,k);
00882         return TRUE;  // store op redefined
00883       }
00884     }
00885       }
00886   }
00887   }
00888   // else load:
00889   // vector load inserted at first load, 
00890   // so check if result of load is used
00891   // E.g. load d=r1,0
00892   //  op =d2
00893   //  load d2=r1,4
00894   // However, this requires knowing the future load....
00895   // so wait until reach that load and then check in Can_Add_Op.
00896 
00897   return FALSE; // is safe to ignore
00898 }
00899 
00900 // go through ops and combine contiguous loads/stores into vector instructions
00901 extern void Create_Vector_Load_Stores (void)
00902 {
00903   BB *bb;
00904   OP *op;
00905   std::list<vector_info_t*> vlist;
00906   std::list<vector_info_t*>::iterator vlist_it;
00907   vector_info_t *v;
00908   BOOL added = FALSE;
00909   MEM_POOL vec_pool;
00910   MEM_POOL_Initialize (&vec_pool, "vector_loadstore", FALSE);
00911   tracing = Get_Trace(TP_EBO, 0x200);
00912   num_vectors = 0;
00913   Create_VInstruction_Maps();
00914 
00915   for (bb = REGION_First_BB; bb != NULL; bb = BB_next(bb)) {
00916     // could keep list of vector pointers and reuse them,
00917     // but simpler to just push and pop at each bb.
00918     MEM_POOL_Push(&vec_pool);
00919 
00920     FOR_ALL_BB_OPs (bb, op) {
00921 
00922       if (Is_Potential_Load_Or_Store (op)) {
00923   // add to existing vector or start new vector
00924         added = FALSE;
00925         for (vlist_it = vlist.begin(); vlist_it != vlist.end(); ++vlist_it) {
00926           v = *vlist_it;
00927     if (Vector_Can_Add_Op (v, op)) {
00928       Add_To_Vector (v, op);
00929             added = TRUE;
00930       break;
00931     }
00932     // check if op interferes with vector (stores to offset in vector)
00933           else if (OP_Interferes_With_Vector (op, v)) {
00934       // cannot continue with vector, so emit it if can
00935       if (Vector_Is_Possible (v)) {
00936     Emit_Vector (v);
00937       }
00938       Clear_Vector(v);  // future iterations will ignore vector
00939           }
00940         }
00941         if ( ! added) {
00942     v = TYPE_MEM_POOL_ALLOC(vector_info_t,&vec_pool);
00943     // put at end of list so earlier vectors will finish first.
00944     vlist.push_back(v); 
00945         if (tracing) { 
00946     fprintf(TFile, "start vector in bb %d\n", BB_id(bb));
00947     Print_OP_No_SrcLine(op);
00948     }
00949     Start_Vector (v,op);
00950         }
00951       }
00952       else {
00953         // check for interfering op
00954         for (vlist_it = vlist.begin(); vlist_it != vlist.end(); ++vlist_it) {
00955           v = *vlist_it;
00956           if (OP_Interferes_With_Vector (op, v)) {
00957       // cannot continue with vector, so emit it if can
00958       if (Vector_Is_Possible (v)) {
00959     Emit_Vector (v);
00960       }
00961       Clear_Vector(v);  // future iterations will ignore vector
00962           }
00963     // else can ignore op
00964         }
00965       }
00966     }
00967       
00968     // end of BB, so emit any remaining vectors
00969     for (vlist_it = vlist.begin(); vlist_it != vlist.end(); ++vlist_it) {
00970       v = *vlist_it;
00971       if (Vector_Is_Possible (v)) {
00972   Emit_Vector (v);
00973       }
00974     }
00975     vlist.clear();
00976     MEM_POOL_Pop(&vec_pool);
00977   }
00978   if (tracing) fprintf(TFile, "%d vectors created\n", num_vectors);
00979 
00980   V2InstructionMap.clear();
00981   V4InstructionMap.clear();
00982   MEM_POOL_Delete (&vec_pool);
00983 }
00984