Open64: osprey/cygnus/opcodes/m32r-desc.c Source File

00001 /*
00002  * Copyright 2003, 2004, 2005, 2006 PathScale, Inc.  All Rights Reserved.
00003  */
00004 
00005 /* CPU data for m32r.
00006 
00007 THIS FILE IS MACHINE GENERATED WITH CGEN.
00008 
00009 Copyright 1996-2005 Free Software Foundation, Inc.
00010 
00011 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00012 
00013 This program is free software; you can redistribute it and/or modify
00014 it under the terms of the GNU General Public License as published by
00015 the Free Software Foundation; either version 2, or (at your option)
00016 any later version.
00017 
00018 This program is distributed in the hope that it will be useful,
00019 but WITHOUT ANY WARRANTY; without even the implied warranty of
00020 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00021 GNU General Public License for more details.
00022 
00023 You should have received a copy of the GNU General Public License along
00024 with this program; if not, write to the Free Software Foundation, Inc.,
00025 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00026 
00027 */
00028 
00029 #include "sysdep.h"
00030 #include <stdio.h>
00031 #include <stdarg.h>
00032 #include "ansidecl.h"
00033 #include "bfd.h"
00034 #include "symcat.h"
00035 #include "m32r-desc.h"
00036 #include "m32r-opc.h"
00037 #include "opintl.h"
00038 #include "libiberty.h"
00039 #include "xregex.h"
00040 
00041 /* Attributes.  */
00042 
00043 static const CGEN_ATTR_ENTRY bool_attr[] =
00044 {
00045   { "#f", 0 },
00046   { "#t", 1 },
00047   { 0, 0 }
00048 };
00049 
00050 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00051 {
00052   { "base", MACH_BASE },
00053   { "m32r", MACH_M32R },
00054   { "m32rx", MACH_M32RX },
00055   { "m32r2", MACH_M32R2 },
00056   { "max", MACH_MAX },
00057   { 0, 0 }
00058 };
00059 
00060 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00061 {
00062   { "m32r", ISA_M32R },
00063   { "max", ISA_MAX },
00064   { 0, 0 }
00065 };
00066 
00067 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
00068 {
00069   { "NONE", PIPE_NONE },
00070   { "O", PIPE_O },
00071   { "S", PIPE_S },
00072   { "OS", PIPE_OS },
00073   { "O_OS", PIPE_O_OS },
00074   { 0, 0 }
00075 };
00076 
00077 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
00078 {
00079   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00080   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00081   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00082   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00083   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00084   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00085   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00086   { "RELOC", &bool_attr[0], &bool_attr[0] },
00087   { 0, 0, 0 }
00088 };
00089 
00090 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
00091 {
00092   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00093   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00094   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00095   { "PC", &bool_attr[0], &bool_attr[0] },
00096   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00097   { 0, 0, 0 }
00098 };
00099 
00100 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
00101 {
00102   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00103   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00104   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00105   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00106   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00107   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00108   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00109   { "RELAX", &bool_attr[0], &bool_attr[0] },
00110   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00111   { "RELOC", &bool_attr[0], &bool_attr[0] },
00112   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
00113   { 0, 0, 0 }
00114 };
00115 
00116 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
00117 {
00118   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00119   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
00120   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00121   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00122   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00123   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00124   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00125   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00126   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00127   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00128   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00129   { "PBB", &bool_attr[0], &bool_attr[0] },
00130   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
00131   { "SPECIAL", &bool_attr[0], &bool_attr[0] },
00132   { "SPECIAL_M32R", &bool_attr[0], &bool_attr[0] },
00133   { "SPECIAL_FLOAT", &bool_attr[0], &bool_attr[0] },
00134   { 0, 0, 0 }
00135 };
00136 
00137 /* Instruction set variants.  */
00138 
00139 static const CGEN_ISA m32r_cgen_isa_table[] = {
00140   { "m32r", 32, 32, 16, 32 },
00141   { 0, 0, 0, 0, 0 }
00142 };
00143 
00144 /* Machine variants.  */
00145 
00146 static const CGEN_MACH m32r_cgen_mach_table[] = {
00147   { "m32r", "m32r", MACH_M32R, 0 },
00148   { "m32rx", "m32rx", MACH_M32RX, 0 },
00149   { "m32r2", "m32r2", MACH_M32R2, 0 },
00150   { 0, 0, 0, 0 }
00151 };
00152 
00153 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
00154 {
00155   { "fp", 13, {0, {0}}, 0, 0 },
00156   { "lr", 14, {0, {0}}, 0, 0 },
00157   { "sp", 15, {0, {0}}, 0, 0 },
00158   { "r0", 0, {0, {0}}, 0, 0 },
00159   { "r1", 1, {0, {0}}, 0, 0 },
00160   { "r2", 2, {0, {0}}, 0, 0 },
00161   { "r3", 3, {0, {0}}, 0, 0 },
00162   { "r4", 4, {0, {0}}, 0, 0 },
00163   { "r5", 5, {0, {0}}, 0, 0 },
00164   { "r6", 6, {0, {0}}, 0, 0 },
00165   { "r7", 7, {0, {0}}, 0, 0 },
00166   { "r8", 8, {0, {0}}, 0, 0 },
00167   { "r9", 9, {0, {0}}, 0, 0 },
00168   { "r10", 10, {0, {0}}, 0, 0 },
00169   { "r11", 11, {0, {0}}, 0, 0 },
00170   { "r12", 12, {0, {0}}, 0, 0 },
00171   { "r13", 13, {0, {0}}, 0, 0 },
00172   { "r14", 14, {0, {0}}, 0, 0 },
00173   { "r15", 15, {0, {0}}, 0, 0 }
00174 };
00175 
00176 CGEN_KEYWORD m32r_cgen_opval_gr_names =
00177 {
00178   & m32r_cgen_opval_gr_names_entries[0],
00179   19,
00180   0, 0, 0, 0, ""
00181 };
00182 
00183 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
00184 {
00185   { "psw", 0, {0, {0}}, 0, 0 },
00186   { "cbr", 1, {0, {0}}, 0, 0 },
00187   { "spi", 2, {0, {0}}, 0, 0 },
00188   { "spu", 3, {0, {0}}, 0, 0 },
00189   { "bpc", 6, {0, {0}}, 0, 0 },
00190   { "bbpsw", 8, {0, {0}}, 0, 0 },
00191   { "bbpc", 14, {0, {0}}, 0, 0 },
00192   { "evb", 5, {0, {0}}, 0, 0 },
00193   { "cr0", 0, {0, {0}}, 0, 0 },
00194   { "cr1", 1, {0, {0}}, 0, 0 },
00195   { "cr2", 2, {0, {0}}, 0, 0 },
00196   { "cr3", 3, {0, {0}}, 0, 0 },
00197   { "cr4", 4, {0, {0}}, 0, 0 },
00198   { "cr5", 5, {0, {0}}, 0, 0 },
00199   { "cr6", 6, {0, {0}}, 0, 0 },
00200   { "cr7", 7, {0, {0}}, 0, 0 },
00201   { "cr8", 8, {0, {0}}, 0, 0 },
00202   { "cr9", 9, {0, {0}}, 0, 0 },
00203   { "cr10", 10, {0, {0}}, 0, 0 },
00204   { "cr11", 11, {0, {0}}, 0, 0 },
00205   { "cr12", 12, {0, {0}}, 0, 0 },
00206   { "cr13", 13, {0, {0}}, 0, 0 },
00207   { "cr14", 14, {0, {0}}, 0, 0 },
00208   { "cr15", 15, {0, {0}}, 0, 0 }
00209 };
00210 
00211 CGEN_KEYWORD m32r_cgen_opval_cr_names =
00212 {
00213   & m32r_cgen_opval_cr_names_entries[0],
00214   24,
00215   0, 0, 0, 0, ""
00216 };
00217 
00218 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
00219 {
00220   { "a0", 0, {0, {0}}, 0, 0 },
00221   { "a1", 1, {0, {0}}, 0, 0 }
00222 };
00223 
00224 CGEN_KEYWORD m32r_cgen_opval_h_accums =
00225 {
00226   & m32r_cgen_opval_h_accums_entries[0],
00227   2,
00228   0, 0, 0, 0, ""
00229 };
00230 
00231 
00232 /* The hardware table.  */
00233 
00234 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00235 #define A(a) (1 << CGEN_HW_##a)
00236 #else
00237 #define A(a) (1 << CGEN_HW_a)
00238 #endif
00239 
00240 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
00241 {
00242   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00243   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00244   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00245   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00246   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00247   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
00248   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00249   { "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00250   { "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00251   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
00252   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
00253   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00254   { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } } },
00255   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00256   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00257   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00258   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00259   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00260   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
00261 };
00262 
00263 #undef A
00264 
00265 
00266 /* The instruction field table.  */
00267 
00268 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00269 #define A(a) (1 << CGEN_IFLD_##a)
00270 #else
00271 #define A(a) (1 << CGEN_IFLD_a)
00272 #endif
00273 
00274 const CGEN_IFLD m32r_cgen_ifld_table[] =
00275 {
00276   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
00277   { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
00278   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
00279   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00280   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
00281   { M32R_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
00282   { M32R_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
00283   { M32R_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00284   { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
00285   { M32R_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } }  },
00286   { M32R_F_UIMM3, "f-uimm3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } }  },
00287   { M32R_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } }  },
00288   { M32R_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } }  },
00289   { M32R_F_UIMM8, "f-uimm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00290   { M32R_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } }  },
00291   { M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
00292   { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
00293   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00294   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00295   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00296   { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
00297   { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
00298   { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
00299   { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
00300   { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
00301   { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
00302   { M32R_F_BIT4, "f-bit4", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } }  },
00303   { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
00304   { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
00305   { 0, 0, 0, 0, 0, 0, {0, {0}} }
00306 };
00307 
00308 #undef A
00309 
00310 
00311 
00312 /* multi ifield declarations */
00313 
00314 
00315 
00316 /* multi ifield definitions */
00317 
00318 
00319 /* The operand table.  */
00320 
00321 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00322 #define A(a) (1 << CGEN_OPERAND_##a)
00323 #else
00324 #define A(a) (1 << CGEN_OPERAND_a)
00325 #endif
00326 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00327 #define OPERAND(op) M32R_OPERAND_##op
00328 #else
00329 #define OPERAND(op) M32R_OPERAND_op
00330 #endif
00331 
00332 const CGEN_OPERAND m32r_cgen_operand_table[] =
00333 {
00334 /* pc: program counter */
00335   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
00336     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } }, 
00337     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00338 /* sr: source register */
00339   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
00340     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
00341     { 0, { (1<<MACH_BASE) } }  },
00342 /* dr: destination register */
00343   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
00344     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
00345     { 0, { (1<<MACH_BASE) } }  },
00346 /* src1: source register 1 */
00347   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
00348     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
00349     { 0, { (1<<MACH_BASE) } }  },
00350 /* src2: source register 2 */
00351   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
00352     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
00353     { 0, { (1<<MACH_BASE) } }  },
00354 /* scr: source control register */
00355   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
00356     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } }, 
00357     { 0, { (1<<MACH_BASE) } }  },
00358 /* dcr: destination control register */
00359   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
00360     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } }, 
00361     { 0, { (1<<MACH_BASE) } }  },
00362 /* simm8: 8 bit signed immediate */
00363   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
00364     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } }, 
00365     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00366 /* simm16: 16 bit signed immediate */
00367   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
00368     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 
00369     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00370 /* uimm3: 3 bit unsigned number */
00371   { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
00372     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM3] } }, 
00373     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00374 /* uimm4: 4 bit trap number */
00375   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
00376     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } }, 
00377     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00378 /* uimm5: 5 bit shift count */
00379   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
00380     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } }, 
00381     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00382 /* uimm8: 8 bit unsigned immediate */
00383   { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
00384     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM8] } }, 
00385     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00386 /* uimm16: 16 bit unsigned immediate */
00387   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
00388     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 
00389     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00390 /* imm1: 1 bit immediate */
00391   { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
00392     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } }, 
00393     { 0|A(HASH_PREFIX), { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
00394 /* accd: accumulator destination register */
00395   { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
00396     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } }, 
00397     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
00398 /* accs: accumulator source register */
00399   { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
00400     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } }, 
00401     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
00402 /* acc: accumulator reg (d) */
00403   { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
00404     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } }, 
00405     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2) } }  },
00406 /* hash: # prefix */
00407   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
00408     { 0, { (const PTR) 0 } }, 
00409     { 0, { (1<<MACH_BASE) } }  },
00410 /* hi16: high 16 bit immediate, sign optional */
00411   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
00412     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } }, 
00413     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
00414 /* slo16: 16 bit signed immediate, for low() */
00415   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
00416     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } }, 
00417     { 0, { (1<<MACH_BASE) } }  },
00418 /* ulo16: 16 bit unsigned immediate, for low() */
00419   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
00420     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } }, 
00421     { 0, { (1<<MACH_BASE) } }  },
00422 /* uimm24: 24 bit address */
00423   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
00424     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } }, 
00425     { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
00426 /* disp8: 8 bit displacement */
00427   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
00428     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } }, 
00429     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00430 /* disp16: 16 bit displacement */
00431   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
00432     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } }, 
00433     { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00434 /* disp24: 24 bit displacement */
00435   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
00436     { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } }, 
00437     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00438 /* condbit: condition bit */
00439   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
00440     { 0, { (const PTR) 0 } }, 
00441     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00442 /* accum: accumulator */
00443   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
00444     { 0, { (const PTR) 0 } }, 
00445     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00446 /* sentinel */
00447   { 0, 0, 0, 0, 0,
00448     { 0, { (const PTR) 0 } },
00449     { 0, { 0 } } }
00450 };
00451 
00452 #undef A
00453 
00454 
00455 /* The instruction table.  */
00456 
00457 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00458 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00459 #define A(a) (1 << CGEN_INSN_##a)
00460 #else
00461 #define A(a) (1 << CGEN_INSN_a)
00462 #endif
00463 
00464 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
00465 {
00466   /* Special null first entry.
00467      A `num' value of zero is thus invalid.
00468      Also, the special `invalid' insn resides here.  */
00469   { 0, 0, 0, 0, {0, {0}} },
00470 /* add $dr,$sr */
00471   {
00472     M32R_INSN_ADD, "add", "add", 16,
00473     { 0, { (1<<MACH_BASE), PIPE_OS } }
00474   },
00475 /* add3 $dr,$sr,$hash$slo16 */
00476   {
00477     M32R_INSN_ADD3, "add3", "add3", 32,
00478     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00479   },
00480 /* and $dr,$sr */
00481   {
00482     M32R_INSN_AND, "and", "and", 16,
00483     { 0, { (1<<MACH_BASE), PIPE_OS } }
00484   },
00485 /* and3 $dr,$sr,$uimm16 */
00486   {
00487     M32R_INSN_AND3, "and3", "and3", 32,
00488     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00489   },
00490 /* or $dr,$sr */
00491   {
00492     M32R_INSN_OR, "or", "or", 16,
00493     { 0, { (1<<MACH_BASE), PIPE_OS } }
00494   },
00495 /* or3 $dr,$sr,$hash$ulo16 */
00496   {
00497     M32R_INSN_OR3, "or3", "or3", 32,
00498     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00499   },
00500 /* xor $dr,$sr */
00501   {
00502     M32R_INSN_XOR, "xor", "xor", 16,
00503     { 0, { (1<<MACH_BASE), PIPE_OS } }
00504   },
00505 /* xor3 $dr,$sr,$uimm16 */
00506   {
00507     M32R_INSN_XOR3, "xor3", "xor3", 32,
00508     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00509   },
00510 /* addi $dr,$simm8 */
00511   {
00512     M32R_INSN_ADDI, "addi", "addi", 16,
00513     { 0, { (1<<MACH_BASE), PIPE_OS } }
00514   },
00515 /* addv $dr,$sr */
00516   {
00517     M32R_INSN_ADDV, "addv", "addv", 16,
00518     { 0, { (1<<MACH_BASE), PIPE_OS } }
00519   },
00520 /* addv3 $dr,$sr,$simm16 */
00521   {
00522     M32R_INSN_ADDV3, "addv3", "addv3", 32,
00523     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00524   },
00525 /* addx $dr,$sr */
00526   {
00527     M32R_INSN_ADDX, "addx", "addx", 16,
00528     { 0, { (1<<MACH_BASE), PIPE_OS } }
00529   },
00530 /* bc.s $disp8 */
00531   {
00532     M32R_INSN_BC8, "bc8", "bc.s", 16,
00533     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
00534   },
00535 /* bc.l $disp24 */
00536   {
00537     M32R_INSN_BC24, "bc24", "bc.l", 32,
00538     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00539   },
00540 /* beq $src1,$src2,$disp16 */
00541   {
00542     M32R_INSN_BEQ, "beq", "beq", 32,
00543     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00544   },
00545 /* beqz $src2,$disp16 */
00546   {
00547     M32R_INSN_BEQZ, "beqz", "beqz", 32,
00548     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00549   },
00550 /* bgez $src2,$disp16 */
00551   {
00552     M32R_INSN_BGEZ, "bgez", "bgez", 32,
00553     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00554   },
00555 /* bgtz $src2,$disp16 */
00556   {
00557     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
00558     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00559   },
00560 /* blez $src2,$disp16 */
00561   {
00562     M32R_INSN_BLEZ, "blez", "blez", 32,
00563     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00564   },
00565 /* bltz $src2,$disp16 */
00566   {
00567     M32R_INSN_BLTZ, "bltz", "bltz", 32,
00568     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00569   },
00570 /* bnez $src2,$disp16 */
00571   {
00572     M32R_INSN_BNEZ, "bnez", "bnez", 32,
00573     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00574   },
00575 /* bl.s $disp8 */
00576   {
00577     M32R_INSN_BL8, "bl8", "bl.s", 16,
00578     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
00579   },
00580 /* bl.l $disp24 */
00581   {
00582     M32R_INSN_BL24, "bl24", "bl.l", 32,
00583     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00584   },
00585 /* bcl.s $disp8 */
00586   {
00587     M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
00588     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
00589   },
00590 /* bcl.l $disp24 */
00591   {
00592     M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
00593     { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
00594   },
00595 /* bnc.s $disp8 */
00596   {
00597     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
00598     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
00599   },
00600 /* bnc.l $disp24 */
00601   {
00602     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
00603     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00604   },
00605 /* bne $src1,$src2,$disp16 */
00606   {
00607     M32R_INSN_BNE, "bne", "bne", 32,
00608     { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00609   },
00610 /* bra.s $disp8 */
00611   {
00612     M32R_INSN_BRA8, "bra8", "bra.s", 16,
00613     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
00614   },
00615 /* bra.l $disp24 */
00616   {
00617     M32R_INSN_BRA24, "bra24", "bra.l", 32,
00618     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
00619   },
00620 /* bncl.s $disp8 */
00621   {
00622     M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
00623     { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
00624   },
00625 /* bncl.l $disp24 */
00626   {
00627     M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
00628     { 0|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
00629   },
00630 /* cmp $src1,$src2 */
00631   {
00632     M32R_INSN_CMP, "cmp", "cmp", 16,
00633     { 0, { (1<<MACH_BASE), PIPE_OS } }
00634   },
00635 /* cmpi $src2,$simm16 */
00636   {
00637     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
00638     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00639   },
00640 /* cmpu $src1,$src2 */
00641   {
00642     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
00643     { 0, { (1<<MACH_BASE), PIPE_OS } }
00644   },
00645 /* cmpui $src2,$simm16 */
00646   {
00647     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
00648     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00649   },
00650 /* cmpeq $src1,$src2 */
00651   {
00652     M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
00653     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
00654   },
00655 /* cmpz $src2 */
00656   {
00657     M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
00658     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
00659   },
00660 /* div $dr,$sr */
00661   {
00662     M32R_INSN_DIV, "div", "div", 32,
00663     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00664   },
00665 /* divu $dr,$sr */
00666   {
00667     M32R_INSN_DIVU, "divu", "divu", 32,
00668     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00669   },
00670 /* rem $dr,$sr */
00671   {
00672     M32R_INSN_REM, "rem", "rem", 32,
00673     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00674   },
00675 /* remu $dr,$sr */
00676   {
00677     M32R_INSN_REMU, "remu", "remu", 32,
00678     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00679   },
00680 /* remh $dr,$sr */
00681   {
00682     M32R_INSN_REMH, "remh", "remh", 32,
00683     { 0, { (1<<MACH_M32R2), PIPE_NONE } }
00684   },
00685 /* remuh $dr,$sr */
00686   {
00687     M32R_INSN_REMUH, "remuh", "remuh", 32,
00688     { 0, { (1<<MACH_M32R2), PIPE_NONE } }
00689   },
00690 /* remb $dr,$sr */
00691   {
00692     M32R_INSN_REMB, "remb", "remb", 32,
00693     { 0, { (1<<MACH_M32R2), PIPE_NONE } }
00694   },
00695 /* remub $dr,$sr */
00696   {
00697     M32R_INSN_REMUB, "remub", "remub", 32,
00698     { 0, { (1<<MACH_M32R2), PIPE_NONE } }
00699   },
00700 /* divuh $dr,$sr */
00701   {
00702     M32R_INSN_DIVUH, "divuh", "divuh", 32,
00703     { 0, { (1<<MACH_M32R2), PIPE_NONE } }
00704   },
00705 /* divb $dr,$sr */
00706   {
00707     M32R_INSN_DIVB, "divb", "divb", 32,
00708     { 0, { (1<<MACH_M32R2), PIPE_NONE } }
00709   },
00710 /* divub $dr,$sr */
00711   {
00712     M32R_INSN_DIVUB, "divub", "divub", 32,
00713     { 0, { (1<<MACH_M32R2), PIPE_NONE } }
00714   },
00715 /* divh $dr,$sr */
00716   {
00717     M32R_INSN_DIVH, "divh", "divh", 32,
00718     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
00719   },
00720 /* jc $sr */
00721   {
00722     M32R_INSN_JC, "jc", "jc", 16,
00723     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
00724   },
00725 /* jnc $sr */
00726   {
00727     M32R_INSN_JNC, "jnc", "jnc", 16,
00728     { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
00729   },
00730 /* jl $sr */
00731   {
00732     M32R_INSN_JL, "jl", "jl", 16,
00733     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
00734   },
00735 /* jmp $sr */
00736   {
00737     M32R_INSN_JMP, "jmp", "jmp", 16,
00738     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
00739   },
00740 /* ld $dr,@$sr */
00741   {
00742     M32R_INSN_LD, "ld", "ld", 16,
00743     { 0, { (1<<MACH_BASE), PIPE_O } }
00744   },
00745 /* ld $dr,@($slo16,$sr) */
00746   {
00747     M32R_INSN_LD_D, "ld-d", "ld", 32,
00748     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00749   },
00750 /* ldb $dr,@$sr */
00751   {
00752     M32R_INSN_LDB, "ldb", "ldb", 16,
00753     { 0, { (1<<MACH_BASE), PIPE_O } }
00754   },
00755 /* ldb $dr,@($slo16,$sr) */
00756   {
00757     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
00758     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00759   },
00760 /* ldh $dr,@$sr */
00761   {
00762     M32R_INSN_LDH, "ldh", "ldh", 16,
00763     { 0, { (1<<MACH_BASE), PIPE_O } }
00764   },
00765 /* ldh $dr,@($slo16,$sr) */
00766   {
00767     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
00768     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00769   },
00770 /* ldub $dr,@$sr */
00771   {
00772     M32R_INSN_LDUB, "ldub", "ldub", 16,
00773     { 0, { (1<<MACH_BASE), PIPE_O } }
00774   },
00775 /* ldub $dr,@($slo16,$sr) */
00776   {
00777     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
00778     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00779   },
00780 /* lduh $dr,@$sr */
00781   {
00782     M32R_INSN_LDUH, "lduh", "lduh", 16,
00783     { 0, { (1<<MACH_BASE), PIPE_O } }
00784   },
00785 /* lduh $dr,@($slo16,$sr) */
00786   {
00787     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
00788     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00789   },
00790 /* ld $dr,@$sr+ */
00791   {
00792     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
00793     { 0, { (1<<MACH_BASE), PIPE_O } }
00794   },
00795 /* ld24 $dr,$uimm24 */
00796   {
00797     M32R_INSN_LD24, "ld24", "ld24", 32,
00798     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00799   },
00800 /* ldi8 $dr,$simm8 */
00801   {
00802     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
00803     { 0, { (1<<MACH_BASE), PIPE_OS } }
00804   },
00805 /* ldi16 $dr,$hash$slo16 */
00806   {
00807     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
00808     { 0, { (1<<MACH_BASE), PIPE_NONE } }
00809   },
00810 /* lock $dr,@$sr */
00811   {
00812     M32R_INSN_LOCK, "lock", "lock", 16,
00813     { 0, { (1<<MACH_BASE), PIPE_O } }
00814   },
00815 /* machi $src1,$src2 */
00816   {
00817     M32R_INSN_MACHI, "machi", "machi", 16,
00818     { 0, { (1<<MACH_M32R), PIPE_S } }
00819   },
00820 /* machi $src1,$src2,$acc */
00821   {
00822     M32R_INSN_MACHI_A, "machi-a", "machi", 16,
00823     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00824   },
00825 /* maclo $src1,$src2 */
00826   {
00827     M32R_INSN_MACLO, "maclo", "maclo", 16,
00828     { 0, { (1<<MACH_M32R), PIPE_S } }
00829   },
00830 /* maclo $src1,$src2,$acc */
00831   {
00832     M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
00833     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00834   },
00835 /* macwhi $src1,$src2 */
00836   {
00837     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
00838     { 0, { (1<<MACH_M32R), PIPE_S } }
00839   },
00840 /* macwhi $src1,$src2,$acc */
00841   {
00842     M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
00843     { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00844   },
00845 /* macwlo $src1,$src2 */
00846   {
00847     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
00848     { 0, { (1<<MACH_M32R), PIPE_S } }
00849   },
00850 /* macwlo $src1,$src2,$acc */
00851   {
00852     M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
00853     { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00854   },
00855 /* mul $dr,$sr */
00856   {
00857     M32R_INSN_MUL, "mul", "mul", 16,
00858     { 0, { (1<<MACH_BASE), PIPE_S } }
00859   },
00860 /* mulhi $src1,$src2 */
00861   {
00862     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
00863     { 0, { (1<<MACH_M32R), PIPE_S } }
00864   },
00865 /* mulhi $src1,$src2,$acc */
00866   {
00867     M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
00868     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00869   },
00870 /* mullo $src1,$src2 */
00871   {
00872     M32R_INSN_MULLO, "mullo", "mullo", 16,
00873     { 0, { (1<<MACH_M32R), PIPE_S } }
00874   },
00875 /* mullo $src1,$src2,$acc */
00876   {
00877     M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
00878     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00879   },
00880 /* mulwhi $src1,$src2 */
00881   {
00882     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
00883     { 0, { (1<<MACH_M32R), PIPE_S } }
00884   },
00885 /* mulwhi $src1,$src2,$acc */
00886   {
00887     M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
00888     { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00889   },
00890 /* mulwlo $src1,$src2 */
00891   {
00892     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
00893     { 0, { (1<<MACH_M32R), PIPE_S } }
00894   },
00895 /* mulwlo $src1,$src2,$acc */
00896   {
00897     M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
00898     { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00899   },
00900 /* mv $dr,$sr */
00901   {
00902     M32R_INSN_MV, "mv", "mv", 16,
00903     { 0, { (1<<MACH_BASE), PIPE_OS } }
00904   },
00905 /* mvfachi $dr */
00906   {
00907     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
00908     { 0, { (1<<MACH_M32R), PIPE_S } }
00909   },
00910 /* mvfachi $dr,$accs */
00911   {
00912     M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
00913     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00914   },
00915 /* mvfaclo $dr */
00916   {
00917     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
00918     { 0, { (1<<MACH_M32R), PIPE_S } }
00919   },
00920 /* mvfaclo $dr,$accs */
00921   {
00922     M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
00923     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00924   },
00925 /* mvfacmi $dr */
00926   {
00927     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
00928     { 0, { (1<<MACH_M32R), PIPE_S } }
00929   },
00930 /* mvfacmi $dr,$accs */
00931   {
00932     M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
00933     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00934   },
00935 /* mvfc $dr,$scr */
00936   {
00937     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
00938     { 0, { (1<<MACH_BASE), PIPE_O } }
00939   },
00940 /* mvtachi $src1 */
00941   {
00942     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
00943     { 0, { (1<<MACH_M32R), PIPE_S } }
00944   },
00945 /* mvtachi $src1,$accs */
00946   {
00947     M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
00948     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00949   },
00950 /* mvtaclo $src1 */
00951   {
00952     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
00953     { 0, { (1<<MACH_M32R), PIPE_S } }
00954   },
00955 /* mvtaclo $src1,$accs */
00956   {
00957     M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
00958     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00959   },
00960 /* mvtc $sr,$dcr */
00961   {
00962     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
00963     { 0, { (1<<MACH_BASE), PIPE_O } }
00964   },
00965 /* neg $dr,$sr */
00966   {
00967     M32R_INSN_NEG, "neg", "neg", 16,
00968     { 0, { (1<<MACH_BASE), PIPE_OS } }
00969   },
00970 /* nop */
00971   {
00972     M32R_INSN_NOP, "nop", "nop", 16,
00973     { 0, { (1<<MACH_BASE), PIPE_OS } }
00974   },
00975 /* not $dr,$sr */
00976   {
00977     M32R_INSN_NOT, "not", "not", 16,
00978     { 0, { (1<<MACH_BASE), PIPE_OS } }
00979   },
00980 /* rac */
00981   {
00982     M32R_INSN_RAC, "rac", "rac", 16,
00983     { 0, { (1<<MACH_M32R), PIPE_S } }
00984   },
00985 /* rac $accd,$accs,$imm1 */
00986   {
00987     M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
00988     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00989   },
00990 /* rach */
00991   {
00992     M32R_INSN_RACH, "rach", "rach", 16,
00993     { 0, { (1<<MACH_M32R), PIPE_S } }
00994   },
00995 /* rach $accd,$accs,$imm1 */
00996   {
00997     M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
00998     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
00999   },
01000 /* rte */
01001   {
01002     M32R_INSN_RTE, "rte", "rte", 16,
01003     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
01004   },
01005 /* seth $dr,$hash$hi16 */
01006   {
01007     M32R_INSN_SETH, "seth", "seth", 32,
01008     { 0, { (1<<MACH_BASE), PIPE_NONE } }
01009   },
01010 /* sll $dr,$sr */
01011   {
01012     M32R_INSN_SLL, "sll", "sll", 16,
01013     { 0, { (1<<MACH_BASE), PIPE_O_OS } }
01014   },
01015 /* sll3 $dr,$sr,$simm16 */
01016   {
01017     M32R_INSN_SLL3, "sll3", "sll3", 32,
01018     { 0, { (1<<MACH_BASE), PIPE_NONE } }
01019   },
01020 /* slli $dr,$uimm5 */
01021   {
01022     M32R_INSN_SLLI, "slli", "slli", 16,
01023     { 0, { (1<<MACH_BASE), PIPE_O_OS } }
01024   },
01025 /* sra $dr,$sr */
01026   {
01027     M32R_INSN_SRA, "sra", "sra", 16,
01028     { 0, { (1<<MACH_BASE), PIPE_O_OS } }
01029   },
01030 /* sra3 $dr,$sr,$simm16 */
01031   {
01032     M32R_INSN_SRA3, "sra3", "sra3", 32,
01033     { 0, { (1<<MACH_BASE), PIPE_NONE } }
01034   },
01035 /* srai $dr,$uimm5 */
01036   {
01037     M32R_INSN_SRAI, "srai", "srai", 16,
01038     { 0, { (1<<MACH_BASE), PIPE_O_OS } }
01039   },
01040 /* srl $dr,$sr */
01041   {
01042     M32R_INSN_SRL, "srl", "srl", 16,
01043     { 0, { (1<<MACH_BASE), PIPE_O_OS } }
01044   },
01045 /* srl3 $dr,$sr,$simm16 */
01046   {
01047     M32R_INSN_SRL3, "srl3", "srl3", 32,
01048     { 0, { (1<<MACH_BASE), PIPE_NONE } }
01049   },
01050 /* srli $dr,$uimm5 */
01051   {
01052     M32R_INSN_SRLI, "srli", "srli", 16,
01053     { 0, { (1<<MACH_BASE), PIPE_O_OS } }
01054   },
01055 /* st $src1,@$src2 */
01056   {
01057     M32R_INSN_ST, "st", "st", 16,
01058     { 0, { (1<<MACH_BASE), PIPE_O } }
01059   },
01060 /* st $src1,@($slo16,$src2) */
01061   {
01062     M32R_INSN_ST_D, "st-d", "st", 32,
01063     { 0, { (1<<MACH_BASE), PIPE_NONE } }
01064   },
01065 /* stb $src1,@$src2 */
01066   {
01067     M32R_INSN_STB, "stb", "stb", 16,
01068     { 0, { (1<<MACH_BASE), PIPE_O } }
01069   },
01070 /* stb $src1,@($slo16,$src2) */
01071   {
01072     M32R_INSN_STB_D, "stb-d", "stb", 32,
01073     { 0, { (1<<MACH_BASE), PIPE_NONE } }
01074   },
01075 /* sth $src1,@$src2 */
01076   {
01077     M32R_INSN_STH, "sth", "sth", 16,
01078     { 0, { (1<<MACH_BASE), PIPE_O } }
01079   },
01080 /* sth $src1,@($slo16,$src2) */
01081   {
01082     M32R_INSN_STH_D, "sth-d", "sth", 32,
01083     { 0, { (1<<MACH_BASE), PIPE_NONE } }
01084   },
01085 /* st $src1,@+$src2 */
01086   {
01087     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
01088     { 0, { (1<<MACH_BASE), PIPE_O } }
01089   },
01090 /* sth $src1,@$src2+ */
01091   {
01092     M32R_INSN_STH_PLUS, "sth-plus", "sth", 16,
01093     { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
01094   },
01095 /* stb $src1,@$src2+ */
01096   {
01097     M32R_INSN_STB_PLUS, "stb-plus", "stb", 16,
01098     { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
01099   },
01100 /* st $src1,@-$src2 */
01101   {
01102     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
01103     { 0, { (1<<MACH_BASE), PIPE_O } }
01104   },
01105 /* sub $dr,$sr */
01106   {
01107     M32R_INSN_SUB, "sub", "sub", 16,
01108     { 0, { (1<<MACH_BASE), PIPE_OS } }
01109   },
01110 /* subv $dr,$sr */
01111   {
01112     M32R_INSN_SUBV, "subv", "subv", 16,
01113     { 0, { (1<<MACH_BASE), PIPE_OS } }
01114   },
01115 /* subx $dr,$sr */
01116   {
01117     M32R_INSN_SUBX, "subx", "subx", 16,
01118     { 0, { (1<<MACH_BASE), PIPE_OS } }
01119   },
01120 /* trap $uimm4 */
01121   {
01122     M32R_INSN_TRAP, "trap", "trap", 16,
01123     { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
01124   },
01125 /* unlock $src1,@$src2 */
01126   {
01127     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
01128     { 0, { (1<<MACH_BASE), PIPE_O } }
01129   },
01130 /* satb $dr,$sr */
01131   {
01132     M32R_INSN_SATB, "satb", "satb", 32,
01133     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
01134   },
01135 /* sath $dr,$sr */
01136   {
01137     M32R_INSN_SATH, "sath", "sath", 32,
01138     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
01139   },
01140 /* sat $dr,$sr */
01141   {
01142     M32R_INSN_SAT, "sat", "sat", 32,
01143     { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
01144   },
01145 /* pcmpbz $src2 */
01146   {
01147     M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
01148     { 0|A(SPECIAL), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_OS } }
01149   },
01150 /* sadd */
01151   {
01152     M32R_INSN_SADD, "sadd", "sadd", 16,
01153     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01154   },
01155 /* macwu1 $src1,$src2 */
01156   {
01157     M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
01158     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01159   },
01160 /* msblo $src1,$src2 */
01161   {
01162     M32R_INSN_MSBLO, "msblo", "msblo", 16,
01163     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01164   },
01165 /* mulwu1 $src1,$src2 */
01166   {
01167     M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
01168     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01169   },
01170 /* maclh1 $src1,$src2 */
01171   {
01172     M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
01173     { 0, { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01174   },
01175 /* sc */
01176   {
01177     M32R_INSN_SC, "sc", "sc", 16,
01178     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
01179   },
01180 /* snc */
01181   {
01182     M32R_INSN_SNC, "snc", "snc", 16,
01183     { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
01184   },
01185 /* clrpsw $uimm8 */
01186   {
01187     M32R_INSN_CLRPSW, "clrpsw", "clrpsw", 16,
01188     { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
01189   },
01190 /* setpsw $uimm8 */
01191   {
01192     M32R_INSN_SETPSW, "setpsw", "setpsw", 16,
01193     { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
01194   },
01195 /* bset $uimm3,@($slo16,$sr) */
01196   {
01197     M32R_INSN_BSET, "bset", "bset", 32,
01198     { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
01199   },
01200 /* bclr $uimm3,@($slo16,$sr) */
01201   {
01202     M32R_INSN_BCLR, "bclr", "bclr", 32,
01203     { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_NONE } }
01204   },
01205 /* btst $uimm3,$sr */
01206   {
01207     M32R_INSN_BTST, "btst", "btst", 16,
01208     { 0|A(SPECIAL_M32R), { (1<<MACH_BASE), PIPE_O } }
01209   },
01210 };
01211 
01212 #undef OP
01213 #undef A
01214 
01215 /* Initialize anything needed to be done once, before any cpu_open call.  */
01216 static void init_tables PARAMS ((void));
01217 
01218 static void
01219 init_tables ()
01220 {
01221 }
01222 
01223 static const CGEN_MACH * lookup_mach_via_bfd_name
01224   PARAMS ((const CGEN_MACH *, const char *));
01225 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
01226 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
01227 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
01228 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
01229 static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
01230 
01231 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
01232 
01233 static const CGEN_MACH *
01234 lookup_mach_via_bfd_name (table, name)
01235      const CGEN_MACH *table;
01236      const char *name;
01237 {
01238   while (table->name)
01239     {
01240       if (strcmp (name, table->bfd_name) == 0)
01241   return table;
01242       ++table;
01243     }
01244   abort ();
01245 }
01246 
01247 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
01248 
01249 static void
01250 build_hw_table (cd)
01251      CGEN_CPU_TABLE *cd;
01252 {
01253   int i;
01254   int machs = cd->machs;
01255   const CGEN_HW_ENTRY *init = & m32r_cgen_hw_table[0];
01256   /* MAX_HW is only an upper bound on the number of selected entries.
01257      However each entry is indexed by it's enum so there can be holes in
01258      the table.  */
01259   const CGEN_HW_ENTRY **selected =
01260     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
01261 
01262   cd->hw_table.init_entries = init;
01263   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
01264   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
01265   /* ??? For now we just use machs to determine which ones we want.  */
01266   for (i = 0; init[i].name != NULL; ++i)
01267     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
01268   & machs)
01269       selected[init[i].type] = &init[i];
01270   cd->hw_table.entries = selected;
01271   cd->hw_table.num_entries = MAX_HW;
01272 }
01273 
01274 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
01275 
01276 static void
01277 build_ifield_table (cd)
01278      CGEN_CPU_TABLE *cd;
01279 {
01280   cd->ifld_table = & m32r_cgen_ifld_table[0];
01281 }
01282 
01283 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.  */
01284 
01285 static void
01286 build_operand_table (cd)
01287      CGEN_CPU_TABLE *cd;
01288 {
01289   int i;
01290   int machs = cd->machs;
01291   const CGEN_OPERAND *init = & m32r_cgen_operand_table[0];
01292   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
01293      However each entry is indexed by it's enum so there can be holes in
01294      the table.  */
01295   const CGEN_OPERAND **selected =
01296     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01297 
01298   cd->operand_table.init_entries = init;
01299   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
01300   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01301   /* ??? For now we just use mach to determine which ones we want.  */
01302   for (i = 0; init[i].name != NULL; ++i)
01303     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
01304   & machs)
01305       selected[init[i].type] = &init[i];
01306   cd->operand_table.entries = selected;
01307   cd->operand_table.num_entries = MAX_OPERANDS;
01308 }
01309 
01310 /* Subroutine of m32r_cgen_cpu_open to build the hardware table.
01311    ??? This could leave out insns not supported by the specified mach/isa,
01312    but that would cause errors like "foo only supported by bar" to become
01313    "unknown insn", so for now we include all insns and require the app to
01314    do the checking later.
01315    ??? On the other hand, parsing of such insns may require their hardware or
01316    operand elements to be in the table [which they mightn't be].  */
01317 
01318 static void
01319 build_insn_table (cd)
01320      CGEN_CPU_TABLE *cd;
01321 {
01322   int i;
01323   const CGEN_IBASE *ib = & m32r_cgen_insn_table[0];
01324   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
01325 
01326   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
01327   for (i = 0; i < MAX_INSNS; ++i)
01328     insns[i].base = &ib[i];
01329   cd->insn_table.init_entries = insns;
01330   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
01331   cd->insn_table.num_init_entries = MAX_INSNS;
01332 }
01333 
01334 /* Subroutine of m32r_cgen_cpu_open to rebuild the tables.  */
01335 
01336 static void
01337 m32r_cgen_rebuild_tables (cd)
01338      CGEN_CPU_TABLE *cd;
01339 {
01340   int i;
01341   unsigned int isas = cd->isas;
01342   unsigned int machs = cd->machs;
01343 
01344   cd->int_insn_p = CGEN_INT_INSN_P;
01345 
01346   /* Data derived from the isa spec.  */
01347 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
01348   cd->default_insn_bitsize = UNSET;
01349   cd->base_insn_bitsize = UNSET;
01350   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
01351   cd->max_insn_bitsize = 0;
01352   for (i = 0; i < MAX_ISAS; ++i)
01353     if (((1 << i) & isas) != 0)
01354       {
01355   const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
01356 
01357   /* Default insn sizes of all selected isas must be
01358      equal or we set the result to 0, meaning "unknown".  */
01359   if (cd->default_insn_bitsize == UNSET)
01360     cd->default_insn_bitsize = isa->default_insn_bitsize;
01361   else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
01362     ; /* this is ok */
01363   else
01364     cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
01365 
01366   /* Base insn sizes of all selected isas must be equal
01367      or we set the result to 0, meaning "unknown".  */
01368   if (cd->base_insn_bitsize == UNSET)
01369     cd->base_insn_bitsize = isa->base_insn_bitsize;
01370   else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
01371     ; /* this is ok */
01372   else
01373     cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
01374 
01375   /* Set min,max insn sizes.  */
01376   if (isa->min_insn_bitsize < cd->min_insn_bitsize)
01377     cd->min_insn_bitsize = isa->min_insn_bitsize;
01378   if (isa->max_insn_bitsize > cd->max_insn_bitsize)
01379     cd->max_insn_bitsize = isa->max_insn_bitsize;
01380       }
01381 
01382   /* Data derived from the mach spec.  */
01383   for (i = 0; i < MAX_MACHS; ++i)
01384     if (((1 << i) & machs) != 0)
01385       {
01386   const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
01387 
01388   if (mach->insn_chunk_bitsize != 0)
01389   {
01390     if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
01391       {
01392         fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
01393            cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
01394         abort ();
01395       }
01396 
01397     cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
01398   }
01399       }
01400 
01401   /* Determine which hw elements are used by MACH.  */
01402   build_hw_table (cd);
01403 
01404   /* Build the ifield table.  */
01405   build_ifield_table (cd);
01406 
01407   /* Determine which operands are used by MACH/ISA.  */
01408   build_operand_table (cd);
01409 
01410   /* Build the instruction table.  */
01411   build_insn_table (cd);
01412 }
01413 
01414 /* Initialize a cpu table and return a descriptor.
01415    It's much like opening a file, and must be the first function called.
01416    The arguments are a set of (type/value) pairs, terminated with
01417    CGEN_CPU_OPEN_END.
01418 
01419    Currently supported values:
01420    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
01421    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
01422    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
01423    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
01424    CGEN_CPU_OPEN_END:     terminates arguments
01425 
01426    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
01427    precluded.
01428 
01429    ??? We only support ISO C stdargs here, not K&R.
01430    Laziness, plus experiment to see if anything requires K&R - eventually
01431    K&R will no longer be supported - e.g. GDB is currently trying this.  */
01432 
01433 CGEN_CPU_DESC
01434 m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
01435 {
01436   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
01437   static int init_p;
01438   unsigned int isas = 0;  /* 0 = "unspecified" */
01439   unsigned int machs = 0; /* 0 = "unspecified" */
01440   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
01441   va_list ap;
01442 
01443   if (! init_p)
01444     {
01445       init_tables ();
01446       init_p = 1;
01447     }
01448 
01449   memset (cd, 0, sizeof (*cd));
01450 
01451   va_start (ap, arg_type);
01452   while (arg_type != CGEN_CPU_OPEN_END)
01453     {
01454       switch (arg_type)
01455   {
01456   case CGEN_CPU_OPEN_ISAS :
01457     isas = va_arg (ap, unsigned int);
01458     break;
01459   case CGEN_CPU_OPEN_MACHS :
01460     machs = va_arg (ap, unsigned int);
01461     break;
01462   case CGEN_CPU_OPEN_BFDMACH :
01463     {
01464       const char *name = va_arg (ap, const char *);
01465       const CGEN_MACH *mach =
01466         lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
01467 
01468       machs |= 1 << mach->num;
01469       break;
01470     }
01471   case CGEN_CPU_OPEN_ENDIAN :
01472     endian = va_arg (ap, enum cgen_endian);
01473     break;
01474   default :
01475     fprintf (stderr, "m32r_cgen_cpu_open: unsupported argument `%d'\n",
01476        arg_type);
01477     abort (); /* ??? return NULL? */
01478   }
01479       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
01480     }
01481   va_end (ap);
01482 
01483   /* mach unspecified means "all" */
01484   if (machs == 0)
01485     machs = (1 << MAX_MACHS) - 1;
01486   /* base mach is always selected */
01487   machs |= 1;
01488   /* isa unspecified means "all" */
01489   if (isas == 0)
01490     isas = (1 << MAX_ISAS) - 1;
01491   if (endian == CGEN_ENDIAN_UNKNOWN)
01492     {
01493       /* ??? If target has only one, could have a default.  */
01494       fprintf (stderr, "m32r_cgen_cpu_open: no endianness specified\n");
01495       abort ();
01496     }
01497 
01498   cd->isas = isas;
01499   cd->machs = machs;
01500   cd->endian = endian;
01501   /* FIXME: for the sparc case we can determine insn-endianness statically.
01502      The worry here is where both data and insn endian can be independently
01503      chosen, in which case this function will need another argument.
01504      Actually, will want to allow for more arguments in the future anyway.  */
01505   cd->insn_endian = endian;
01506 
01507   /* Table (re)builder.  */
01508   cd->rebuild_tables = m32r_cgen_rebuild_tables;
01509   m32r_cgen_rebuild_tables (cd);
01510 
01511   /* Default to not allowing signed overflow.  */
01512   cd->signed_overflow_ok_p = 0;
01513   
01514   return (CGEN_CPU_DESC) cd;
01515 }
01516 
01517 /* Cover fn to m32r_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
01518    MACH_NAME is the bfd name of the mach.  */
01519 
01520 CGEN_CPU_DESC
01521 m32r_cgen_cpu_open_1 (mach_name, endian)
01522      const char *mach_name;
01523      enum cgen_endian endian;
01524 {
01525   return m32r_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
01526              CGEN_CPU_OPEN_ENDIAN, endian,
01527              CGEN_CPU_OPEN_END);
01528 }
01529 
01530 /* Close a cpu table.
01531    ??? This can live in a machine independent file, but there's currently
01532    no place to put this file (there's no libcgen).  libopcodes is the wrong
01533    place as some simulator ports use this but they don't use libopcodes.  */
01534 
01535 void
01536 m32r_cgen_cpu_close (cd)
01537      CGEN_CPU_DESC cd;
01538 {
01539   unsigned int i;
01540   const CGEN_INSN *insns;
01541 
01542   if (cd->macro_insn_table.init_entries)
01543     {
01544       insns = cd->macro_insn_table.init_entries;
01545       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
01546   {
01547     if (CGEN_INSN_RX ((insns)))
01548       regfree (CGEN_INSN_RX (insns));
01549   }
01550     }
01551 
01552   if (cd->insn_table.init_entries)
01553     {
01554       insns = cd->insn_table.init_entries;
01555       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
01556   {
01557     if (CGEN_INSN_RX (insns))
01558       regfree (CGEN_INSN_RX (insns));
01559   }
01560     }
01561 
01562   
01563 
01564   if (cd->macro_insn_table.init_entries)
01565     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
01566 
01567   if (cd->insn_table.init_entries)
01568     free ((CGEN_INSN *) cd->insn_table.init_entries);
01569 
01570   if (cd->hw_table.entries)
01571     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
01572 
01573   if (cd->operand_table.entries)
01574     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
01575 
01576   free (cd);
01577 }
01578