00001 /* 00002 * Copyright 2003, 2004, 2005, 2006 PathScale, Inc. All Rights Reserved. 00003 */ 00004 00005 /* mips.h. Mips opcode list for GDB, the GNU debugger. 00006 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 00007 2003, 2004, 2005 00008 Free Software Foundation, Inc. 00009 Contributed by Ralph Campbell and OSF 00010 Commented and modified by Ian Lance Taylor, Cygnus Support 00011 00012 This file is part of GDB, GAS, and the GNU binutils. 00013 00014 GDB, GAS, and the GNU binutils are free software; you can redistribute 00015 them and/or modify them under the terms of the GNU General Public 00016 License as published by the Free Software Foundation; either version 00017 1, or (at your option) any later version. 00018 00019 GDB, GAS, and the GNU binutils are distributed in the hope that they 00020 will be useful, but WITHOUT ANY WARRANTY; without even the implied 00021 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 00022 the GNU General Public License for more details. 00023 00024 You should have received a copy of the GNU General Public License 00025 along with this file; see the file COPYING. If not, write to the Free 00026 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 00027 00028 #ifndef _MIPS_H_ 00029 #define _MIPS_H_ 00030 00031 /* These are bit masks and shift counts to use to access the various 00032 fields of an instruction. To retrieve the X field of an 00033 instruction, use the expression 00034 (i >> OP_SH_X) & OP_MASK_X 00035 To set the same field (to j), use 00036 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 00037 00038 Make sure you use fields that are appropriate for the instruction, 00039 of course. 00040 00041 The 'i' format uses OP, RS, RT and IMMEDIATE. 00042 00043 The 'j' format uses OP and TARGET. 00044 00045 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 00046 00047 The 'b' format uses OP, RS, RT and DELTA. 00048 00049 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 00050 00051 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 00052 00053 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 00054 breakpoint instruction are not defined; Kane says the breakpoint 00055 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 00056 only use ten bits). An optional two-operand form of break/sdbbp 00057 allows the lower ten bits to be set too, and MIPS32 and later 00058 architectures allow 20 bits to be set with a signal operand 00059 (using CODE20). 00060 00061 The syscall instruction uses CODE20. 00062 00063 The general coprocessor instructions use COPZ. */ 00064 00065 #define OP_MASK_OP 0x3f 00066 #define OP_SH_OP 26 00067 #define OP_MASK_RS 0x1f 00068 #define OP_SH_RS 21 00069 #define OP_MASK_FR 0x1f 00070 #define OP_SH_FR 21 00071 #define OP_MASK_FMT 0x1f 00072 #define OP_SH_FMT 21 00073 #define OP_MASK_BCC 0x7 00074 #define OP_SH_BCC 18 00075 #define OP_MASK_CODE 0x3ff 00076 #define OP_SH_CODE 16 00077 #define OP_MASK_CODE2 0x3ff 00078 #define OP_SH_CODE2 6 00079 #define OP_MASK_RT 0x1f 00080 #define OP_SH_RT 16 00081 #define OP_MASK_FT 0x1f 00082 #define OP_SH_FT 16 00083 #define OP_MASK_CACHE 0x1f 00084 #define OP_SH_CACHE 16 00085 #define OP_MASK_RD 0x1f 00086 #define OP_SH_RD 11 00087 #define OP_MASK_FS 0x1f 00088 #define OP_SH_FS 11 00089 #define OP_MASK_PREFX 0x1f 00090 #define OP_SH_PREFX 11 00091 #define OP_MASK_CCC 0x7 00092 #define OP_SH_CCC 8 00093 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 00094 #define OP_SH_CODE20 6 00095 #define OP_MASK_SHAMT 0x1f 00096 #define OP_SH_SHAMT 6 00097 #define OP_MASK_FD 0x1f 00098 #define OP_SH_FD 6 00099 #define OP_MASK_TARGET 0x3ffffff 00100 #define OP_SH_TARGET 0 00101 #define OP_MASK_COPZ 0x1ffffff 00102 #define OP_SH_COPZ 0 00103 #define OP_MASK_IMMEDIATE 0xffff 00104 #define OP_SH_IMMEDIATE 0 00105 #define OP_MASK_DELTA 0xffff 00106 #define OP_SH_DELTA 0 00107 #define OP_MASK_FUNCT 0x3f 00108 #define OP_SH_FUNCT 0 00109 #define OP_MASK_SPEC 0x3f 00110 #define OP_SH_SPEC 0 00111 #define OP_SH_LOCC 8 /* FP condition code. */ 00112 #define OP_SH_HICC 18 /* FP condition code. */ 00113 #define OP_MASK_CC 0x7 00114 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 00115 #define OP_MASK_COP1NORM 0x1 /* a single bit. */ 00116 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 00117 #define OP_MASK_COP1SPEC 0xf 00118 #define OP_MASK_COP1SCLR 0x4 00119 #define OP_MASK_COP1CMP 0x3 00120 #define OP_SH_COP1CMP 4 00121 #define OP_SH_FORMAT 21 /* FP short format field. */ 00122 #define OP_MASK_FORMAT 0x7 00123 #define OP_SH_TRUE 16 00124 #define OP_MASK_TRUE 0x1 00125 #define OP_SH_GE 17 00126 #define OP_MASK_GE 0x01 00127 #define OP_SH_UNSIGNED 16 00128 #define OP_MASK_UNSIGNED 0x1 00129 #define OP_SH_HINT 16 00130 #define OP_MASK_HINT 0x1f 00131 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 00132 #define OP_MASK_MMI 0x3f 00133 #define OP_SH_MMISUB 6 00134 #define OP_MASK_MMISUB 0x1f 00135 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 00136 #define OP_SH_PERFREG 1 00137 #define OP_SH_SEL 0 /* Coprocessor select field. */ 00138 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 00139 #define OP_SH_CODE19 6 /* 19 bit wait code. */ 00140 #define OP_MASK_CODE19 0x7ffff 00141 #define OP_SH_ALN 21 00142 #define OP_MASK_ALN 0x7 00143 #define OP_SH_VSEL 21 00144 #define OP_MASK_VSEL 0x1f 00145 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 00146 but 0x8-0xf don't select bytes. */ 00147 #define OP_SH_VECBYTE 22 00148 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 00149 #define OP_SH_VECALIGN 21 00150 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 00151 #define OP_SH_INSMSB 11 00152 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 00153 #define OP_SH_EXTMSBD 11 00154 00155 #define OP_OP_COP0 0x10 00156 #define OP_OP_COP1 0x11 00157 #define OP_OP_COP2 0x12 00158 #define OP_OP_COP3 0x13 00159 #define OP_OP_LWC1 0x31 00160 #define OP_OP_LWC2 0x32 00161 #define OP_OP_LWC3 0x33 /* a.k.a. pref */ 00162 #define OP_OP_LDC1 0x35 00163 #define OP_OP_LDC2 0x36 00164 #define OP_OP_LDC3 0x37 /* a.k.a. ld */ 00165 #define OP_OP_SWC1 0x39 00166 #define OP_OP_SWC2 0x3a 00167 #define OP_OP_SWC3 0x3b 00168 #define OP_OP_SDC1 0x3d 00169 #define OP_OP_SDC2 0x3e 00170 #define OP_OP_SDC3 0x3f /* a.k.a. sd */ 00171 00172 /* Values in the 'VSEL' field. */ 00173 #define MDMX_FMTSEL_IMM_QH 0x1d 00174 #define MDMX_FMTSEL_IMM_OB 0x1e 00175 #define MDMX_FMTSEL_VEC_QH 0x15 00176 #define MDMX_FMTSEL_VEC_OB 0x16 00177 00178 /* This structure holds information for a particular instruction. */ 00179 00180 struct mips_opcode 00181 { 00182 /* The name of the instruction. */ 00183 const char *name; 00184 /* A string describing the arguments for this instruction. */ 00185 const char *args; 00186 /* The basic opcode for the instruction. When assembling, this 00187 opcode is modified by the arguments to produce the actual opcode 00188 that is used. If pinfo is INSN_MACRO, then this is 0. */ 00189 unsigned long match; 00190 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 00191 relevant portions of the opcode when disassembling. If the 00192 actual opcode anded with the match field equals the opcode field, 00193 then we have found the correct instruction. If pinfo is 00194 INSN_MACRO, then this field is the macro identifier. */ 00195 unsigned long mask; 00196 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 00197 of bits describing the instruction, notably any relevant hazard 00198 information. */ 00199 unsigned long pinfo; 00200 /* A collection of additional bits describing the instruction. */ 00201 unsigned long pinfo2; 00202 /* A collection of bits describing the instruction sets of which this 00203 instruction or macro is a member. */ 00204 unsigned long membership; 00205 }; 00206 00207 /* These are the characters which may appear in the args field of an 00208 instruction. They appear in the order in which the fields appear 00209 when the instruction is used. Commas and parentheses in the args 00210 string are ignored when assembling, and written into the output 00211 when disassembling. 00212 00213 Each of these characters corresponds to a mask field defined above. 00214 00215 "<" 5 bit shift amount (OP_*_SHAMT) 00216 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 00217 "a" 26 bit target address (OP_*_TARGET) 00218 "b" 5 bit base register (OP_*_RS) 00219 "c" 10 bit breakpoint code (OP_*_CODE) 00220 "d" 5 bit destination register specifier (OP_*_RD) 00221 "h" 5 bit prefx hint (OP_*_PREFX) 00222 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 00223 "j" 16 bit signed immediate (OP_*_DELTA) 00224 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 00225 Also used for immediate operands in vr5400 vector insns. 00226 "o" 16 bit signed offset (OP_*_DELTA) 00227 "p" 16 bit PC relative branch target address (OP_*_DELTA) 00228 "q" 10 bit extra breakpoint code (OP_*_CODE2) 00229 "r" 5 bit same register used as both source and target (OP_*_RS) 00230 "s" 5 bit source register specifier (OP_*_RS) 00231 "t" 5 bit target register (OP_*_RT) 00232 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 00233 "v" 5 bit same register used as both source and destination (OP_*_RS) 00234 "w" 5 bit same register used as both target and destination (OP_*_RT) 00235 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 00236 (used by clo and clz) 00237 "C" 25 bit coprocessor function code (OP_*_COPZ) 00238 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 00239 "J" 19 bit wait function code (OP_*_CODE19) 00240 "x" accept and ignore register name 00241 "z" must be zero register 00242 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 00243 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). 00244 Enforces: 0 <= pos < 32. 00245 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). 00246 Requires that "+A" or "+E" occur first to set position. 00247 Enforces: 0 < (pos+size) <= 32. 00248 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). 00249 Requires that "+A" or "+E" occur first to set position. 00250 Enforces: 0 < (pos+size) <= 32. 00251 (Also used by "dext" w/ different limits, but limits for 00252 that are checked by the M_DEXT macro.) 00253 "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). 00254 Enforces: 32 <= pos < 64. 00255 "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). 00256 Requires that "+A" or "+E" occur first to set position. 00257 Enforces: 32 < (pos+size) <= 64. 00258 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 00259 Requires that "+A" or "+E" occur first to set position. 00260 Enforces: 32 < (pos+size) <= 64. 00261 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 00262 Requires that "+A" or "+E" occur first to set position. 00263 Enforces: 32 < (pos+size) <= 64. 00264 00265 Floating point instructions: 00266 "D" 5 bit destination register (OP_*_FD) 00267 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 00268 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 00269 "S" 5 bit fs source 1 register (OP_*_FS) 00270 "T" 5 bit ft source 2 register (OP_*_FT) 00271 "R" 5 bit fr source 3 register (OP_*_FR) 00272 "V" 5 bit same register used as floating source and destination (OP_*_FS) 00273 "W" 5 bit same register used as floating target and destination (OP_*_FT) 00274 00275 Coprocessor instructions: 00276 "E" 5 bit target register (OP_*_RT) 00277 "G" 5 bit destination register (OP_*_RD) 00278 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 00279 "P" 5 bit performance-monitor register (OP_*_PERFREG) 00280 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 00281 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 00282 see also "k" above 00283 "+D" Combined destination register ("G") and sel ("H") for CP0 ops, 00284 for pretty-printing in disassembly only. 00285 00286 Macro instructions: 00287 "A" General 32 bit expression 00288 "I" 32 bit immediate (value placed in imm_expr). 00289 "+I" 32 bit immediate (value placed in imm2_expr). 00290 "F" 64 bit floating point constant in .rdata 00291 "L" 64 bit floating point constant in .lit8 00292 "f" 32 bit floating point constant 00293 "l" 32 bit floating point constant in .lit4 00294 00295 MDMX instruction operands (note that while these use the FP register 00296 fields, they accept both $fN and $vN names for the registers): 00297 "O" MDMX alignment offset (OP_*_ALN) 00298 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 00299 "X" MDMX destination register (OP_*_FD) 00300 "Y" MDMX source register (OP_*_FS) 00301 "Z" MDMX source register (OP_*_FT) 00302 00303 Other: 00304 "()" parens surrounding optional value 00305 "," separates operands 00306 "[]" brackets around index for vector-op scalar operand specifier (vr5400) 00307 "+" Start of extension sequence. 00308 00309 Characters used so far, for quick reference when adding more: 00310 "%[]<>(),+" 00311 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 00312 "abcdefhijklopqrstuvwxz" 00313 00314 Extension character sequences used so far ("+" followed by the 00315 following), for quick reference when adding more: 00316 "ABCDEFGHI" 00317 */ 00318 00319 /* These are the bits which may be set in the pinfo field of an 00320 instructions, if it is not equal to INSN_MACRO. */ 00321 00322 /* Modifies the general purpose register in OP_*_RD. */ 00323 #define INSN_WRITE_GPR_D 0x00000001 00324 /* Modifies the general purpose register in OP_*_RT. */ 00325 #define INSN_WRITE_GPR_T 0x00000002 00326 /* Modifies general purpose register 31. */ 00327 #define INSN_WRITE_GPR_31 0x00000004 00328 /* Modifies the floating point register in OP_*_FD. */ 00329 #define INSN_WRITE_FPR_D 0x00000008 00330 /* Modifies the floating point register in OP_*_FS. */ 00331 #define INSN_WRITE_FPR_S 0x00000010 00332 /* Modifies the floating point register in OP_*_FT. */ 00333 #define INSN_WRITE_FPR_T 0x00000020 00334 /* Reads the general purpose register in OP_*_RS. */ 00335 #define INSN_READ_GPR_S 0x00000040 00336 /* Reads the general purpose register in OP_*_RT. */ 00337 #define INSN_READ_GPR_T 0x00000080 00338 /* Reads the floating point register in OP_*_FS. */ 00339 #define INSN_READ_FPR_S 0x00000100 00340 /* Reads the floating point register in OP_*_FT. */ 00341 #define INSN_READ_FPR_T 0x00000200 00342 /* Reads the floating point register in OP_*_FR. */ 00343 #define INSN_READ_FPR_R 0x00000400 00344 /* Modifies coprocessor condition code. */ 00345 #define INSN_WRITE_COND_CODE 0x00000800 00346 /* Reads coprocessor condition code. */ 00347 #define INSN_READ_COND_CODE 0x00001000 00348 /* TLB operation. */ 00349 #define INSN_TLB 0x00002000 00350 /* Reads coprocessor register other than floating point register. */ 00351 #define INSN_COP 0x00004000 00352 /* Instruction loads value from memory, requiring delay. */ 00353 #define INSN_LOAD_MEMORY_DELAY 0x00008000 00354 /* Instruction loads value from coprocessor, requiring delay. */ 00355 #define INSN_LOAD_COPROC_DELAY 0x00010000 00356 /* Instruction has unconditional branch delay slot. */ 00357 #define INSN_UNCOND_BRANCH_DELAY 0x00020000 00358 /* Instruction has conditional branch delay slot. */ 00359 #define INSN_COND_BRANCH_DELAY 0x00040000 00360 /* Conditional branch likely: if branch not taken, insn nullified. */ 00361 #define INSN_COND_BRANCH_LIKELY 0x00080000 00362 /* Moves to coprocessor register, requiring delay. */ 00363 #define INSN_COPROC_MOVE_DELAY 0x00100000 00364 /* Loads coprocessor register from memory, requiring delay. */ 00365 #define INSN_COPROC_MEMORY_DELAY 0x00200000 00366 /* Reads the HI register. */ 00367 #define INSN_READ_HI 0x00400000 00368 /* Reads the LO register. */ 00369 #define INSN_READ_LO 0x00800000 00370 /* Modifies the HI register. */ 00371 #define INSN_WRITE_HI 0x01000000 00372 /* Modifies the LO register. */ 00373 #define INSN_WRITE_LO 0x02000000 00374 /* Takes a trap (easier to keep out of delay slot). */ 00375 #define INSN_TRAP 0x04000000 00376 /* Instruction stores value into memory. */ 00377 #define INSN_STORE_MEMORY 0x08000000 00378 /* Instruction uses single precision floating point. */ 00379 #define FP_S 0x10000000 00380 /* Instruction uses double precision floating point. */ 00381 #define FP_D 0x20000000 00382 /* Instruction is part of the tx39's integer multiply family. */ 00383 #define INSN_MULT 0x40000000 00384 /* Instruction synchronize shared memory. */ 00385 #define INSN_SYNC 0x80000000 00386 00387 /* These are the bits which may be set in the pinfo2 field of an 00388 instruction. */ 00389 00390 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 00391 #define INSN2_ALIAS 0x00000001 00392 /* Instruction reads MDMX accumulator. */ 00393 #define INSN2_READ_MDMX_ACC 0x00000002 00394 /* Instruction writes MDMX accumulator. */ 00395 #define INSN2_WRITE_MDMX_ACC 0x00000004 00396 00397 /* Instruction is actually a macro. It should be ignored by the 00398 disassembler, and requires special treatment by the assembler. */ 00399 #define INSN_MACRO 0xffffffff 00400 00401 /* Masks used to mark instructions to indicate which MIPS ISA level 00402 they were introduced in. ISAs, as defined below, are logical 00403 ORs of these bits, indicating that they support the instructions 00404 defined at the given level. */ 00405 00406 #define INSN_ISA_MASK 0x00000fff 00407 #define INSN_ISA1 0x00000001 00408 #define INSN_ISA2 0x00000002 00409 #define INSN_ISA3 0x00000004 00410 #define INSN_ISA4 0x00000008 00411 #define INSN_ISA5 0x00000010 00412 #define INSN_ISA32 0x00000020 00413 #define INSN_ISA64 0x00000040 00414 #define INSN_ISA32R2 0x00000080 00415 #define INSN_ISA64R2 0x00000100 00416 00417 /* Masks used for MIPS-defined ASEs. */ 00418 #define INSN_ASE_MASK 0x0000f000 00419 00420 /* MIPS 16 ASE */ 00421 #define INSN_MIPS16 0x00002000 00422 /* MIPS-3D ASE */ 00423 #define INSN_MIPS3D 0x00004000 00424 /* MDMX ASE */ 00425 #define INSN_MDMX 0x00008000 00426 00427 /* Chip specific instructions. These are bitmasks. */ 00428 00429 /* MIPS R4650 instruction. */ 00430 #define INSN_4650 0x00010000 00431 /* LSI R4010 instruction. */ 00432 #define INSN_4010 0x00020000 00433 /* NEC VR4100 instruction. */ 00434 #define INSN_4100 0x00040000 00435 /* Toshiba R3900 instruction. */ 00436 #define INSN_3900 0x00080000 00437 /* MIPS R10000 instruction. */ 00438 #define INSN_10000 0x00100000 00439 /* Broadcom SB-1 instruction. */ 00440 #define INSN_SB1 0x00200000 00441 /* NEC VR4111/VR4181 instruction. */ 00442 #define INSN_4111 0x00400000 00443 /* NEC VR4120 instruction. */ 00444 #define INSN_4120 0x00800000 00445 /* NEC VR5400 instruction. */ 00446 #define INSN_5400 0x01000000 00447 /* NEC VR5500 instruction. */ 00448 #define INSN_5500 0x02000000 00449 00450 /* MIPS ISA defines, use instead of hardcoding ISA level. */ 00451 00452 #define ISA_UNKNOWN 0 /* Gas internal use. */ 00453 #define ISA_MIPS1 (INSN_ISA1) 00454 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) 00455 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) 00456 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) 00457 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) 00458 00459 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) 00460 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) 00461 00462 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) 00463 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) 00464 00465 00466 /* CPU defines, use instead of hardcoding processor number. Keep this 00467 in sync with bfd/archures.c in order for machine selection to work. */ 00468 #define CPU_UNKNOWN 0 /* Gas internal use. */ 00469 #define CPU_R3000 3000 00470 #define CPU_R3900 3900 00471 #define CPU_R4000 4000 00472 #define CPU_R4010 4010 00473 #define CPU_VR4100 4100 00474 #define CPU_R4111 4111 00475 #define CPU_VR4120 4120 00476 #define CPU_R4300 4300 00477 #define CPU_R4400 4400 00478 #define CPU_R4600 4600 00479 #define CPU_R4650 4650 00480 #define CPU_R5000 5000 00481 #define CPU_VR5400 5400 00482 #define CPU_VR5500 5500 00483 #define CPU_R6000 6000 00484 #define CPU_RM7000 7000 00485 #define CPU_R8000 8000 00486 #define CPU_RM9000 9000 00487 #define CPU_R10000 10000 00488 #define CPU_R12000 12000 00489 #define CPU_MIPS16 16 00490 #define CPU_MIPS32 32 00491 #define CPU_MIPS32R2 33 00492 #define CPU_MIPS5 5 00493 #define CPU_MIPS64 64 00494 #define CPU_MIPS64R2 65 00495 #define CPU_SB1 12310201 /* octal 'SB', 01. */ 00496 00497 /* Test for membership in an ISA including chip specific ISAs. INSN 00498 is pointer to an element of the opcode table; ISA is the specified 00499 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 00500 test, or zero if no CPU specific ISA test is desired. */ 00501 00502 #define OPCODE_IS_MEMBER(insn, isa, cpu) \ 00503 (((insn)->membership & isa) != 0 \ 00504 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ 00505 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ 00506 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ 00507 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ 00508 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ 00509 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ 00510 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ 00511 && ((insn)->membership & INSN_10000) != 0) \ 00512 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ 00513 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ 00514 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ 00515 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ 00516 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ 00517 || 0) /* Please keep this term for easier source merging. */ 00518 00519 /* This is a list of macro expanded instructions. 00520 00521 _I appended means immediate 00522 _A appended means address 00523 _AB appended means address with base register 00524 _D appended means 64 bit floating point constant 00525 _S appended means 32 bit floating point constant. */ 00526 00527 enum 00528 { 00529 M_ABS, 00530 M_ADD_I, 00531 M_ADDU_I, 00532 M_AND_I, 00533 M_BEQ, 00534 M_BEQ_I, 00535 M_BEQL_I, 00536 M_BGE, 00537 M_BGEL, 00538 M_BGE_I, 00539 M_BGEL_I, 00540 M_BGEU, 00541 M_BGEUL, 00542 M_BGEU_I, 00543 M_BGEUL_I, 00544 M_BGT, 00545 M_BGTL, 00546 M_BGT_I, 00547 M_BGTL_I, 00548 M_BGTU, 00549 M_BGTUL, 00550 M_BGTU_I, 00551 M_BGTUL_I, 00552 M_BLE, 00553 M_BLEL, 00554 M_BLE_I, 00555 M_BLEL_I, 00556 M_BLEU, 00557 M_BLEUL, 00558 M_BLEU_I, 00559 M_BLEUL_I, 00560 M_BLT, 00561 M_BLTL, 00562 M_BLT_I, 00563 M_BLTL_I, 00564 M_BLTU, 00565 M_BLTUL, 00566 M_BLTU_I, 00567 M_BLTUL_I, 00568 M_BNE, 00569 M_BNE_I, 00570 M_BNEL_I, 00571 M_DABS, 00572 M_DADD_I, 00573 M_DADDU_I, 00574 M_DDIV_3, 00575 M_DDIV_3I, 00576 M_DDIVU_3, 00577 M_DDIVU_3I, 00578 M_DEXT, 00579 M_DINS, 00580 M_DIV_3, 00581 M_DIV_3I, 00582 M_DIVU_3, 00583 M_DIVU_3I, 00584 M_DLA_AB, 00585 M_DLCA_AB, 00586 M_DLI, 00587 M_DMUL, 00588 M_DMUL_I, 00589 M_DMULO, 00590 M_DMULO_I, 00591 M_DMULOU, 00592 M_DMULOU_I, 00593 M_DREM_3, 00594 M_DREM_3I, 00595 M_DREMU_3, 00596 M_DREMU_3I, 00597 M_DSUB_I, 00598 M_DSUBU_I, 00599 M_DSUBU_I_2, 00600 M_J_A, 00601 M_JAL_1, 00602 M_JAL_2, 00603 M_JAL_A, 00604 M_L_DOB, 00605 M_L_DAB, 00606 M_LA_AB, 00607 M_LB_A, 00608 M_LB_AB, 00609 M_LBU_A, 00610 M_LBU_AB, 00611 M_LCA_AB, 00612 M_LD_A, 00613 M_LD_OB, 00614 M_LD_AB, 00615 M_LDC1_AB, 00616 M_LDC2_AB, 00617 M_LDC3_AB, 00618 M_LDL_AB, 00619 M_LDR_AB, 00620 M_LH_A, 00621 M_LH_AB, 00622 M_LHU_A, 00623 M_LHU_AB, 00624 M_LI, 00625 M_LI_D, 00626 M_LI_DD, 00627 M_LI_S, 00628 M_LI_SS, 00629 M_LL_AB, 00630 M_LLD_AB, 00631 M_LS_A, 00632 M_LW_A, 00633 M_LW_AB, 00634 M_LWC0_A, 00635 M_LWC0_AB, 00636 M_LWC1_A, 00637 M_LWC1_AB, 00638 M_LWC2_A, 00639 M_LWC2_AB, 00640 M_LWC3_A, 00641 M_LWC3_AB, 00642 M_LWL_A, 00643 M_LWL_AB, 00644 M_LWR_A, 00645 M_LWR_AB, 00646 M_LWU_AB, 00647 M_MOVE, 00648 M_MUL, 00649 M_MUL_I, 00650 M_MULO, 00651 M_MULO_I, 00652 M_MULOU, 00653 M_MULOU_I, 00654 M_NOR_I, 00655 M_OR_I, 00656 M_REM_3, 00657 M_REM_3I, 00658 M_REMU_3, 00659 M_REMU_3I, 00660 M_DROL, 00661 M_ROL, 00662 M_DROL_I, 00663 M_ROL_I, 00664 M_DROR, 00665 M_ROR, 00666 M_DROR_I, 00667 M_ROR_I, 00668 M_S_DA, 00669 M_S_DOB, 00670 M_S_DAB, 00671 M_S_S, 00672 M_SC_AB, 00673 M_SCD_AB, 00674 M_SD_A, 00675 M_SD_OB, 00676 M_SD_AB, 00677 M_SDC1_AB, 00678 M_SDC2_AB, 00679 M_SDC3_AB, 00680 M_SDL_AB, 00681 M_SDR_AB, 00682 M_SEQ, 00683 M_SEQ_I, 00684 M_SGE, 00685 M_SGE_I, 00686 M_SGEU, 00687 M_SGEU_I, 00688 M_SGT, 00689 M_SGT_I, 00690 M_SGTU, 00691 M_SGTU_I, 00692 M_SLE, 00693 M_SLE_I, 00694 M_SLEU, 00695 M_SLEU_I, 00696 M_SLT_I, 00697 M_SLTU_I, 00698 M_SNE, 00699 M_SNE_I, 00700 M_SB_A, 00701 M_SB_AB, 00702 M_SH_A, 00703 M_SH_AB, 00704 M_SW_A, 00705 M_SW_AB, 00706 M_SWC0_A, 00707 M_SWC0_AB, 00708 M_SWC1_A, 00709 M_SWC1_AB, 00710 M_SWC2_A, 00711 M_SWC2_AB, 00712 M_SWC3_A, 00713 M_SWC3_AB, 00714 M_SWL_A, 00715 M_SWL_AB, 00716 M_SWR_A, 00717 M_SWR_AB, 00718 M_SUB_I, 00719 M_SUBU_I, 00720 M_SUBU_I_2, 00721 M_TEQ_I, 00722 M_TGE_I, 00723 M_TGEU_I, 00724 M_TLT_I, 00725 M_TLTU_I, 00726 M_TNE_I, 00727 M_TRUNCWD, 00728 M_TRUNCWS, 00729 M_ULD, 00730 M_ULD_A, 00731 M_ULH, 00732 M_ULH_A, 00733 M_ULHU, 00734 M_ULHU_A, 00735 M_ULW, 00736 M_ULW_A, 00737 M_USH, 00738 M_USH_A, 00739 M_USW, 00740 M_USW_A, 00741 M_USD, 00742 M_USD_A, 00743 M_XOR_I, 00744 M_COP0, 00745 M_COP1, 00746 M_COP2, 00747 M_COP3, 00748 M_NUM_MACROS 00749 }; 00750 00751 00752 /* The order of overloaded instructions matters. Label arguments and 00753 register arguments look the same. Instructions that can have either 00754 for arguments must apear in the correct order in this table for the 00755 assembler to pick the right one. In other words, entries with 00756 immediate operands must apear after the same instruction with 00757 registers. 00758 00759 Many instructions are short hand for other instructions (i.e., The 00760 jal <register> instruction is short for jalr <register>). */ 00761 00762 extern const struct mips_opcode mips_builtin_opcodes[]; 00763 extern const int bfd_mips_num_builtin_opcodes; 00764 extern struct mips_opcode *mips_opcodes; 00765 extern int bfd_mips_num_opcodes; 00766 #define NUMOPCODES bfd_mips_num_opcodes 00767 00768 00769 /* The rest of this file adds definitions for the mips16 TinyRISC 00770 processor. */ 00771 00772 /* These are the bitmasks and shift counts used for the different 00773 fields in the instruction formats. Other than OP, no masks are 00774 provided for the fixed portions of an instruction, since they are 00775 not needed. 00776 00777 The I format uses IMM11. 00778 00779 The RI format uses RX and IMM8. 00780 00781 The RR format uses RX, and RY. 00782 00783 The RRI format uses RX, RY, and IMM5. 00784 00785 The RRR format uses RX, RY, and RZ. 00786 00787 The RRI_A format uses RX, RY, and IMM4. 00788 00789 The SHIFT format uses RX, RY, and SHAMT. 00790 00791 The I8 format uses IMM8. 00792 00793 The I8_MOVR32 format uses RY and REGR32. 00794 00795 The IR_MOV32R format uses REG32R and MOV32Z. 00796 00797 The I64 format uses IMM8. 00798 00799 The RI64 format uses RY and IMM5. 00800 */ 00801 00802 #define MIPS16OP_MASK_OP 0x1f 00803 #define MIPS16OP_SH_OP 11 00804 #define MIPS16OP_MASK_IMM11 0x7ff 00805 #define MIPS16OP_SH_IMM11 0 00806 #define MIPS16OP_MASK_RX 0x7 00807 #define MIPS16OP_SH_RX 8 00808 #define MIPS16OP_MASK_IMM8 0xff 00809 #define MIPS16OP_SH_IMM8 0 00810 #define MIPS16OP_MASK_RY 0x7 00811 #define MIPS16OP_SH_RY 5 00812 #define MIPS16OP_MASK_IMM5 0x1f 00813 #define MIPS16OP_SH_IMM5 0 00814 #define MIPS16OP_MASK_RZ 0x7 00815 #define MIPS16OP_SH_RZ 2 00816 #define MIPS16OP_MASK_IMM4 0xf 00817 #define MIPS16OP_SH_IMM4 0 00818 #define MIPS16OP_MASK_REGR32 0x1f 00819 #define MIPS16OP_SH_REGR32 0 00820 #define MIPS16OP_MASK_REG32R 0x1f 00821 #define MIPS16OP_SH_REG32R 3 00822 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 00823 #define MIPS16OP_MASK_MOVE32Z 0x7 00824 #define MIPS16OP_SH_MOVE32Z 0 00825 #define MIPS16OP_MASK_IMM6 0x3f 00826 #define MIPS16OP_SH_IMM6 5 00827 00828 /* These are the characters which may appears in the args field of an 00829 instruction. They appear in the order in which the fields appear 00830 when the instruction is used. Commas and parentheses in the args 00831 string are ignored when assembling, and written into the output 00832 when disassembling. 00833 00834 "y" 3 bit register (MIPS16OP_*_RY) 00835 "x" 3 bit register (MIPS16OP_*_RX) 00836 "z" 3 bit register (MIPS16OP_*_RZ) 00837 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 00838 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 00839 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 00840 "0" zero register ($0) 00841 "S" stack pointer ($sp or $29) 00842 "P" program counter 00843 "R" return address register ($ra or $31) 00844 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 00845 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 00846 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 00847 "a" 26 bit jump address 00848 "e" 11 bit extension value 00849 "l" register list for entry instruction 00850 "L" register list for exit instruction 00851 00852 The remaining codes may be extended. Except as otherwise noted, 00853 the full extended operand is a 16 bit signed value. 00854 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 00855 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 00856 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 00857 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 00858 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 00859 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 00860 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 00861 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 00862 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 00863 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 00864 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 00865 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 00866 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 00867 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 00868 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 00869 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 00870 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 00871 "q" 11 bit branch address (MIPS16OP_*_IMM11) 00872 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 00873 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 00874 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 00875 */ 00876 00877 /* For the mips16, we use the same opcode table format and a few of 00878 the same flags. However, most of the flags are different. */ 00879 00880 /* Modifies the register in MIPS16OP_*_RX. */ 00881 #define MIPS16_INSN_WRITE_X 0x00000001 00882 /* Modifies the register in MIPS16OP_*_RY. */ 00883 #define MIPS16_INSN_WRITE_Y 0x00000002 00884 /* Modifies the register in MIPS16OP_*_RZ. */ 00885 #define MIPS16_INSN_WRITE_Z 0x00000004 00886 /* Modifies the T ($24) register. */ 00887 #define MIPS16_INSN_WRITE_T 0x00000008 00888 /* Modifies the SP ($29) register. */ 00889 #define MIPS16_INSN_WRITE_SP 0x00000010 00890 /* Modifies the RA ($31) register. */ 00891 #define MIPS16_INSN_WRITE_31 0x00000020 00892 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ 00893 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 00894 /* Reads the register in MIPS16OP_*_RX. */ 00895 #define MIPS16_INSN_READ_X 0x00000080 00896 /* Reads the register in MIPS16OP_*_RY. */ 00897 #define MIPS16_INSN_READ_Y 0x00000100 00898 /* Reads the register in MIPS16OP_*_MOVE32Z. */ 00899 #define MIPS16_INSN_READ_Z 0x00000200 00900 /* Reads the T ($24) register. */ 00901 #define MIPS16_INSN_READ_T 0x00000400 00902 /* Reads the SP ($29) register. */ 00903 #define MIPS16_INSN_READ_SP 0x00000800 00904 /* Reads the RA ($31) register. */ 00905 #define MIPS16_INSN_READ_31 0x00001000 00906 /* Reads the program counter. */ 00907 #define MIPS16_INSN_READ_PC 0x00002000 00908 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ 00909 #define MIPS16_INSN_READ_GPR_X 0x00004000 00910 /* Is a branch insn. */ 00911 #define MIPS16_INSN_BRANCH 0x00010000 00912 00913 /* The following flags have the same value for the mips16 opcode 00914 table: 00915 INSN_UNCOND_BRANCH_DELAY 00916 INSN_COND_BRANCH_DELAY 00917 INSN_COND_BRANCH_LIKELY (never used) 00918 INSN_READ_HI 00919 INSN_READ_LO 00920 INSN_WRITE_HI 00921 INSN_WRITE_LO 00922 INSN_TRAP 00923 INSN_ISA3 00924 */ 00925 00926 extern const struct mips_opcode mips16_opcodes[]; 00927 extern const int bfd_mips16_num_opcodes; 00928 00929 #endif /* _MIPS_H_ */
1.5.6