osprey/kg++fe/gnu/combine.c

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/* Optimize by combining instructions for GNU compiler.
   Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2, or (at your option) any later
version.

GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING.  If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA.  */

/* This module is essentially the "combiner" phase of the U. of Arizona
   Portable Optimizer, but redone to work on our list-structured
   representation for RTL instead of their string representation.

   The LOG_LINKS of each insn identify the most recent assignment
   to each REG used in the insn.  It is a list of previous insns,
   each of which contains a SET for a REG that is used in this insn
   and not used or set in between.  LOG_LINKs never cross basic blocks.
   They were set up by the preceding pass (lifetime analysis).

   We try to combine each pair of insns joined by a logical link.
   We also try to combine triples of insns A, B and C when
   C has a link back to B and B has a link back to A.

   LOG_LINKS does not have links for use of the CC0.  They don't
   need to, because the insn that sets the CC0 is always immediately
   before the insn that tests it.  So we always regard a branch
   insn as having a logical link to the preceding insn.  The same is true
   for an insn explicitly using CC0.

   We check (with use_crosses_set_p) to avoid combining in such a way
   as to move a computation to a place where its value would be different.

   Combination is done by mathematically substituting the previous
   insn(s) values for the regs they set into the expressions in
   the later insns that refer to these regs.  If the result is a valid insn
   for our target machine, according to the machine description,
   we install it, delete the earlier insns, and update the data flow
   information (LOG_LINKS and REG_NOTES) for what we did.

   There are a few exceptions where the dataflow information created by
   flow.c aren't completely updated:

   - reg_live_length is not updated
   - reg_n_refs is not adjusted in the rare case when a register is
     no longer required in a computation
   - there are extremely rare cases (see distribute_regnotes) when a
     REG_DEAD note is lost
   - a LOG_LINKS entry that refers to an insn with multiple SETs may be
     removed because there is no way to know which register it was
     linking

   To simplify substitution, we combine only when the earlier insn(s)
   consist of only a single assignment.  To simplify updating afterward,
   we never combine when a subroutine call appears in the middle.

   Since we do not represent assignments to CC0 explicitly except when that
   is all an insn does, there is no LOG_LINKS entry in an insn that uses
   the condition code for the insn that set the condition code.
   Fortunately, these two insns must be consecutive.
   Therefore, every JUMP_INSN is taken to have an implicit logical link
   to the preceding insn.  This is not quite right, since non-jumps can
   also use the condition code; but in practice such insns would not
   combine anyway.  */

#include "config.h"
#include "system.h"
#include "rtl.h"
#include "tm_p.h"
#include "flags.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "basic-block.h"
#include "insn-config.h"
#include "function.h"
/* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
#include "expr.h"
#include "insn-attr.h"
#include "recog.h"
#include "real.h"
#include "toplev.h"

/* It is not safe to use ordinary gen_lowpart in combine.
   Use gen_lowpart_for_combine instead.  See comments there.  */
#define gen_lowpart dont_use_gen_lowpart_you_dummy

/* Number of attempts to combine instructions in this function.  */

static int combine_attempts;

/* Number of attempts that got as far as substitution in this function.  */

static int combine_merges;

/* Number of instructions combined with added SETs in this function.  */

static int combine_extras;

/* Number of instructions combined in this function.  */

static int combine_successes;

/* Totals over entire compilation.  */

static int total_attempts, total_merges, total_extras, total_successes;


/* Vector mapping INSN_UIDs to cuids.
   The cuids are like uids but increase monotonically always.
   Combine always uses cuids so that it can compare them.
   But actually renumbering the uids, which we used to do,
   proves to be a bad idea because it makes it hard to compare
   the dumps produced by earlier passes with those from later passes.  */

static int *uid_cuid;
static int max_uid_cuid;

/* Get the cuid of an insn.  */

#define INSN_CUID(INSN) \
(INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])

/* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
   BITS_PER_WORD would invoke undefined behavior.  Work around it.  */

#define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
  (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)

#define nonzero_bits(X, M) \
  cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)

#define num_sign_bit_copies(X, M) \
  cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)

/* Maximum register number, which is the size of the tables below.  */

static unsigned int combine_max_regno;

/* Record last point of death of (hard or pseudo) register n.  */

static rtx *reg_last_death;

/* Record last point of modification of (hard or pseudo) register n.  */

static rtx *reg_last_set;

/* Record the cuid of the last insn that invalidated memory
   (anything that writes memory, and subroutine calls, but not pushes).  */

static int mem_last_set;

/* Record the cuid of the last CALL_INSN
   so we can tell whether a potential combination crosses any calls.  */

static int last_call_cuid;

/* When `subst' is called, this is the insn that is being modified
   (by combining in a previous insn).  The PATTERN of this insn
   is still the old pattern partially modified and it should not be
   looked at, but this may be used to examine the successors of the insn
   to judge whether a simplification is valid.  */

static rtx subst_insn;

/* This is an insn that belongs before subst_insn, but is not currently
   on the insn chain.  */

static rtx subst_prev_insn;

/* This is the lowest CUID that `subst' is currently dealing with.
   get_last_value will not return a value if the register was set at or
   after this CUID.  If not for this mechanism, we could get confused if
   I2 or I1 in try_combine were an insn that used the old value of a register
   to obtain a new value.  In that case, we might erroneously get the
   new value of the register when we wanted the old one.  */

static int subst_low_cuid;

/* This contains any hard registers that are used in newpat; reg_dead_at_p
   must consider all these registers to be always live.  */

static HARD_REG_SET newpat_used_regs;

/* This is an insn to which a LOG_LINKS entry has been added.  If this
   insn is the earlier than I2 or I3, combine should rescan starting at
   that location.  */

static rtx added_links_insn;

/* Basic block in which we are performing combines.  */
static basic_block this_basic_block;

/* A bitmap indicating which blocks had registers go dead at entry.
   After combine, we'll need to re-do global life analysis with
   those blocks as starting points.  */
static sbitmap refresh_blocks;
static int need_refresh;

/* The next group of arrays allows the recording of the last value assigned
   to (hard or pseudo) register n.  We use this information to see if an
   operation being processed is redundant given a prior operation performed
   on the register.  For example, an `and' with a constant is redundant if
   all the zero bits are already known to be turned off.

   We use an approach similar to that used by cse, but change it in the
   following ways:

   (1) We do not want to reinitialize at each label.
   (2) It is useful, but not critical, to know the actual value assigned
       to a register.  Often just its form is helpful.

   Therefore, we maintain the following arrays:

   reg_last_set_value   the last value assigned
   reg_last_set_label   records the value of label_tick when the
        register was assigned
   reg_last_set_table_tick  records the value of label_tick when a
        value using the register is assigned
   reg_last_set_invalid   set to nonzero when it is not valid
        to use the value of this register in some
        register's value

   To understand the usage of these tables, it is important to understand
   the distinction between the value in reg_last_set_value being valid
   and the register being validly contained in some other expression in the
   table.

   Entry I in reg_last_set_value is valid if it is nonzero, and either
   reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.

   Register I may validly appear in any expression returned for the value
   of another register if reg_n_sets[i] is 1.  It may also appear in the
   value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
   reg_last_set_invalid[j] is zero.

   If an expression is found in the table containing a register which may
   not validly appear in an expression, the register is replaced by
   something that won't match, (clobber (const_int 0)).

   reg_last_set_invalid[i] is set nonzero when register I is being assigned
   to and reg_last_set_table_tick[i] == label_tick.  */

/* Record last value assigned to (hard or pseudo) register n.  */

static rtx *reg_last_set_value;

/* Record the value of label_tick when the value for register n is placed in
   reg_last_set_value[n].  */

static int *reg_last_set_label;

/* Record the value of label_tick when an expression involving register n
   is placed in reg_last_set_value.  */

static int *reg_last_set_table_tick;

/* Set nonzero if references to register n in expressions should not be
   used.  */

static char *reg_last_set_invalid;

/* Incremented for each label.  */

static int label_tick;

/* Some registers that are set more than once and used in more than one
   basic block are nevertheless always set in similar ways.  For example,
   a QImode register may be loaded from memory in two places on a machine
   where byte loads zero extend.

   We record in the following array what we know about the nonzero
   bits of a register, specifically which bits are known to be zero.

   If an entry is zero, it means that we don't know anything special.  */

static unsigned HOST_WIDE_INT *reg_nonzero_bits;

/* Mode used to compute significance in reg_nonzero_bits.  It is the largest
   integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */

static enum machine_mode nonzero_bits_mode;

/* Nonzero if we know that a register has some leading bits that are always
   equal to the sign bit.  */

static unsigned char *reg_sign_bit_copies;

/* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
   It is zero while computing them and after combine has completed.  This
   former test prevents propagating values based on previously set values,
   which can be incorrect if a variable is modified in a loop.  */

static int nonzero_sign_valid;

/* These arrays are maintained in parallel with reg_last_set_value
   and are used to store the mode in which the register was last set,
   the bits that were known to be zero when it was last set, and the
   number of sign bits copies it was known to have when it was last set.  */

static enum machine_mode *reg_last_set_mode;
static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
static char *reg_last_set_sign_bit_copies;

/* Record one modification to rtl structure
   to be undone by storing old_contents into *where.
   is_int is 1 if the contents are an int.  */

struct undo
{
  struct undo *next;
  int is_int;
  union {rtx r; int i;} old_contents;
  union {rtx *r; int *i;} where;
};

/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
   num_undo says how many are currently recorded.

   other_insn is nonzero if we have modified some other insn in the process
   of working on subst_insn.  It must be verified too.  */

struct undobuf
{
  struct undo *undos;
  struct undo *frees;
  rtx other_insn;
};

static struct undobuf undobuf;

/* Number of times the pseudo being substituted for
   was found and replaced.  */

static int n_occurrences;

static void do_SUBST      PARAMS ((rtx *, rtx));
static void do_SUBST_INT    PARAMS ((int *, int));
static void init_reg_last_arrays  PARAMS ((void));
static void setup_incoming_promotions   PARAMS ((void));
static void set_nonzero_bits_and_sign_copies  PARAMS ((rtx, rtx, void *));
static int cant_combine_insn_p  PARAMS ((rtx));
static int can_combine_p  PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
static int sets_function_arg_p  PARAMS ((rtx));
static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
static int contains_muldiv  PARAMS ((rtx));
static rtx try_combine    PARAMS ((rtx, rtx, rtx, int *));
static void undo_all    PARAMS ((void));
static void undo_commit   PARAMS ((void));
static rtx *find_split_point  PARAMS ((rtx *, rtx));
static rtx subst    PARAMS ((rtx, rtx, rtx, int, int));
static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
static rtx simplify_if_then_else  PARAMS ((rtx));
static rtx simplify_set   PARAMS ((rtx));
static rtx simplify_logical PARAMS ((rtx, int));
static rtx expand_compound_operation  PARAMS ((rtx));
static rtx expand_field_assignment  PARAMS ((rtx));
static rtx make_extraction  PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
           rtx, unsigned HOST_WIDE_INT, int,
           int, int));
static rtx extract_left_shift PARAMS ((rtx, int));
static rtx make_compound_operation  PARAMS ((rtx, enum rtx_code));
static int get_pos_from_mask  PARAMS ((unsigned HOST_WIDE_INT,
           unsigned HOST_WIDE_INT *));
static rtx force_to_mode  PARAMS ((rtx, enum machine_mode,
           unsigned HOST_WIDE_INT, rtx, int));
static rtx if_then_else_cond  PARAMS ((rtx, rtx *, rtx *));
static rtx known_cond   PARAMS ((rtx, enum rtx_code, rtx, rtx));
static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
static rtx make_field_assignment  PARAMS ((rtx));
static rtx apply_distributive_law  PARAMS ((rtx));
static rtx simplify_and_const_int  PARAMS ((rtx, enum machine_mode, rtx,
              unsigned HOST_WIDE_INT));
static unsigned HOST_WIDE_INT cached_nonzero_bits
        PARAMS ((rtx, enum machine_mode, rtx,
           enum machine_mode,
           unsigned HOST_WIDE_INT));
static unsigned HOST_WIDE_INT nonzero_bits1
        PARAMS ((rtx, enum machine_mode, rtx,
           enum machine_mode,
           unsigned HOST_WIDE_INT));
static unsigned int cached_num_sign_bit_copies
        PARAMS ((rtx, enum machine_mode, rtx,
           enum machine_mode, unsigned int));
static unsigned int num_sign_bit_copies1
        PARAMS ((rtx, enum machine_mode, rtx,
           enum machine_mode, unsigned int));
static int merge_outer_ops  PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
           enum rtx_code, HOST_WIDE_INT,
           enum machine_mode, int *));
static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
           rtx, int));
static int recog_for_combine  PARAMS ((rtx *, rtx, rtx *));
static rtx gen_lowpart_for_combine  PARAMS ((enum machine_mode, rtx));
static rtx gen_binary   PARAMS ((enum rtx_code, enum machine_mode,
           rtx, rtx));
static enum rtx_code simplify_comparison  PARAMS ((enum rtx_code, rtx *, rtx *));
static void update_table_tick PARAMS ((rtx));
static void record_value_for_reg  PARAMS ((rtx, rtx, rtx));
static void check_promoted_subreg PARAMS ((rtx, rtx));
static void record_dead_and_set_regs_1  PARAMS ((rtx, rtx, void *));
static void record_dead_and_set_regs  PARAMS ((rtx));
static int get_last_value_validate  PARAMS ((rtx *, rtx, int, int));
static rtx get_last_value PARAMS ((rtx));
static int use_crosses_set_p  PARAMS ((rtx, int));
static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
static int reg_dead_at_p  PARAMS ((rtx, rtx));
static void move_deaths   PARAMS ((rtx, rtx, int, rtx, rtx *));
static int reg_bitfield_target_p  PARAMS ((rtx, rtx));
static void distribute_notes  PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
static void distribute_links  PARAMS ((rtx));
static void mark_used_regs_combine PARAMS ((rtx));
static int insn_cuid    PARAMS ((rtx));
static void record_promoted_value PARAMS ((rtx, rtx));
static rtx reversed_comparison  PARAMS ((rtx, enum machine_mode, rtx, rtx));
static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));

/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
   insn.  The substitution can be undone by undo_all.  If INTO is already
   set to NEWVAL, do not record this change.  Because computing NEWVAL might
   also call SUBST, we have to compute it before we put anything into
   the undo table.  */

static void
do_SUBST (into, newval)
     rtx *into, newval;
{
  struct undo *buf;
  rtx oldval = *into;

  if (oldval == newval)
    return;

  /* We'd like to catch as many invalid transformations here as
     possible.  Unfortunately, there are way too many mode changes
     that are perfectly valid, so we'd waste too much effort for
     little gain doing the checks here.  Focus on catching invalid
     transformations involving integer constants.  */
  if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
      && GET_CODE (newval) == CONST_INT)
    {
      /* Sanity check that we're replacing oldval with a CONST_INT
   that is a valid sign-extension for the original mode.  */
      if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
             GET_MODE (oldval)))
  abort ();

      /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
   CONST_INT is not valid, because after the replacement, the
   original mode would be gone.  Unfortunately, we can't tell
   when do_SUBST is called to replace the operand thereof, so we
   perform this test on oldval instead, checking whether an
   invalid replacement took place before we got here.  */
      if ((GET_CODE (oldval) == SUBREG
     && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
    || (GET_CODE (oldval) == ZERO_EXTEND
        && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
  abort ();
     }

  if (undobuf.frees)
    buf = undobuf.frees, undobuf.frees = buf->next;
  else
    buf = (struct undo *) xmalloc (sizeof (struct undo));

  buf->is_int = 0;
  buf->where.r = into;
  buf->old_contents.r = oldval;
  *into = newval;

  buf->next = undobuf.undos, undobuf.undos = buf;
}

#define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))

/* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
   for the value of a HOST_WIDE_INT value (including CONST_INT) is
   not safe.  */

static void
do_SUBST_INT (into, newval)
     int *into, newval;
{
  struct undo *buf;
  int oldval = *into;

  if (oldval == newval)
    return;

  if (undobuf.frees)
    buf = undobuf.frees, undobuf.frees = buf->next;
  else
    buf = (struct undo *) xmalloc (sizeof (struct undo));

  buf->is_int = 1;
  buf->where.i = into;
  buf->old_contents.i = oldval;
  *into = newval;

  buf->next = undobuf.undos, undobuf.undos = buf;
}

#define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))

/* Main entry point for combiner.  F is the first insn of the function.
   NREGS is the first unused pseudo-reg number.

   Return nonzero if the combiner has turned an indirect jump
   instruction into a direct jump.  */
int
combine_instructions (f, nregs)
     rtx f;
     unsigned int nregs;
{
  rtx insn, next;
#ifdef HAVE_cc0
  rtx prev;
#endif
  int i;
  rtx links, nextlinks;

  int new_direct_jump_p = 0;

  combine_attempts = 0;
  combine_merges = 0;
  combine_extras = 0;
  combine_successes = 0;

  combine_max_regno = nregs;

  reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
          xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
  reg_sign_bit_copies
    = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));

  reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
  reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
  reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
  reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
  reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
  reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
  reg_last_set_mode
    = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
  reg_last_set_nonzero_bits
    = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
  reg_last_set_sign_bit_copies
    = (char *) xmalloc (nregs * sizeof (char));

  init_reg_last_arrays ();

  init_recog_no_volatile ();

  /* Compute maximum uid value so uid_cuid can be allocated.  */

  for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
    if (INSN_UID (insn) > i)
      i = INSN_UID (insn);

  uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
  max_uid_cuid = i;

  nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);

  /* Don't use reg_nonzero_bits when computing it.  This can cause problems
     when, for example, we have j <<= 1 in a loop.  */

  nonzero_sign_valid = 0;

  /* Compute the mapping from uids to cuids.
     Cuids are numbers assigned to insns, like uids,
     except that cuids increase monotonically through the code.

     Scan all SETs and see if we can deduce anything about what
     bits are known to be zero for some registers and how many copies
     of the sign bit are known to exist for those registers.

     Also set any known values so that we can use it while searching
     for what bits are known to be set.  */

  label_tick = 1;

  /* We need to initialize it here, because record_dead_and_set_regs may call
     get_last_value.  */
  subst_prev_insn = NULL_RTX;

  setup_incoming_promotions ();

  refresh_blocks = sbitmap_alloc (last_basic_block);
  sbitmap_zero (refresh_blocks);
  need_refresh = 0;

  for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
    {
      uid_cuid[INSN_UID (insn)] = ++i;
      subst_low_cuid = i;
      subst_insn = insn;

      if (INSN_P (insn))
  {
    note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
           NULL);
    record_dead_and_set_regs (insn);

#ifdef AUTO_INC_DEC
    for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
      if (REG_NOTE_KIND (links) == REG_INC)
        set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
            NULL);
#endif
  }

      if (GET_CODE (insn) == CODE_LABEL)
  label_tick++;
    }

  nonzero_sign_valid = 1;

  /* Now scan all the insns in forward order.  */

  label_tick = 1;
  last_call_cuid = 0;
  mem_last_set = 0;
  init_reg_last_arrays ();
  setup_incoming_promotions ();

  FOR_EACH_BB (this_basic_block)
    {
      for (insn = this_basic_block->head;
           insn != NEXT_INSN (this_basic_block->end);
     insn = next ? next : NEXT_INSN (insn))
  {
    next = 0;

    if (GET_CODE (insn) == CODE_LABEL)
      label_tick++;

    else if (INSN_P (insn))
      {
        /* See if we know about function return values before this
     insn based upon SUBREG flags.  */
        check_promoted_subreg (insn, PATTERN (insn));

        /* Try this insn with each insn it links back to.  */

        for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
    if ((next = try_combine (insn, XEXP (links, 0),
           NULL_RTX, &new_direct_jump_p)) != 0)
      goto retry;

        /* Try each sequence of three linked insns ending with this one.  */

        for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
    {
      rtx link = XEXP (links, 0);

      /* If the linked insn has been replaced by a note, then there
         is no point in pursuing this chain any further.  */
      if (GET_CODE (link) == NOTE)
        continue;

      for (nextlinks = LOG_LINKS (link);
           nextlinks;
           nextlinks = XEXP (nextlinks, 1))
        if ((next = try_combine (insn, link,
               XEXP (nextlinks, 0),
               &new_direct_jump_p)) != 0)
          goto retry;
    }

#ifdef HAVE_cc0
        /* Try to combine a jump insn that uses CC0
     with a preceding insn that sets CC0, and maybe with its
     logical predecessor as well.
     This is how we make decrement-and-branch insns.
     We need this special code because data flow connections
     via CC0 do not get entered in LOG_LINKS.  */

        if (GET_CODE (insn) == JUMP_INSN
      && (prev = prev_nonnote_insn (insn)) != 0
      && GET_CODE (prev) == INSN
      && sets_cc0_p (PATTERN (prev)))
    {
      if ((next = try_combine (insn, prev,
             NULL_RTX, &new_direct_jump_p)) != 0)
        goto retry;

      for (nextlinks = LOG_LINKS (prev); nextlinks;
           nextlinks = XEXP (nextlinks, 1))
        if ((next = try_combine (insn, prev,
               XEXP (nextlinks, 0),
               &new_direct_jump_p)) != 0)
          goto retry;
    }

        /* Do the same for an insn that explicitly references CC0.  */
        if (GET_CODE (insn) == INSN
      && (prev = prev_nonnote_insn (insn)) != 0
      && GET_CODE (prev) == INSN
      && sets_cc0_p (PATTERN (prev))
      && GET_CODE (PATTERN (insn)) == SET
      && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
    {
      if ((next = try_combine (insn, prev,
             NULL_RTX, &new_direct_jump_p)) != 0)
        goto retry;

      for (nextlinks = LOG_LINKS (prev); nextlinks;
           nextlinks = XEXP (nextlinks, 1))
        if ((next = try_combine (insn, prev,
               XEXP (nextlinks, 0),
               &new_direct_jump_p)) != 0)
          goto retry;
    }

        /* Finally, see if any of the insns that this insn links to
     explicitly references CC0.  If so, try this insn, that insn,
     and its predecessor if it sets CC0.  */
        for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
    if (GET_CODE (XEXP (links, 0)) == INSN
        && GET_CODE (PATTERN (XEXP (links, 0))) == SET
        && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
        && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
        && GET_CODE (prev) == INSN
        && sets_cc0_p (PATTERN (prev))
        && (next = try_combine (insn, XEXP (links, 0),
              prev, &new_direct_jump_p)) != 0)
      goto retry;
#endif

        /* Try combining an insn with two different insns whose results it
     uses.  */
        for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
    for (nextlinks = XEXP (links, 1); nextlinks;
         nextlinks = XEXP (nextlinks, 1))
      if ((next = try_combine (insn, XEXP (links, 0),
             XEXP (nextlinks, 0),
             &new_direct_jump_p)) != 0)
        goto retry;

        if (GET_CODE (insn) != NOTE)
    record_dead_and_set_regs (insn);

      retry:
        ;
      }
  }
    }
  clear_bb_flags ();

  EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
           BASIC_BLOCK (i)->flags |= BB_DIRTY);
  new_direct_jump_p |= purge_all_dead_edges (0);
  delete_noop_moves (f);

  update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
            PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
            | PROP_KILL_DEAD_CODE);

  /* Clean up.  */
  sbitmap_free (refresh_blocks);
  free (reg_nonzero_bits);
  free (reg_sign_bit_copies);
  free (reg_last_death);
  free (reg_last_set);
  free (reg_last_set_value);
  free (reg_last_set_table_tick);
  free (reg_last_set_label);
  free (reg_last_set_invalid);
  free (reg_last_set_mode);
  free (reg_last_set_nonzero_bits);
  free (reg_last_set_sign_bit_copies);
  free (uid_cuid);

  {
    struct undo *undo, *next;
    for (undo = undobuf.frees; undo; undo = next)
      {
  next = undo->next;
  free (undo);
      }
    undobuf.frees = 0;
  }

  total_attempts += combine_attempts;
  total_merges += combine_merges;
  total_extras += combine_extras;
  total_successes += combine_successes;

  nonzero_sign_valid = 0;

  /* Make recognizer allow volatile MEMs again.  */
  init_recog ();

  return new_direct_jump_p;
}

/* Wipe the reg_last_xxx arrays in preparation for another pass.  */

static void
init_reg_last_arrays ()
{
  unsigned int nregs = combine_max_regno;

  memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
  memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
  memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
  memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
  memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
  memset (reg_last_set_invalid, 0, nregs * sizeof (char));
  memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
  memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
  memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
}

/* Set up any promoted values for incoming argument registers.  */

static void
setup_incoming_promotions ()
{
#ifdef PROMOTE_FUNCTION_ARGS
  unsigned int regno;
  rtx reg;
  enum machine_mode mode;
  int unsignedp;
  rtx first = get_insns ();

#ifndef OUTGOING_REGNO
#define OUTGOING_REGNO(N) N
#endif
  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
    /* Check whether this register can hold an incoming pointer
       argument.  FUNCTION_ARG_REGNO_P tests outgoing register
       numbers, so translate if necessary due to register windows.  */
    if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
  && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
      {
  record_value_for_reg
    (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
               : SIGN_EXTEND),
              GET_MODE (reg),
              gen_rtx_CLOBBER (mode, const0_rtx)));
      }
#endif
}

/* Called via note_stores.  If X is a pseudo that is narrower than
   HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.

   If we are setting only a portion of X and we can't figure out what
   portion, assume all bits will be used since we don't know what will
   be happening.

   Similarly, set how many bits of X are known to be copies of the sign bit
   at all locations in the function.  This is the smallest number implied
   by any set of X.  */

static void
set_nonzero_bits_and_sign_copies (x, set, data)
     rtx x;
     rtx set;
     void *data ATTRIBUTE_UNUSED;
{
  unsigned int num;

  if (GET_CODE (x) == REG
      && REGNO (x) >= FIRST_PSEUDO_REGISTER
      /* If this register is undefined at the start of the file, we can't
   say what its contents were.  */
      && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
      && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
    {
      if (set == 0 || GET_CODE (set) == CLOBBER)
  {
    reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
    reg_sign_bit_copies[REGNO (x)] = 1;
    return;
  }

      /* If this is a complex assignment, see if we can convert it into a
   simple assignment.  */
      set = expand_field_assignment (set);

      /* If this is a simple assignment, or we have a paradoxical SUBREG,
   set what we know about X.  */

      if (SET_DEST (set) == x
    || (GET_CODE (SET_DEST (set)) == SUBREG
        && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
      > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
        && SUBREG_REG (SET_DEST (set)) == x))
  {
    rtx src = SET_SRC (set);

#ifdef SHORT_IMMEDIATES_SIGN_EXTEND
    /* If X is narrower than a word and SRC is a non-negative
       constant that would appear negative in the mode of X,
       sign-extend it for use in reg_nonzero_bits because some
       machines (maybe most) will actually do the sign-extension
       and this is the conservative approach.

       ??? For 2.5, try to tighten up the MD files in this regard
       instead of this kludge.  */

    if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
        && GET_CODE (src) == CONST_INT
        && INTVAL (src) > 0
        && 0 != (INTVAL (src)
           & ((HOST_WIDE_INT) 1
        << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
      src = GEN_INT (INTVAL (src)
         | ((HOST_WIDE_INT) (-1)
            << GET_MODE_BITSIZE (GET_MODE (x))));
#endif

    /* Don't call nonzero_bits if it cannot change anything.  */
    if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
      reg_nonzero_bits[REGNO (x)]
        |= nonzero_bits (src, nonzero_bits_mode);
    num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
    if (reg_sign_bit_copies[REGNO (x)] == 0
        || reg_sign_bit_copies[REGNO (x)] > num)
      reg_sign_bit_copies[REGNO (x)] = num;
  }
      else
  {
    reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
    reg_sign_bit_copies[REGNO (x)] = 1;
  }
    }
}

/* See if INSN can be combined into I3.  PRED and SUCC are optionally
   insns that were previously combined into I3 or that will be combined
   into the merger of INSN and I3.

   Return 0 if the combination is not allowed for any reason.

   If the combination is allowed, *PDEST will be set to the single
   destination of INSN and *PSRC to the single source, and this function
   will return 1.  */

static int
can_combine_p (insn, i3, pred, succ, pdest, psrc)
     rtx insn;
     rtx i3;
     rtx pred ATTRIBUTE_UNUSED;
     rtx succ;
     rtx *pdest, *psrc;
{
  int i;
  rtx set = 0, src, dest;
  rtx p;
#ifdef AUTO_INC_DEC
  rtx link;
#endif
  int all_adjacent = (succ ? (next_active_insn (insn) == succ
            && next_active_insn (succ) == i3)
          : next_active_insn (insn) == i3);

  /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
     or a PARALLEL consisting of such a SET and CLOBBERs.

     If INSN has CLOBBER parallel parts, ignore them for our processing.
     By definition, these happen during the execution of the insn.  When it
     is merged with another insn, all bets are off.  If they are, in fact,
     needed and aren't also supplied in I3, they may be added by
     recog_for_combine.  Otherwise, it won't match.

     We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
     note.

     Get the source and destination of INSN.  If more than one, can't
     combine.  */

  if (GET_CODE (PATTERN (insn)) == SET)
    set = PATTERN (insn);
  else if (GET_CODE (PATTERN (insn)) == PARALLEL
     && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
    {
      for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
  {
    rtx elt = XVECEXP (PATTERN (insn), 0, i);

    switch (GET_CODE (elt))
      {
      /* This is important to combine floating point insns
         for the SH4 port.  */
      case USE:
        /* Combining an isolated USE doesn't make sense.
     We depend here on combinable_i3pat to reject them.  */
        /* The code below this loop only verifies that the inputs of
     the SET in INSN do not change.  We call reg_set_between_p
     to verify that the REG in the USE does not change between
     I3 and INSN.
     If the USE in INSN was for a pseudo register, the matching
     insn pattern will likely match any register; combining this
     with any other USE would only be safe if we knew that the
     used registers have identical values, or if there was
     something to tell them apart, e.g. different modes.  For
     now, we forgo such complicated tests and simply disallow
     combining of USES of pseudo registers with any other USE.  */
        if (GET_CODE (XEXP (elt, 0)) == REG
      && GET_CODE (PATTERN (i3)) == PARALLEL)
    {
      rtx i3pat = PATTERN (i3);
      int i = XVECLEN (i3pat, 0) - 1;
      unsigned int regno = REGNO (XEXP (elt, 0));

      do
        {
          rtx i3elt = XVECEXP (i3pat, 0, i);

          if (GET_CODE (i3elt) == USE
        && GET_CODE (XEXP (i3elt, 0)) == REG
        && (REGNO (XEXP (i3elt, 0)) == regno
            ? reg_set_between_p (XEXP (elt, 0),
               PREV_INSN (insn), i3)
            : regno >= FIRST_PSEUDO_REGISTER))
      return 0;
        }
      while (--i >= 0);
    }
        break;

        /* We can ignore CLOBBERs.  */
      case CLOBBER:
        break;

      case SET:
        /* Ignore SETs whose result isn't used but not those that
     have side-effects.  */
        if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
      && ! side_effects_p (elt))
    break;

        /* If we have already found a SET, this is a second one and
     so we cannot combine with this insn.  */
        if (set)
    return 0;

        set = elt;
        break;

      default:
        /* Anything else means we can't combine.  */
        return 0;
      }
  }

      if (set == 0
    /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
       so don't do anything with it.  */
    || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
  return 0;
    }
  else
    return 0;

  if (set == 0)
    return 0;

  set = expand_field_assignment (set);
  src = SET_SRC (set), dest = SET_DEST (set);

  /* Don't eliminate a store in the stack pointer.  */
  if (dest == stack_pointer_rtx
      /* If we couldn't eliminate a field assignment, we can't combine.  */
      || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
      /* Don't combine with an insn that sets a register to itself if it has
   a REG_EQUAL note.  This may be part of a REG_NO_CONFLICT sequence.  */
      || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
      /* Can't merge an ASM_OPERANDS.  */
      || GET_CODE (src) == ASM_OPERANDS
      /* Can't merge a function call.  */
      || GET_CODE (src) == CALL
      /* Don't eliminate a function call argument.  */
      || (GET_CODE (i3) == CALL_INSN
    && (find_reg_fusage (i3, USE, dest)
        || (GET_CODE (dest) == REG
      && REGNO (dest) < FIRST_PSEUDO_REGISTER
      && global_regs[REGNO (dest)])))
      /* Don't substitute into an incremented register.  */
      || FIND_REG_INC_NOTE (i3, dest)
      || (succ && FIND_REG_INC_NOTE (succ, dest))
#if 0
      /* Don't combine the end of a libcall into anything.  */
      /* ??? This gives worse code, and appears to be unnecessary, since no
   pass after flow uses REG_LIBCALL/REG_RETVAL notes.  Local-alloc does
   use REG_RETVAL notes for noconflict blocks, but other code here
   makes sure that those insns don't disappear.  */
      || find_reg_note (insn, REG_RETVAL, NULL_RTX)
#endif
      /* Make sure that DEST is not used after SUCC but before I3.  */
      || (succ && ! all_adjacent
    && reg_used_between_p (dest, succ, i3))
      /* Make sure that the value that is to be substituted for the register
   does not use any registers whose values alter in between.  However,
   If the insns are adjacent, a use can't cross a set even though we
   think it might (this can happen for a sequence of insns each setting
   the same destination; reg_last_set of that register might point to
   a NOTE).  If INSN has a REG_EQUIV note, the register is always
   equivalent to the memory so the substitution is valid even if there
   are intervening stores.  Also, don't move a volatile asm or
   UNSPEC_VOLATILE across any other insns.  */
      || (! all_adjacent
    && (((GET_CODE (src) != MEM
    || ! find_reg_note (insn, REG_EQUIV, src))
         && use_crosses_set_p (src, INSN_CUID (insn)))
        || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
        || GET_CODE (src) == UNSPEC_VOLATILE))
      /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
   better register allocation by not doing the combine.  */
      || find_reg_note (i3, REG_NO_CONFLICT, dest)
      || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
      /* Don't combine across a CALL_INSN, because that would possibly
   change whether the life span of some REGs crosses calls or not,
   and it is a pain to update that information.
   Exception: if source is a constant, moving it later can't hurt.
   Accept that special case, because it helps -fforce-addr a lot.  */
      || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
    return 0;

  /* DEST must either be a REG or CC0.  */
  if (GET_CODE (dest) == REG)
    {
      /* If register alignment is being enforced for multi-word items in all
   cases except for parameters, it is possible to have a register copy
   insn referencing a hard register that is not allowed to contain the
   mode being copied and which would not be valid as an operand of most
   insns.  Eliminate this problem by not combining with such an insn.

   Also, on some machines we don't want to extend the life of a hard
   register.  */

      if (GET_CODE (src) == REG
    && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
         && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
        /* Don't extend the life of a hard register unless it is
     user variable (if we have few registers) or it can't
     fit into the desired register (meaning something special
     is going on).
     Also avoid substituting a return register into I3, because
     reload can't handle a conflict with constraints of other
     inputs.  */
        || (REGNO (src) < FIRST_PSEUDO_REGISTER
      && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
  return 0;
    }
  else if (GET_CODE (dest) != CC0)
    return 0;

  /* Don't substitute for a register intended as a clobberable operand.
     Similarly, don't substitute an expression containing a register that
     will be clobbered in I3.  */
  if (GET_CODE (PATTERN (i3)) == PARALLEL)
    for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
      if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
    && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
               src)
        || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
  return 0;

  /* If INSN contains anything volatile, or is an `asm' (whether volatile
     or not), reject, unless nothing volatile comes between it and I3 */

  if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
    {
      /* Make sure succ doesn't contain a volatile reference.  */
      if (succ != 0 && volatile_refs_p (PATTERN (succ)))
        return 0;

      for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
        if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
    return 0;
    }

  /* If INSN is an asm, and DEST is a hard register, reject, since it has
     to be an explicit register variable, and was chosen for a reason.  */

  if (GET_CODE (src) == ASM_OPERANDS
      && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
    return 0;

  /* If there are any volatile insns between INSN and I3, reject, because
     they might affect machine state.  */

  for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
    if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
      return 0;

  /* If INSN or I2 contains an autoincrement or autodecrement,
     make sure that register is not used between there and I3,
     and not already used in I3 either.
     Also insist that I3 not be a jump; if it were one
     and the incremented register were spilled, we would lose.  */

#ifdef AUTO_INC_DEC
  for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
    if (REG_NOTE_KIND (link) == REG_INC
  && (GET_CODE (i3) == JUMP_INSN
      || reg_used_between_p (XEXP (link, 0), insn, i3)
      || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
      return 0;
#endif

#ifdef HAVE_cc0
  /* Don't combine an insn that follows a CC0-setting insn.
     An insn that uses CC0 must not be separated from the one that sets it.
     We do, however, allow I2 to follow a CC0-setting insn if that insn
     is passed as I1; in that case it will be deleted also.
     We also allow combining in this case if all the insns are adjacent
     because that would leave the two CC0 insns adjacent as well.
     It would be more logical to test whether CC0 occurs inside I1 or I2,
     but that would be much slower, and this ought to be equivalent.  */

  p = prev_nonnote_insn (insn);
  if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
      && ! all_adjacent)
    return 0;
#endif

  /* If we get here, we have passed all the tests and the combination is
     to be allowed.  */

  *pdest = dest;
  *psrc = src;

  return 1;
}

/* Check if PAT is an insn - or a part of it - used to set up an
   argument for a function in a hard register.  */

static int
sets_function_arg_p (pat)
     rtx pat;
{
  int i;
  rtx inner_dest;

  switch (GET_CODE (pat))
    {
    case INSN:
      return sets_function_arg_p (PATTERN (pat));

    case PARALLEL:
      for (i = XVECLEN (pat, 0); --i >= 0;)
  if (sets_function_arg_p (XVECEXP (pat, 0, i)))
    return 1;

      break;

    case SET:
      inner_dest = SET_DEST (pat);
      while (GET_CODE (inner_dest) == STRICT_LOW_PART
       || GET_CODE (inner_dest) == SUBREG
       || GET_CODE (inner_dest) == ZERO_EXTRACT)
  inner_dest = XEXP (inner_dest, 0);

      return (GET_CODE (inner_dest) == REG
        && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
        && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));

    default:
      break;
    }

  return 0;
}

/* LOC is the location within I3 that contains its pattern or the component
   of a PARALLEL of the pattern.  We validate that it is valid for combining.

   One problem is if I3 modifies its output, as opposed to replacing it
   entirely, we can't allow the output to contain I2DEST or I1DEST as doing
   so would produce an insn that is not equivalent to the original insns.

   Consider:

         (set (reg:DI 101) (reg:DI 100))
   (set (subreg:SI (reg:DI 101) 0) <foo>)

   This is NOT equivalent to:

         (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
        (set (reg:DI 101) (reg:DI 100))])

   Not only does this modify 100 (in which case it might still be valid
   if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.

   We can also run into a problem if I2 sets a register that I1
   uses and I1 gets directly substituted into I3 (not via I2).  In that
   case, we would be getting the wrong value of I2DEST into I3, so we
   must reject the combination.  This case occurs when I2 and I1 both
   feed into I3, rather than when I1 feeds into I2, which feeds into I3.
   If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
   of a SET must prevent combination from occurring.

   Before doing the above check, we first try to expand a field assignment
   into a set of logical operations.

   If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
   we place a register that is both set and used within I3.  If more than one
   such register is detected, we fail.

   Return 1 if the combination is valid, zero otherwise.  */

static int
combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
     rtx i3;
     rtx *loc;
     rtx i2dest;
     rtx i1dest;
     int i1_not_in_src;
     rtx *pi3dest_killed;
{
  rtx x = *loc;

  if (GET_CODE (x) == SET)
    {
      rtx set = expand_field_assignment (x);
      rtx dest = SET_DEST (set);
      rtx src = SET_SRC (set);
      rtx inner_dest = dest;

#if 0
      rtx inner_src = src;
#endif

      SUBST (*loc, set);

      while (GET_CODE (inner_dest) == STRICT_LOW_PART
       || GET_CODE (inner_dest) == SUBREG
       || GET_CODE (inner_dest) == ZERO_EXTRACT)
  inner_dest = XEXP (inner_dest, 0);

  /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
     was added.  */
#if 0
      while (GET_CODE (inner_src) == STRICT_LOW_PART
       || GET_CODE (inner_src) == SUBREG
       || GET_CODE (inner_src) == ZERO_EXTRACT)
  inner_src = XEXP (inner_src, 0);

      /* If it is better that two different modes keep two different pseudos,
   avoid combining them.  This avoids producing the following pattern
   on a 386:
    (set (subreg:SI (reg/v:QI 21) 0)
         (lshiftrt:SI (reg/v:SI 20)
             (const_int 24)))
   If that were made, reload could not handle the pair of
   reg 20/21, since it would try to get any GENERAL_REGS
   but some of them don't handle QImode.  */

      if (rtx_equal_p (inner_src, i2dest)
    && GET_CODE (inner_dest) == REG
    && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
  return 0;
#endif

      /* Check for the case where I3 modifies its output, as
   discussed above.  */
      if ((inner_dest != dest
     && (reg_overlap_mentioned_p (i2dest, inner_dest)
         || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))

    /* This is the same test done in can_combine_p except we can't test
       all_adjacent; we don't have to, since this instruction will stay
       in place, thus we are not considering increasing the lifetime of
       INNER_DEST.

       Also, if this insn sets a function argument, combining it with
       something that might need a spill could clobber a previous
       function argument; the all_adjacent test in can_combine_p also
       checks this; here, we do a more specific test for this case.  */

    || (GET_CODE (inner_dest) == REG
        && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
        && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
          GET_MODE (inner_dest))))
    || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
  return 0;

      /* If DEST is used in I3, it is being killed in this insn,
   so record that for later.
   Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
   STACK_POINTER_REGNUM, since these are always considered to be
   live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
      if (pi3dest_killed && GET_CODE (dest) == REG
    && reg_referenced_p (dest, PATTERN (i3))
    && REGNO (dest) != FRAME_POINTER_REGNUM
#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
    && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
#endif
#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
    && (REGNO (dest) != ARG_POINTER_REGNUM
        || ! fixed_regs [REGNO (dest)])
#endif
    && REGNO (dest) != STACK_POINTER_REGNUM)
  {
    if (*pi3dest_killed)
      return 0;

    *pi3dest_killed = dest;
  }
    }

  else if (GET_CODE (x) == PARALLEL)
    {
      int i;

      for (i = 0; i < XVECLEN (x, 0); i++)
  if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
        i1_not_in_src, pi3dest_killed))
    return 0;
    }

  return 1;
}

/* Return 1 if X is an arithmetic expression that contains a multiplication
   and division.  We don't count multiplications by powers of two here.  */

static int
contains_muldiv (x)
     rtx x;
{
  switch (GET_CODE (x))
    {
    case MOD:  case DIV:  case UMOD:  case UDIV:
      return 1;

    case MULT:
      return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
    && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
    default:
      switch (GET_RTX_CLASS (GET_CODE (x)))
  {
  case 'c':  case '<':  case '2':
    return contains_muldiv (XEXP (x, 0))
      || contains_muldiv (XEXP (x, 1));

  case '1':
    return contains_muldiv (XEXP (x, 0));

  default:
    return 0;
  }
    }
}

/* Determine whether INSN can be used in a combination.  Return nonzero if
   not.  This is used in try_combine to detect early some cases where we
   can't perform combinations.  */

static int
cant_combine_insn_p (insn)
     rtx insn;
{
  rtx set;
  rtx src, dest;

  /* If this isn't really an insn, we can't do anything.
     This can occur when flow deletes an insn that it has merged into an
     auto-increment address.  */
  if (! INSN_P (insn))
    return 1;

  /* Never combine loads and stores involving hard regs.  The register
     allocator can usually handle such reg-reg moves by tying.  If we allow
     the combiner to make substitutions of hard regs, we risk aborting in
     reload on machines that have SMALL_REGISTER_CLASSES.
     As an exception, we allow combinations involving fixed regs; these are
     not available to the register allocator so there's no risk involved.  */

  set = single_set (insn);
  if (! set)
    return 0;
  src = SET_SRC (set);
  dest = SET_DEST (set);
  if (GET_CODE (src) == SUBREG)
    src = SUBREG_REG (src);
  if (GET_CODE (dest) == SUBREG)
    dest = SUBREG_REG (dest);
  if (REG_P (src) && REG_P (dest)
      && ((REGNO (src) < FIRST_PSEUDO_REGISTER
     && ! fixed_regs[REGNO (src)])
    || (REGNO (dest) < FIRST_PSEUDO_REGISTER
        && ! fixed_regs[REGNO (dest)])))
    return 1;

  return 0;
}

/* Try to combine the insns I1 and I2 into I3.
   Here I1 and I2 appear earlier than I3.
   I1 can be zero; then we combine just I2 into I3.

   If we are combining three insns and the resulting insn is not recognized,
   try splitting it into two insns.  If that happens, I2 and I3 are retained
   and I1 is pseudo-deleted by turning it into a NOTE.  Otherwise, I1 and I2
   are pseudo-deleted.

   Return 0 if the combination does not work.  Then nothing is changed.
   If we did the combination, return the insn at which combine should
   resume scanning.

   Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
   new direct jump instruction.  */

static rtx
try_combine (i3, i2, i1, new_direct_jump_p)
     rtx i3, i2, i1;
     int *new_direct_jump_p;
{
  /* New patterns for I3 and I2, respectively.  */
  rtx newpat, newi2pat = 0;
  int substed_i2 = 0, substed_i1 = 0;
  /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead.  */
  int added_sets_1, added_sets_2;
  /* Total number of SETs to put into I3.  */
  int total_sets;
  /* Nonzero is I2's body now appears in I3.  */
  int i2_is_used;
  /* INSN_CODEs for new I3, new I2, and user of condition code.  */
  int insn_code_number, i2_code_number = 0, other_code_number = 0;
  /* Contains I3 if the destination of I3 is used in its source, which means
     that the old life of I3 is being killed.  If that usage is placed into
     I2 and not in I3, a REG_DEAD note must be made.  */
  rtx i3dest_killed = 0;
  /* SET_DEST and SET_SRC of I2 and I1.  */
  rtx i2dest, i2src, i1dest = 0, i1src = 0;
  /* PATTERN (I2), or a copy of it in certain cases.  */
  rtx i2pat;
  /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
  int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
  int i1_feeds_i3 = 0;
  /* Notes that must be added to REG_NOTES in I3 and I2.  */
  rtx new_i3_notes, new_i2_notes;
  /* Notes that we substituted I3 into I2 instead of the normal case.  */
  int i3_subst_into_i2 = 0;
  /* Notes that I1, I2 or I3 is a MULT operation.  */
  int have_mult = 0;

  int maxreg;
  rtx temp;
  rtx link;
  int i;

  /* Exit early if one of the insns involved can't be used for
     combinations.  */
  if (cant_combine_insn_p (i3)
      || cant_combine_insn_p (i2)
      || (i1 && cant_combine_insn_p (i1))
      /* We also can't do anything if I3 has a
   REG_LIBCALL note since we don't want to disrupt the contiguity of a
   libcall.  */
#if 0
      /* ??? This gives worse code, and appears to be unnecessary, since no
   pass after flow uses REG_LIBCALL/REG_RETVAL notes.  */
      || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
#endif
      )
    return 0;

  combine_attempts++;
  undobuf.other_insn = 0;

  /* Reset the hard register usage information.  */
  CLEAR_HARD_REG_SET (newpat_used_regs);

  /* If I1 and I2 both feed I3, they can be in any order.  To simplify the
     code below, set I1 to be the earlier of the two insns.  */
  if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
    temp = i1, i1 = i2, i2 = temp;

  added_links_insn = 0;

  /* First check for one important special-case that the code below will
     not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
     and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
     we may be able to replace that destination with the destination of I3.
     This occurs in the common code where we compute both a quotient and
     remainder into a structure, in which case we want to do the computation
     directly into the structure to avoid register-register copies.

     Note that this case handles both multiple sets in I2 and also
     cases where I2 has a number of CLOBBER or PARALLELs.

     We make very conservative checks below and only try to handle the
     most common cases of this.  For example, we only handle the case
     where I2 and I3 are adjacent to avoid making difficult register
     usage tests.  */

  if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
      && GET_CODE (SET_SRC (PATTERN (i3))) == REG
      && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
      && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
      && GET_CODE (PATTERN (i2)) == PARALLEL
      && ! side_effects_p (SET_DEST (PATTERN (i3)))
      /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
   below would need to check what is inside (and reg_overlap_mentioned_p
   doesn't support those codes anyway).  Don't allow those destinations;
   the resulting insn isn't likely to be recognized anyway.  */
      && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
      && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
      && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
            SET_DEST (PATTERN (i3)))
      && next_real_insn (i2) == i3)
    {
      rtx p2 = PATTERN (i2);

      /* Make sure that the destination of I3,
   which we are going to substitute into one output of I2,
   is not used within another output of I2.  We must avoid making this:
   (parallel [(set (mem (reg 69)) ...)
        (set (reg 69) ...)])
   which is not well-defined as to order of actions.
   (Besides, reload can't handle output reloads for this.)

   The problem can also happen if the dest of I3 is a memory ref,
   if another dest in I2 is an indirect memory ref.  */
      for (i = 0; i < XVECLEN (p2, 0); i++)
  if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
       || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
      && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
          SET_DEST (XVECEXP (p2, 0, i))))
    break;

      if (i == XVECLEN (p2, 0))
  for (i = 0; i < XVECLEN (p2, 0); i++)
    if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
         || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
        && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
      {
        combine_merges++;

        subst_insn = i3;
        subst_low_cuid = INSN_CUID (i2);

        added_sets_2 = added_sets_1 = 0;
        i2dest = SET_SRC (PATTERN (i3));

        /* Replace the dest in I2 with our dest and make the resulting
     insn the new pattern for I3.  Then skip to where we
     validate the pattern.  Everything was set up above.  */
        SUBST (SET_DEST (XVECEXP (p2, 0, i)),
         SET_DEST (PATTERN (i3)));

        newpat = p2;
        i3_subst_into_i2 = 1;
        goto validate_replacement;
      }
    }

  /* If I2 is setting a double-word pseudo to a constant and I3 is setting
     one of those words to another constant, merge them by making a new
     constant.  */
  if (i1 == 0
      && (temp = single_set (i2)) != 0
      && (GET_CODE (SET_SRC (temp)) == CONST_INT
    || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
      && GET_CODE (SET_DEST (temp)) == REG
      && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
      && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
      && GET_CODE (PATTERN (i3)) == SET
      && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
      && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
      && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
      && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
      && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
    {
      HOST_WIDE_INT lo, hi;

      if (GET_CODE (SET_SRC (temp)) == CONST_INT)
  lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
      else
  {
    lo = CONST_DOUBLE_LOW (SET_SRC (temp));
    hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
  }

      if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
  {
    /* We don't handle the case of the target word being wider
       than a host wide int.  */
    if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
      abort ();

    lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
    lo |= (INTVAL (SET_SRC (PATTERN (i3))) 
     & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
  }
      else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
  hi = INTVAL (SET_SRC (PATTERN (i3)));
      else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
  {
    int sign = -(int) ((unsigned HOST_WIDE_INT) lo
           >> (HOST_BITS_PER_WIDE_INT - 1));

    lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
       (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
    lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
     (INTVAL (SET_SRC (PATTERN (i3)))));
    if (hi == sign)
      hi = lo < 0 ? -1 : 0;
  }
      else
  /* We don't handle the case of the higher word not fitting
     entirely in either hi or lo.  */
  abort ();

      combine_merges++;
      subst_insn = i3;
      subst_low_cuid = INSN_CUID (i2);
      added_sets_2 = added_sets_1 = 0;
      i2dest = SET_DEST (temp);

      SUBST (SET_SRC (temp),
       immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));

      newpat = PATTERN (i2);
      goto validate_replacement;
    }

#ifndef HAVE_cc0
  /* If we have no I1 and I2 looks like:
  (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
       (set Y OP)])
     make up a dummy I1 that is
  (set Y OP)
     and change I2 to be
        (set (reg:CC X) (compare:CC Y (const_int 0)))

     (We can ignore any trailing CLOBBERs.)

     This undoes a previous combination and allows us to match a branch-and-
     decrement insn.  */

  if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
      && XVECLEN (PATTERN (i2), 0) >= 2
      && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
      && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
    == MODE_CC)
      && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
      && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
      && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
      && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
      && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
          SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
    {
      for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
  if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
    break;

      if (i == 1)
  {
    /* We make I1 with the same INSN_UID as I2.  This gives it
       the same INSN_CUID for value tracking.  Our fake I1 will
       never appear in the insn stream so giving it the same INSN_UID
       as I2 will not cause a problem.  */

    subst_prev_insn = i1
      = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
          BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
          XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
          NULL_RTX);

    SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
    SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
     SET_DEST (PATTERN (i1)));
  }
    }
#endif

  /* Verify that I2 and I1 are valid for combining.  */
  if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
      || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
    {
      undo_all ();
      return 0;
    }

  /* Record whether I2DEST is used in I2SRC and similarly for the other
     cases.  Knowing this will help in register status updating below.  */
  i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
  i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
  i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);

  /* See if I1 directly feeds into I3.  It does if I1DEST is not used
     in I2SRC.  */
  i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);

  /* Ensure that I3's pattern can be the destination of combines.  */
  if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
        i1 && i2dest_in_i1src && i1_feeds_i3,
        &i3dest_killed))
    {
      undo_all ();
      return 0;
    }

  /* See if any of the insns is a MULT operation.  Unless one is, we will
     reject a combination that is, since it must be slower.  Be conservative
     here.  */
  if (GET_CODE (i2src) == MULT
      || (i1 != 0 && GET_CODE (i1src) == MULT)
      || (GET_CODE (PATTERN (i3)) == SET
    && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
    have_mult = 1;

  /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
     We used to do this EXCEPT in one case: I3 has a post-inc in an
     output operand.  However, that exception can give rise to insns like
  mov r3,(r3)+
     which is a famous insn on the PDP-11 where the value of r3 used as the
     source was model-dependent.  Avoid this sort of thing.  */

#if 0
  if (!(GET_CODE (PATTERN (i3)) == SET
  && GET_CODE (SET_SRC (PATTERN (i3))) == REG
  && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
  && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
      || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
    /* It's not the exception.  */
#endif
#ifdef AUTO_INC_DEC
    for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
      if (REG_NOTE_KIND (link) == REG_INC
    && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
        || (i1 != 0
      && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
  {
    undo_all ();
    return 0;
  }
#endif

  /* See if the SETs in I1 or I2 need to be kept around in the merged
     instruction: whenever the value set there is still needed past I3.
     For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.

     For the SET in I1, we have two cases:  If I1 and I2 independently
     feed into I3, the set in I1 needs to be kept around if I1DEST dies
     or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
     in I1 needs to be kept around unless I1DEST dies or is set in either
     I2 or I3.  We can distinguish these cases by seeing if I2SRC mentions
     I1DEST.  If so, we know I1 feeds into I2.  */

  added_sets_2 = ! dead_or_set_p (i3, i2dest);

  added_sets_1
    = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
         : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));

  /* If the set in I2 needs to be kept around, we must make a copy of
     PATTERN (I2), so that when we substitute I1SRC for I1DEST in
     PATTERN (I2), we are only substituting for the original I1DEST, not into
     an already-substituted copy.  This also prevents making self-referential
     rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
     I2DEST.  */

  i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
     ? gen_rtx_SET (VOIDmode, i2dest, i2src)
     : PATTERN (i2));

  if (added_sets_2)
    i2pat = copy_rtx (i2pat);

  combine_merges++;

  /* Substitute in the latest insn for the regs set by the earlier ones.  */

  maxreg = max_reg_num ();

  subst_insn = i3;

  /* It is possible that the source of I2 or I1 may be performing an
     unneeded operation, such as a ZERO_EXTEND of something that is known
     to have the high part zero.  Handle that case by letting subst look at
     the innermost one of them.

     Another way to do this would be to have a function that tries to
     simplify a single insn instead of merging two or more insns.  We don't
     do this because of the potential of infinite loops and because
     of the potential extra memory required.  However, doing it the way
     we are is a bit of a kludge and doesn't catch all cases.

     But only do this if -fexpensive-optimizations since it slows things down
     and doesn't usually win.  */

  if (flag_expensive_optimizations)
    {
      /* Pass pc_rtx so no substitutions are done, just simplifications.
   The cases that we are interested in here do not involve the few
   cases were is_replaced is checked.  */
      if (i1)
  {
    subst_low_cuid = INSN_CUID (i1);
    i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
  }
      else
  {
    subst_low_cuid = INSN_CUID (i2);
    i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
  }
    }

#ifndef HAVE_cc0
  /* Many machines that don't use CC0 have insns that can both perform an
     arithmetic operation and set the condition code.  These operations will
     be represented as a PARALLEL with the first element of the vector
     being a COMPARE of an arithmetic operation with the constant zero.
     The second element of the vector will set some pseudo to the result
     of the same arithmetic operation.  If we simplify the COMPARE, we won't
     match such a pattern and so will generate an extra insn.   Here we test
     for this case, where both the comparison and the operation result are
     needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
     I2SRC.  Later we will make the PARALLEL that contains I2.  */

  if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
      && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
      && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
      && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
    {
#ifdef EXTRA_CC_MODES
      rtx *cc_use;
      enum machine_mode compare_mode;
#endif

      newpat = PATTERN (i3);
      SUBST (XEXP (SET_SRC (newpat), 0), i2src);

      i2_is_used = 1;

#ifdef EXTRA_CC_MODES
      /* See if a COMPARE with the operand we substituted in should be done
   with the mode that is currently being used.  If not, do the same
   processing we do in `subst' for a SET; namely, if the destination
   is used only once, try to replace it with a register of the proper
   mode and also replace the COMPARE.  */
      if (undobuf.other_insn == 0
    && (cc_use = find_single_use (SET_DEST (newpat), i3,
          &undobuf.other_insn))
    && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
                i2src, const0_rtx))
        != GET_MODE (SET_DEST (newpat))))
  {
    unsigned int regno = REGNO (SET_DEST (newpat));
    rtx new_dest = gen_rtx_REG (compare_mode, regno);

    if (regno < FIRST_PSEUDO_REGISTER
        || (REG_N_SETS (regno) == 1 && ! added_sets_2
      && ! REG_USERVAR_P (SET_DEST (newpat))))
      {
        if (regno >= FIRST_PSEUDO_REGISTER)
    SUBST (regno_reg_rtx[regno], new_dest);

        SUBST (SET_DEST (newpat), new_dest);
        SUBST (XEXP (*cc_use, 0), new_dest);
        SUBST (SET_SRC (newpat),
         gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
      }
    else
      undobuf.other_insn = 0;
  }
#endif
    }
  else
#endif
    {
      n_occurrences = 0;    /* `subst' counts here */

      /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
   need to make a unique copy of I2SRC each time we substitute it
   to avoid self-referential rtl.  */

      subst_low_cuid = INSN_CUID (i2);
      newpat = subst (PATTERN (i3), i2dest, i2src, 0,
          ! i1_feeds_i3 && i1dest_in_i1src);
      substed_i2 = 1;

      /* Record whether i2's body now appears within i3's body.  */
      i2_is_used = n_occurrences;
    }

  /* If we already got a failure, don't try to do more.  Otherwise,
     try to substitute in I1 if we have it.  */

  if (i1 && GET_CODE (newpat) != CLOBBER)
    {
      /* Before we can do this substitution, we must redo the test done
   above (see detailed comments there) that ensures  that I1DEST
   isn't mentioned in any SETs in NEWPAT that are field assignments.  */

      if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
            0, (rtx*) 0))
  {
    undo_all ();
    return 0;
  }

      n_occurrences = 0;
      subst_low_cuid = INSN_CUID (i1);
      newpat = subst (newpat, i1dest, i1src, 0, 0);
      substed_i1 = 1;
    }

  /* Fail if an autoincrement side-effect has been duplicated.  Be careful
     to count all the ways that I2SRC and I1SRC can be used.  */
  if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
       && i2_is_used + added_sets_2 > 1)
      || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
    && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
        > 1))
      /* Fail if we tried to make a new register (we used to abort, but there's
   really no reason to).  */
      || max_reg_num () != maxreg
      /* Fail if we couldn't do something and have a CLOBBER.  */
      || GET_CODE (newpat) == CLOBBER
      /* Fail if this new pattern is a MULT and we didn't have one before
   at the outer level.  */
      || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
    && ! have_mult))
    {
      undo_all ();
      return 0;
    }

  /* If the actions of the earlier insns must be kept
     in addition to substituting them into the latest one,
     we must make a new PARALLEL for the latest insn
     to hold additional the SETs.  */

  if (added_sets_1 || added_sets_2)
    {
      combine_extras++;

      if (GET_CODE (newpat) == PARALLEL)
  {
    rtvec old = XVEC (newpat, 0);
    total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
    newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
    memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
      sizeof (old->elem[0]) * old->num_elem);
  }
      else
  {
    rtx old = newpat;
    total_sets = 1 + added_sets_1 + added_sets_2;
    newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
    XVECEXP (newpat, 0, 0) = old;
  }

      if (added_sets_1)
  XVECEXP (newpat, 0, --total_sets)
    = (GET_CODE (PATTERN (i1)) == PARALLEL
       ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));

      if (added_sets_2)
  {
    /* If there is no I1, use I2's body as is.  We used to also not do
       the subst call below if I2 was substituted into I3,
       but that could lose a simplification.  */
    if (i1 == 0)
      XVECEXP (newpat, 0, --total_sets) = i2pat;
    else
      /* See comment where i2pat is assigned.  */
      XVECEXP (newpat, 0, --total_sets)
        = subst (i2pat, i1dest, i1src, 0, 0);
  }
    }

  /* We come here when we are replacing a destination in I2 with the
     destination of I3.  */
 validate_replacement:

  /* Note which hard regs this insn has as inputs.  */
  mark_used_regs_combine (newpat);

  /* Is the result of combination a valid instruction?  */
  insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);

  /* If the result isn't valid, see if it is a PARALLEL of two SETs where
     the second SET's destination is a register that is unused.  In that case,
     we just need the first SET.   This can occur when simplifying a divmod
     insn.  We *must* test for this case here because the code below that
     splits two independent SETs doesn't handle this case correctly when it
     updates the register status.  Also check the case where the first
     SET's destination is unused.  That would not cause incorrect code, but
     does cause an unneeded insn to remain.  */

  if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
      && XVECLEN (newpat, 0) == 2
      && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
      && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
      && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
      && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
      && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
      && asm_noperands (newpat) < 0)
    {
      newpat = XVECEXP (newpat, 0, 0);
      insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
    }

  else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
     && XVECLEN (newpat, 0) == 2
     && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
     && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
     && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
     && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
     && asm_noperands (newpat) < 0)
    {
      newpat = XVECEXP (newpat, 0, 1);
      insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
    }

  /* If we were combining three insns and the result is a simple SET
     with no ASM_OPERANDS that wasn't recognized, try to split it into two
     insns.  There are two ways to do this.  It can be split using a
     machine-specific method (like when you have an addition of a large
     constant) or by combine in the function find_split_point.  */

  if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
      && asm_noperands (newpat) < 0)
    {
      rtx m_split, *split;
      rtx ni2dest = i2dest;

      /* See if the MD file can split NEWPAT.  If it can't, see if letting it
   use I2DEST as a scratch register will help.  In the latter case,
   convert I2DEST to the mode of the source of NEWPAT if we can.  */

      m_split = split_insns (newpat, i3);

      /* We can only use I2DEST as a scratch reg if it doesn't overlap any
   inputs of NEWPAT.  */

      /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
   possible to try that as a scratch reg.  This would require adding
   more code to make it work though.  */

      if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
  {
    /* If I2DEST is a hard register or the only use of a pseudo,
       we can change its mode.  */
    if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
        && GET_MODE (SET_DEST (newpat)) != VOIDmode
        && GET_CODE (i2dest) == REG
        && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
      || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
          && ! REG_USERVAR_P (i2dest))))
      ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
           REGNO (i2dest));

    m_split = split_insns (gen_rtx_PARALLEL
         (VOIDmode,
          gen_rtvec (2, newpat,
               gen_rtx_CLOBBER (VOIDmode,
                    ni2dest))),
         i3);
    /* If the split with the mode-changed register didn't work, try
       the original register.  */
    if (! m_split && ni2dest != i2dest)
      {
        ni2dest = i2dest;
        m_split = split_insns (gen_rtx_PARALLEL
             (VOIDmode,
              gen_rtvec (2, newpat,
             gen_rtx_CLOBBER (VOIDmode,
                  i2dest))),
             i3);
      }
  }

      if (m_split && NEXT_INSN (m_split) == NULL_RTX)
  {
    m_split = PATTERN (m_split);
    insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
    if (insn_code_number >= 0)
      newpat = m_split;
  }
      else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
         && (next_real_insn (i2) == i3
       || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
  {
    rtx i2set, i3set;
    rtx newi3pat = PATTERN (NEXT_INSN (m_split));
    newi2pat = PATTERN (m_split);

    i3set = single_set (NEXT_INSN (m_split));
    i2set = single_set (m_split);

    /* In case we changed the mode of I2DEST, replace it in the
       pseudo-register table here.  We can't do it above in case this
       code doesn't get executed and we do a split the other way.  */

    if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
      SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);

    i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);

    /* If I2 or I3 has multiple SETs, we won't know how to track
       register status, so don't use these insns.  If I2's destination
       is used between I2 and I3, we also can't use these insns.  */

    if (i2_code_number >= 0 && i2set && i3set
        && (next_real_insn (i2) == i3
      || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
      insn_code_number = recog_for_combine (&newi3pat, i3,
              &new_i3_notes);
    if (insn_code_number >= 0)
      newpat = newi3pat;

    /* It is possible that both insns now set the destination of I3.
       If so, we must show an extra use of it.  */

    if (insn_code_number >= 0)
      {
        rtx new_i3_dest = SET_DEST (i3set);
        rtx new_i2_dest = SET_DEST (i2set);

        while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
         || GET_CODE (new_i3_dest) == STRICT_LOW_PART
         || GET_CODE (new_i3_dest) == SUBREG)
    new_i3_dest = XEXP (new_i3_dest, 0);

        while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
         || GET_CODE (new_i2_dest) == STRICT_LOW_PART
         || GET_CODE (new_i2_dest) == SUBREG)
    new_i2_dest = XEXP (new_i2_dest, 0);

        if (GET_CODE (new_i3_dest) == REG
      && GET_CODE (new_i2_dest) == REG
      && REGNO (new_i3_dest) == REGNO (new_i2_dest))
    REG_N_SETS (REGNO (new_i2_dest))++;
      }
  }

      /* If we can split it and use I2DEST, go ahead and see if that
   helps things be recognized.  Verify that none of the registers
   are set between I2 and I3.  */
      if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
#ifdef HAVE_cc0
    && GET_CODE (i2dest) == REG
#endif
    /* We need I2DEST in the proper mode.  If it is a hard register
       or the only use of a pseudo, we can change its mode.  */
    && (GET_MODE (*split) == GET_MODE (i2dest)
        || GET_MODE (*split) == VOIDmode
        || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
        || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
      && ! REG_USERVAR_P (i2dest)))
    && (next_real_insn (i2) == i3
        || ! use_crosses_set_p (*split, INSN_CUID (i2)))
    /* We can't overwrite I2DEST if its value is still used by
       NEWPAT.  */
    && ! reg_referenced_p (i2dest, newpat))
  {
    rtx newdest = i2dest;
    enum rtx_code split_code = GET_CODE (*split);
    enum machine_mode split_mode = GET_MODE (*split);

    /* Get NEWDEST as a register in the proper mode.  We have already
       validated that we can do this.  */
    if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
      {
        newdest = gen_rtx_REG (split_mode, REGNO (i2dest));

        if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
    SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
      }

    /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
       an ASHIFT.  This can occur if it was inside a PLUS and hence
       appeared to be a memory address.  This is a kludge.  */
    if (split_code == MULT
        && GET_CODE (XEXP (*split, 1)) == CONST_INT
        && INTVAL (XEXP (*split, 1)) > 0
        && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
      {
        SUBST (*split, gen_rtx_ASHIFT (split_mode,
               XEXP (*split, 0), GEN_INT (i)));
        /* Update split_code because we may not have a multiply
     anymore.  */
        split_code = GET_CODE (*split);
      }

#ifdef INSN_SCHEDULING
    /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
       be written as a ZERO_EXTEND.  */
    if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
      {
#ifdef LOAD_EXTEND_OP
        /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
     what it really is.  */
        if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
      == SIGN_EXTEND)
    SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
                SUBREG_REG (*split)));
        else
#endif
    SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
                SUBREG_REG (*split)));
      }
#endif

    newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
    SUBST (*split, newdest);
    i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);

    /* If the split point was a MULT and we didn't have one before,
       don't use one now.  */
    if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
      insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
  }
    }

  /* Check for a case where we loaded from memory in a narrow mode and
     then sign extended it, but we need both registers.  In that case,
     we have a PARALLEL with both loads from the same memory location.
     We can split this into a load from memory followed by a register-register
     copy.  This saves at least one insn, more if register allocation can
     eliminate the copy.

     We cannot do this if the destination of the first assignment is a
     condition code register or cc0.  We eliminate this case by making sure
     the SET_DEST and SET_SRC have the same mode.

     We cannot do this if the destination of the second assignment is
     a register that we have already assumed is zero-extended.  Similarly
     for a SUBREG of such a register.  */

  else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
     && GET_CODE (newpat) == PARALLEL
     && XVECLEN (newpat, 0) == 2
     && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
     && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
     && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
         == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
     && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
     && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
         XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
     && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
           INSN_CUID (i2))
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
     && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
     (GET_CODE (temp) == REG
      && reg_nonzero_bits[REGNO (temp)] != 0
      && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
      && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
      && (reg_nonzero_bits[REGNO (temp)]
          != GET_MODE_MASK (word_mode))))
     && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
     && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
         (GET_CODE (temp) == REG
          && reg_nonzero_bits[REGNO (temp)] != 0
          && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
          && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
          && (reg_nonzero_bits[REGNO (temp)]
        != GET_MODE_MASK (word_mode)))))
     && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
           SET_SRC (XVECEXP (newpat, 0, 1)))
     && ! find_reg_note (i3, REG_UNUSED,
             SET_DEST (XVECEXP (newpat, 0, 0))))
    {
      rtx ni2dest;

      newi2pat = XVECEXP (newpat, 0, 0);
      ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
      newpat = XVECEXP (newpat, 0, 1);
      SUBST (SET_SRC (newpat),
       gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
      i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);

      if (i2_code_number >= 0)
  insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);

      if (insn_code_number >= 0)
  {
    rtx insn;
    rtx link;

    /* If we will be able to accept this, we have made a change to the
       destination of I3.  This can invalidate a LOG_LINKS pointing
       to I3.  No other part of combine.c makes such a transformation.

       The new I3 will have a destination that was previously the
       destination of I1 or I2 and which was used in i2 or I3.  Call
       distribute_links to make a LOG_LINK from the next use of
       that destination.  */

    PATTERN (i3) = newpat;
    distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));

    /* I3 now uses what used to be its destination and which is
       now I2's destination.  That means we need a LOG_LINK from
       I3 to I2.  But we used to have one, so we still will.

       However, some later insn might be using I2's dest and have
       a LOG_LINK pointing at I3.  We must remove this link.
       The simplest way to remove the link is to point it at I1,
       which we know will be a NOTE.  */

    for (insn = NEXT_INSN (i3);
         insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
      || insn != this_basic_block->next_bb->head);
         insn = NEXT_INSN (insn))
      {
        if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
    {
      for (link = LOG_LINKS (insn); link;
           link = XEXP (link, 1))
        if (XEXP (link, 0) == i3)
          XEXP (link, 0) = i1;

      break;
    }
      }
  }
    }

  /* Similarly, check for a case where we have a PARALLEL of two independent
     SETs but we started with three insns.  In this case, we can do the sets
     as two separate insns.  This case occurs when some SET allows two
     other insns to combine, but the destination of that SET is still live.  */

  else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
     && GET_CODE (newpat) == PARALLEL
     && XVECLEN (newpat, 0) == 2
     && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
     && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
     && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
           INSN_CUID (i2))
     /* Don't pass sets with (USE (MEM ...)) dests to the following.  */
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
     && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
     && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
          XVECEXP (newpat, 0, 0))
     && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
          XVECEXP (newpat, 0, 1))
     && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
     && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
    {
      /* Normally, it doesn't matter which of the two is done first,
   but it does if one references cc0.  In that case, it has to
   be first.  */
#ifdef HAVE_cc0
      if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
  {
    newi2pat = XVECEXP (newpat, 0, 0);
    newpat = XVECEXP (newpat, 0, 1);
  }
      else
#endif
  {
    newi2pat = XVECEXP (newpat, 0, 1);
    newpat = XVECEXP (newpat, 0, 0);
  }

      i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);

      if (i2_code_number >= 0)
  insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
    }

  /* If it still isn't recognized, fail and change things back the way they
     were.  */
  if ((insn_code_number < 0
       /* Is the result a reasonable ASM_OPERANDS?  */
       && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
    {
      undo_all ();
      return 0;
    }

  /* If we had to change another insn, make sure it is valid also.  */
  if (undobuf.other_insn)
    {
      rtx other_pat = PATTERN (undobuf.other_insn);
      rtx new_other_notes;
      rtx note, next;

      CLEAR_HARD_REG_SET (newpat_used_regs);

      other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
               &new_other_notes);

      if (other_code_number < 0 && ! check_asm_operands (other_pat))
  {
    undo_all ();
    return 0;
  }

      PATTERN (undobuf.other_insn) = other_pat;

      /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
   are still valid.  Then add any non-duplicate notes added by
   recog_for_combine.  */
      for (note = REG_NOTES (undobuf.other_insn); note; note = next)
  {
    next = XEXP (note, 1);

    if (REG_NOTE_KIND (note) == REG_UNUSED
        && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
      {
        if (GET_CODE (XEXP (note, 0)) == REG)
    REG_N_DEATHS (REGNO (XEXP (note, 0)))--;

        remove_note (undobuf.other_insn, note);
      }
  }

      for (note = new_other_notes; note; note = XEXP (note, 1))
  if (GET_CODE (XEXP (note, 0)) == REG)
    REG_N_DEATHS (REGNO (XEXP (note, 0)))++;

      distribute_notes (new_other_notes, undobuf.other_insn,
      undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
    }
#ifdef HAVE_cc0
  /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
     they are adjacent to each other or not.  */
  {
    rtx p = prev_nonnote_insn (i3);
    if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
  && sets_cc0_p (newi2pat))
      {
  undo_all ();
  return 0;
      }
  }
#endif

  /* We now know that we can do this combination.  Merge the insns and
     update the status of registers and LOG_LINKS.  */

  {
    rtx i3notes, i2notes, i1notes = 0;
    rtx i3links, i2links, i1links = 0;
    rtx midnotes = 0;
    unsigned int regno;
    /* Compute which registers we expect to eliminate.  newi2pat may be setting
       either i3dest or i2dest, so we must check it.  Also, i1dest may be the
       same as i3dest, in which case newi2pat may be setting i1dest.  */
    rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
       || i2dest_in_i2src || i2dest_in_i1src
       ? 0 : i2dest);
    rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
       || (newi2pat && reg_set_p (i1dest, newi2pat))
       ? 0 : i1dest);

    /* Get the old REG_NOTES and LOG_LINKS from all our insns and
       clear them.  */
    i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
    i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
    if (i1)
      i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);

    /* Ensure that we do not have something that should not be shared but
       occurs multiple times in the new insns.  Check this by first
       resetting all the `used' flags and then copying anything is shared.  */

    reset_used_flags (i3notes);
    reset_used_flags (i2notes);
    reset_used_flags (i1notes);
    reset_used_flags (newpat);
    reset_used_flags (newi2pat);
    if (undobuf.other_insn)
      reset_used_flags (PATTERN (undobuf.other_insn));

    i3notes = copy_rtx_if_shared (i3notes);
    i2notes = copy_rtx_if_shared (i2notes);
    i1notes = copy_rtx_if_shared (i1notes);
    newpat = copy_rtx_if_shared (newpat);
    newi2pat = copy_rtx_if_shared (newi2pat);
    if (undobuf.other_insn)
      reset_used_flags (PATTERN (undobuf.other_insn));

    INSN_CODE (i3) = insn_code_number;
    PATTERN (i3) = newpat;

    if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
      {
  rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);

  reset_used_flags (call_usage);
  call_usage = copy_rtx (call_usage);

  if (substed_i2)
    replace_rtx (call_usage, i2dest, i2src);

  if (substed_i1)
    replace_rtx (call_usage, i1dest, i1src);

  CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
      }

    if (undobuf.other_insn)
      INSN_CODE (undobuf.other_insn) = other_code_number;

    /* We had one special case above where I2 had more than one set and
       we replaced a destination of one of those sets with the destination
       of I3.  In that case, we have to update LOG_LINKS of insns later
       in this basic block.  Note that this (expensive) case is rare.

       Also, in this case, we must pretend that all REG_NOTEs for I2
       actually came from I3, so that REG_UNUSED notes from I2 will be
       properly handled.  */

    if (i3_subst_into_i2)
      {
  for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
    if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
        && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
        && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
        && ! find_reg_note (i2, REG_UNUSED,
          SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
      for (temp = NEXT_INSN (i2);
     temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
        || this_basic_block->head != temp);
     temp = NEXT_INSN (temp))
        if (temp != i3 && INSN_P (temp))
    for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
      if (XEXP (link, 0) == i2)
        XEXP (link, 0) = i3;

  if (i3notes)
    {
      rtx link = i3notes;
      while (XEXP (link, 1))
        link = XEXP (link, 1);
      XEXP (link, 1) = i2notes;
    }
  else
    i3notes = i2notes;
  i2notes = 0;
      }

    LOG_LINKS (i3) = 0;
    REG_NOTES (i3) = 0;
    LOG_LINKS (i2) = 0;
    REG_NOTES (i2) = 0;

    if (newi2pat)
      {
  INSN_CODE (i2) = i2_code_number;
  PATTERN (i2) = newi2pat;
      }
    else
      {
  PUT_CODE (i2, NOTE);
  NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
  NOTE_SOURCE_FILE (i2) = 0;
      }

    if (i1)
      {
  LOG_LINKS (i1) = 0;
  REG_NOTES (i1) = 0;
  PUT_CODE (i1, NOTE);
  NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
  NOTE_SOURCE_FILE (i1) = 0;
      }

    /* Get death notes for everything that is now used in either I3 or
       I2 and used to die in a previous insn.  If we built two new
       patterns, move from I1 to I2 then I2 to I3 so that we get the
       proper movement on registers that I2 modifies.  */

    if (newi2pat)
      {
  move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
  move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
      }
    else
      move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
       i3, &midnotes);

    /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
    if (i3notes)
      distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
      elim_i2, elim_i1);
    if (i2notes)
      distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
      elim_i2, elim_i1);
    if (i1notes)
      distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
      elim_i2, elim_i1);
    if (midnotes)
      distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
      elim_i2, elim_i1);

    /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
       know these are REG_UNUSED and want them to go to the desired insn,
       so we always pass it as i3.  We have not counted the notes in
       reg_n_deaths yet, so we need to do so now.  */

    if (newi2pat && new_i2_notes)
      {
  for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
    if (GET_CODE (XEXP (temp, 0)) == REG)
      REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;

  distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
      }

    if (new_i3_notes)
      {
  for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
    if (GET_CODE (XEXP (temp, 0)) == REG)
      REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;

  distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
      }

    /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
       put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
       I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
       in that case, it might delete I2.  Similarly for I2 and I1.
       Show an additional death due to the REG_DEAD note we make here.  If
       we discard it in distribute_notes, we will decrement it again.  */

    if (i3dest_killed)
      {
  if (GET_CODE (i3dest_killed) == REG)
    REG_N_DEATHS (REGNO (i3dest_killed))++;

  if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
    distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
                 NULL_RTX),
          NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
  else
    distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
                 NULL_RTX),
          NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
          elim_i2, elim_i1);
      }

    if (i2dest_in_i2src)
      {
  if (GET_CODE (i2dest) == REG)
    REG_N_DEATHS (REGNO (i2dest))++;

  if (newi2pat && reg_set_p (i2dest, newi2pat))
    distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
          NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
  else
    distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
          NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
          NULL_RTX, NULL_RTX);
      }

    if (i1dest_in_i1src)
      {
  if (GET_CODE (i1dest) == REG)
    REG_N_DEATHS (REGNO (i1dest))++;

  if (newi2pat && reg_set_p (i1dest, newi2pat))
    distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
          NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
  else
    distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
          NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
          NULL_RTX, NULL_RTX);
      }

    distribute_links (i3links);
    distribute_links (i2links);
    distribute_links (i1links);

    if (GET_CODE (i2dest) == REG)
      {
  rtx link;
  rtx i2_insn = 0, i2_val = 0, set;

  /* The insn that used to set this register doesn't exist, and
     this life of the register may not exist either.  See if one of
     I3's links points to an insn that sets I2DEST.  If it does,
     that is now the last known value for I2DEST. If we don't update
     this and I2 set the register to a value that depended on its old
     contents, we will get confused.  If this insn is used, thing
     will be set correctly in combine_instructions.  */

  for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
    if ((set = single_set (XEXP (link, 0))) != 0
        && rtx_equal_p (i2dest, SET_DEST (set)))
      i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);

  record_value_for_reg (i2dest, i2_insn, i2_val);

  /* If the reg formerly set in I2 died only once and that was in I3,
     zero its use count so it won't make `reload' do any work.  */
  if (! added_sets_2
      && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
      && ! i2dest_in_i2src)
    {
      regno = REGNO (i2dest);
      REG_N_SETS (regno)--;
    }
      }

    if (i1 && GET_CODE (i1dest) == REG)
      {
  rtx link;
  rtx i1_insn = 0, i1_val = 0, set;

  for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
    if ((set = single_set (XEXP (link, 0))) != 0
        && rtx_equal_p (i1dest, SET_DEST (set)))
      i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);

  record_value_for_reg (i1dest, i1_insn, i1_val);

  regno = REGNO (i1dest);
  if (! added_sets_1 && ! i1dest_in_i1src)
    REG_N_SETS (regno)--;
      }

    /* Update reg_nonzero_bits et al for any changes that may have been made
       to this insn.  The order of set_nonzero_bits_and_sign_copies() is
       important.  Because newi2pat can affect nonzero_bits of newpat */
    if (newi2pat)
      note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
    note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);

    /* Set new_direct_jump_p if a new return or simple jump instruction
       has been created.

       If I3 is now an unconditional jump, ensure that it has a
       BARRIER following it since it may have initially been a
       conditional jump.  It may also be the last nonnote insn.  */

    if (returnjump_p (i3) || any_uncondjump_p (i3))
      {
  *new_direct_jump_p = 1;

  if ((temp = next_nonnote_insn (i3)) == NULL_RTX
      || GET_CODE (temp) != BARRIER)
    emit_barrier_after (i3);
      }

    if (undobuf.other_insn != NULL_RTX
  && (returnjump_p (undobuf.other_insn)
      || any_uncondjump_p (undobuf.other_insn)))
      {
  *new_direct_jump_p = 1;

  if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
      || GET_CODE (temp) != BARRIER)
    emit_barrier_after (undobuf.other_insn);
      }
  
    /* An NOOP jump does not need barrier, but it does need cleaning up
       of CFG.  */
    if (GET_CODE (newpat) == SET
  && SET_SRC (newpat) == pc_rtx
  && SET_DEST (newpat) == pc_rtx)
      *new_direct_jump_p = 1;
  }

  combine_successes++;
  undo_commit ();

  /* Clear this here, so that subsequent get_last_value calls are not
     affected.  */
  subst_prev_insn = NULL_RTX;

  if (added_links_insn
      && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
      && INSN_CUID (added_links_insn) < INSN_CUID (i3))
    return added_links_insn;
  else
    return newi2pat ? i2 : i3;
}

/* Undo all the modifications recorded in undobuf.  */

static void
undo_all ()
{
  struct undo *undo, *next;

  for (undo = undobuf.undos; undo; undo = next)
    {
      next = undo->next;
      if (undo->is_int)
  *undo->where.i = undo->old_contents.i;
      else
  *undo->where.r = undo->old_contents.r;

      undo->next = undobuf.frees;
      undobuf.frees = undo;
    }

  undobuf.undos = 0;

  /* Clear this here, so that subsequent get_last_value calls are not
     affected.  */
  subst_prev_insn = NULL_RTX;
}

/* We've committed to accepting the changes we made.  Move all
   of the undos to the free list.  */

static void
undo_commit ()
{
  struct undo *undo, *next;

  for (undo = undobuf.undos; undo; undo = next)
    {
      next = undo->next;
      undo->next = undobuf.frees;
      undobuf.frees = undo;
    }
  undobuf.undos = 0;
}


/* Find the innermost point within the rtx at LOC, possibly LOC itself,
   where we have an arithmetic expression and return that point.  LOC will
   be inside INSN.

   try_combine will call this function to see if an insn can be split into
   two insns.  */

static rtx *
find_split_point (loc, insn)
     rtx *loc;
     rtx insn;
{
  rtx x = *loc;
  enum rtx_code code = GET_CODE (x);
  rtx *split;
  unsigned HOST_WIDE_INT len = 0;
  HOST_WIDE_INT pos = 0;
  int unsignedp = 0;
  rtx inner = NULL_RTX;

  /* First special-case some codes.  */
  switch (code)
    {
    case SUBREG:
#ifdef INSN_SCHEDULING
      /* If we are making a paradoxical SUBREG invalid, it becomes a split
   point.  */
      if (GET_CODE (SUBREG_REG (x)) == MEM)
  return loc;
#endif
      return find_split_point (&SUBREG_REG (x), insn);

    case MEM:
#ifdef HAVE_lo_sum
      /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
   using LO_SUM and HIGH.  */
      if (GET_CODE (XEXP (x, 0)) == CONST
    || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
  {
    SUBST (XEXP (x, 0),
     gen_rtx_LO_SUM (Pmode,
         gen_rtx_HIGH (Pmode, XEXP (x, 0)),
         XEXP (x, 0)));
    return &XEXP (XEXP (x, 0), 0);
  }
#endif

      /* If we have a PLUS whose second operand is a constant and the
   address is not valid, perhaps will can split it up using
   the machine-specific way to split large constants.  We use
   the first pseudo-reg (one of the virtual regs) as a placeholder;
   it will not remain in the result.  */
      if (GET_CODE (XEXP (x, 0)) == PLUS
    && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
    && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
  {
    rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
    rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
         subst_insn);

    /* This should have produced two insns, each of which sets our
       placeholder.  If the source of the second is a valid address,
       we can make put both sources together and make a split point
       in the middle.  */

    if (seq
        && NEXT_INSN (seq) != NULL_RTX
        && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
        && GET_CODE (seq) == INSN
        && GET_CODE (PATTERN (seq)) == SET
        && SET_DEST (PATTERN (seq)) == reg
        && ! reg_mentioned_p (reg,
            SET_SRC (PATTERN (seq)))
        && GET_CODE (NEXT_INSN (seq)) == INSN
        && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
        && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
        && memory_address_p (GET_MODE (x),
           SET_SRC (PATTERN (NEXT_INSN (seq)))))
      {
        rtx src1 = SET_SRC (PATTERN (seq));
        rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));

        /* Replace the placeholder in SRC2 with SRC1.  If we can
     find where in SRC2 it was placed, that can become our
     split point and we can replace this address with SRC2.
     Just try two obvious places.  */

        src2 = replace_rtx (src2, reg, src1);
        split = 0;
        if (XEXP (src2, 0) == src1)
    split = &XEXP (src2, 0);
        else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
           && XEXP (XEXP (src2, 0), 0) == src1)
    split = &XEXP (XEXP (src2, 0), 0);

        if (split)
    {
      SUBST (XEXP (x, 0), src2);
      return split;
    }
      }

    /* If that didn't work, perhaps the first operand is complex and
       needs to be computed separately, so make a split point there.
       This will occur on machines that just support REG + CONST
       and have a constant moved through some previous computation.  */

    else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
       && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
       && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
           == 'o')))
      return &XEXP (XEXP (x, 0), 0);
  }
      break;

    case SET:
#ifdef HAVE_cc0
      /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
   ZERO_EXTRACT, the most likely reason why this doesn't match is that
   we need to put the operand into a register.  So split at that
   point.  */

      if (SET_DEST (x) == cc0_rtx
    && GET_CODE (SET_SRC (x)) != COMPARE
    && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
    && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
    && ! (GET_CODE (SET_SRC (x)) == SUBREG
    && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
  return &SET_SRC (x);
#endif

      /* See if we can split SET_SRC as it stands.  */
      split = find_split_point (&SET_SRC (x), insn);
      if (split && split != &SET_SRC (x))
  return split;

      /* See if we can split SET_DEST as it stands.  */
      split = find_split_point (&SET_DEST (x), insn);
      if (split && split != &SET_DEST (x))
  return split;

      /* See if this is a bitfield assignment with everything constant.  If
   so, this is an IOR of an AND, so split it into that.  */
      if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
    && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
        <= HOST_BITS_PER_WIDE_INT)
    && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
    && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
    && GET_CODE (SET_SRC (x)) == CONST_INT
    && ((INTVAL (XEXP (SET_DEST (x), 1))
         + INTVAL (XEXP (SET_DEST (x), 2)))
        <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
    && ! side_effects_p (XEXP (SET_DEST (x), 0)))
  {
    HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
    unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
    unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
    rtx dest = XEXP (SET_DEST (x), 0);
    enum machine_mode mode = GET_MODE (dest);
    unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;

    if (BITS_BIG_ENDIAN)
      pos = GET_MODE_BITSIZE (mode) - len - pos;

    if (src == mask)
      SUBST (SET_SRC (x),
       gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
    else
      SUBST (SET_SRC (x),
       gen_binary (IOR, mode,
             gen_binary (AND, mode, dest,
             gen_int_mode (~(mask << pos),
               mode)),
             GEN_INT (src << pos)));

    SUBST (SET_DEST (x), dest);

    split = find_split_point (&SET_SRC (x), insn);
    if (split && split != &SET_SRC (x))
      return split;
  }

      /* Otherwise, see if this is an operation that we can split into two.
   If so, try to split that.  */
      code = GET_CODE (SET_SRC (x));

      switch (code)
  {
  case AND:
    /* If we are AND'ing with a large constant that is only a single
       bit and the result is only being used in a context where we
       need to know if it is zero or nonzero, replace it with a bit
       extraction.  This will avoid the large constant, which might
       have taken more than one insn to make.  If the constant were
       not a valid argument to the AND but took only one insn to make,
       this is no worse, but if it took more than one insn, it will
       be better.  */

    if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
        && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
        && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
        && GET_CODE (SET_DEST (x)) == REG
        && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
        && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
        && XEXP (*split, 0) == SET_DEST (x)
        && XEXP (*split, 1) == const0_rtx)
      {
        rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
            XEXP (SET_SRC (x), 0),
            pos, NULL_RTX, 1, 1, 0, 0);
        if (extraction != 0)
    {
      SUBST (SET_SRC (x), extraction);
      return find_split_point (loc, insn);
    }
      }
    break;

  case NE:
    /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
       is known to be on, this can be converted into a NEG of a shift.  */
    if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
        && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
        && 1 <= (pos = exact_log2
           (nonzero_bits (XEXP (SET_SRC (x), 0),
              GET_MODE (XEXP (SET_SRC (x), 0))))))
      {
        enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));

        SUBST (SET_SRC (x),
         gen_rtx_NEG (mode,
          gen_rtx_LSHIFTRT (mode,
                XEXP (SET_SRC (x), 0),
                GEN_INT (pos))));

        split = find_split_point (&SET_SRC (x), insn);
        if (split && split != &SET_SRC (x))
    return split;
      }
    break;

  case SIGN_EXTEND:
    inner = XEXP (SET_SRC (x), 0);

    /* We can't optimize if either mode is a partial integer
       mode as we don't know how many bits are significant
       in those modes.  */
    if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
        || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
      break;

    pos = 0;
    len = GET_MODE_BITSIZE (GET_MODE (inner));
    unsignedp = 0;
    break;

  case SIGN_EXTRACT:
  case ZERO_EXTRACT:
    if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
        && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
      {
        inner = XEXP (SET_SRC (x), 0);
        len = INTVAL (XEXP (SET_SRC (x), 1));
        pos = INTVAL (XEXP (SET_SRC (x), 2));

        if (BITS_BIG_ENDIAN)
    pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
        unsignedp = (code == ZERO_EXTRACT);
      }
    break;

  default:
    break;
  }

      if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
  {
    enum machine_mode mode = GET_MODE (SET_SRC (x));

    /* For unsigned, we have a choice of a shift followed by an
       AND or two shifts.  Use two shifts for field sizes where the
       constant might be too large.  We assume here that we can
       always at least get 8-bit constants in an AND insn, which is
       true for every current RISC.  */

    if (unsignedp && len <= 8)
      {
        SUBST (SET_SRC (x),
         gen_rtx_AND (mode,
          gen_rtx_LSHIFTRT
          (mode, gen_lowpart_for_combine (mode, inner),
           GEN_INT (pos)),
          GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));

        split = find_split_point (&SET_SRC (x), insn);
        if (split && split != &SET_SRC (x))
    return split;
      }
    else
      {
        SUBST (SET_SRC (x),
         gen_rtx_fmt_ee
         (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
          gen_rtx_ASHIFT (mode,
              gen_lowpart_for_combine (mode, inner),
              GEN_INT (GET_MODE_BITSIZE (mode)
                 - len - pos)),
          GEN_INT (GET_MODE_BITSIZE (mode) - len)));

        split = find_split_point (&SET_SRC (x), insn);
        if (split && split != &SET_SRC (x))
    return split;
      }
  }

      /* See if this is a simple operation with a constant as the second
   operand.  It might be that this constant is out of range and hence
   could be used as a split point.  */
      if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
     || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
     || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
    && CONSTANT_P (XEXP (SET_SRC (x), 1))
    && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
        || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
          == 'o'))))
  return &XEXP (SET_SRC (x), 1);

      /* Finally, see if this is a simple operation with its first operand
   not in a register.  The operation might require this operand in a
   register, so return it as a split point.  We can always do this
   because if the first operand were another operation, we would have
   already found it as a split point.  */
      if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
     || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
     || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
     || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
    && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
  return &XEXP (SET_SRC (x), 0);

      return 0;

    case AND:
    case IOR:
      /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
   it is better to write this as (not (ior A B)) so we can split it.
   Similarly for IOR.  */
      if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
  {
    SUBST (*loc,
     gen_rtx_NOT (GET_MODE (x),
            gen_rtx_fmt_ee (code == IOR ? AND : IOR,
                GET_MODE (x),
                XEXP (XEXP (x, 0), 0),
                XEXP (XEXP (x, 1), 0))));
    return find_split_point (loc, insn);
  }

      /* Many RISC machines have a large set of logical insns.  If the
   second operand is a NOT, put it first so we will try to split the
   other operand first.  */
      if (GET_CODE (XEXP (x, 1)) == NOT)
  {
    rtx tem = XEXP (x, 0);
    SUBST (XEXP (x, 0), XEXP (x, 1));
    SUBST (XEXP (x, 1), tem);
  }
      break;

    default:
      break;
    }

  /* Otherwise, select our actions depending on our rtx class.  */
  switch (GET_RTX_CLASS (code))
    {
    case 'b':     /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
    case '3':
      split = find_split_point (&XEXP (x, 2), insn);
      if (split)
  return split;
      /* ... fall through ...  */
    case '2':
    case 'c':
    case '<':
      split = find_split_point (&XEXP (x, 1), insn);
      if (split)
  return split;
      /* ... fall through ...  */
    case '1':
      /* Some machines have (and (shift ...) ...) insns.  If X is not
   an AND, but XEXP (X, 0) is, use it as our split point.  */
      if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
  return &XEXP (x, 0);

      split = find_split_point (&XEXP (x, 0), insn);
      if (split)
  return split;
      return loc;
    }

  /* Otherwise, we don't have a split point.  */
  return 0;
}

/* Throughout X, replace FROM with TO, and return the result.
   The result is TO if X is FROM;
   otherwise the result is X, but its contents may have been modified.
   If they were modified, a record was made in undobuf so that
   undo_all will (among other things) return X to its original state.

   If the number of changes necessary is too much to record to undo,
   the excess changes are not made, so the result is invalid.
   The changes already made can still be undone.
   undobuf.num_undo is incremented for such changes, so by testing that
   the caller can tell whether the result is valid.

   `n_occurrences' is incremented each time FROM is replaced.

   IN_DEST is nonzero if we are processing the SET_DEST of a SET.

   UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
   by copying if `n_occurrences' is nonzero.  */

static rtx
subst (x, from, to, in_dest, unique_copy)
     rtx x, from, to;
     int in_dest;
     int unique_copy;
{
  enum rtx_code code = GET_CODE (x);
  enum machine_mode op0_mode = VOIDmode;
  const char *fmt;
  int len, i;
  rtx new;

/* Two expressions are equal if they are identical copies of a shared
   RTX or if they are both registers with the same register number
   and mode.  */

#define COMBINE_RTX_EQUAL_P(X,Y)      \
  ((X) == (Y)           \
   || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
       && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))

  if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
    {
      n_occurrences++;
      return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
    }

  /* If X and FROM are the same register but different modes, they will
     not have been seen as equal above.  However, flow.c will make a
     LOG_LINKS entry for that case.  If we do nothing, we will try to
     rerecognize our original insn and, when it succeeds, we will
     delete the feeding insn, which is incorrect.

     So force this insn not to match in this (rare) case.  */
  if (! in_dest && code == REG && GET_CODE (from) == REG
      && REGNO (x) == REGNO (from))
    return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);

  /* If this is an object, we are done unless it is a MEM or LO_SUM, both
     of which may contain things that can be combined.  */
  if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
    return x;

  /* It is possible to have a subexpression appear twice in the insn.
     Suppose that FROM is a register that appears within TO.
     Then, after that subexpression has been scanned once by `subst',
     the second time it is scanned, TO may be found.  If we were
     to scan TO here, we would find FROM within it and create a
     self-referent rtl structure which is completely wrong.  */
  if (COMBINE_RTX_EQUAL_P (x, to))
    return to;

  /* Parallel asm_operands need special attention because all of the
     inputs are shared across the arms.  Furthermore, unsharing the
     rtl results in recognition failures.  Failure to handle this case
     specially can result in circular rtl.

     Solve this by doing a normal pass across the first entry of the
     parallel, and only processing the SET_DESTs of the subsequent
     entries.  Ug.  */

  if (code == PARALLEL
      && GET_CODE (XVECEXP (x, 0, 0)) == SET
      && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
    {
      new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);

      /* If this substitution failed, this whole thing fails.  */
      if (GET_CODE (new) == CLOBBER
    && XEXP (new, 0) == const0_rtx)
  return new;

      SUBST (XVECEXP (x, 0, 0), new);

      for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
  {
    rtx dest = SET_DEST (XVECEXP (x, 0, i));

    if (GET_CODE (dest) != REG
        && GET_CODE (dest) != CC0
        && GET_CODE (dest) != PC)
      {
        new = subst (dest, from, to, 0, unique_copy);

        /* If this substitution failed, this whole thing fails.  */
        if (GET_CODE (new) == CLOBBER
      && XEXP (new, 0) == const0_rtx)
    return new;

        SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
      }
  }
    }
  else
    {
      len = GET_RTX_LENGTH (code);
      fmt = GET_RTX_FORMAT (code);

      /* We don't need to process a SET_DEST that is a register, CC0,
   or PC, so set up to skip this common case.  All other cases
   where we want to suppress replacing something inside a
   SET_SRC are handled via the IN_DEST operand.  */
      if (code == SET
    && (GET_CODE (SET_DEST (x)) == REG
        || GET_CODE (SET_DEST (x)) == CC0
        || GET_CODE (SET_DEST (x)) == PC))
  fmt = "ie";

      /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
   constant.  */
      if (fmt[0] == 'e')
  op0_mode = GET_MODE (XEXP (x, 0));

      for (i = 0; i < len; i++)
  {
    if (fmt[i] == 'E')
      {
        int j;
        for (j = XVECLEN (x, i) - 1; j >= 0; j--)
    {
      if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
        {
          new = (unique_copy && n_occurrences
           ? copy_rtx (to) : to);
          n_occurrences++;
        }
      else
        {
          new = subst (XVECEXP (x, i, j), from, to, 0,
           unique_copy);

          /* If this substitution failed, this whole thing
       fails.  */
          if (GET_CODE (new) == CLOBBER
        && XEXP (new, 0) == const0_rtx)
      return new;
        }

      SUBST (XVECEXP (x, i, j), new);
    }
      }
    else if (fmt[i] == 'e')
      {
        /* If this is a register being set, ignore it.  */
        new = XEXP (x, i);
        if (in_dest
      && (code == SUBREG || code == STRICT_LOW_PART
          || code == ZERO_EXTRACT)
      && i == 0
      && GET_CODE (new) == REG)
    ;

        else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
    {
      /* In general, don't install a subreg involving two
         modes not tieable.  It can worsen register
         allocation, and can even make invalid reload
         insns, since the reg inside may need to be copied
         from in the outside mode, and that may be invalid
         if it is an fp reg copied in integer mode.

         We allow two exceptions to this: It is valid if
         it is inside another SUBREG and the mode of that
         SUBREG and the mode of the inside of TO is
         tieable and it is valid if X is a SET that copies
         FROM to CC0.  */

      if (GET_CODE (to) == SUBREG
          && ! MODES_TIEABLE_P (GET_MODE (to),
              GET_MODE (SUBREG_REG (to)))
          && ! (code == SUBREG
          && MODES_TIEABLE_P (GET_MODE (x),
            GET_MODE (SUBREG_REG (to))))
#ifdef HAVE_cc0
          && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
#endif
          )
        return gen_rtx_CLOBBER (VOIDmode, const0_rtx);

#ifdef CANNOT_CHANGE_MODE_CLASS
      if (code == SUBREG
          && GET_CODE (to) == REG
          && REGNO (to) < FIRST_PSEUDO_REGISTER
          && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
               GET_MODE (to),
               GET_MODE (x)))
        return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
#endif

      new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
      n_occurrences++;
    }
        else
    /* If we are in a SET_DEST, suppress most cases unless we
       have gone inside a MEM, in which case we want to
       simplify the address.  We assume here that things that
       are actually part of the destination have their inner
       parts in the first expression.  This is true for SUBREG,
       STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
       things aside from REG and MEM that should appear in a
       SET_DEST.  */
    new = subst (XEXP (x, i), from, to,
           (((in_dest
        && (code == SUBREG || code == STRICT_LOW_PART
            || code == ZERO_EXTRACT))
             || code == SET)
            && i == 0), unique_copy);

        /* If we found that we will have to reject this combination,
     indicate that by returning the CLOBBER ourselves, rather than
     an expression containing it.  This will speed things up as
     well as prevent accidents where two CLOBBERs are considered
     to be equal, thus producing an incorrect simplification.  */

        if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
    return new;

        if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
    {
      enum machine_mode mode = GET_MODE (x);

      x = simplify_subreg (GET_MODE (x), new,
               GET_MODE (SUBREG_REG (x)),
               SUBREG_BYTE (x));
      if (! x)
        x = gen_rtx_CLOBBER (mode, const0_rtx);
    }
        else if (GET_CODE (new) == CONST_INT
           && GET_CODE (x) == ZERO_EXTEND)
    {
      x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
            new, GET_MODE (XEXP (x, 0)));
      if (! x)
        abort ();
    }
        else
    SUBST (XEXP (x, i), new);
      }
  }
    }

  /* Try to simplify X.  If the simplification changed the code, it is likely
     that further simplification will help, so loop, but limit the number
     of repetitions that will be performed.  */

  for (i = 0; i < 4; i++)
    {
      /* If X is sufficiently simple, don't bother trying to do anything
   with it.  */
      if (code != CONST_INT && code != REG && code != CLOBBER)
  x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);

      if (GET_CODE (x) == code)
  break;

      code = GET_CODE (x);

      /* We no longer know the original mode of operand 0 since we
   have changed the form of X)  */
      op0_mode = VOIDmode;
    }

  return x;
}

/* Simplify X, a piece of RTL.  We just operate on the expression at the
   outer level; call `subst' to simplify recursively.  Return the new
   expression.

   OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
   will be the iteration even if an expression with a code different from
   X is returned; IN_DEST is nonzero if we are inside a SET_DEST.  */

static rtx
combine_simplify_rtx (x, op0_mode, last, in_dest)
     rtx x;
     enum machine_mode op0_mode;
     int last;
     int in_dest;
{
  enum rtx_code code = GET_CODE (x);
  enum machine_mode mode = GET_MODE (x);
  rtx temp;
  rtx reversed;
  int i;

  /* If this is a commutative operation, put a constant last and a complex
     expression first.  We don't need to do this for comparisons here.  */
  if (GET_RTX_CLASS (code) == 'c'
      && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
    {
      temp = XEXP (x, 0);
      SUBST (XEXP (x, 0), XEXP (x, 1));
      SUBST (XEXP (x, 1), temp);
    }

  /* If this is a PLUS, MINUS, or MULT, and the first operand is the
     sign extension of a PLUS with a constant, reverse the order of the sign
     extension and the addition. Note that this not the same as the original
     code, but overflow is undefined for signed values.  Also note that the
     PLUS will have been partially moved "inside" the sign-extension, so that
     the first operand of X will really look like:
         (ashiftrt (plus (ashift A C4) C5) C4).
     We convert this to
         (plus (ashiftrt (ashift A C4) C2) C4)
     and replace the first operand of X with that expression.  Later parts
     of this function may simplify the expression further.

     For example, if we start with (mult (sign_extend (plus A C1)) C2),
     we swap the SIGN_EXTEND and PLUS.  Later code will apply the
     distributive law to produce (plus (mult (sign_extend X) C1) C3).

     We do this to simplify address expressions.  */

  if ((code == PLUS || code == MINUS || code == MULT)
      && GET_CODE (XEXP (x, 0)) == ASHIFTRT
      && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
      && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
      && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
      && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
      && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
      && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
      && (temp = simplify_binary_operation (ASHIFTRT, mode,
              XEXP (XEXP (XEXP (x, 0), 0), 1),
              XEXP (XEXP (x, 0), 1))) != 0)
    {
      rtx new
  = simplify_shift_const (NULL_RTX, ASHIFT, mode,
        XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
        INTVAL (XEXP (XEXP (x, 0), 1)));

      new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
          INTVAL (XEXP (XEXP (x, 0), 1)));

      SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
    }

  /* If this is a simple operation applied to an IF_THEN_ELSE, try
     applying it to the arms of the IF_THEN_ELSE.  This often simplifies
     things.  Check for cases where both arms are testing the same
     condition.

     Don't do anything if all operands are very simple.  */

  if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
  || GET_RTX_CLASS (code) == '<')
       && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
      && ! (GET_CODE (XEXP (x, 0)) == SUBREG
      && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
          == 'o')))
     || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
         && ! (GET_CODE (XEXP (x, 1)) == SUBREG
         && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
       == 'o')))))
      || (GET_RTX_CLASS (code) == '1'
    && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
         && ! (GET_CODE (XEXP (x, 0)) == SUBREG
         && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
       == 'o'))))))
    {
      rtx cond, true_rtx, false_rtx;

      cond = if_then_else_cond (x, &true_rtx, &false_rtx);
      if (cond != 0
    /* If everything is a comparison, what we have is highly unlikely
       to be simpler, so don't use it.  */
    && ! (GET_RTX_CLASS (code) == '<'
    && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
        || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
  {
    rtx cop1 = const0_rtx;
    enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);

    if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
      return x;

    /* Simplify the alternative arms; this may collapse the true and
       false arms to store-flag values.  */
    true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
    false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);

    /* If true_rtx and false_rtx are not general_operands, an if_then_else
       is unlikely to be simpler.  */
    if (general_operand (true_rtx, VOIDmode)
        && general_operand (false_rtx, VOIDmode))
      {
        /* Restarting if we generate a store-flag expression will cause
     us to loop.  Just drop through in this case.  */

        /* If the result values are STORE_FLAG_VALUE and zero, we can
     just make the comparison operation.  */
        if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
    x = gen_binary (cond_code, mode, cond, cop1);
        else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
           && reverse_condition (cond_code) != UNKNOWN)
    x = gen_binary (reverse_condition (cond_code),
        mode, cond, cop1);

        /* Likewise, we can make the negate of a comparison operation
     if the result values are - STORE_FLAG_VALUE and zero.  */
        else if (GET_CODE (true_rtx) == CONST_INT
           && INTVAL (true_rtx) == - STORE_FLAG_VALUE
           && false_rtx == const0_rtx)
    x = simplify_gen_unary (NEG, mode,
          gen_binary (cond_code, mode, cond,
                cop1),
          mode);
        else if (GET_CODE (false_rtx) == CONST_INT
           && INTVAL (false_rtx) == - STORE_FLAG_VALUE
           && true_rtx == const0_rtx)
    x = simplify_gen_unary (NEG, mode,
          gen_binary (reverse_condition
                (cond_code),
                mode, cond, cop1),
          mode);
        else
    return gen_rtx_IF_THEN_ELSE (mode,
               gen_binary (cond_code, VOIDmode,
               cond, cop1),
               true_rtx, false_rtx);

        code = GET_CODE (x);
        op0_mode = VOIDmode;
      }
  }
    }

  /* Try to fold this expression in case we have constants that weren't
     present before.  */
  temp = 0;
  switch (GET_RTX_CLASS (code))
    {
    case '1':
      temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
      break;
    case '<':
      {
  enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
  if (cmp_mode == VOIDmode)
    {
      cmp_mode = GET_MODE (XEXP (x, 1));
      if (cmp_mode == VOIDmode)
        cmp_mode = op0_mode;
    }
  temp = simplify_relational_operation (code, cmp_mode,
                XEXP (x, 0), XEXP (x, 1));
      }
#ifdef FLOAT_STORE_FLAG_VALUE
      if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
  {
    if (temp == const0_rtx)
      temp = CONST0_RTX (mode);
    else
      temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
             mode);
  }
#endif
      break;
    case 'c':
    case '2':
      temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
      break;
    case 'b':
    case '3':
      temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
           XEXP (x, 1), XEXP (x, 2));
      break;
    }

  if (temp)
    {
      x = temp;
      code = GET_CODE (temp);
      op0_mode = VOIDmode;
      mode = GET_MODE (temp);
    }

  /* First see if we can apply the inverse distributive law.  */
  if (code == PLUS || code == MINUS
      || code == AND || code == IOR || code == XOR)
    {
      x = apply_distributive_law (x);
      code = GET_CODE (x);
      op0_mode = VOIDmode;
    }

  /* If CODE is an associative operation not otherwise handled, see if we
     can associate some operands.  This can win if they are constants or
     if they are logically related (i.e. (a & b) & a).  */
  if ((code == PLUS || code == MINUS || code == MULT || code == DIV
       || code == AND || code == IOR || code == XOR
       || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
      && ((INTEGRAL_MODE_P (mode) && code != DIV)
    || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
    {
      if (GET_CODE (XEXP (x, 0)) == code)
  {
    rtx other = XEXP (XEXP (x, 0), 0);
    rtx inner_op0 = XEXP (XEXP (x, 0), 1);
    rtx inner_op1 = XEXP (x, 1);
    rtx inner;

    /* Make sure we pass the constant operand if any as the second
       one if this is a commutative operation.  */
    if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
      {
        rtx tem = inner_op0;
        inner_op0 = inner_op1;
        inner_op1 = tem;
      }
    inner = simplify_binary_operation (code == MINUS ? PLUS
               : code == DIV ? MULT
               : code,
               mode, inner_op0, inner_op1);

    /* For commutative operations, try the other pair if that one
       didn't simplify.  */
    if (inner == 0 && GET_RTX_CLASS (code) == 'c')
      {
        other = XEXP (XEXP (x, 0), 1);
        inner = simplify_binary_operation (code, mode,
             XEXP (XEXP (x, 0), 0),
             XEXP (x, 1));
      }

    if (inner)
      return gen_binary (code, mode, other, inner);
  }
    }

  /* A little bit of algebraic simplification here.  */
  switch (code)
    {
    case MEM:
      /* Ensure that our address has any ASHIFTs converted to MULT in case
   address-recognizing predicates are called later.  */
      temp = make_compound_operation (XEXP (x, 0), MEM);
      SUBST (XEXP (x, 0), temp);
      break;

    case SUBREG:
      if (op0_mode == VOIDmode)
  op0_mode = GET_MODE (SUBREG_REG (x));

      /* simplify_subreg can't use gen_lowpart_for_combine.  */
      if (CONSTANT_P (SUBREG_REG (x))
    && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
       /* Don't call gen_lowpart_for_combine if the inner mode
    is VOIDmode and we cannot simplify it, as SUBREG without
    inner mode is invalid.  */
    && (GET_MODE (SUBREG_REG (x)) != VOIDmode
        || gen_lowpart_common (mode, SUBREG_REG (x))))
  return gen_lowpart_for_combine (mode, SUBREG_REG (x));

      if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
        break;
      {
  rtx temp;
  temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
        SUBREG_BYTE (x));
  if (temp)
    return temp;
      }

      /* Don't change the mode of the MEM if that would change the meaning
   of the address.  */
      if (GET_CODE (SUBREG_REG (x)) == MEM
    && (MEM_VOLATILE_P (SUBREG_REG (x))
        || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
  return gen_rtx_CLOBBER (mode, const0_rtx);

      /* Note that we cannot do any narrowing for non-constants since
   we might have been counting on using the fact that some bits were
   zero.  We now do this in the SET.  */

      break;

    case NOT:
      /* (not (plus X -1)) can become (neg X).  */
      if (GET_CODE (XEXP (x, 0)) == PLUS
    && XEXP (XEXP (x, 0), 1) == constm1_rtx)
  return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));

      /* Similarly, (not (neg X)) is (plus X -1).  */
      if (GET_CODE (XEXP (x, 0)) == NEG)
  return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);

      /* (not (xor X C)) for C constant is (xor X D) with D = ~C.  */
      if (GET_CODE (XEXP (x, 0)) == XOR
    && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
    && (temp = simplify_unary_operation (NOT, mode,
                 XEXP (XEXP (x, 0), 1),
                 mode)) != 0)
  return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);

      /* (not (ashift 1 X)) is (rotate ~1 X).  We used to do this for operands
   other than 1, but that is not valid.  We could do a similar
   simplification for (not (lshiftrt C X)) where C is just the sign bit,
   but this doesn't seem common enough to bother with.  */
      if (GET_CODE (XEXP (x, 0)) == ASHIFT
    && XEXP (XEXP (x, 0), 0) == const1_rtx)
  return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
               const1_rtx, mode),
             XEXP (XEXP (x, 0), 1));

      if (GET_CODE (XEXP (x, 0)) == SUBREG
    && subreg_lowpart_p (XEXP (x, 0))
    && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
        < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
    && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
    && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
  {
    enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));

    x = gen_rtx_ROTATE (inner_mode,
            simplify_gen_unary (NOT, inner_mode, const1_rtx,
              inner_mode),
            XEXP (SUBREG_REG (XEXP (x, 0)), 1));
    return gen_lowpart_for_combine (mode, x);
  }

      /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
   reversing the comparison code if valid.  */
      if (STORE_FLAG_VALUE == -1
    && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
    && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
                XEXP (XEXP (x, 0), 1))))
  return reversed;

      /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
   is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
   perform the above simplification.  */

      if (STORE_FLAG_VALUE == -1
    && GET_CODE (XEXP (x, 0)) == ASHIFTRT
    && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
    && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
  return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);

      /* Apply De Morgan's laws to reduce number of patterns for machines
   with negating logical insns (and-not, nand, etc.).  If result has
   only one NOT, put it first, since that is how the patterns are
   coded.  */

      if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
  {
    rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
    enum machine_mode op_mode;

    op_mode = GET_MODE (in1);
    in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);

    op_mode = GET_MODE (in2);
    if (op_mode == VOIDmode)
      op_mode = mode;
    in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);

    if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
      {
        rtx tem = in2;
        in2 = in1; in1 = tem;
      }

    return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
         mode, in1, in2);
  }
      break;

    case NEG:
      /* (neg (plus X 1)) can become (not X).  */
      if (GET_CODE (XEXP (x, 0)) == PLUS
    && XEXP (XEXP (x, 0), 1) == const1_rtx)
  return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));

      /* Similarly, (neg (not X)) is (plus X 1).  */
      if (GET_CODE (XEXP (x, 0)) == NOT)
  return plus_constant (XEXP (XEXP (x, 0), 0), 1);

      /* (neg (minus X Y)) can become (minus Y X).  This transformation
   isn't safe for modes with signed zeros, since if X and Y are
   both +0, (minus Y X) is the same as (minus X Y).  If the rounding
   mode is towards +infinity (or -infinity) then the two expressions
   will be rounded differently.  */
      if (GET_CODE (XEXP (x, 0)) == MINUS
    && !HONOR_SIGNED_ZEROS (mode)
    && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
  return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
         XEXP (XEXP (x, 0), 0));

      /* (neg (plus A B)) is canonicalized to (minus (neg A) B).  */
      if (GET_CODE (XEXP (x, 0)) == PLUS
    && !HONOR_SIGNED_ZEROS (mode)
    && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
  {
    temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
    temp = combine_simplify_rtx (temp, mode, last, in_dest);
    return gen_binary (MINUS, mode, temp, XEXP (XEXP (x, 0), 1));
  }

      /* (neg (mult A B)) becomes (mult (neg A) B).  
         This works even for floating-point values.  */
      if (GET_CODE (XEXP (x, 0)) == MULT)
  {
    temp = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 0), 0), mode);
    return gen_binary (MULT, mode, temp, XEXP (XEXP (x, 0), 1));
  }

      /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1.  */
      if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
    && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
  return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);

      /* NEG commutes with ASHIFT since it is multiplication.  Only do this
   if we can then eliminate the NEG (e.g.,
   if the operand is a constant).  */

      if (GET_CODE (XEXP (x, 0)) == ASHIFT)
  {
    temp = simplify_unary_operation (NEG, mode,
             XEXP (XEXP (x, 0), 0), mode);
    if (temp)
      return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
  }

      temp = expand_compound_operation (XEXP (x, 0));

      /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
   replaced by (lshiftrt X C).  This will convert
   (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */

      if (GET_CODE (temp) == ASHIFTRT
    && GET_CODE (XEXP (temp, 1)) == CONST_INT
    && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
  return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
             INTVAL (XEXP (temp, 1)));

      /* If X has only a single bit that might be nonzero, say, bit I, convert
   (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
   MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
   (sign_extract X 1 Y).  But only do this if TEMP isn't a register
   or a SUBREG of one since we'd be making the expression more
   complex if it was just a register.  */

      if (GET_CODE (temp) != REG
    && ! (GET_CODE (temp) == SUBREG
    && GET_CODE (SUBREG_REG (temp)) == REG)
    && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
  {
    rtx temp1 = simplify_shift_const
      (NULL_RTX, ASHIFTRT, mode,
       simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
           GET_MODE_BITSIZE (mode) - 1 - i),
       GET_MODE_BITSIZE (mode) - 1 - i);

    /* If all we did was surround TEMP with the two shifts, we
       haven't improved anything, so don't use it.  Otherwise,
       we are better off with TEMP1.  */
    if (GET_CODE (temp1) != ASHIFTRT
        || GET_CODE (XEXP (temp1, 0)) != ASHIFT
        || XEXP (XEXP (temp1, 0), 0) != temp)
      return temp1;
  }
      break;

    case TRUNCATE:
      /* We can't handle truncation to a partial integer mode here
   because we don't know the real bitsize of the partial
   integer mode.  */
      if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
  break;

      if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
    && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
            GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
  SUBST (XEXP (x, 0),
         force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
            GET_MODE_MASK (mode), NULL_RTX, 0));

      /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI.  */
      if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
     || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
    && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
  return XEXP (XEXP (x, 0), 0);

      /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
   (OP:SI foo:SI) if OP is NEG or ABS.  */
      if ((GET_CODE (XEXP (x, 0)) == ABS
     || GET_CODE (XEXP (x, 0)) == NEG)
    && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
        || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
    && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
  return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
           XEXP (XEXP (XEXP (x, 0), 0), 0), mode);

      /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
   (truncate:SI x).  */
      if (GET_CODE (XEXP (x, 0)) == SUBREG
    && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
    && subreg_lowpart_p (XEXP (x, 0)))
  return SUBREG_REG (XEXP (x, 0));

      /* If we know that the value is already truncated, we can
         replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
         is nonzero for the corresponding modes.  But don't do this
         for an (LSHIFTRT (MULT ...)) since this will cause problems
         with the umulXi3_highpart patterns.  */
      if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
         GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
    && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
       >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
    && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
    && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
  return gen_lowpart_for_combine (mode, XEXP (x, 0));

      /* A truncate of a comparison can be replaced with a subreg if
         STORE_FLAG_VALUE permits.  This is like the previous test,
         but it works even if the comparison is done in a mode larger
         than HOST_BITS_PER_WIDE_INT.  */
      if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
    && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
    && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
  return gen_lowpart_for_combine (mode, XEXP (x, 0));

      /* Similarly, a truncate of a register whose value is a
         comparison can be replaced with a subreg if STORE_FLAG_VALUE
         permits.  */
      if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
    && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
    && (temp = get_last_value (XEXP (x, 0)))
    && GET_RTX_CLASS (GET_CODE (temp)) == '<')
  return gen_lowpart_for_combine (mode, XEXP (x, 0));

      break;

    case FLOAT_TRUNCATE:
      /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF.  */
      if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
    && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
  return XEXP (XEXP (x, 0), 0);

      /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
   (OP:SF foo:SF) if OP is NEG or ABS.  */
      if ((GET_CODE (XEXP (x, 0)) == ABS
     || GET_CODE (XEXP (x, 0)) == NEG)
    && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
    && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
  return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
           XEXP (XEXP (XEXP (x, 0), 0), 0), mode);

      /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
   is (float_truncate:SF x).  */
      if (GET_CODE (XEXP (x, 0)) == SUBREG
    && subreg_lowpart_p (XEXP (x, 0))
    && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
  return SUBREG_REG (XEXP (x, 0));
      break;

#ifdef HAVE_cc0
    case COMPARE:
      /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
   using cc0, in which case we want to leave it as a COMPARE
   so we can distinguish it from a register-register-copy.  */
      if (XEXP (x, 1) == const0_rtx)
  return XEXP (x, 0);

      /* x - 0 is the same as x unless x's mode has signed zeros and
   allows rounding towards -infinity.  Under those conditions,
   0 - 0 is -0.  */
      if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
      && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
    && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
  return XEXP (x, 0);
      break;
#endif

    case CONST:
      /* (const (const X)) can become (const X).  Do it this way rather than
   returning the inner CONST since CONST can be shared with a
   REG_EQUAL note.  */
      if (GET_CODE (XEXP (x, 0)) == CONST)
  SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
      break;

#ifdef HAVE_lo_sum
    case LO_SUM:
      /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
   can add in an offset.  find_split_point will split this address up
   again if it doesn't match.  */
      if (GET_CODE (XEXP (x, 0)) == HIGH
    && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
  return XEXP (x, 1);
      break;
#endif

    case PLUS:
      /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
       */
      if (GET_CODE (XEXP (x, 0)) == MULT 
    && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
  {
    rtx in1, in2;
   
    in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
    in2 = XEXP (XEXP (x, 0), 1);
    return gen_binary (MINUS, mode, XEXP (x, 1),
           gen_binary (MULT, mode, in1, in2));
  }

      /* If we have (plus (plus (A const) B)), associate it so that CONST is
   outermost.  That's because that's the way indexed addresses are
   supposed to appear.  This code used to check many more cases, but
   they are now checked elsewhere.  */
      if (GET_CODE (XEXP (x, 0)) == PLUS
    && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
  return gen_binary (PLUS, mode,
         gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
               XEXP (x, 1)),
         XEXP (XEXP (x, 0), 1));

      /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
   when c is (const_int (pow2 + 1) / 2) is a sign extension of a
   bit-field and can be replaced by either a sign_extend or a
   sign_extract.  The `and' may be a zero_extend and the two
   <c>, -<c> constants may be reversed.  */
      if (GET_CODE (XEXP (x, 0)) == XOR
    && GET_CODE (XEXP (x, 1)) == CONST_INT
    && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
    && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
    && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
        || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
    && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
    && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
         && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
         && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
       == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
        || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
      && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
          == (unsigned int) i + 1))))
  return simplify_shift_const
    (NULL_RTX, ASHIFTRT, mode,
     simplify_shift_const (NULL_RTX, ASHIFT, mode,
         XEXP (XEXP (XEXP (x, 0), 0), 0),
         GET_MODE_BITSIZE (mode) - (i + 1)),
     GET_MODE_BITSIZE (mode) - (i + 1));

      /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
   C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
   is 1.  This produces better code than the alternative immediately
   below.  */
      if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
    && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
        || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
    && (reversed = reversed_comparison (XEXP (x, 0), mode,
                XEXP (XEXP (x, 0), 0),
                XEXP (XEXP (x, 0), 1))))
  return
    simplify_gen_unary (NEG, mode, reversed, mode);

      /* If only the low-order bit of X is possibly nonzero, (plus x -1)
   can become (ashiftrt (ashift (xor x 1) C) C) where C is
   the bitsize of the mode - 1.  This allows simplification of
   "a = (b & 8) == 0;"  */
      if (XEXP (x, 1) == constm1_rtx
    && GET_CODE (XEXP (x, 0)) != REG
    && ! (GET_CODE (XEXP (x,0)) == SUBREG
    && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
    && nonzero_bits (XEXP (x, 0), mode) == 1)
  return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
     simplify_shift_const (NULL_RTX, ASHIFT, mode,
         gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
         GET_MODE_BITSIZE (mode) - 1),
     GET_MODE_BITSIZE (mode) - 1);

      /* If we are adding two things that have no bits in common, convert
   the addition into an IOR.  This will often be further simplified,
   for example in cases like ((a & 1) + (a & 2)), which can
   become a & 3.  */

      if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
    && (nonzero_bits (XEXP (x, 0), mode)
        & nonzero_bits (XEXP (x, 1), mode)) == 0)
  {
    /* Try to simplify the expression further.  */
    rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
    temp = combine_simplify_rtx (tor, mode, last, in_dest);

    /* If we could, great.  If not, do not go ahead with the IOR
       replacement, since PLUS appears in many special purpose
       address arithmetic instructions.  */
    if (GET_CODE (temp) != CLOBBER && temp != tor)
      return temp;
  }
      break;

    case MINUS:
      /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
   by reversing the comparison code if valid.  */
      if (STORE_FLAG_VALUE == 1
    && XEXP (x, 0) == const1_rtx
    && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
    && (reversed = reversed_comparison (XEXP (x, 1), mode,
                XEXP (XEXP (x, 1), 0),
                XEXP (XEXP (x, 1), 1))))
  return reversed;

      /* (minus <foo> (and <foo> (const_int -pow2))) becomes
   (and <foo> (const_int pow2-1))  */
      if (GET_CODE (XEXP (x, 1)) == AND
    && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
    && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
    && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
  return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
               -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);

      /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
       */
      if (GET_CODE (XEXP (x, 1)) == MULT 
    && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
  {
    rtx in1, in2;
   
    in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
    in2 = XEXP (XEXP (x, 1), 1);
    return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
           XEXP (x, 0));
  }

       /* Canonicalize (minus (neg A) (mult B C)) to 
    (minus (mult (neg B) C) A). */
      if (GET_CODE (XEXP (x, 1)) == MULT 
    && GET_CODE (XEXP (x, 0)) == NEG)
  {
    rtx in1, in2;
   
    in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
    in2 = XEXP (XEXP (x, 1), 1);
    return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
           XEXP (XEXP (x, 0), 0));
  }

      /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
   integers.  */
      if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
  return gen_binary (MINUS, mode,
         gen_binary (MINUS, mode, XEXP (x, 0),
               XEXP (XEXP (x, 1), 0)),
         XEXP (XEXP (x, 1), 1));
      break;

    case MULT:
      /* If we have (mult (plus A B) C), apply the distributive law and then
   the inverse distributive law to see if things simplify.  This
   occurs mostly in addresses, often when unrolling loops.  */

      if (GET_CODE (XEXP (x, 0)) == PLUS)
  {
    x = apply_distributive_law
      (gen_binary (PLUS, mode,
       gen_binary (MULT, mode,
             XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
       gen_binary (MULT, mode,
             XEXP (XEXP (x, 0), 1),
             copy_rtx (XEXP (x, 1)))));

    if (GET_CODE (x) != MULT)
      return x;
  }
      /* Try simplify a*(b/c) as (a*b)/c.  */
      if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
    && GET_CODE (XEXP (x, 0)) == DIV)
  {
    rtx tem = simplify_binary_operation (MULT, mode,
                 XEXP (XEXP (x, 0), 0),
                 XEXP (x, 1));
    if (tem)
      return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
  }
      break;

    case UDIV:
      /* If this is a divide by a power of two, treat it as a shift if
   its first operand is a shift.  */
      if (GET_CODE (XEXP (x, 1)) == CONST_INT
    && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
    && (GET_CODE (XEXP (x, 0)) == ASHIFT
        || GET_CODE (XEXP (x, 0)) == LSHIFTRT
        || GET_CODE (XEXP (x, 0)) == ASHIFTRT
        || GET_CODE (XEXP (x, 0)) == ROTATE
        || GET_CODE (XEXP (x, 0)) == ROTATERT))
  return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
      break;

    case EQ:  case NE:
    case GT:  case GTU:  case GE:  case GEU:
    case LT:  case LTU:  case LE:  case LEU:
    case UNEQ:  case LTGT:
    case UNGT:  case UNGE:
    case UNLT:  case UNLE:
    case UNORDERED: case ORDERED:
      /* If the first operand is a condition code, we can't do anything
   with it.  */
      if (GET_CODE (XEXP (x, 0)) == COMPARE
    || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
#ifdef HAVE_cc0
        && XEXP (x, 0) != cc0_rtx
#endif
        ))
  {
    rtx op0 = XEXP (x, 0);
    rtx op1 = XEXP (x, 1);
    enum rtx_code new_code;

    if (GET_CODE (op0) == COMPARE)
      op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);

    /* Simplify our comparison, if possible.  */
    new_code = simplify_comparison (code, &op0, &op1);

    /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
       if only the low-order bit is possibly nonzero in X (such as when
       X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
       (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
       known to be either 0 or -1, NE becomes a NEG and EQ becomes
       (plus X 1).

       Remove any ZERO_EXTRACT we made when thinking this was a
       comparison.  It may now be simpler to use, e.g., an AND.  If a
       ZERO_EXTRACT is indeed appropriate, it will be placed back by
       the call to make_compound_operation in the SET case.  */

    if (STORE_FLAG_VALUE == 1
        && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
        && op1 == const0_rtx
        && mode == GET_MODE (op0)
        && nonzero_bits (op0, mode) == 1)
      return gen_lowpart_for_combine (mode,
              expand_compound_operation (op0));

    else if (STORE_FLAG_VALUE == 1
       && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
       && op1 == const0_rtx
       && mode == GET_MODE (op0)
       && (num_sign_bit_copies (op0, mode)
           == GET_MODE_BITSIZE (mode)))
      {
        op0 = expand_compound_operation (op0);
        return simplify_gen_unary (NEG, mode,
           gen_lowpart_for_combine (mode, op0),
           mode);
      }

    else if (STORE_FLAG_VALUE == 1
       && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
       && op1 == const0_rtx
       && mode == GET_MODE (op0)
       && nonzero_bits (op0, mode) == 1)
      {
        op0 = expand_compound_operation (op0);
        return gen_binary (XOR, mode,
         gen_lowpart_for_combine (mode, op0),
         const1_rtx);
      }

    else if (STORE_FLAG_VALUE == 1
       && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
       && op1 == const0_rtx
       && mode == GET_MODE (op0)
       && (num_sign_bit_copies (op0, mode)
           == GET_MODE_BITSIZE (mode)))
      {
        op0 = expand_compound_operation (op0);
        return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
      }

    /* If STORE_FLAG_VALUE is -1, we have cases similar to
       those above.  */
    if (STORE_FLAG_VALUE == -1
        && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
        && op1 == const0_rtx
        && (num_sign_bit_copies (op0, mode)
      == GET_MODE_BITSIZE (mode)))
      return gen_lowpart_for_combine (mode,
              expand_compound_operation (op0));

    else if (STORE_FLAG_VALUE == -1
       && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
       && op1 == const0_rtx
       && mode == GET_MODE (op0)
       && nonzero_bits (op0, mode) == 1)
      {
        op0 = expand_compound_operation (op0);
        return simplify_gen_unary (NEG, mode,
           gen_lowpart_for_combine (mode, op0),
           mode);
      }

    else if (STORE_FLAG_VALUE == -1
       && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
       && op1 == const0_rtx
       && mode == GET_MODE (op0)
       && (num_sign_bit_copies (op0, mode)
           == GET_MODE_BITSIZE (mode)))
      {
        op0 = expand_compound_operation (op0);
        return simplify_gen_unary (NOT, mode,
           gen_lowpart_for_combine (mode, op0),
           mode);
      }

    /* If X is 0/1, (eq X 0) is X-1.  */
    else if (STORE_FLAG_VALUE == -1
       && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
       && op1 == const0_rtx
       && mode == GET_MODE (op0)
       && nonzero_bits (op0, mode) == 1)
      {
        op0 = expand_compound_operation (op0);
        return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
      }

    /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
       one bit that might be nonzero, we can convert (ne x 0) to
       (ashift x c) where C puts the bit in the sign bit.  Remove any
       AND with STORE_FLAG_VALUE when we are done, since we are only
       going to test the sign bit.  */
    if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
        && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
        && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
      == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
        && op1 == const0_rtx
        && mode == GET_MODE (op0)
        && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
      {
        x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
          expand_compound_operation (op0),
          GET_MODE_BITSIZE (mode) - 1 - i);
        if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
    return XEXP (x, 0);
        else
    return x;
      }

    /* If the code changed, return a whole new comparison.  */
    if (new_code != code)
      return gen_rtx_fmt_ee (new_code, mode, op0, op1);

    /* Otherwise, keep this operation, but maybe change its operands.
       This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
    SUBST (XEXP (x, 0), op0);
    SUBST (XEXP (x, 1), op1);
  }
      break;

    case IF_THEN_ELSE:
      return simplify_if_then_else (x);

    case ZERO_EXTRACT:
    case SIGN_EXTRACT:
    case ZERO_EXTEND:
    case SIGN_EXTEND:
      /* If we are processing SET_DEST, we are done.  */
      if (in_dest)
  return x;

      return expand_compound_operation (x);

    case SET:
      return simplify_set (x);

    case AND:
    case IOR:
    case XOR:
      return simplify_logical (x, last);

    case ABS:
      /* (abs (neg <foo>)) -> (abs <foo>) */
      if (GET_CODE (XEXP (x, 0)) == NEG)
  SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));

      /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
         do nothing.  */
      if (GET_MODE (XEXP (x, 0)) == VOIDmode)
  break;

      /* If operand is something known to be positive, ignore the ABS.  */
      if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
    || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
         <= HOST_BITS_PER_WIDE_INT)
        && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
       & ((HOST_WIDE_INT) 1
          << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
      == 0)))
  return XEXP (x, 0);

      /* If operand is known to be only -1 or 0, convert ABS to NEG.  */
      if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
  return gen_rtx_NEG (mode, XEXP (x, 0));

      break;

    case FFS:
      /* (ffs (*_extend <X>)) = (ffs <X>) */
      if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
    || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
  SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
      break;

    case FLOAT:
      /* (float (sign_extend <X>)) = (float <X>).  */
      if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
  SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
      break;

    case ASHIFT:
    case LSHIFTRT:
    case ASHIFTRT:
    case ROTATE:
    case ROTATERT:
      /* If this is a shift by a constant amount, simplify it.  */
      if (GET_CODE (XEXP (x, 1)) == CONST_INT)
  return simplify_shift_const (x, code, mode, XEXP (x, 0),
             INTVAL (XEXP (x, 1)));

#ifdef SHIFT_COUNT_TRUNCATED
      else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
  SUBST (XEXP (x, 1),
         force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
            ((HOST_WIDE_INT) 1
             << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
            - 1,
            NULL_RTX, 0));
#endif

      break;

    case VEC_SELECT:
      {
  rtx op0 = XEXP (x, 0);
  rtx op1 = XEXP (x, 1);
  int len;

  if (GET_CODE (op1) != PARALLEL)
    abort ();
  len = XVECLEN (op1, 0);
  if (len == 1
      && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
      && GET_CODE (op0) == VEC_CONCAT)
    {
      int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));

      /* Try to find the element in the VEC_CONCAT.  */
      for (;;)
        {
    if (GET_MODE (op0) == GET_MODE (x))
      return op0;
    if (GET_CODE (op0) == VEC_CONCAT)
      {
        HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
        if (op0_size < offset)
          op0 = XEXP (op0, 0);
        else
          {
      offset -= op0_size;
      op0 = XEXP (op0, 1);
          }
      }
    else
      break;
        }
    }
      }

      break;

    default:
      break;
    }

  return x;
}

/* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */

static rtx
simplify_if_then_else (x)
     rtx x;
{
  enum machine_mode mode = GET_MODE (x);
  rtx cond = XEXP (x, 0);
  rtx true_rtx = XEXP (x, 1);
  rtx false_rtx = XEXP (x, 2);
  enum rtx_code true_code = GET_CODE (cond);
  int comparison_p = GET_RTX_CLASS (true_code) == '<';
  rtx temp;
  int i;
  enum rtx_code false_code;
  rtx reversed;

  /* Simplify storing of the truth value.  */
  if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
    return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));

  /* Also when the truth value has to be reversed.  */
  if (comparison_p
      && true_rtx == const0_rtx && false_rtx == const_true_rtx
      && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
            XEXP (cond, 1))))
    return reversed;

  /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
     in it is being compared against certain values.  Get the true and false
     comparisons and see if that says anything about the value of each arm.  */

  if (comparison_p
      && ((false_code = combine_reversed_comparison_code (cond))
    != UNKNOWN)
      && GET_CODE (XEXP (cond, 0)) == REG)
    {
      HOST_WIDE_INT nzb;
      rtx from = XEXP (cond, 0);
      rtx true_val = XEXP (cond, 1);
      rtx false_val = true_val;
      int swapped = 0;

      /* If FALSE_CODE is EQ, swap the codes and arms.  */

      if (false_code == EQ)
  {
    swapped = 1, true_code = EQ, false_code = NE;
    temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
  }

      /* If we are comparing against zero and the expression being tested has
   only a single bit that might be nonzero, that is its value when it is
   not equal to zero.  Similarly if it is known to be -1 or 0.  */

      if (true_code == EQ && true_val == const0_rtx
    && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
  false_code = EQ, false_val = GEN_INT (nzb);
      else if (true_code == EQ && true_val == const0_rtx
         && (num_sign_bit_copies (from, GET_MODE (from))
       == GET_MODE_BITSIZE (GET_MODE (from))))
  false_code = EQ, false_val = constm1_rtx;

      /* Now simplify an arm if we know the value of the register in the
   branch and it is used in the arm.  Be careful due to the potential
   of locally-shared RTL.  */

      if (reg_mentioned_p (from, true_rtx))
  true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
              from, true_val),
          pc_rtx, pc_rtx, 0, 0);
      if (reg_mentioned_p (from, false_rtx))
  false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
           from, false_val),
           pc_rtx, pc_rtx, 0, 0);

      SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
      SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);

      true_rtx = XEXP (x, 1);
      false_rtx = XEXP (x, 2);
      true_code = GET_CODE (cond);
    }

  /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
     reversed, do so to avoid needing two sets of patterns for
     subtract-and-branch insns.  Similarly if we have a constant in the true
     arm, the false arm is the same as the first operand of the comparison, or
     the false arm is more complicated than the true arm.  */

  if (comparison_p
      && combine_reversed_comparison_code (cond) != UNKNOWN
      && (true_rtx == pc_rtx
    || (CONSTANT_P (true_rtx)
        && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
    || true_rtx == const0_rtx
    || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
        && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
    || (GET_CODE (true_rtx) == SUBREG
        && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
        && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
    || reg_mentioned_p (true_rtx, false_rtx)
    || rtx_equal_p (false_rtx, XEXP (cond, 0))))
    {
      true_code = reversed_comparison_code (cond, NULL);
      SUBST (XEXP (x, 0),
       reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
          XEXP (cond, 1)));

      SUBST (XEXP (x, 1), false_rtx);
      SUBST (XEXP (x, 2), true_rtx);

      temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
      cond = XEXP (x, 0);

      /* It is possible that the conditional has been simplified out.  */
      true_code = GET_CODE (cond);
      comparison_p = GET_RTX_CLASS (true_code) == '<';
    }

  /* If the two arms are identical, we don't need the comparison.  */

  if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
    return true_rtx;

  /* Convert a == b ? b : a to "a".  */
  if (true_code == EQ && ! side_effects_p (cond)
      && !HONOR_NANS (mode)
      && rtx_equal_p (XEXP (cond, 0), false_rtx)
      && rtx_equal_p (XEXP (cond, 1), true_rtx))
    return false_rtx;
  else if (true_code == NE && ! side_effects_p (cond)
     && !HONOR_NANS (mode)
     && rtx_equal_p (XEXP (cond, 0), true_rtx)
     && rtx_equal_p (XEXP (cond, 1), false_rtx))
    return true_rtx;

  /* Look for cases where we have (abs x) or (neg (abs X)).  */

  if (GET_MODE_CLASS (mode) == MODE_INT
      && GET_CODE (false_rtx) == NEG
      && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
      && comparison_p
      && rtx_equal_p (true_rtx, XEXP (cond, 0))
      && ! side_effects_p (true_rtx))
    switch (true_code)
      {
      case GT:
      case GE:
  return simplify_gen_unary (ABS, mode, true_rtx, mode);
      case LT:
      case LE:
  return
    simplify_gen_unary (NEG, mode,
            simplify_gen_unary (ABS, mode, true_rtx, mode),
            mode);
      default:
  break;
      }

  /* Look for MIN or MAX.  */

  if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
      && comparison_p
      && rtx_equal_p (XEXP (cond, 0), true_rtx)
      && rtx_equal_p (XEXP (cond, 1), false_rtx)
      && ! side_effects_p (cond))
    switch (true_code)
      {
      case GE:
      case GT:
  return gen_binary (SMAX, mode, true_rtx, false_rtx);
      case LE:
      case LT:
  return gen_binary (SMIN, mode, true_rtx, false_rtx);
      case GEU:
      case GTU:
  return gen_binary (UMAX, mode, true_rtx, false_rtx);
      case LEU:
      case LTU:
  return gen_binary (UMIN, mode, true_rtx, false_rtx);
      default:
  break;
      }

  /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
     second operand is zero, this can be done as (OP Z (mult COND C2)) where
     C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
     SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
     We can do this kind of thing in some cases when STORE_FLAG_VALUE is
     neither 1 or -1, but it isn't worth checking for.  */

  if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
      && comparison_p
      && GET_MODE_CLASS (mode) == MODE_INT
      && ! side_effects_p (x))
    {
      rtx t = make_compound_operation (true_rtx, SET);
      rtx f = make_compound_operation (false_rtx, SET);
      rtx cond_op0 = XEXP (cond, 0);
      rtx cond_op1 = XEXP (cond, 1);
      enum rtx_code op = NIL, extend_op = NIL;
      enum machine_mode m = mode;
      rtx z = 0, c1 = NULL_RTX;

      if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
     || GET_CODE (t) == IOR || GET_CODE (t) == XOR
     || GET_CODE (t) == ASHIFT
     || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
    && rtx_equal_p (XEXP (t, 0), f))
  c1 = XEXP (t, 1), op = GET_CODE (t), z = f;

      /* If an identity-zero op is commutative, check whether there
   would be a match if we swapped the operands.  */
      else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
    || GET_CODE (t) == XOR)
         && rtx_equal_p (XEXP (t, 1), f))
  c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
      else if (GET_CODE (t) == SIGN_EXTEND
         && (GET_CODE (XEXP (t, 0)) == PLUS
       || GET_CODE (XEXP (t, 0)) == MINUS
       || GET_CODE (XEXP (t, 0)) == IOR
       || GET_CODE (XEXP (t, 0)) == XOR
       || GET_CODE (XEXP (t, 0)) == ASHIFT
       || GET_CODE (XEXP (t, 0)) == LSHIFTRT
       || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
         && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
         && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
         && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
         && (num_sign_bit_copies (f, GET_MODE (f))
       > (unsigned int)
         (GET_MODE_BITSIZE (mode)
          - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
  {
    c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
    extend_op = SIGN_EXTEND;
    m = GET_MODE (XEXP (t, 0));
  }
      else if (GET_CODE (t) == SIGN_EXTEND
         && (GET_CODE (XEXP (t, 0)) == PLUS
       || GET_CODE (XEXP (t, 0)) == IOR
       || GET_CODE (XEXP (t, 0)) == XOR)
         && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
         && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
         && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
         && (num_sign_bit_copies (f, GET_MODE (f))
       > (unsigned int)
         (GET_MODE_BITSIZE (mode)
          - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
  {
    c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
    extend_op = SIGN_EXTEND;
    m = GET_MODE (XEXP (t, 0));
  }
      else if (GET_CODE (t) == ZERO_EXTEND
         && (GET_CODE (XEXP (t, 0)) == PLUS
       || GET_CODE (XEXP (t, 0)) == MINUS
       || GET_CODE (XEXP (t, 0)) == IOR
       || GET_CODE (XEXP (t, 0)) == XOR
       || GET_CODE (XEXP (t, 0)) == ASHIFT
       || GET_CODE (XEXP (t, 0)) == LSHIFTRT
       || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
         && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
         && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
         && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
         && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
         && ((nonzero_bits (f, GET_MODE (f))
        & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
       == 0))
  {
    c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
    extend_op = ZERO_EXTEND;
    m = GET_MODE (XEXP (t, 0));
  }
      else if (GET_CODE (t) == ZERO_EXTEND
         && (GET_CODE (XEXP (t, 0)) == PLUS
       || GET_CODE (XEXP (t, 0)) == IOR
       || GET_CODE (XEXP (t, 0)) == XOR)
         && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
         && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
         && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
         && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
         && ((nonzero_bits (f, GET_MODE (f))
        & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
       == 0))
  {
    c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
    extend_op = ZERO_EXTEND;
    m = GET_MODE (XEXP (t, 0));
  }

      if (z)
  {
    temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
      pc_rtx, pc_rtx, 0, 0);
    temp = gen_binary (MULT, m, temp,
           gen_binary (MULT, m, c1, const_true_rtx));
    temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
    temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);

    if (extend_op != NIL)
      temp = simplify_gen_unary (extend_op, mode, temp, m);

    return temp;
  }
    }

  /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
     1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
     negation of a single bit, we can convert this operation to a shift.  We
     can actually do this more generally, but it doesn't seem worth it.  */

  if (true_code == NE && XEXP (cond, 1) == const0_rtx
      && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
      && ((1 == nonzero_bits (XEXP (cond, 0), mode)
     && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
    || ((num_sign_bit_copies (XEXP (cond, 0), mode)
         == GET_MODE_BITSIZE (mode))
        && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
    return
      simplify_shift_const (NULL_RTX, ASHIFT, mode,
          gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);

  return x;
}

/* Simplify X, a SET expression.  Return the new expression.  */

static rtx
simplify_set (x)
     rtx x;
{
  rtx src = SET_SRC (x);
  rtx dest = SET_DEST (x);
  enum machine_mode mode
    = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
  rtx other_insn;
  rtx *cc_use;

  /* (set (pc) (return)) gets written as (return).  */
  if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
    return src;

  /* Now that we know for sure which bits of SRC we are using, see if we can
     simplify the expression for the object knowing that we only need the
     low-order bits.  */

  if (GET_MODE_CLASS (mode) == MODE_INT
      && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
    {
      src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
      SUBST (SET_SRC (x), src);
    }

  /* If we are setting CC0 or if the source is a COMPARE, look for the use of
     the comparison result and try to simplify it unless we already have used
     undobuf.other_insn.  */
  if ((GET_MODE_CLASS (mode) == MODE_CC
       || GET_CODE (src) == COMPARE
       || CC0_P (dest))
      && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
      && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
      && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
      && rtx_equal_p (XEXP (*cc_use, 0), dest))
    {
      enum rtx_code old_code = GET_CODE (*cc_use);
      enum rtx_code new_code;
      rtx op0, op1, tmp;
      int other_changed = 0;
      enum machine_mode compare_mode = GET_MODE (dest);
      enum machine_mode tmp_mode;

      if (GET_CODE (src) == COMPARE)
  op0 = XEXP (src, 0), op1 = XEXP (src, 1);
      else
  op0 = src, op1 = const0_rtx;

      /* Check whether the comparison is known at compile time.  */
      if (GET_MODE (op0) != VOIDmode)
  tmp_mode = GET_MODE (op0);
      else if (GET_MODE (op1) != VOIDmode)
  tmp_mode = GET_MODE (op1);
      else
  tmp_mode = compare_mode;
      tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
      if (tmp != NULL_RTX)
  {
    rtx pat = PATTERN (other_insn);
    undobuf.other_insn = other_insn;
    SUBST (*cc_use, tmp);

    /* Attempt to simplify CC user.  */
    if (GET_CODE (pat) == SET)
      {
        rtx new = simplify_rtx (SET_SRC (pat));
        if (new != NULL_RTX)
    SUBST (SET_SRC (pat), new);
      }

    /* Convert X into a no-op move.  */
    SUBST (SET_DEST (x), pc_rtx);
    SUBST (SET_SRC (x), pc_rtx);
    return x;
  }

      /* Simplify our comparison, if possible.  */
      new_code = simplify_comparison (old_code, &op0, &op1);

#ifdef EXTRA_CC_MODES
      /* If this machine has CC modes other than CCmode, check to see if we
   need to use a different CC mode here.  */
      compare_mode = SELECT_CC_MODE (new_code, op0, op1);
#endif /* EXTRA_CC_MODES */

#if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
      /* If the mode changed, we have to change SET_DEST, the mode in the
   compare, and the mode in the place SET_DEST is used.  If SET_DEST is
   a hard register, just build new versions with the proper mode.  If it
   is a pseudo, we lose unless it is only time we set the pseudo, in
   which case we can safely change its mode.  */
      if (compare_mode != GET_MODE (dest))
  {
    unsigned int regno = REGNO (dest);
    rtx new_dest = gen_rtx_REG (compare_mode, regno);

    if (regno < FIRST_PSEUDO_REGISTER
        || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
      {
        if (regno >= FIRST_PSEUDO_REGISTER)
    SUBST (regno_reg_rtx[regno], new_dest);

        SUBST (SET_DEST (x), new_dest);
        SUBST (XEXP (*cc_use, 0), new_dest);
        other_changed = 1;

        dest = new_dest;
      }
  }
#endif

      /* If the code changed, we have to build a new comparison in
   undobuf.other_insn.  */
      if (new_code != old_code)
  {
    unsigned HOST_WIDE_INT mask;

    SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
            dest, const0_rtx));

    /* If the only change we made was to change an EQ into an NE or
       vice versa, OP0 has only one bit that might be nonzero, and OP1
       is zero, check if changing the user of the condition code will
       produce a valid insn.  If it won't, we can keep the original code
       in that insn by surrounding our operation with an XOR.  */

    if (((old_code == NE && new_code == EQ)
         || (old_code == EQ && new_code == NE))
        && ! other_changed && op1 == const0_rtx
        && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
        && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
      {
        rtx pat = PATTERN (other_insn), note = 0;

        if ((recog_for_combine (&pat, other_insn, &note) < 0
       && ! check_asm_operands (pat)))
    {
      PUT_CODE (*cc_use, old_code);
      other_insn = 0;

      op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
    }
      }

    other_changed = 1;
  }

      if (other_changed)
  undobuf.other_insn = other_insn;

#ifdef HAVE_cc0
      /* If we are now comparing against zero, change our source if
   needed.  If we do not use cc0, we always have a COMPARE.  */
      if (op1 == const0_rtx && dest == cc0_rtx)
  {
    SUBST (SET_SRC (x), op0);
    src = op0;
  }
      else
#endif

      /* Otherwise, if we didn't previously have a COMPARE in the
   correct mode, we need one.  */
      if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
  {
    SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
    src = SET_SRC (x);
  }
      else
  {
    /* Otherwise, update the COMPARE if needed.  */
    SUBST (XEXP (src, 0), op0);
    SUBST (XEXP (src, 1), op1);
  }
    }
  else
    {
      /* Get SET_SRC in a form where we have placed back any
   compound expressions.  Then do the checks below.  */
      src = make_compound_operation (src, SET);
      SUBST (SET_SRC (x), src);
    }

  /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
     and X being a REG or (subreg (reg)), we may be able to convert this to
     (set (subreg:m2 x) (op)).

     We can always do this if M1 is narrower than M2 because that means that
     we only care about the low bits of the result.

     However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
     perform a narrower operation than requested since the high-order bits will
     be undefined.  On machine where it is defined, this transformation is safe
     as long as M1 and M2 have the same number of words.  */

  if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
      && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
      && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
     / UNITS_PER_WORD)
    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
#ifndef WORD_REGISTER_OPERATIONS
      && (GET_MODE_SIZE (GET_MODE (src))
    < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
#endif
#ifdef CANNOT_CHANGE_MODE_CLASS
      && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
      && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
           GET_MODE (SUBREG_REG (src)), 
           GET_MODE (src)))
#endif
      && (GET_CODE (dest) == REG
    || (GET_CODE (dest) == SUBREG
        && GET_CODE (SUBREG_REG (dest)) == REG)))
    {
      SUBST (SET_DEST (x),
       gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
              dest));
      SUBST (SET_SRC (x), SUBREG_REG (src));

      src = SET_SRC (x), dest = SET_DEST (x);
    }

#ifdef HAVE_cc0
  /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
     in SRC.  */
  if (dest == cc0_rtx
      && GET_CODE (src) == SUBREG
      && subreg_lowpart_p (src)
      && (GET_MODE_BITSIZE (GET_MODE (src))
    < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
    {
      rtx inner = SUBREG_REG (src);
      enum machine_mode inner_mode = GET_MODE (inner);

      /* Here we make sure that we don't have a sign bit on.  */
      if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
    && (nonzero_bits (inner, inner_mode)
        < ((unsigned HOST_WIDE_INT) 1
     << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
  {
    SUBST (SET_SRC (x), inner);
    src = SET_SRC (x);
  }
    }
#endif

#ifdef LOAD_EXTEND_OP
  /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
     would require a paradoxical subreg.  Replace the subreg with a
     zero_extend to avoid the reload that would otherwise be required.  */

  if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
      && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
      && SUBREG_BYTE (src) == 0
      && (GET_MODE_SIZE (GET_MODE (src))
    > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
      && GET_CODE (SUBREG_REG (src)) == MEM)
    {
      SUBST (SET_SRC (x),
       gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
          GET_MODE (src), SUBREG_REG (src)));

      src = SET_SRC (x);
    }
#endif

  /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
     are comparing an item known to be 0 or -1 against 0, use a logical
     operation instead. Check for one of the arms being an IOR of the other
     arm with some value.  We compute three terms to be IOR'ed together.  In
     practice, at most two will be nonzero.  Then we do the IOR's.  */

  if (GET_CODE (dest) != PC
      && GET_CODE (src) == IF_THEN_ELSE
      && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
      && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
      && XEXP (XEXP (src, 0), 1) == const0_rtx
      && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
#ifdef HAVE_conditional_move
      && ! can_conditionally_move_p (GET_MODE (src))
#endif
      && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
             GET_MODE (XEXP (XEXP (src, 0), 0)))
    == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
      && ! side_effects_p (src))
    {
      rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
          ? XEXP (src, 1) : XEXP (src, 2));
      rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
       ? XEXP (src, 2) : XEXP (src, 1));
      rtx term1 = const0_rtx, term2, term3;

      if (GET_CODE (true_rtx) == IOR
    && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
  term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
      else if (GET_CODE (true_rtx) == IOR
         && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
  term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
      else if (GET_CODE (false_rtx) == IOR
         && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
  term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
      else if (GET_CODE (false_rtx) == IOR
         && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
  term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;

      term2 = gen_binary (AND, GET_MODE (src),
        XEXP (XEXP (src, 0), 0), true_rtx);
      term3 = gen_binary (AND, GET_MODE (src),
        simplify_gen_unary (NOT, GET_MODE (src),
                XEXP (XEXP (src, 0), 0),
                GET_MODE (src)),
        false_rtx);

      SUBST (SET_SRC (x),
       gen_binary (IOR, GET_MODE (src),
       gen_binary (IOR, GET_MODE (src), term1, term2),
       term3));

      src = SET_SRC (x);
    }

  /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
     whole thing fail.  */
  if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
    return src;
  else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
    return dest;
  else
    /* Convert this into a field assignment operation, if possible.  */
    return make_field_assignment (x);
}

/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
   result.  LAST is nonzero if this is the last retry.  */

static rtx
simplify_logical (x, last)
     rtx x;
     int last;
{
  enum machine_mode mode = GET_MODE (x);
  rtx op0 = XEXP (x, 0);
  rtx op1 = XEXP (x, 1);
  rtx reversed;

  switch (GET_CODE (x))
    {
    case AND:
      /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
   insn (and may simplify more).  */
      if (GET_CODE (op0) == XOR
    && rtx_equal_p (XEXP (op0, 0), op1)
    && ! side_effects_p (op1))
  x = gen_binary (AND, mode,
      simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
      op1);

      if (GET_CODE (op0) == XOR
    && rtx_equal_p (XEXP (op0, 1), op1)
    && ! side_effects_p (op1))
  x = gen_binary (AND, mode,
      simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
      op1);

      /* Similarly for (~(A ^ B)) & A.  */
      if (GET_CODE (op0) == NOT
    && GET_CODE (XEXP (op0, 0)) == XOR
    && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
    && ! side_effects_p (op1))
  x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);

      if (GET_CODE (op0) == NOT
    && GET_CODE (XEXP (op0, 0)) == XOR
    && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
    && ! side_effects_p (op1))
  x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);

      /* We can call simplify_and_const_int only if we don't lose
   any (sign) bits when converting INTVAL (op1) to
   "unsigned HOST_WIDE_INT".  */
      if (GET_CODE (op1) == CONST_INT
    && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
        || INTVAL (op1) > 0))
  {
    x = simplify_and_const_int (x, mode, op0, INTVAL (op1));

    /* If we have (ior (and (X C1) C2)) and the next restart would be
       the last, simplify this by making C1 as small as possible
       and then exit.  */
    if (last
        && GET_CODE (x) == IOR && GET_CODE (op0) == AND
        && GET_CODE (XEXP (op0, 1)) == CONST_INT
        && GET_CODE (op1) == CONST_INT)
      return gen_binary (IOR, mode,
             gen_binary (AND, mode, XEXP (op0, 0),
             GEN_INT (INTVAL (XEXP (op0, 1))
                & ~INTVAL (op1))), op1);

    if (GET_CODE (x) != AND)
      return x;

    if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
        || GET_RTX_CLASS (GET_CODE (x)) == '2')
      op0 = XEXP (x, 0), op1 = XEXP (x, 1);
  }

      /* Convert (A | B) & A to A.  */
      if (GET_CODE (op0) == IOR
    && (rtx_equal_p (XEXP (op0, 0), op1)
        || rtx_equal_p (XEXP (op0, 1), op1))
    && ! side_effects_p (XEXP (op0, 0))
    && ! side_effects_p (XEXP (op0, 1)))
  return op1;

      /* In the following group of tests (and those in case IOR below),
   we start with some combination of logical operations and apply
   the distributive law followed by the inverse distributive law.
   Most of the time, this results in no change.  However, if some of
   the operands are the same or inverses of each other, simplifications
   will result.

   For example, (and (ior A B) (not B)) can occur as the result of
   expanding a bit field assignment.  When we apply the distributive
   law to this, we get (ior (and (A (not B))) (and (B (not B)))),
   which then simplifies to (and (A (not B))).

   If we have (and (ior A B) C), apply the distributive law and then
   the inverse distributive law to see if things simplify.  */

      if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
  {
    x = apply_distributive_law
      (gen_binary (GET_CODE (op0), mode,
       gen_binary (AND, mode, XEXP (op0, 0), op1),
       gen_binary (AND, mode, XEXP (op0, 1),
             copy_rtx (op1))));
    if (GET_CODE (x) != AND)
      return x;
  }

      if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
  return apply_distributive_law
    (gen_binary (GET_CODE (op1), mode,
           gen_binary (AND, mode, XEXP (op1, 0), op0),
           gen_binary (AND, mode, XEXP (op1, 1),
           copy_rtx (op0))));

      /* Similarly, taking advantage of the fact that
   (and (not A) (xor B C)) == (xor (ior A B) (ior A C))  */

      if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
  return apply_distributive_law
    (gen_binary (XOR, mode,
           gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
           gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
           XEXP (op1, 1))));

      else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
  return apply_distributive_law
    (gen_binary (XOR, mode,
           gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
           gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
      break;

    case IOR:
      /* (ior A C) is C if all bits of A that might be nonzero are on in C.  */
      if (GET_CODE (op1) == CONST_INT
    && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
    && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
  return op1;

      /* Convert (A & B) | A to A.  */
      if (GET_CODE (op0) == AND
    && (rtx_equal_p (XEXP (op0, 0), op1)
        || rtx_equal_p (XEXP (op0, 1), op1))
    && ! side_effects_p (XEXP (op0, 0))
    && ! side_effects_p (XEXP (op0, 1)))
  return op1;

      /* If we have (ior (and A B) C), apply the distributive law and then
   the inverse distributive law to see if things simplify.  */

      if (GET_CODE (op0) == AND)
  {
    x = apply_distributive_law
      (gen_binary (AND, mode,
       gen_binary (IOR, mode, XEXP (op0, 0), op1),
       gen_binary (IOR, mode, XEXP (op0, 1),
             copy_rtx (op1))));

    if (GET_CODE (x) != IOR)
      return x;
  }

      if (GET_CODE (op1) == AND)
  {
    x = apply_distributive_law
      (gen_binary (AND, mode,
       gen_binary (IOR, mode, XEXP (op1, 0), op0),
       gen_binary (IOR, mode, XEXP (op1, 1),
             copy_rtx (op0))));

    if (GET_CODE (x) != IOR)
      return x;
  }

      /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
   mode size to (rotate A CX).  */

      if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
     || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
    && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
    && GET_CODE (XEXP (op0, 1)) == CONST_INT
    && GET_CODE (XEXP (op1, 1)) == CONST_INT
    && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
        == GET_MODE_BITSIZE (mode)))
  return gen_rtx_ROTATE (mode, XEXP (op0, 0),
             (GET_CODE (op0) == ASHIFT
        ? XEXP (op0, 1) : XEXP (op1, 1)));

      /* If OP0 is (ashiftrt (plus ...) C), it might actually be
   a (sign_extend (plus ...)).  If so, OP1 is a CONST_INT, and the PLUS
   does not affect any of the bits in OP1, it can really be done
   as a PLUS and we can associate.  We do this by seeing if OP1
   can be safely shifted left C bits.  */
      if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
    && GET_CODE (XEXP (op0, 0)) == PLUS
    && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
    && GET_CODE (XEXP (op0, 1)) == CONST_INT
    && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
  {
    int count = INTVAL (XEXP (op0, 1));
    HOST_WIDE_INT mask = INTVAL (op1) << count;

    if (mask >> count == INTVAL (op1)
        && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
      {
        SUBST (XEXP (XEXP (op0, 0), 1),
         GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
        return op0;
      }
  }
      break;

    case XOR:
      /* If we are XORing two things that have no bits in common,
   convert them into an IOR.  This helps to detect rotation encoded
   using those methods and possibly other simplifications.  */

      if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
    && (nonzero_bits (op0, mode)
        & nonzero_bits (op1, mode)) == 0)
  return (gen_binary (IOR, mode, op0, op1));

      /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
   Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
   (NOT y).  */
      {
  int num_negated = 0;

  if (GET_CODE (op0) == NOT)
    num_negated++, op0 = XEXP (op0, 0);
  if (GET_CODE (op1) == NOT)
    num_negated++, op1 = XEXP (op1, 0);

  if (num_negated == 2)
    {
      SUBST (XEXP (x, 0), op0);
      SUBST (XEXP (x, 1), op1);
    }
  else if (num_negated == 1)
    return
      simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
        mode);
      }

      /* Convert (xor (and A B) B) to (and (not A) B).  The latter may
   correspond to a machine insn or result in further simplifications
   if B is a constant.  */

      if (GET_CODE (op0) == AND
    && rtx_equal_p (XEXP (op0, 1), op1)
    && ! side_effects_p (op1))
  return gen_binary (AND, mode,
         simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
         op1);

      else if (GET_CODE (op0) == AND
         && rtx_equal_p (XEXP (op0, 0), op1)
         && ! side_effects_p (op1))
  return gen_binary (AND, mode,
         simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
         op1);

      /* (xor (comparison foo bar) (const_int 1)) can become the reversed
   comparison if STORE_FLAG_VALUE is 1.  */
      if (STORE_FLAG_VALUE == 1
    && op1 == const1_rtx
    && GET_RTX_CLASS (GET_CODE (op0)) == '<'
    && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
                XEXP (op0, 1))))
  return reversed;

      /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
   is (lt foo (const_int 0)), so we can perform the above
   simplification if STORE_FLAG_VALUE is 1.  */

      if (STORE_FLAG_VALUE == 1
    && op1 == const1_rtx
    && GET_CODE (op0) == LSHIFTRT
    && GET_CODE (XEXP (op0, 1)) == CONST_INT
    && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
  return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);

      /* (xor (comparison foo bar) (const_int sign-bit))
   when STORE_FLAG_VALUE is the sign bit.  */
      if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
    && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
        == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
    && op1 == const_true_rtx
    && GET_RTX_CLASS (GET_CODE (op0)) == '<'
    && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
                XEXP (op0, 1))))
  return reversed;

      break;

    default:
      abort ();
    }

  return x;
}

/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
   operations" because they can be replaced with two more basic operations.
   ZERO_EXTEND is also considered "compound" because it can be replaced with
   an AND operation, which is simpler, though only one operation.

   The function expand_compound_operation is called with an rtx expression
   and will convert it to the appropriate shifts and AND operations,
   simplifying at each stage.

   The function make_compound_operation is called to convert an expression
   consisting of shifts and ANDs into the equivalent compound expression.
   It is the inverse of this function, loosely speaking.  */

static rtx
expand_compound_operation (x)
     rtx x;
{
  unsigned HOST_WIDE_INT pos = 0, len;
  int unsignedp = 0;
  unsigned int modewidth;
  rtx tem;

  switch (GET_CODE (x))
    {
    case ZERO_EXTEND:
      unsignedp = 1;
    case SIGN_EXTEND:
      /* We can't necessarily use a const_int for a multiword mode;
   it depends on implicitly extending the value.
   Since we don't know the right way to extend it,
   we can't tell whether the implicit way is right.

   Even for a mode that is no wider than a const_int,
   we can't win, because we need to sign extend one of its bits through
   the rest of it, and we don't know which bit.  */
      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
  return x;

      /* Return if (subreg:MODE FROM 0) is not a safe replacement for
   (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
   because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
   reloaded. If not for that, MEM's would very rarely be safe.

   Reject MODEs bigger than a word, because we might not be able
   to reference a two-register group starting with an arbitrary register
   (and currently gen_lowpart might crash for a SUBREG).  */

      if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
  return x;

      /* Reject MODEs that aren't scalar integers because turning vector
   or complex modes into shifts causes problems.  */

      if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
  return x;

      len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
      /* If the inner object has VOIDmode (the only way this can happen
   is if it is an ASM_OPERANDS), we can't do anything since we don't
   know how much masking to do.  */
      if (len == 0)
  return x;

      break;

    case ZERO_EXTRACT:
      unsignedp = 1;
    case SIGN_EXTRACT:
      /* If the operand is a CLOBBER, just return it.  */
      if (GET_CODE (XEXP (x, 0)) == CLOBBER)
  return XEXP (x, 0);

      if (GET_CODE (XEXP (x, 1)) != CONST_INT
    || GET_CODE (XEXP (x, 2)) != CONST_INT
    || GET_MODE (XEXP (x, 0)) == VOIDmode)
  return x;

      /* Reject MODEs that aren't scalar integers because turning vector
   or complex modes into shifts causes problems.  */

      if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
  return x;

      len = INTVAL (XEXP (x, 1));
      pos = INTVAL (XEXP (x, 2));

      /* If this goes outside the object being extracted, replace the object
   with a (use (mem ...)) construct that only combine understands
   and is used only for this purpose.  */
      if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
  SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));

      if (BITS_BIG_ENDIAN)
  pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;

      break;

    default:
      return x;
    }
  /* Convert sign extension to zero extension, if we know that the high
     bit is not set, as this is easier to optimize.  It will be converted
     back to cheaper alternative in make_extraction.  */
  if (GET_CODE (x) == SIGN_EXTEND
      && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
    && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
    & ~(((unsigned HOST_WIDE_INT)
          GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
         >> 1))
         == 0)))
    {
      rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
      return expand_compound_operation (temp);
    }

  /* We can optimize some special cases of ZERO_EXTEND.  */
  if (GET_CODE (x) == ZERO_EXTEND)
    {
      /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
         know that the last value didn't have any inappropriate bits
         set.  */
      if (GET_CODE (XEXP (x, 0)) == TRUNCATE
    && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
    && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
    && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
        & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
  return XEXP (XEXP (x, 0), 0);

      /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
      if (GET_CODE (XEXP (x, 0)) == SUBREG
    && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
    && subreg_lowpart_p (XEXP (x, 0))
    && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
    && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
        & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
  return SUBREG_REG (XEXP (x, 0));

      /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
         is a comparison and STORE_FLAG_VALUE permits.  This is like
         the first case, but it works even when GET_MODE (x) is larger
         than HOST_WIDE_INT.  */
      if (GET_CODE (XEXP (x, 0)) == TRUNCATE
    && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
    && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
    && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
        <= HOST_BITS_PER_WIDE_INT)
    && ((HOST_WIDE_INT) STORE_FLAG_VALUE
        & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
  return XEXP (XEXP (x, 0), 0);

      /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
      if (GET_CODE (XEXP (x, 0)) == SUBREG
    && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
    && subreg_lowpart_p (XEXP (x, 0))
    && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
    && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
        <= HOST_BITS_PER_WIDE_INT)
    && ((HOST_WIDE_INT) STORE_FLAG_VALUE
        & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
  return SUBREG_REG (XEXP (x, 0));

    }

  /* If we reach here, we want to return a pair of shifts.  The inner
     shift is a left shift of BITSIZE - POS - LEN bits.  The outer
     shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
     logical depending on the value of UNSIGNEDP.

     If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
     converted into an AND of a shift.

     We must check for the case where the left shift would have a negative
     count.  This can happen in a case like (x >> 31) & 255 on machines
     that can't shift by a constant.  On those machines, we would first
     combine the shift with the AND to produce a variable-position
     extraction.  Then the constant of 31 would be substituted in to produce
     a such a position.  */

  modewidth = GET_MODE_BITSIZE (GET_MODE (x));
  if (modewidth + len >= pos)
    tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
        GET_MODE (x),
        simplify_shift_const (NULL_RTX, ASHIFT,
                  GET_MODE (x),
                  XEXP (x, 0),
                  modewidth - pos - len),
        modewidth - len);

  else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
    tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
          simplify_shift_const (NULL_RTX, LSHIFTRT,
              GET_MODE (x),
              XEXP (x, 0), pos),
          ((HOST_WIDE_INT) 1 << len) - 1);
  else
    /* Any other cases we can't handle.  */
    return x;

  /* If we couldn't do this for some reason, return the original
     expression.  */
  if (GET_CODE (tem) == CLOBBER)
    return x;

  return tem;
}

/* X is a SET which contains an assignment of one object into
   a part of another (such as a bit-field assignment, STRICT_LOW_PART,
   or certain SUBREGS). If possible, convert it into a series of
   logical operations.

   We half-heartedly support variable positions, but do not at all
   support variable lengths.  */

static rtx
expand_field_assignment (x)
     rtx x;
{
  rtx inner;
  rtx pos;      /* Always counts from low bit.  */
  int len;
  rtx mask;
  enum machine_mode compute_mode;

  /* Loop until we find something we can't simplify.  */
  while (1)
    {
      if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
    && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
  {
    inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
    len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
    pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
  }
      else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
         && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
  {
    inner = XEXP (SET_DEST (x), 0);
    len = INTVAL (XEXP (SET_DEST (x), 1));
    pos = XEXP (SET_DEST (x), 2);

    /* If the position is constant and spans the width of INNER,
       surround INNER  with a USE to indicate this.  */
    if (GET_CODE (pos) == CONST_INT
        && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
      inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);

    if (BITS_BIG_ENDIAN)
      {
        if (GET_CODE (pos) == CONST_INT)
    pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
             - INTVAL (pos));
        else if (GET_CODE (pos) == MINUS
           && GET_CODE (XEXP (pos, 1)) == CONST_INT
           && (INTVAL (XEXP (pos, 1))
         == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
    /* If position is ADJUST - X, new position is X.  */
    pos = XEXP (pos, 0);
        else
    pos = gen_binary (MINUS, GET_MODE (pos),
          GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
             - len),
          pos);
      }
  }

      /* A SUBREG between two modes that occupy the same numbers of words
   can be done by moving the SUBREG to the source.  */
      else if (GET_CODE (SET_DEST (x)) == SUBREG
         /* We need SUBREGs to compute nonzero_bits properly.  */
         && nonzero_sign_valid
         && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
       == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
  {
    x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
         gen_lowpart_for_combine
         (GET_MODE (SUBREG_REG (SET_DEST (x))),
          SET_SRC (x)));
    continue;
  }
      else
  break;

      while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
  inner = SUBREG_REG (inner);

      compute_mode = GET_MODE (inner);

      /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
      if (! SCALAR_INT_MODE_P (compute_mode))
  {
    enum machine_mode imode;

    /* Don't do anything for vector or complex integral types.  */
    if (! FLOAT_MODE_P (compute_mode))
      break;

    /* Try to find an integral mode to pun with.  */
    imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
    if (imode == BLKmode)
      break;

    compute_mode = imode;
    inner = gen_lowpart_for_combine (imode, inner);
  }

      /* Compute a mask of LEN bits, if we can do this on the host machine.  */
      if (len < HOST_BITS_PER_WIDE_INT)
  mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
      else
  break;

      /* Now compute the equivalent expression.  Make a copy of INNER
   for the SET_DEST in case it is a MEM into which we will substitute;
   we don't want shared RTL in that case.  */
      x = gen_rtx_SET
  (VOIDmode, copy_rtx (inner),
   gen_binary (IOR, compute_mode,
         gen_binary (AND, compute_mode,
         simplify_gen_unary (NOT, compute_mode,
                 gen_binary (ASHIFT,
                 compute_mode,
                 mask, pos),
                 compute_mode),
         inner),
         gen_binary (ASHIFT, compute_mode,
         gen_binary (AND, compute_mode,
               gen_lowpart_for_combine
               (compute_mode, SET_SRC (x)),
               mask),
         pos)));
    }

  return x;
}

/* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
   it is an RTX that represents a variable starting position; otherwise,
   POS is the (constant) starting bit position (counted from the LSB).

   INNER may be a USE.  This will occur when we started with a bitfield
   that went outside the boundary of the object in memory, which is
   allowed on most machines.  To isolate this case, we produce a USE
   whose mode is wide enough and surround the MEM with it.  The only
   code that understands the USE is this routine.  If it is not removed,
   it will cause the resulting insn not to match.

   UNSIGNEDP is nonzero for an unsigned reference and zero for a
   signed reference.

   IN_DEST is nonzero if this is a reference in the destination of a
   SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
   a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
   be used.

   IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
   ZERO_EXTRACT should be built even for bits starting at bit 0.

   MODE is the desired mode of the result (if IN_DEST == 0).

   The result is an RTX for the extraction or NULL_RTX if the target
   can't handle it.  */

static rtx
make_extraction (mode, inner, pos, pos_rtx, len,
     unsignedp, in_dest, in_compare)
     enum machine_mode mode;
     rtx inner;
     HOST_WIDE_INT pos;
     rtx pos_rtx;
     unsigned HOST_WIDE_INT len;
     int unsignedp;
     int in_dest, in_compare;
{
  /* This mode describes the size of the storage area
     to fetch the overall value from.  Within that, we
     ignore the POS lowest bits, etc.  */
  enum machine_mode is_mode = GET_MODE (inner);
  enum machine_mode inner_mode;
  enum machine_mode wanted_inner_mode = byte_mode;
  enum machine_mode wanted_inner_reg_mode = word_mode;
  enum machine_mode pos_mode = word_mode;
  enum machine_mode extraction_mode = word_mode;
  enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
  int spans_byte = 0;
  rtx new = 0;
  rtx orig_pos_rtx = pos_rtx;
  HOST_WIDE_INT orig_pos;

  /* Get some information about INNER and get the innermost object.  */
  if (GET_CODE (inner) == USE)
    /* (use:SI (mem:QI foo)) stands for (mem:SI foo).  */
    /* We don't need to adjust the position because we set up the USE
       to pretend that it was a full-word object.  */
    spans_byte = 1, inner = XEXP (inner, 0);
  else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
    {
      /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
   consider just the QI as the memory to extract from.
   The subreg adds or removes high bits; its mode is
   irrelevant to the meaning of this extraction,
   since POS and LEN count from the lsb.  */
      if (GET_CODE (SUBREG_REG (inner)) == MEM)
  is_mode = GET_MODE (SUBREG_REG (inner));
      inner = SUBREG_REG (inner);
    }
  else if (GET_CODE (inner) == ASHIFT
     && GET_CODE (XEXP (inner, 1)) == CONST_INT
     && pos_rtx == 0 && pos == 0
     && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
    {
      /* We're extracting the least significant bits of an rtx
   (ashift X (const_int C)), where LEN > C.  Extract the
   least significant (LEN - C) bits of X, giving an rtx
   whose mode is MODE, then shift it left C times.  */
      new = make_extraction (mode, XEXP (inner, 0),
           0, 0, len - INTVAL (XEXP (inner, 1)),
           unsignedp, in_dest, in_compare);
      if (new != 0)
  return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
    }

  inner_mode = GET_MODE (inner);

  if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
    pos = INTVAL (pos_rtx), pos_rtx = 0;

  /* See if this can be done without an extraction.  We never can if the
     width of the field is not the same as that of some integer mode. For
     registers, we can only avoid the extraction if the position is at the
     low-order bit and this is either not in the destination or we have the
     appropriate STRICT_LOW_PART operation available.

     For MEM, we can avoid an extract if the field starts on an appropriate
     boundary and we can change the mode of the memory reference.  However,
     we cannot directly access the MEM if we have a USE and the underlying
     MEM is not TMODE.  This combination means that MEM was being used in a
     context where bits outside its mode were being referenced; that is only
     valid in bit-field insns.  */

  if (tmode != BLKmode
      && ! (spans_byte && inner_mode != tmode)
      && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
     && GET_CODE (inner) != MEM
     && (! in_dest
         || (GET_CODE (inner) == REG
       && have_insn_for (STRICT_LOW_PART, tmode))))
    || (GET_CODE (inner) == MEM && pos_rtx == 0
        && (pos
      % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
         : BITS_PER_UNIT)) == 0
        /* We can't do this if we are widening INNER_MODE (it
     may not be aligned, for one thing).  */
        && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
        && (inner_mode == tmode
      || (! mode_dependent_address_p (XEXP (inner, 0))
          && ! MEM_VOLATILE_P (inner))))))
    {
      /* If INNER is a MEM, make a new MEM that encompasses just the desired
   field.  If the original and current mode are the same, we need not
   adjust the offset.  Otherwise, we do if bytes big endian.

   If INNER is not a MEM, get a piece consisting of just the field
   of interest (in this case POS % BITS_PER_WORD must be 0).  */

      if (GET_CODE (inner) == MEM)
  {
    HOST_WIDE_INT offset;

    /* POS counts from lsb, but make OFFSET count in memory order.  */
    if (BYTES_BIG_ENDIAN)
      offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
    else
      offset = pos / BITS_PER_UNIT;

    new = adjust_address_nv (inner, tmode, offset);
  }
      else if (GET_CODE (inner) == REG)
  {
    /* We can't call gen_lowpart_for_combine here since we always want
       a SUBREG and it would sometimes return a new hard register.  */
    if (tmode != inner_mode)
      {
        HOST_WIDE_INT final_word = pos / BITS_PER_WORD;

        if (WORDS_BIG_ENDIAN
      && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
    final_word = ((GET_MODE_SIZE (inner_mode)
             - GET_MODE_SIZE (tmode))
            / UNITS_PER_WORD) - final_word;

        final_word *= UNITS_PER_WORD;
        if (BYTES_BIG_ENDIAN &&
      GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
    final_word += (GET_MODE_SIZE (inner_mode)
             - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;

        /* Avoid creating invalid subregs, for example when
     simplifying (x>>32)&255.  */
        if (final_word >= GET_MODE_SIZE (inner_mode))
    return