Open64: osprey/cygnus/opcodes/fr30-desc.c Source File

00001 /*
00002  * Copyright 2003, 2004, 2005, 2006 PathScale, Inc.  All Rights Reserved.
00003  */
00004 
00005 /* CPU data for fr30.
00006 
00007 THIS FILE IS MACHINE GENERATED WITH CGEN.
00008 
00009 Copyright 1996-2005 Free Software Foundation, Inc.
00010 
00011 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00012 
00013 This program is free software; you can redistribute it and/or modify
00014 it under the terms of the GNU General Public License as published by
00015 the Free Software Foundation; either version 2, or (at your option)
00016 any later version.
00017 
00018 This program is distributed in the hope that it will be useful,
00019 but WITHOUT ANY WARRANTY; without even the implied warranty of
00020 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00021 GNU General Public License for more details.
00022 
00023 You should have received a copy of the GNU General Public License along
00024 with this program; if not, write to the Free Software Foundation, Inc.,
00025 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00026 
00027 */
00028 
00029 #include "sysdep.h"
00030 #include <stdio.h>
00031 #include <stdarg.h>
00032 #include "ansidecl.h"
00033 #include "bfd.h"
00034 #include "symcat.h"
00035 #include "fr30-desc.h"
00036 #include "fr30-opc.h"
00037 #include "opintl.h"
00038 #include "libiberty.h"
00039 #include "xregex.h"
00040 
00041 /* Attributes.  */
00042 
00043 static const CGEN_ATTR_ENTRY bool_attr[] =
00044 {
00045   { "#f", 0 },
00046   { "#t", 1 },
00047   { 0, 0 }
00048 };
00049 
00050 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00051 {
00052   { "base", MACH_BASE },
00053   { "fr30", MACH_FR30 },
00054   { "max", MACH_MAX },
00055   { 0, 0 }
00056 };
00057 
00058 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00059 {
00060   { "fr30", ISA_FR30 },
00061   { "max", ISA_MAX },
00062   { 0, 0 }
00063 };
00064 
00065 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
00066 {
00067   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00068   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00069   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00070   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00071   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00072   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00073   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00074   { 0, 0, 0 }
00075 };
00076 
00077 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
00078 {
00079   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00080   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00081   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00082   { "PC", &bool_attr[0], &bool_attr[0] },
00083   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00084   { 0, 0, 0 }
00085 };
00086 
00087 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
00088 {
00089   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00090   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00091   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00092   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00093   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00094   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00095   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00096   { "RELAX", &bool_attr[0], &bool_attr[0] },
00097   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00098   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
00099   { 0, 0, 0 }
00100 };
00101 
00102 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
00103 {
00104   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00105   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00106   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00107   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00108   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00109   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00110   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00111   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00112   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00113   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00114   { "PBB", &bool_attr[0], &bool_attr[0] },
00115   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00116   { 0, 0, 0 }
00117 };
00118 
00119 /* Instruction set variants.  */
00120 
00121 static const CGEN_ISA fr30_cgen_isa_table[] = {
00122   { "fr30", 16, 16, 16, 48 },
00123   { 0, 0, 0, 0, 0 }
00124 };
00125 
00126 /* Machine variants.  */
00127 
00128 static const CGEN_MACH fr30_cgen_mach_table[] = {
00129   { "fr30", "fr30", MACH_FR30, 0 },
00130   { 0, 0, 0, 0 }
00131 };
00132 
00133 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
00134 {
00135   { "r0", 0, {0, {0}}, 0, 0 },
00136   { "r1", 1, {0, {0}}, 0, 0 },
00137   { "r2", 2, {0, {0}}, 0, 0 },
00138   { "r3", 3, {0, {0}}, 0, 0 },
00139   { "r4", 4, {0, {0}}, 0, 0 },
00140   { "r5", 5, {0, {0}}, 0, 0 },
00141   { "r6", 6, {0, {0}}, 0, 0 },
00142   { "r7", 7, {0, {0}}, 0, 0 },
00143   { "r8", 8, {0, {0}}, 0, 0 },
00144   { "r9", 9, {0, {0}}, 0, 0 },
00145   { "r10", 10, {0, {0}}, 0, 0 },
00146   { "r11", 11, {0, {0}}, 0, 0 },
00147   { "r12", 12, {0, {0}}, 0, 0 },
00148   { "r13", 13, {0, {0}}, 0, 0 },
00149   { "r14", 14, {0, {0}}, 0, 0 },
00150   { "r15", 15, {0, {0}}, 0, 0 },
00151   { "ac", 13, {0, {0}}, 0, 0 },
00152   { "fp", 14, {0, {0}}, 0, 0 },
00153   { "sp", 15, {0, {0}}, 0, 0 }
00154 };
00155 
00156 CGEN_KEYWORD fr30_cgen_opval_gr_names =
00157 {
00158   & fr30_cgen_opval_gr_names_entries[0],
00159   19,
00160   0, 0, 0, 0, ""
00161 };
00162 
00163 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
00164 {
00165   { "cr0", 0, {0, {0}}, 0, 0 },
00166   { "cr1", 1, {0, {0}}, 0, 0 },
00167   { "cr2", 2, {0, {0}}, 0, 0 },
00168   { "cr3", 3, {0, {0}}, 0, 0 },
00169   { "cr4", 4, {0, {0}}, 0, 0 },
00170   { "cr5", 5, {0, {0}}, 0, 0 },
00171   { "cr6", 6, {0, {0}}, 0, 0 },
00172   { "cr7", 7, {0, {0}}, 0, 0 },
00173   { "cr8", 8, {0, {0}}, 0, 0 },
00174   { "cr9", 9, {0, {0}}, 0, 0 },
00175   { "cr10", 10, {0, {0}}, 0, 0 },
00176   { "cr11", 11, {0, {0}}, 0, 0 },
00177   { "cr12", 12, {0, {0}}, 0, 0 },
00178   { "cr13", 13, {0, {0}}, 0, 0 },
00179   { "cr14", 14, {0, {0}}, 0, 0 },
00180   { "cr15", 15, {0, {0}}, 0, 0 }
00181 };
00182 
00183 CGEN_KEYWORD fr30_cgen_opval_cr_names =
00184 {
00185   & fr30_cgen_opval_cr_names_entries[0],
00186   16,
00187   0, 0, 0, 0, ""
00188 };
00189 
00190 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
00191 {
00192   { "tbr", 0, {0, {0}}, 0, 0 },
00193   { "rp", 1, {0, {0}}, 0, 0 },
00194   { "ssp", 2, {0, {0}}, 0, 0 },
00195   { "usp", 3, {0, {0}}, 0, 0 },
00196   { "mdh", 4, {0, {0}}, 0, 0 },
00197   { "mdl", 5, {0, {0}}, 0, 0 }
00198 };
00199 
00200 CGEN_KEYWORD fr30_cgen_opval_dr_names =
00201 {
00202   & fr30_cgen_opval_dr_names_entries[0],
00203   6,
00204   0, 0, 0, 0, ""
00205 };
00206 
00207 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
00208 {
00209   { "ps", 0, {0, {0}}, 0, 0 }
00210 };
00211 
00212 CGEN_KEYWORD fr30_cgen_opval_h_ps =
00213 {
00214   & fr30_cgen_opval_h_ps_entries[0],
00215   1,
00216   0, 0, 0, 0, ""
00217 };
00218 
00219 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
00220 {
00221   { "r13", 0, {0, {0}}, 0, 0 }
00222 };
00223 
00224 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
00225 {
00226   & fr30_cgen_opval_h_r13_entries[0],
00227   1,
00228   0, 0, 0, 0, ""
00229 };
00230 
00231 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
00232 {
00233   { "r14", 0, {0, {0}}, 0, 0 }
00234 };
00235 
00236 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
00237 {
00238   & fr30_cgen_opval_h_r14_entries[0],
00239   1,
00240   0, 0, 0, 0, ""
00241 };
00242 
00243 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
00244 {
00245   { "r15", 0, {0, {0}}, 0, 0 }
00246 };
00247 
00248 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
00249 {
00250   & fr30_cgen_opval_h_r15_entries[0],
00251   1,
00252   0, 0, 0, 0, ""
00253 };
00254 
00255 
00256 /* The hardware table.  */
00257 
00258 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00259 #define A(a) (1 << CGEN_HW_##a)
00260 #else
00261 #define A(a) (1 << CGEN_HW_a)
00262 #endif
00263 
00264 const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
00265 {
00266   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00267   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00268   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00269   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00270   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00271   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
00272   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
00273   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
00274   { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { (1<<MACH_BASE) } } },
00275   { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { (1<<MACH_BASE) } } },
00276   { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { (1<<MACH_BASE) } } },
00277   { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { (1<<MACH_BASE) } } },
00278   { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { (1<<MACH_BASE) } } },
00279   { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00280   { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00281   { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00282   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00283   { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00284   { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00285   { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00286   { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00287   { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00288   { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00289   { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00290   { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00291   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
00292 };
00293 
00294 #undef A
00295 
00296 
00297 /* The instruction field table.  */
00298 
00299 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00300 #define A(a) (1 << CGEN_IFLD_##a)
00301 #else
00302 #define A(a) (1 << CGEN_IFLD_a)
00303 #endif
00304 
00305 const CGEN_IFLD fr30_cgen_ifld_table[] =
00306 {
00307   { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
00308   { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
00309   { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { (1<<MACH_BASE) } }  },
00310   { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
00311   { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00312   { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
00313   { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { (1<<MACH_BASE) } }  },
00314   { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { (1<<MACH_BASE) } }  },
00315   { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { (1<<MACH_BASE) } }  },
00316   { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00317   { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
00318   { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00319   { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
00320   { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00321   { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
00322   { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00323   { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
00324   { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00325   { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { (1<<MACH_BASE) } }  },
00326   { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00327   { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00328   { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00329   { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
00330   { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00331   { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { (1<<MACH_BASE) } }  },
00332   { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE) } }  },
00333   { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
00334   { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { (1<<MACH_BASE) } }  },
00335   { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
00336   { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
00337   { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { (1<<MACH_BASE) } }  },
00338   { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00339   { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00340   { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00341   { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00342   { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00343   { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00344   { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00345   { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00346   { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00347   { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00348   { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { (1<<MACH_BASE) } }  },
00349   { 0, 0, 0, 0, 0, 0, {0, {0}} }
00350 };
00351 
00352 #undef A
00353 
00354 
00355 
00356 /* multi ifield declarations */
00357 
00358 const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
00359 
00360 
00361 /* multi ifield definitions */
00362 
00363 const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
00364 {
00365     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_4] } },
00366     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_16] } },
00367     { 0, { (const PTR) 0 } }
00368 };
00369 
00370 /* The operand table.  */
00371 
00372 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00373 #define A(a) (1 << CGEN_OPERAND_##a)
00374 #else
00375 #define A(a) (1 << CGEN_OPERAND_a)
00376 #endif
00377 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00378 #define OPERAND(op) FR30_OPERAND_##op
00379 #else
00380 #define OPERAND(op) FR30_OPERAND_op
00381 #endif
00382 
00383 const CGEN_OPERAND fr30_cgen_operand_table[] =
00384 {
00385 /* pc: program counter */
00386   { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
00387     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } }, 
00388     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00389 /* Ri: destination register */
00390   { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
00391     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } }, 
00392     { 0, { (1<<MACH_BASE) } }  },
00393 /* Rj: source register */
00394   { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
00395     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } }, 
00396     { 0, { (1<<MACH_BASE) } }  },
00397 /* Ric: target register coproc insn */
00398   { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
00399     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } }, 
00400     { 0, { (1<<MACH_BASE) } }  },
00401 /* Rjc: source register coproc insn */
00402   { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
00403     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } }, 
00404     { 0, { (1<<MACH_BASE) } }  },
00405 /* CRi: coprocessor register */
00406   { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
00407     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } }, 
00408     { 0, { (1<<MACH_BASE) } }  },
00409 /* CRj: coprocessor register */
00410   { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
00411     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } }, 
00412     { 0, { (1<<MACH_BASE) } }  },
00413 /* Rs1: dedicated register */
00414   { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
00415     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } }, 
00416     { 0, { (1<<MACH_BASE) } }  },
00417 /* Rs2: dedicated register */
00418   { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
00419     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } }, 
00420     { 0, { (1<<MACH_BASE) } }  },
00421 /* R13: General Register 13 */
00422   { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
00423     { 0, { (const PTR) 0 } }, 
00424     { 0, { (1<<MACH_BASE) } }  },
00425 /* R14: General Register 14 */
00426   { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
00427     { 0, { (const PTR) 0 } }, 
00428     { 0, { (1<<MACH_BASE) } }  },
00429 /* R15: General Register 15 */
00430   { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
00431     { 0, { (const PTR) 0 } }, 
00432     { 0, { (1<<MACH_BASE) } }  },
00433 /* ps: Program Status register */
00434   { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
00435     { 0, { (const PTR) 0 } }, 
00436     { 0, { (1<<MACH_BASE) } }  },
00437 /* u4: 4  bit unsigned immediate */
00438   { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
00439     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } }, 
00440     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00441 /* u4c: 4  bit unsigned immediate */
00442   { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
00443     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } }, 
00444     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00445 /* u8: 8  bit unsigned immediate */
00446   { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
00447     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } }, 
00448     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00449 /* i8: 8  bit unsigned immediate */
00450   { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
00451     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } }, 
00452     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00453 /* udisp6: 6  bit unsigned immediate */
00454   { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
00455     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } }, 
00456     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00457 /* disp8: 8  bit signed   immediate */
00458   { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
00459     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } }, 
00460     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00461 /* disp9: 9  bit signed   immediate */
00462   { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
00463     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } }, 
00464     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00465 /* disp10: 10 bit signed   immediate */
00466   { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
00467     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } }, 
00468     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00469 /* s10: 10 bit signed   immediate */
00470   { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
00471     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } }, 
00472     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00473 /* u10: 10 bit unsigned immediate */
00474   { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
00475     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } }, 
00476     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00477 /* i32: 32 bit immediate */
00478   { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
00479     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } }, 
00480     { 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
00481 /* m4: 4  bit negative immediate */
00482   { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
00483     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } }, 
00484     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00485 /* i20: 20 bit immediate */
00486   { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
00487     { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } }, 
00488     { 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
00489 /* dir8: 8  bit direct address */
00490   { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
00491     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } }, 
00492     { 0, { (1<<MACH_BASE) } }  },
00493 /* dir9: 9  bit direct address */
00494   { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
00495     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } }, 
00496     { 0, { (1<<MACH_BASE) } }  },
00497 /* dir10: 10 bit direct address */
00498   { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
00499     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } }, 
00500     { 0, { (1<<MACH_BASE) } }  },
00501 /* label9: 9  bit pc relative address */
00502   { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
00503     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } }, 
00504     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00505 /* label12: 12 bit pc relative address */
00506   { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
00507     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } }, 
00508     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00509 /* reglist_low_ld: 8 bit low register mask for ldm */
00510   { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
00511     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } }, 
00512     { 0, { (1<<MACH_BASE) } }  },
00513 /* reglist_hi_ld: 8 bit high register mask for ldm */
00514   { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
00515     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } }, 
00516     { 0, { (1<<MACH_BASE) } }  },
00517 /* reglist_low_st: 8 bit low register mask for stm */
00518   { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
00519     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } }, 
00520     { 0, { (1<<MACH_BASE) } }  },
00521 /* reglist_hi_st: 8 bit high register mask for stm */
00522   { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
00523     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } }, 
00524     { 0, { (1<<MACH_BASE) } }  },
00525 /* cc: condition codes */
00526   { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
00527     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } }, 
00528     { 0, { (1<<MACH_BASE) } }  },
00529 /* ccc: coprocessor calc */
00530   { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
00531     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } }, 
00532     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
00533 /* nbit: negative   bit */
00534   { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
00535     { 0, { (const PTR) 0 } }, 
00536     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00537 /* vbit: overflow   bit */
00538   { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
00539     { 0, { (const PTR) 0 } }, 
00540     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00541 /* zbit: zero       bit */
00542   { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
00543     { 0, { (const PTR) 0 } }, 
00544     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00545 /* cbit: carry      bit */
00546   { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
00547     { 0, { (const PTR) 0 } }, 
00548     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00549 /* ibit: interrupt  bit */
00550   { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
00551     { 0, { (const PTR) 0 } }, 
00552     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00553 /* sbit: stack      bit */
00554   { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
00555     { 0, { (const PTR) 0 } }, 
00556     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00557 /* tbit: trace trap bit */
00558   { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
00559     { 0, { (const PTR) 0 } }, 
00560     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00561 /* d0bit: division 0 bit */
00562   { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
00563     { 0, { (const PTR) 0 } }, 
00564     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00565 /* d1bit: division 1 bit */
00566   { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
00567     { 0, { (const PTR) 0 } }, 
00568     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00569 /* ccr: condition code bits */
00570   { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
00571     { 0, { (const PTR) 0 } }, 
00572     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00573 /* scr: system condition bits */
00574   { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
00575     { 0, { (const PTR) 0 } }, 
00576     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00577 /* ilm: interrupt level mask */
00578   { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
00579     { 0, { (const PTR) 0 } }, 
00580     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00581 /* sentinel */
00582   { 0, 0, 0, 0, 0,
00583     { 0, { (const PTR) 0 } },
00584     { 0, { 0 } } }
00585 };
00586 
00587 #undef A
00588 
00589 
00590 /* The instruction table.  */
00591 
00592 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00593 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00594 #define A(a) (1 << CGEN_INSN_##a)
00595 #else
00596 #define A(a) (1 << CGEN_INSN_a)
00597 #endif
00598 
00599 static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
00600 {
00601   /* Special null first entry.
00602      A `num' value of zero is thus invalid.
00603      Also, the special `invalid' insn resides here.  */
00604   { 0, 0, 0, 0, {0, {0}} },
00605 /* add $Rj,$Ri */
00606   {
00607     FR30_INSN_ADD, "add", "add", 16,
00608     { 0, { (1<<MACH_BASE) } }
00609   },
00610 /* add $u4,$Ri */
00611   {
00612     FR30_INSN_ADDI, "addi", "add", 16,
00613     { 0, { (1<<MACH_BASE) } }
00614   },
00615 /* add2 $m4,$Ri */
00616   {
00617     FR30_INSN_ADD2, "add2", "add2", 16,
00618     { 0, { (1<<MACH_BASE) } }
00619   },
00620 /* addc $Rj,$Ri */
00621   {
00622     FR30_INSN_ADDC, "addc", "addc", 16,
00623     { 0, { (1<<MACH_BASE) } }
00624   },
00625 /* addn $Rj,$Ri */
00626   {
00627     FR30_INSN_ADDN, "addn", "addn", 16,
00628     { 0, { (1<<MACH_BASE) } }
00629   },
00630 /* addn $u4,$Ri */
00631   {
00632     FR30_INSN_ADDNI, "addni", "addn", 16,
00633     { 0, { (1<<MACH_BASE) } }
00634   },
00635 /* addn2 $m4,$Ri */
00636   {
00637     FR30_INSN_ADDN2, "addn2", "addn2", 16,
00638     { 0, { (1<<MACH_BASE) } }
00639   },
00640 /* sub $Rj,$Ri */
00641   {
00642     FR30_INSN_SUB, "sub", "sub", 16,
00643     { 0, { (1<<MACH_BASE) } }
00644   },
00645 /* subc $Rj,$Ri */
00646   {
00647     FR30_INSN_SUBC, "subc", "subc", 16,
00648     { 0, { (1<<MACH_BASE) } }
00649   },
00650 /* subn $Rj,$Ri */
00651   {
00652     FR30_INSN_SUBN, "subn", "subn", 16,
00653     { 0, { (1<<MACH_BASE) } }
00654   },
00655 /* cmp $Rj,$Ri */
00656   {
00657     FR30_INSN_CMP, "cmp", "cmp", 16,
00658     { 0, { (1<<MACH_BASE) } }
00659   },
00660 /* cmp $u4,$Ri */
00661   {
00662     FR30_INSN_CMPI, "cmpi", "cmp", 16,
00663     { 0, { (1<<MACH_BASE) } }
00664   },
00665 /* cmp2 $m4,$Ri */
00666   {
00667     FR30_INSN_CMP2, "cmp2", "cmp2", 16,
00668     { 0, { (1<<MACH_BASE) } }
00669   },
00670 /* and $Rj,$Ri */
00671   {
00672     FR30_INSN_AND, "and", "and", 16,
00673     { 0, { (1<<MACH_BASE) } }
00674   },
00675 /* or $Rj,$Ri */
00676   {
00677     FR30_INSN_OR, "or", "or", 16,
00678     { 0, { (1<<MACH_BASE) } }
00679   },
00680 /* eor $Rj,$Ri */
00681   {
00682     FR30_INSN_EOR, "eor", "eor", 16,
00683     { 0, { (1<<MACH_BASE) } }
00684   },
00685 /* and $Rj,@$Ri */
00686   {
00687     FR30_INSN_ANDM, "andm", "and", 16,
00688     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00689   },
00690 /* andh $Rj,@$Ri */
00691   {
00692     FR30_INSN_ANDH, "andh", "andh", 16,
00693     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00694   },
00695 /* andb $Rj,@$Ri */
00696   {
00697     FR30_INSN_ANDB, "andb", "andb", 16,
00698     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00699   },
00700 /* or $Rj,@$Ri */
00701   {
00702     FR30_INSN_ORM, "orm", "or", 16,
00703     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00704   },
00705 /* orh $Rj,@$Ri */
00706   {
00707     FR30_INSN_ORH, "orh", "orh", 16,
00708     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00709   },
00710 /* orb $Rj,@$Ri */
00711   {
00712     FR30_INSN_ORB, "orb", "orb", 16,
00713     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00714   },
00715 /* eor $Rj,@$Ri */
00716   {
00717     FR30_INSN_EORM, "eorm", "eor", 16,
00718     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00719   },
00720 /* eorh $Rj,@$Ri */
00721   {
00722     FR30_INSN_EORH, "eorh", "eorh", 16,
00723     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00724   },
00725 /* eorb $Rj,@$Ri */
00726   {
00727     FR30_INSN_EORB, "eorb", "eorb", 16,
00728     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00729   },
00730 /* bandl $u4,@$Ri */
00731   {
00732     FR30_INSN_BANDL, "bandl", "bandl", 16,
00733     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00734   },
00735 /* borl $u4,@$Ri */
00736   {
00737     FR30_INSN_BORL, "borl", "borl", 16,
00738     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00739   },
00740 /* beorl $u4,@$Ri */
00741   {
00742     FR30_INSN_BEORL, "beorl", "beorl", 16,
00743     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00744   },
00745 /* bandh $u4,@$Ri */
00746   {
00747     FR30_INSN_BANDH, "bandh", "bandh", 16,
00748     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00749   },
00750 /* borh $u4,@$Ri */
00751   {
00752     FR30_INSN_BORH, "borh", "borh", 16,
00753     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00754   },
00755 /* beorh $u4,@$Ri */
00756   {
00757     FR30_INSN_BEORH, "beorh", "beorh", 16,
00758     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00759   },
00760 /* btstl $u4,@$Ri */
00761   {
00762     FR30_INSN_BTSTL, "btstl", "btstl", 16,
00763     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00764   },
00765 /* btsth $u4,@$Ri */
00766   {
00767     FR30_INSN_BTSTH, "btsth", "btsth", 16,
00768     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00769   },
00770 /* mul $Rj,$Ri */
00771   {
00772     FR30_INSN_MUL, "mul", "mul", 16,
00773     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00774   },
00775 /* mulu $Rj,$Ri */
00776   {
00777     FR30_INSN_MULU, "mulu", "mulu", 16,
00778     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00779   },
00780 /* mulh $Rj,$Ri */
00781   {
00782     FR30_INSN_MULH, "mulh", "mulh", 16,
00783     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00784   },
00785 /* muluh $Rj,$Ri */
00786   {
00787     FR30_INSN_MULUH, "muluh", "muluh", 16,
00788     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00789   },
00790 /* div0s $Ri */
00791   {
00792     FR30_INSN_DIV0S, "div0s", "div0s", 16,
00793     { 0, { (1<<MACH_BASE) } }
00794   },
00795 /* div0u $Ri */
00796   {
00797     FR30_INSN_DIV0U, "div0u", "div0u", 16,
00798     { 0, { (1<<MACH_BASE) } }
00799   },
00800 /* div1 $Ri */
00801   {
00802     FR30_INSN_DIV1, "div1", "div1", 16,
00803     { 0, { (1<<MACH_BASE) } }
00804   },
00805 /* div2 $Ri */
00806   {
00807     FR30_INSN_DIV2, "div2", "div2", 16,
00808     { 0, { (1<<MACH_BASE) } }
00809   },
00810 /* div3 */
00811   {
00812     FR30_INSN_DIV3, "div3", "div3", 16,
00813     { 0, { (1<<MACH_BASE) } }
00814   },
00815 /* div4s */
00816   {
00817     FR30_INSN_DIV4S, "div4s", "div4s", 16,
00818     { 0, { (1<<MACH_BASE) } }
00819   },
00820 /* lsl $Rj,$Ri */
00821   {
00822     FR30_INSN_LSL, "lsl", "lsl", 16,
00823     { 0, { (1<<MACH_BASE) } }
00824   },
00825 /* lsl $u4,$Ri */
00826   {
00827     FR30_INSN_LSLI, "lsli", "lsl", 16,
00828     { 0, { (1<<MACH_BASE) } }
00829   },
00830 /* lsl2 $u4,$Ri */
00831   {
00832     FR30_INSN_LSL2, "lsl2", "lsl2", 16,
00833     { 0, { (1<<MACH_BASE) } }
00834   },
00835 /* lsr $Rj,$Ri */
00836   {
00837     FR30_INSN_LSR, "lsr", "lsr", 16,
00838     { 0, { (1<<MACH_BASE) } }
00839   },
00840 /* lsr $u4,$Ri */
00841   {
00842     FR30_INSN_LSRI, "lsri", "lsr", 16,
00843     { 0, { (1<<MACH_BASE) } }
00844   },
00845 /* lsr2 $u4,$Ri */
00846   {
00847     FR30_INSN_LSR2, "lsr2", "lsr2", 16,
00848     { 0, { (1<<MACH_BASE) } }
00849   },
00850 /* asr $Rj,$Ri */
00851   {
00852     FR30_INSN_ASR, "asr", "asr", 16,
00853     { 0, { (1<<MACH_BASE) } }
00854   },
00855 /* asr $u4,$Ri */
00856   {
00857     FR30_INSN_ASRI, "asri", "asr", 16,
00858     { 0, { (1<<MACH_BASE) } }
00859   },
00860 /* asr2 $u4,$Ri */
00861   {
00862     FR30_INSN_ASR2, "asr2", "asr2", 16,
00863     { 0, { (1<<MACH_BASE) } }
00864   },
00865 /* ldi:8 $i8,$Ri */
00866   {
00867     FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
00868     { 0, { (1<<MACH_BASE) } }
00869   },
00870 /* ldi:20 $i20,$Ri */
00871   {
00872     FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
00873     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00874   },
00875 /* ldi:32 $i32,$Ri */
00876   {
00877     FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
00878     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00879   },
00880 /* ld @$Rj,$Ri */
00881   {
00882     FR30_INSN_LD, "ld", "ld", 16,
00883     { 0, { (1<<MACH_BASE) } }
00884   },
00885 /* lduh @$Rj,$Ri */
00886   {
00887     FR30_INSN_LDUH, "lduh", "lduh", 16,
00888     { 0, { (1<<MACH_BASE) } }
00889   },
00890 /* ldub @$Rj,$Ri */
00891   {
00892     FR30_INSN_LDUB, "ldub", "ldub", 16,
00893     { 0, { (1<<MACH_BASE) } }
00894   },
00895 /* ld @($R13,$Rj),$Ri */
00896   {
00897     FR30_INSN_LDR13, "ldr13", "ld", 16,
00898     { 0, { (1<<MACH_BASE) } }
00899   },
00900 /* lduh @($R13,$Rj),$Ri */
00901   {
00902     FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
00903     { 0, { (1<<MACH_BASE) } }
00904   },
00905 /* ldub @($R13,$Rj),$Ri */
00906   {
00907     FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
00908     { 0, { (1<<MACH_BASE) } }
00909   },
00910 /* ld @($R14,$disp10),$Ri */
00911   {
00912     FR30_INSN_LDR14, "ldr14", "ld", 16,
00913     { 0, { (1<<MACH_BASE) } }
00914   },
00915 /* lduh @($R14,$disp9),$Ri */
00916   {
00917     FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
00918     { 0, { (1<<MACH_BASE) } }
00919   },
00920 /* ldub @($R14,$disp8),$Ri */
00921   {
00922     FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
00923     { 0, { (1<<MACH_BASE) } }
00924   },
00925 /* ld @($R15,$udisp6),$Ri */
00926   {
00927     FR30_INSN_LDR15, "ldr15", "ld", 16,
00928     { 0, { (1<<MACH_BASE) } }
00929   },
00930 /* ld @$R15+,$Ri */
00931   {
00932     FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
00933     { 0, { (1<<MACH_BASE) } }
00934   },
00935 /* ld @$R15+,$Rs2 */
00936   {
00937     FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
00938     { 0, { (1<<MACH_BASE) } }
00939   },
00940 /* ld @$R15+,$ps */
00941   {
00942     FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
00943     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00944   },
00945 /* st $Ri,@$Rj */
00946   {
00947     FR30_INSN_ST, "st", "st", 16,
00948     { 0, { (1<<MACH_BASE) } }
00949   },
00950 /* sth $Ri,@$Rj */
00951   {
00952     FR30_INSN_STH, "sth", "sth", 16,
00953     { 0, { (1<<MACH_BASE) } }
00954   },
00955 /* stb $Ri,@$Rj */
00956   {
00957     FR30_INSN_STB, "stb", "stb", 16,
00958     { 0, { (1<<MACH_BASE) } }
00959   },
00960 /* st $Ri,@($R13,$Rj) */
00961   {
00962     FR30_INSN_STR13, "str13", "st", 16,
00963     { 0, { (1<<MACH_BASE) } }
00964   },
00965 /* sth $Ri,@($R13,$Rj) */
00966   {
00967     FR30_INSN_STR13H, "str13h", "sth", 16,
00968     { 0, { (1<<MACH_BASE) } }
00969   },
00970 /* stb $Ri,@($R13,$Rj) */
00971   {
00972     FR30_INSN_STR13B, "str13b", "stb", 16,
00973     { 0, { (1<<MACH_BASE) } }
00974   },
00975 /* st $Ri,@($R14,$disp10) */
00976   {
00977     FR30_INSN_STR14, "str14", "st", 16,
00978     { 0, { (1<<MACH_BASE) } }
00979   },
00980 /* sth $Ri,@($R14,$disp9) */
00981   {
00982     FR30_INSN_STR14H, "str14h", "sth", 16,
00983     { 0, { (1<<MACH_BASE) } }
00984   },
00985 /* stb $Ri,@($R14,$disp8) */
00986   {
00987     FR30_INSN_STR14B, "str14b", "stb", 16,
00988     { 0, { (1<<MACH_BASE) } }
00989   },
00990 /* st $Ri,@($R15,$udisp6) */
00991   {
00992     FR30_INSN_STR15, "str15", "st", 16,
00993     { 0, { (1<<MACH_BASE) } }
00994   },
00995 /* st $Ri,@-$R15 */
00996   {
00997     FR30_INSN_STR15GR, "str15gr", "st", 16,
00998     { 0, { (1<<MACH_BASE) } }
00999   },
01000 /* st $Rs2,@-$R15 */
01001   {
01002     FR30_INSN_STR15DR, "str15dr", "st", 16,
01003     { 0, { (1<<MACH_BASE) } }
01004   },
01005 /* st $ps,@-$R15 */
01006   {
01007     FR30_INSN_STR15PS, "str15ps", "st", 16,
01008     { 0, { (1<<MACH_BASE) } }
01009   },
01010 /* mov $Rj,$Ri */
01011   {
01012     FR30_INSN_MOV, "mov", "mov", 16,
01013     { 0, { (1<<MACH_BASE) } }
01014   },
01015 /* mov $Rs1,$Ri */
01016   {
01017     FR30_INSN_MOVDR, "movdr", "mov", 16,
01018     { 0, { (1<<MACH_BASE) } }
01019   },
01020 /* mov $ps,$Ri */
01021   {
01022     FR30_INSN_MOVPS, "movps", "mov", 16,
01023     { 0, { (1<<MACH_BASE) } }
01024   },
01025 /* mov $Ri,$Rs1 */
01026   {
01027     FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
01028     { 0, { (1<<MACH_BASE) } }
01029   },
01030 /* mov $Ri,$ps */
01031   {
01032     FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
01033     { 0, { (1<<MACH_BASE) } }
01034   },
01035 /* jmp @$Ri */
01036   {
01037     FR30_INSN_JMP, "jmp", "jmp", 16,
01038     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
01039   },
01040 /* jmp:d @$Ri */
01041   {
01042     FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
01043     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01044   },
01045 /* call @$Ri */
01046   {
01047     FR30_INSN_CALLR, "callr", "call", 16,
01048     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
01049   },
01050 /* call:d @$Ri */
01051   {
01052     FR30_INSN_CALLRD, "callrd", "call:d", 16,
01053     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01054   },
01055 /* call $label12 */
01056   {
01057     FR30_INSN_CALL, "call", "call", 16,
01058     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
01059   },
01060 /* call:d $label12 */
01061   {
01062     FR30_INSN_CALLD, "calld", "call:d", 16,
01063     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01064   },
01065 /* ret */
01066   {
01067     FR30_INSN_RET, "ret", "ret", 16,
01068     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
01069   },
01070 /* ret:d */
01071   {
01072     FR30_INSN_RET_D, "ret:d", "ret:d", 16,
01073     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01074   },
01075 /* int $u8 */
01076   {
01077     FR30_INSN_INT, "int", "int", 16,
01078     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
01079   },
01080 /* inte */
01081   {
01082     FR30_INSN_INTE, "inte", "inte", 16,
01083     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
01084   },
01085 /* reti */
01086   {
01087     FR30_INSN_RETI, "reti", "reti", 16,
01088     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01089   },
01090 /* bra:d $label9 */
01091   {
01092     FR30_INSN_BRAD, "brad", "bra:d", 16,
01093     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01094   },
01095 /* bra $label9 */
01096   {
01097     FR30_INSN_BRA, "bra", "bra", 16,
01098     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
01099   },
01100 /* bno:d $label9 */
01101   {
01102     FR30_INSN_BNOD, "bnod", "bno:d", 16,
01103     { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01104   },
01105 /* bno $label9 */
01106   {
01107     FR30_INSN_BNO, "bno", "bno", 16,
01108     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01109   },
01110 /* beq:d $label9 */
01111   {
01112     FR30_INSN_BEQD, "beqd", "beq:d", 16,
01113     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01114   },
01115 /* beq $label9 */
01116   {
01117     FR30_INSN_BEQ, "beq", "beq", 16,
01118     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01119   },
01120 /* bne:d $label9 */
01121   {
01122     FR30_INSN_BNED, "bned", "bne:d", 16,
01123     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01124   },
01125 /* bne $label9 */
01126   {
01127     FR30_INSN_BNE, "bne", "bne", 16,
01128     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01129   },
01130 /* bc:d $label9 */
01131   {
01132     FR30_INSN_BCD, "bcd", "bc:d", 16,
01133     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01134   },
01135 /* bc $label9 */
01136   {
01137     FR30_INSN_BC, "bc", "bc", 16,
01138     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01139   },
01140 /* bnc:d $label9 */
01141   {
01142     FR30_INSN_BNCD, "bncd", "bnc:d", 16,
01143     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01144   },
01145 /* bnc $label9 */
01146   {
01147     FR30_INSN_BNC, "bnc", "bnc", 16,
01148     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01149   },
01150 /* bn:d $label9 */
01151   {
01152     FR30_INSN_BND, "bnd", "bn:d", 16,
01153     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01154   },
01155 /* bn $label9 */
01156   {
01157     FR30_INSN_BN, "bn", "bn", 16,
01158     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01159   },
01160 /* bp:d $label9 */
01161   {
01162     FR30_INSN_BPD, "bpd", "bp:d", 16,
01163     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01164   },
01165 /* bp $label9 */
01166   {
01167     FR30_INSN_BP, "bp", "bp", 16,
01168     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01169   },
01170 /* bv:d $label9 */
01171   {
01172     FR30_INSN_BVD, "bvd", "bv:d", 16,
01173     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01174   },
01175 /* bv $label9 */
01176   {
01177     FR30_INSN_BV, "bv", "bv", 16,
01178     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01179   },
01180 /* bnv:d $label9 */
01181   {
01182     FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
01183     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01184   },
01185 /* bnv $label9 */
01186   {
01187     FR30_INSN_BNV, "bnv", "bnv", 16,
01188     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01189   },
01190 /* blt:d $label9 */
01191   {
01192     FR30_INSN_BLTD, "bltd", "blt:d", 16,
01193     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01194   },
01195 /* blt $label9 */
01196   {
01197     FR30_INSN_BLT, "blt", "blt", 16,
01198     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01199   },
01200 /* bge:d $label9 */
01201   {
01202     FR30_INSN_BGED, "bged", "bge:d", 16,
01203     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01204   },
01205 /* bge $label9 */
01206   {
01207     FR30_INSN_BGE, "bge", "bge", 16,
01208     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01209   },
01210 /* ble:d $label9 */
01211   {
01212     FR30_INSN_BLED, "bled", "ble:d", 16,
01213     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01214   },
01215 /* ble $label9 */
01216   {
01217     FR30_INSN_BLE, "ble", "ble", 16,
01218     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01219   },
01220 /* bgt:d $label9 */
01221   {
01222     FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
01223     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01224   },
01225 /* bgt $label9 */
01226   {
01227     FR30_INSN_BGT, "bgt", "bgt", 16,
01228     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01229   },
01230 /* bls:d $label9 */
01231   {
01232     FR30_INSN_BLSD, "blsd", "bls:d", 16,
01233     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01234   },
01235 /* bls $label9 */
01236   {
01237     FR30_INSN_BLS, "bls", "bls", 16,
01238     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01239   },
01240 /* bhi:d $label9 */
01241   {
01242     FR30_INSN_BHID, "bhid", "bhi:d", 16,
01243     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
01244   },
01245 /* bhi $label9 */
01246   {
01247     FR30_INSN_BHI, "bhi", "bhi", 16,
01248     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { (1<<MACH_BASE) } }
01249   },
01250 /* dmov $R13,@$dir10 */
01251   {
01252     FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
01253     { 0, { (1<<MACH_BASE) } }
01254   },
01255 /* dmovh $R13,@$dir9 */
01256   {
01257     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
01258     { 0, { (1<<MACH_BASE) } }
01259   },
01260 /* dmovb $R13,@$dir8 */
01261   {
01262     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
01263     { 0, { (1<<MACH_BASE) } }
01264   },
01265 /* dmov @$R13+,@$dir10 */
01266   {
01267     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
01268     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01269   },
01270 /* dmovh @$R13+,@$dir9 */
01271   {
01272     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
01273     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01274   },
01275 /* dmovb @$R13+,@$dir8 */
01276   {
01277     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
01278     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01279   },
01280 /* dmov @$R15+,@$dir10 */
01281   {
01282     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
01283     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01284   },
01285 /* dmov @$dir10,$R13 */
01286   {
01287     FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
01288     { 0, { (1<<MACH_BASE) } }
01289   },
01290 /* dmovh @$dir9,$R13 */
01291   {
01292     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
01293     { 0, { (1<<MACH_BASE) } }
01294   },
01295 /* dmovb @$dir8,$R13 */
01296   {
01297     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
01298     { 0, { (1<<MACH_BASE) } }
01299   },
01300 /* dmov @$dir10,@$R13+ */
01301   {
01302     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
01303     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01304   },
01305 /* dmovh @$dir9,@$R13+ */
01306   {
01307     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
01308     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01309   },
01310 /* dmovb @$dir8,@$R13+ */
01311   {
01312     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
01313     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01314   },
01315 /* dmov @$dir10,@-$R15 */
01316   {
01317     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
01318     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01319   },
01320 /* ldres @$Ri+,$u4 */
01321   {
01322     FR30_INSN_LDRES, "ldres", "ldres", 16,
01323     { 0, { (1<<MACH_BASE) } }
01324   },
01325 /* stres $u4,@$Ri+ */
01326   {
01327     FR30_INSN_STRES, "stres", "stres", 16,
01328     { 0, { (1<<MACH_BASE) } }
01329   },
01330 /* copop $u4c,$ccc,$CRj,$CRi */
01331   {
01332     FR30_INSN_COPOP, "copop", "copop", 32,
01333     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01334   },
01335 /* copld $u4c,$ccc,$Rjc,$CRi */
01336   {
01337     FR30_INSN_COPLD, "copld", "copld", 32,
01338     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01339   },
01340 /* copst $u4c,$ccc,$CRj,$Ric */
01341   {
01342     FR30_INSN_COPST, "copst", "copst", 32,
01343     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01344   },
01345 /* copsv $u4c,$ccc,$CRj,$Ric */
01346   {
01347     FR30_INSN_COPSV, "copsv", "copsv", 32,
01348     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01349   },
01350 /* nop */
01351   {
01352     FR30_INSN_NOP, "nop", "nop", 16,
01353     { 0, { (1<<MACH_BASE) } }
01354   },
01355 /* andccr $u8 */
01356   {
01357     FR30_INSN_ANDCCR, "andccr", "andccr", 16,
01358     { 0, { (1<<MACH_BASE) } }
01359   },
01360 /* orccr $u8 */
01361   {
01362     FR30_INSN_ORCCR, "orccr", "orccr", 16,
01363     { 0, { (1<<MACH_BASE) } }
01364   },
01365 /* stilm $u8 */
01366   {
01367     FR30_INSN_STILM, "stilm", "stilm", 16,
01368     { 0, { (1<<MACH_BASE) } }
01369   },
01370 /* addsp $s10 */
01371   {
01372     FR30_INSN_ADDSP, "addsp", "addsp", 16,
01373     { 0, { (1<<MACH_BASE) } }
01374   },
01375 /* extsb $Ri */
01376   {
01377     FR30_INSN_EXTSB, "extsb", "extsb", 16,
01378     { 0, { (1<<MACH_BASE) } }
01379   },
01380 /* extub $Ri */
01381   {
01382     FR30_INSN_EXTUB, "extub", "extub", 16,
01383     { 0, { (1<<MACH_BASE) } }
01384   },
01385 /* extsh $Ri */
01386   {
01387     FR30_INSN_EXTSH, "extsh", "extsh", 16,
01388     { 0, { (1<<MACH_BASE) } }
01389   },
01390 /* extuh $Ri */
01391   {
01392     FR30_INSN_EXTUH, "extuh", "extuh", 16,
01393     { 0, { (1<<MACH_BASE) } }
01394   },
01395 /* ldm0 ($reglist_low_ld) */
01396   {
01397     FR30_INSN_LDM0, "ldm0", "ldm0", 16,
01398     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01399   },
01400 /* ldm1 ($reglist_hi_ld) */
01401   {
01402     FR30_INSN_LDM1, "ldm1", "ldm1", 16,
01403     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01404   },
01405 /* stm0 ($reglist_low_st) */
01406   {
01407     FR30_INSN_STM0, "stm0", "stm0", 16,
01408     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01409   },
01410 /* stm1 ($reglist_hi_st) */
01411   {
01412     FR30_INSN_STM1, "stm1", "stm1", 16,
01413     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01414   },
01415 /* enter $u10 */
01416   {
01417     FR30_INSN_ENTER, "enter", "enter", 16,
01418     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01419   },
01420 /* leave */
01421   {
01422     FR30_INSN_LEAVE, "leave", "leave", 16,
01423     { 0, { (1<<MACH_BASE) } }
01424   },
01425 /* xchb @$Rj,$Ri */
01426   {
01427     FR30_INSN_XCHB, "xchb", "xchb", 16,
01428     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
01429   },
01430 };
01431 
01432 #undef OP
01433 #undef A
01434 
01435 /* Initialize anything needed to be done once, before any cpu_open call.  */
01436 static void init_tables PARAMS ((void));
01437 
01438 static void
01439 init_tables ()
01440 {
01441 }
01442 
01443 static const CGEN_MACH * lookup_mach_via_bfd_name
01444   PARAMS ((const CGEN_MACH *, const char *));
01445 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
01446 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
01447 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
01448 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
01449 static void fr30_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
01450 
01451 /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name.  */
01452 
01453 static const CGEN_MACH *
01454 lookup_mach_via_bfd_name (table, name)
01455      const CGEN_MACH *table;
01456      const char *name;
01457 {
01458   while (table->name)
01459     {
01460       if (strcmp (name, table->bfd_name) == 0)
01461   return table;
01462       ++table;
01463     }
01464   abort ();
01465 }
01466 
01467 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
01468 
01469 static void
01470 build_hw_table (cd)
01471      CGEN_CPU_TABLE *cd;
01472 {
01473   int i;
01474   int machs = cd->machs;
01475   const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
01476   /* MAX_HW is only an upper bound on the number of selected entries.
01477      However each entry is indexed by it's enum so there can be holes in
01478      the table.  */
01479   const CGEN_HW_ENTRY **selected =
01480     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
01481 
01482   cd->hw_table.init_entries = init;
01483   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
01484   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
01485   /* ??? For now we just use machs to determine which ones we want.  */
01486   for (i = 0; init[i].name != NULL; ++i)
01487     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
01488   & machs)
01489       selected[init[i].type] = &init[i];
01490   cd->hw_table.entries = selected;
01491   cd->hw_table.num_entries = MAX_HW;
01492 }
01493 
01494 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
01495 
01496 static void
01497 build_ifield_table (cd)
01498      CGEN_CPU_TABLE *cd;
01499 {
01500   cd->ifld_table = & fr30_cgen_ifld_table[0];
01501 }
01502 
01503 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
01504 
01505 static void
01506 build_operand_table (cd)
01507      CGEN_CPU_TABLE *cd;
01508 {
01509   int i;
01510   int machs = cd->machs;
01511   const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
01512   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
01513      However each entry is indexed by it's enum so there can be holes in
01514      the table.  */
01515   const CGEN_OPERAND **selected =
01516     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01517 
01518   cd->operand_table.init_entries = init;
01519   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
01520   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01521   /* ??? For now we just use mach to determine which ones we want.  */
01522   for (i = 0; init[i].name != NULL; ++i)
01523     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
01524   & machs)
01525       selected[init[i].type] = &init[i];
01526   cd->operand_table.entries = selected;
01527   cd->operand_table.num_entries = MAX_OPERANDS;
01528 }
01529 
01530 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.
01531    ??? This could leave out insns not supported by the specified mach/isa,
01532    but that would cause errors like "foo only supported by bar" to become
01533    "unknown insn", so for now we include all insns and require the app to
01534    do the checking later.
01535    ??? On the other hand, parsing of such insns may require their hardware or
01536    operand elements to be in the table [which they mightn't be].  */
01537 
01538 static void
01539 build_insn_table (cd)
01540      CGEN_CPU_TABLE *cd;
01541 {
01542   int i;
01543   const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
01544   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
01545 
01546   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
01547   for (i = 0; i < MAX_INSNS; ++i)
01548     insns[i].base = &ib[i];
01549   cd->insn_table.init_entries = insns;
01550   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
01551   cd->insn_table.num_init_entries = MAX_INSNS;
01552 }
01553 
01554 /* Subroutine of fr30_cgen_cpu_open to rebuild the tables.  */
01555 
01556 static void
01557 fr30_cgen_rebuild_tables (cd)
01558      CGEN_CPU_TABLE *cd;
01559 {
01560   int i;
01561   unsigned int isas = cd->isas;
01562   unsigned int machs = cd->machs;
01563 
01564   cd->int_insn_p = CGEN_INT_INSN_P;
01565 
01566   /* Data derived from the isa spec.  */
01567 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
01568   cd->default_insn_bitsize = UNSET;
01569   cd->base_insn_bitsize = UNSET;
01570   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
01571   cd->max_insn_bitsize = 0;
01572   for (i = 0; i < MAX_ISAS; ++i)
01573     if (((1 << i) & isas) != 0)
01574       {
01575   const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
01576 
01577   /* Default insn sizes of all selected isas must be
01578      equal or we set the result to 0, meaning "unknown".  */
01579   if (cd->default_insn_bitsize == UNSET)
01580     cd->default_insn_bitsize = isa->default_insn_bitsize;
01581   else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
01582     ; /* this is ok */
01583   else
01584     cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
01585 
01586   /* Base insn sizes of all selected isas must be equal
01587      or we set the result to 0, meaning "unknown".  */
01588   if (cd->base_insn_bitsize == UNSET)
01589     cd->base_insn_bitsize = isa->base_insn_bitsize;
01590   else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
01591     ; /* this is ok */
01592   else
01593     cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
01594 
01595   /* Set min,max insn sizes.  */
01596   if (isa->min_insn_bitsize < cd->min_insn_bitsize)
01597     cd->min_insn_bitsize = isa->min_insn_bitsize;
01598   if (isa->max_insn_bitsize > cd->max_insn_bitsize)
01599     cd->max_insn_bitsize = isa->max_insn_bitsize;
01600       }
01601 
01602   /* Data derived from the mach spec.  */
01603   for (i = 0; i < MAX_MACHS; ++i)
01604     if (((1 << i) & machs) != 0)
01605       {
01606   const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
01607 
01608   if (mach->insn_chunk_bitsize != 0)
01609   {
01610     if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
01611       {
01612         fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
01613            cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
01614         abort ();
01615       }
01616 
01617     cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
01618   }
01619       }
01620 
01621   /* Determine which hw elements are used by MACH.  */
01622   build_hw_table (cd);
01623 
01624   /* Build the ifield table.  */
01625   build_ifield_table (cd);
01626 
01627   /* Determine which operands are used by MACH/ISA.  */
01628   build_operand_table (cd);
01629 
01630   /* Build the instruction table.  */
01631   build_insn_table (cd);
01632 }
01633 
01634 /* Initialize a cpu table and return a descriptor.
01635    It's much like opening a file, and must be the first function called.
01636    The arguments are a set of (type/value) pairs, terminated with
01637    CGEN_CPU_OPEN_END.
01638 
01639    Currently supported values:
01640    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
01641    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
01642    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
01643    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
01644    CGEN_CPU_OPEN_END:     terminates arguments
01645 
01646    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
01647    precluded.
01648 
01649    ??? We only support ISO C stdargs here, not K&R.
01650    Laziness, plus experiment to see if anything requires K&R - eventually
01651    K&R will no longer be supported - e.g. GDB is currently trying this.  */
01652 
01653 CGEN_CPU_DESC
01654 fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
01655 {
01656   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
01657   static int init_p;
01658   unsigned int isas = 0;  /* 0 = "unspecified" */
01659   unsigned int machs = 0; /* 0 = "unspecified" */
01660   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
01661   va_list ap;
01662 
01663   if (! init_p)
01664     {
01665       init_tables ();
01666       init_p = 1;
01667     }
01668 
01669   memset (cd, 0, sizeof (*cd));
01670 
01671   va_start (ap, arg_type);
01672   while (arg_type != CGEN_CPU_OPEN_END)
01673     {
01674       switch (arg_type)
01675   {
01676   case CGEN_CPU_OPEN_ISAS :
01677     isas = va_arg (ap, unsigned int);
01678     break;
01679   case CGEN_CPU_OPEN_MACHS :
01680     machs = va_arg (ap, unsigned int);
01681     break;
01682   case CGEN_CPU_OPEN_BFDMACH :
01683     {
01684       const char *name = va_arg (ap, const char *);
01685       const CGEN_MACH *mach =
01686         lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
01687 
01688       machs |= 1 << mach->num;
01689       break;
01690     }
01691   case CGEN_CPU_OPEN_ENDIAN :
01692     endian = va_arg (ap, enum cgen_endian);
01693     break;
01694   default :
01695     fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
01696        arg_type);
01697     abort (); /* ??? return NULL? */
01698   }
01699       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
01700     }
01701   va_end (ap);
01702 
01703   /* mach unspecified means "all" */
01704   if (machs == 0)
01705     machs = (1 << MAX_MACHS) - 1;
01706   /* base mach is always selected */
01707   machs |= 1;
01708   /* isa unspecified means "all" */
01709   if (isas == 0)
01710     isas = (1 << MAX_ISAS) - 1;
01711   if (endian == CGEN_ENDIAN_UNKNOWN)
01712     {
01713       /* ??? If target has only one, could have a default.  */
01714       fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
01715       abort ();
01716     }
01717 
01718   cd->isas = isas;
01719   cd->machs = machs;
01720   cd->endian = endian;
01721   /* FIXME: for the sparc case we can determine insn-endianness statically.
01722      The worry here is where both data and insn endian can be independently
01723      chosen, in which case this function will need another argument.
01724      Actually, will want to allow for more arguments in the future anyway.  */
01725   cd->insn_endian = endian;
01726 
01727   /* Table (re)builder.  */
01728   cd->rebuild_tables = fr30_cgen_rebuild_tables;
01729   fr30_cgen_rebuild_tables (cd);
01730 
01731   /* Default to not allowing signed overflow.  */
01732   cd->signed_overflow_ok_p = 0;
01733   
01734   return (CGEN_CPU_DESC) cd;
01735 }
01736 
01737 /* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
01738    MACH_NAME is the bfd name of the mach.  */
01739 
01740 CGEN_CPU_DESC
01741 fr30_cgen_cpu_open_1 (mach_name, endian)
01742      const char *mach_name;
01743      enum cgen_endian endian;
01744 {
01745   return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
01746              CGEN_CPU_OPEN_ENDIAN, endian,
01747              CGEN_CPU_OPEN_END);
01748 }
01749 
01750 /* Close a cpu table.
01751    ??? This can live in a machine independent file, but there's currently
01752    no place to put this file (there's no libcgen).  libopcodes is the wrong
01753    place as some simulator ports use this but they don't use libopcodes.  */
01754 
01755 void
01756 fr30_cgen_cpu_close (cd)
01757      CGEN_CPU_DESC cd;
01758 {
01759   unsigned int i;
01760   const CGEN_INSN *insns;
01761 
01762   if (cd->macro_insn_table.init_entries)
01763     {
01764       insns = cd->macro_insn_table.init_entries;
01765       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
01766   {
01767     if (CGEN_INSN_RX ((insns)))
01768       regfree (CGEN_INSN_RX (insns));
01769   }
01770     }
01771 
01772   if (cd->insn_table.init_entries)
01773     {
01774       insns = cd->insn_table.init_entries;
01775       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
01776   {
01777     if (CGEN_INSN_RX (insns))
01778       regfree (CGEN_INSN_RX (insns));
01779   }
01780     }
01781 
01782   
01783 
01784   if (cd->macro_insn_table.init_entries)
01785     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
01786 
01787   if (cd->insn_table.init_entries)
01788     free ((CGEN_INSN *) cd->insn_table.init_entries);
01789 
01790   if (cd->hw_table.entries)
01791     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
01792 
01793   if (cd->operand_table.entries)
01794     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
01795 
01796   free (cd);
01797 }
01798