osprey/kg++fe/gnu/config/rs6000/rs6000.h File Reference

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Data Types
type	rs6000_cpu_select
type	rs6000_stack
type	machine_function
type	rs6000_args
Defines
#define	OBJECT_XCOFF   1
#define	OBJECT_ELF   2
#define	OBJECT_PEF   3
#define	OBJECT_MACHO   4
#define	TARGET_ELF   (TARGET_OBJECT_FORMAT == OBJECT_ELF)
#define	TARGET_XCOFF   (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
#define	TARGET_MACOS   (TARGET_OBJECT_FORMAT == OBJECT_PEF)
#define	TARGET_MACHO   (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
#define	TARGET_AIX   0
#define	TARGET_CPU_DEFAULT   ((char *)0)
#define	CPP_CPU_SPEC   "%{!mcpu*: \ %{mpower: %{!mpower2: -D_ARCH_PWR}} \ %{mpower2: -D_ARCH_PWR2} \ %{mpowerpc*: -D_ARCH_PPC} \ %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \ %{!mno-power: %{!mpower2: %(cpp_default)}}} \%{mcpu=common: -D_ARCH_COM} \%{mcpu=power: -D_ARCH_PWR} \%{mcpu=power2: -D_ARCH_PWR2} \%{mcpu=powerpc: -D_ARCH_PPC} \%{mcpu=rios: -D_ARCH_PWR} \%{mcpu=rios1: -D_ARCH_PWR} \%{mcpu=rios2: -D_ARCH_PWR2} \%{mcpu=rsc: -D_ARCH_PWR} \%{mcpu=rsc1: -D_ARCH_PWR} \%{mcpu=401: -D_ARCH_PPC} \%{mcpu=403: -D_ARCH_PPC} \%{mcpu=405: -D_ARCH_PPC} \%{mcpu=505: -D_ARCH_PPC} \%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \%{mcpu=602: -D_ARCH_PPC} \%{mcpu=603: -D_ARCH_PPC} \%{mcpu=603e: -D_ARCH_PPC} \%{mcpu=ec603e: -D_ARCH_PPC} \%{mcpu=604: -D_ARCH_PPC} \%{mcpu=604e: -D_ARCH_PPC} \%{mcpu=620: -D_ARCH_PPC} \%{mcpu=740: -D_ARCH_PPC} \%{mcpu=7400: -D_ARCH_PPC} \%{mcpu=7450: -D_ARCH_PPC} \%{mcpu=750: -D_ARCH_PPC} \%{mcpu=801: -D_ARCH_PPC} \%{mcpu=821: -D_ARCH_PPC} \%{mcpu=823: -D_ARCH_PPC} \%{mcpu=860: -D_ARCH_PPC} \%{maltivec: -D__ALTIVEC__}"
#define	ASM_CPU_SPEC   "%{!mcpu*: \ %{mpower: %{!mpower2: -mpwr}} \ %{mpower2: -mpwrx} \ %{mpowerpc*: -mppc} \ %{mno-power: %{!mpowerpc*: -mcom}} \ %{!mno-power: %{!mpower2: %(asm_default)}}} \%{mcpu=common: -mcom} \%{mcpu=power: -mpwr} \%{mcpu=power2: -mpwrx} \%{mcpu=powerpc: -mppc} \%{mcpu=rios: -mpwr} \%{mcpu=rios1: -mpwr} \%{mcpu=rios2: -mpwrx} \%{mcpu=rsc: -mpwr} \%{mcpu=rsc1: -mpwr} \%{mcpu=401: -mppc} \%{mcpu=403: -m403} \%{mcpu=405: -m405} \%{mcpu=505: -mppc} \%{mcpu=601: -m601} \%{mcpu=602: -mppc} \%{mcpu=603: -mppc} \%{mcpu=603e: -mppc} \%{mcpu=ec603e: -mppc} \%{mcpu=604: -mppc} \%{mcpu=604e: -mppc} \%{mcpu=620: -mppc} \%{mcpu=740: -mppc} \%{mcpu=7400: -mppc} \%{mcpu=7450: -mppc} \%{mcpu=750: -mppc} \%{mcpu=801: -mppc} \%{mcpu=821: -mppc} \%{mcpu=823: -mppc} \%{mcpu=860: -mppc} \%{maltivec: -maltivec}"
#define	CPP_DEFAULT_SPEC   ""
#define	ASM_DEFAULT_SPEC   ""
#define	SUBTARGET_EXTRA_SPECS
#define	EXTRA_SPECS
#define	MASK_POWER   0x00000001
#define	MASK_POWER2   0x00000002
#define	MASK_POWERPC   0x00000004
#define	MASK_PPC_GPOPT   0x00000008
#define	MASK_PPC_GFXOPT   0x00000010
#define	MASK_POWERPC64   0x00000020
#define	MASK_NEW_MNEMONICS   0x00000040
#define	MASK_NO_FP_IN_TOC   0x00000080
#define	MASK_NO_SUM_IN_TOC   0x00000100
#define	MASK_MINIMAL_TOC   0x00000200
#define	MASK_64BIT   0x00000400
#define	MASK_SOFT_FLOAT   0x00000800
#define	MASK_MULTIPLE   0x00001000
#define	MASK_MULTIPLE_SET   0x00002000
#define	MASK_STRING   0x00004000
#define	MASK_STRING_SET   0x00008000
#define	MASK_NO_UPDATE   0x00010000
#define	MASK_NO_FUSED_MADD   0x00020000
#define	MASK_SCHED_PROLOG   0x00040000
#define	MASK_ALTIVEC   0x00080000
#define	MASK_AIX_STRUCT_RET   0x00100000
#define	MASK_AIX_STRUCT_RET_SET   0x00200000
#define	TARGET_POWER   (target_flags & MASK_POWER)
#define	TARGET_POWER2   (target_flags & MASK_POWER2)
#define	TARGET_POWERPC   (target_flags & MASK_POWERPC)
#define	TARGET_PPC_GPOPT   (target_flags & MASK_PPC_GPOPT)
#define	TARGET_PPC_GFXOPT   (target_flags & MASK_PPC_GFXOPT)
#define	TARGET_NEW_MNEMONICS   (target_flags & MASK_NEW_MNEMONICS)
#define	TARGET_NO_FP_IN_TOC   (target_flags & MASK_NO_FP_IN_TOC)
#define	TARGET_NO_SUM_IN_TOC   (target_flags & MASK_NO_SUM_IN_TOC)
#define	TARGET_MINIMAL_TOC   (target_flags & MASK_MINIMAL_TOC)
#define	TARGET_64BIT   (target_flags & MASK_64BIT)
#define	TARGET_SOFT_FLOAT   (target_flags & MASK_SOFT_FLOAT)
#define	TARGET_MULTIPLE   (target_flags & MASK_MULTIPLE)
#define	TARGET_MULTIPLE_SET   (target_flags & MASK_MULTIPLE_SET)
#define	TARGET_STRING   (target_flags & MASK_STRING)
#define	TARGET_STRING_SET   (target_flags & MASK_STRING_SET)
#define	TARGET_NO_UPDATE   (target_flags & MASK_NO_UPDATE)
#define	TARGET_NO_FUSED_MADD   (target_flags & MASK_NO_FUSED_MADD)
#define	TARGET_SCHED_PROLOG   (target_flags & MASK_SCHED_PROLOG)
#define	TARGET_ALTIVEC   (target_flags & MASK_ALTIVEC)
#define	TARGET_AIX_STRUCT_RET   (target_flags & MASK_AIX_STRUCT_RET)
#define	TARGET_32BIT   (! TARGET_64BIT)
#define	TARGET_HARD_FLOAT   (! TARGET_SOFT_FLOAT)
#define	TARGET_UPDATE   (! TARGET_NO_UPDATE)
#define	TARGET_FUSED_MADD   (! TARGET_NO_FUSED_MADD)
#define	TARGET_POWERPC64   (target_flags & MASK_POWERPC64)
#define	TARGET_XL_CALL   0
#define	TARGET_SWITCHES
#define	TARGET_DEFAULT   (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
#define	SUBTARGET_SWITCHES
#define	rs6000_cpu_attr   ((enum attr_cpu)rs6000_cpu)
#define	PROCESSOR_COMMON   PROCESSOR_PPC601
#define	PROCESSOR_POWER   PROCESSOR_RIOS1
#define	PROCESSOR_POWERPC   PROCESSOR_PPC604
#define	PROCESSOR_POWERPC64   PROCESSOR_RS64A
#define	PROCESSOR_DEFAULT   PROCESSOR_RIOS1
#define	PROCESSOR_DEFAULT64   PROCESSOR_RS64A
#define	ASSEMBLER_DIALECT   (TARGET_NEW_MNEMONICS ? 1 : 0)
#define	SUBTARGET_OPTIONS
#define	TARGET_OPTIONS
#define	TARGET_DEBUG_STACK   rs6000_debug_stack
#define	TARGET_DEBUG_ARG   rs6000_debug_arg
#define	TARGET_LONG_DOUBLE_128   (rs6000_long_double_type_size == 128)
#define	TARGET_ALTIVEC_ABI   rs6000_altivec_abi
#define	OVERRIDE_OPTIONS   rs6000_override_options (TARGET_CPU_DEFAULT)
#define	OPTIMIZATION_OPTIONS(LEVEL, SIZE)   optimization_options(LEVEL,SIZE)
#define	CAN_DEBUG_WITHOUT_FP
#define	REAL_ARITHMETIC
#define	PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)
#define	PROMOTE_FUNCTION_ARGS
#define	PROMOTE_FUNCTION_RETURN
#define	BITS_BIG_ENDIAN   1
#define	BYTES_BIG_ENDIAN   1
#define	WORDS_BIG_ENDIAN   1
#define	BITS_PER_UNIT   8
#define	BITS_PER_WORD   (! TARGET_POWERPC64 ? 32 : 64)
#define	MAX_BITS_PER_WORD   64
#define	UNITS_PER_WORD   (! TARGET_POWERPC64 ? 4 : 8)
#define	MIN_UNITS_PER_WORD   4
#define	UNITS_PER_FP_WORD   8
#define	UNITS_PER_ALTIVEC_WORD   16
#define	PTRDIFF_TYPE   "int"
#define	SIZE_TYPE   "long unsigned int"
#define	WCHAR_TYPE   "short unsigned int"
#define	WCHAR_TYPE_SIZE   16
#define	SHORT_TYPE_SIZE   16
#define	INT_TYPE_SIZE   32
#define	LONG_TYPE_SIZE   (TARGET_32BIT ? 32 : 64)
#define	MAX_LONG_TYPE_SIZE   64
#define	LONG_LONG_TYPE_SIZE   64
#define	CHAR_TYPE_SIZE   BITS_PER_UNIT
#define	FLOAT_TYPE_SIZE   32
#define	DOUBLE_TYPE_SIZE   64
#define	LONG_DOUBLE_TYPE_SIZE   rs6000_long_double_type_size
#define	MAX_LONG_DOUBLE_TYPE_SIZE   128
#define	LIBGCC2_LONG_DOUBLE_TYPE_SIZE   64
#define	WIDEST_HARDWARE_FP_SIZE   64
#define	POINTER_SIZE   (TARGET_32BIT ? 32 : 64)
#define	PARM_BOUNDARY   (TARGET_32BIT ? 32 : 64)
#define	STACK_BOUNDARY   ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
#define	FUNCTION_BOUNDARY   32
#define	BIGGEST_ALIGNMENT   128
#define	LOCAL_ALIGNMENT(TYPE, ALIGN)   ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : ALIGN)
#define	EMPTY_FIELD_BOUNDARY   32
#define	STRUCTURE_SIZE_BOUNDARY   8
#define	PCC_BITFIELD_TYPE_MATTERS   1
#define	CONSTANT_ALIGNMENT(EXP, ALIGN)
#define	DATA_ALIGNMENT(TYPE, ALIGN)
#define	STRICT_ALIGNMENT   0
#define	SLOW_UNALIGNED_ACCESS(MODE, ALIGN)
#define	FIRST_PSEUDO_REGISTER   110
#define	PRE_GCC3_DWARF_FRAME_REGISTERS   77
#define	FIXED_REGISTERS
#define	CALL_USED_REGISTERS
#define	CALL_REALLY_USED_REGISTERS
#define	MQ_REGNO   64
#define	CR0_REGNO   68
#define	CR1_REGNO   69
#define	CR2_REGNO   70
#define	CR3_REGNO   71
#define	CR4_REGNO   72
#define	MAX_CR_REGNO   75
#define	XER_REGNO   76
#define	FIRST_ALTIVEC_REGNO   77
#define	LAST_ALTIVEC_REGNO   108
#define	TOTAL_ALTIVEC_REGS   (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
#define	VRSAVE_REGNO   109
#define	REG_ALLOC_ORDER
#define	FP_REGNO_P(N)   ((N) >= 32 && (N) <= 63)
#define	CR_REGNO_P(N)   ((N) >= 68 && (N) <= 75)
#define	CR_REGNO_NOT_CR0_P(N)   ((N) >= 69 && (N) <= 75)
#define	INT_REGNO_P(N)   ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
#define	XER_REGNO_P(N)   ((N) == XER_REGNO)
#define	ALTIVEC_REGNO_P(N)   ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
#define	HARD_REGNO_NREGS(REGNO, MODE)
#define	ALTIVEC_VECTOR_MODE(MODE)
#define	VECTOR_MODE_SUPPORTED_P(MODE)   (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))
#define	HARD_REGNO_MODE_OK(REGNO, MODE)
#define	MODES_TIEABLE_P(MODE1, MODE2)
#define	REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)
#define	MEMORY_MOVE_COST(MODE, CLASS, IN)
#define	BRANCH_COST   3
#define	CONDITIONAL_REGISTER_USAGE
#define	STACK_POINTER_REGNUM   1
#define	FRAME_POINTER_REGNUM   31
#define	FRAME_POINTER_REQUIRED   0
#define	ARG_POINTER_REGNUM   67
#define	STATIC_CHAIN_REGNUM   11
#define	LINK_REGISTER_REGNUM   65
#define	COUNT_REGISTER_REGNUM   66
#define	STRUCT_VALUE   0
#define	N_REG_CLASSES   (int) LIM_REG_CLASSES
#define	REG_CLASS_NAMES
#define	REG_CLASS_CONTENTS
#define	REGNO_REG_CLASS(REGNO)
#define	INDEX_REG_CLASS   GENERAL_REGS
#define	BASE_REG_CLASS   BASE_REGS
#define	REG_CLASS_FROM_LETTER(C)
#define	CONST_OK_FOR_LETTER_P(VALUE, C)
#define	CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)
#define	EXTRA_CONSTRAINT(OP, C)
#define	PREFERRED_RELOAD_CLASS(X, CLASS)
#define	SECONDARY_RELOAD_CLASS(CLASS, MODE, IN)   secondary_reload_class (CLASS, MODE, IN)
#define	SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)
#define	CLASS_MAX_NREGS(CLASS, MODE)
#define	CLASS_CANNOT_CHANGE_MODE   FLOAT_REGS
#define	CLASS_CANNOT_CHANGE_MODE_P(FROM, TO)   (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
#define	STACK_GROWS_DOWNWARD
#define	RS6000_REG_SAVE
#define	RS6000_SAVE_AREA
#define	RS6000_SAVE_TOC
#define	RS6000_VARARGS_AREA   0
#define	RS6000_ALIGN(n, a)   (((n) + (a) - 1) & ~((a) - 1))
#define	RS6000_VARARGS_SIZE   ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
#define	STARTING_FRAME_OFFSET
#define	STACK_DYNAMIC_OFFSET(FUNDECL)
#define	FIRST_PARM_OFFSET(FNDECL)   RS6000_SAVE_AREA
#define	ARG_POINTER_CFA_OFFSET(FNDECL)   0
#define	REG_PARM_STACK_SPACE(FNDECL)   RS6000_REG_SAVE
#define	OUTGOING_REG_PARM_STACK_SPACE
#define	STACK_POINTER_OFFSET   RS6000_SAVE_AREA
#define	ACCUMULATE_OUTGOING_ARGS   1
#define	RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE)   0
#define	FUNCTION_VALUE(VALTYPE, FUNC)
#define	LIBCALL_VALUE(MODE)
#define	RETURN_IN_MEMORY(TYPE)
#define	DRAFT_V4_STRUCT_RET   0
#define	DEFAULT_PCC_STRUCT_RETURN   0
#define	STACK_SAVEAREA_MODE(LEVEL)
#define	GP_ARG_MIN_REG   3
#define	GP_ARG_MAX_REG   10
#define	GP_ARG_NUM_REG   (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
#define	FP_ARG_MIN_REG   33
#define	FP_ARG_AIX_MAX_REG   45
#define	FP_ARG_V4_MAX_REG   40
#define	FP_ARG_MAX_REG
#define	FP_ARG_NUM_REG   (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
#define	ALTIVEC_ARG_MIN_REG   (FIRST_ALTIVEC_REGNO + 2)
#define	ALTIVEC_ARG_MAX_REG   (ALTIVEC_ARG_MIN_REG + 11)
#define	ALTIVEC_ARG_NUM_REG   (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
#define	GP_ARG_RETURN   GP_ARG_MIN_REG
#define	FP_ARG_RETURN   FP_ARG_MIN_REG
#define	ALTIVEC_ARG_RETURN   (FIRST_ALTIVEC_REGNO + 2)
#define	CALL_NORMAL   0x00000000
#define	CALL_V4_CLEAR_FP_ARGS   0x00000002
#define	CALL_V4_SET_FP_ARGS   0x00000004
#define	CALL_LONG   0x00000008
#define	FUNCTION_VALUE_REGNO_P(N)
#define	FUNCTION_ARG_REGNO_P(N)
#define	RS6000_ARG_SIZE(MODE, TYPE)
#define	INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT)   init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
#define	INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME)   init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
#define	FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)   function_arg_advance (&CUM, MODE, TYPE, NAMED)
#define	USE_FP_FOR_ARG_P(CUM, MODE, TYPE)
#define	USE_ALTIVEC_FOR_ARG_P(CUM, MODE, TYPE)
#define	FUNCTION_ARG(CUM, MODE, TYPE, NAMED)   function_arg (&CUM, MODE, TYPE, NAMED)
#define	FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)   function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
#define	FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)   function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
#define	FUNCTION_ARG_PADDING(MODE, TYPE)   function_arg_padding (MODE, TYPE)
#define	FUNCTION_ARG_BOUNDARY(MODE, TYPE)   function_arg_boundary (MODE, TYPE)
#define	SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL)   setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
#define	BUILD_VA_LIST_TYPE(VALIST)   (VALIST) = rs6000_build_va_list ()
#define	EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg)   rs6000_va_start (stdarg, valist, nextarg)
#define	EXPAND_BUILTIN_VA_ARG(valist, type)   rs6000_va_arg (valist, type)
#define	PAD_VARARGS_DOWN   (TYPE_MODE (type) != BLKmode)
#define	STRICT_ARGUMENT_NAMING   1
#define	FUNCTION_PROFILER(FILE, LABELNO)   output_function_profiler ((FILE), (LABELNO));
#define	EXIT_IGNORE_STACK   1
#define	EPILOGUE_USES(REGNO)
#define	TRAMPOLINE_SIZE   rs6000_trampoline_size ()
#define	INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT)   rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
#define	RETURN_ADDRESS_OFFSET
#define	RETURN_ADDR_RTX(COUNT, FRAME)   (rs6000_return_addr (COUNT, FRAME))
#define	ELIMINABLE_REGS
#define	CAN_ELIMINATE(FROM, TO)
#define	INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)
#define	HAVE_PRE_DECREMENT   1
#define	HAVE_PRE_INCREMENT   1
#define	REGNO_OK_FOR_INDEX_P(REGNO)
#define	REGNO_OK_FOR_BASE_P(REGNO)
#define	MAX_REGS_PER_ADDRESS   2
#define	CONSTANT_ADDRESS_P(X)
#define	LEGITIMATE_CONSTANT_P(X)
#define	REG_OK_STRICT_FLAG   0
#define	INT_REG_OK_FOR_INDEX_P(X, STRICT)
#define	INT_REG_OK_FOR_BASE_P(X, STRICT)   (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
#define	REG_OK_FOR_INDEX_P(X)   INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
#define	REG_OK_FOR_BASE_P(X)   INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
#define	CONSTANT_POOL_EXPR_P(X)   (constant_pool_expr_p (X))
#define	TOC_RELATIVE_EXPR_P(X)   (toc_relative_expr_p (X))
#define	LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X)
#define	LEGITIMATE_SMALL_DATA_P(MODE, X)
#define	LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET)
#define	LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT)
#define	LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT)
#define	LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT)   (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
#define	LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT)
#define	GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)
#define	LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
#define	LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
#define	GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
#define	RS6000_PIC_OFFSET_TABLE_REGNUM   30
#define	PIC_OFFSET_TABLE_REGNUM   (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
#define	TOC_REGISTER   (TARGET_MINIMAL_TOC ? 30 : 2)
#define	CASE_VECTOR_MODE   SImode
#define	CASE_VECTOR_PC_RELATIVE   1
#define	DEFAULT_SIGNED_CHAR   0
#define	MOVE_MAX   (! TARGET_POWERPC64 ? 4 : 8)
#define	MAX_MOVE_MAX   8
#define	SLOW_BYTE_ACCESS   1
#define	WORD_REGISTER_OPERATIONS
#define	LOAD_EXTEND_OP(MODE)   ZERO_EXTEND
#define	SHORT_IMMEDIATES_SIGN_EXTEND
#define	TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)   1
#define	Pmode   (TARGET_32BIT ? SImode : DImode)
#define	FUNCTION_MODE   (TARGET_32BIT ? SImode : DImode)
#define	NO_FUNCTION_CSE
#define	SHIFT_COUNT_TRUNCATED   (TARGET_POWER ? 1 : 0)
#define	CONST_COSTS(RTX, CODE, OUTER_CODE)
#define	RTX_COSTS(X, CODE, OUTER_CODE)
#define	ADDRESS_COST(RTX)   0
#define	EXTRA_CC_MODES
#define	SELECT_CC_MODE(OP, X, Y)
#define	ASM_COMMENT_START   " #"
#define	TARGET_MEM_FUNCTIONS
#define	ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN)
#define	RS6000_WEAK   0
#define	ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET)
#define	ASM_APP_ON   ""
#define	ASM_APP_OFF   ""
#define	REGISTER_NAMES
#define	DEBUG_REGISTER_NAMES
#define	ADDITIONAL_REGISTER_NAMES
#define	RS6000_CALL_GLUE   "cror 31,31,31"
#define	ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)
#define	ASM_OUTPUT_ALIGN(FILE, LOG)
#define	ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO)
#define	INCOMING_RETURN_ADDR_RTX   gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
#define	DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
#define	EH_RETURN_DATA_REGNO(N)   ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
#define	EH_RETURN_STACKADJ_RTX   gen_rtx_REG (Pmode, 10)
#define	PRINT_OPERAND(FILE, X, CODE)   print_operand (FILE, X, CODE)
#define	PRINT_OPERAND_PUNCT_VALID_P(CODE)   ((CODE) == '.')
#define	PRINT_OPERAND_ADDRESS(FILE, ADDR)   print_operand_address (FILE, ADDR)
#define	PREDICATE_CODES
Typedefs
typedef struct rs6000_stack	rs6000_stack_t
typedef struct rs6000_args	CUMULATIVE_ARGS
Enumerations
enum	processor_type {   PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6, PROCESSOR_I386,   PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, PROCESSOR_K6,   PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_max, PROCESSOR_M88100,   PROCESSOR_M88110, PROCESSOR_M88000, PROCESSOR_700, PROCESSOR_7100,   PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_8000, PROCESSOR_RIOS1,   PROCESSOR_RIOS2, PROCESSOR_RS64A, PROCESSOR_MPCCORE, PROCESSOR_PPC403,   PROCESSOR_PPC405, PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604,   PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750,   PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_SH1, PROCESSOR_SH2,   PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4, PROCESSOR_SH5,   PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900, PROCESSOR_R6000,   PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120,   PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,   PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000, PROCESSOR_R4KC,   PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000, PROCESSOR_SB1,   PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8, PROCESSOR_SUPERSPARC,   PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, PROCESSOR_HYPERSPARC,   PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701, PROCESSOR_V9,   PROCESSOR_ULTRASPARC, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,   PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,   PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,   PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,   PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,   PROCESSOR_SB1, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,   PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,   PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,   PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,   PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,   PROCESSOR_SB1, PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6,   PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO,   PROCESSOR_K6, PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_max,   PROCESSOR_M88100, PROCESSOR_M88110, PROCESSOR_M88000, PROCESSOR_700,   PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_8000,   PROCESSOR_RIOS1, PROCESSOR_RIOS2, PROCESSOR_RS64A, PROCESSOR_MPCCORE,   PROCESSOR_PPC403, PROCESSOR_PPC405, PROCESSOR_PPC601, PROCESSOR_PPC603,   PROCESSOR_PPC604, PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630,   PROCESSOR_PPC750, PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_SH1,   PROCESSOR_SH2, PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4,   PROCESSOR_SH5, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,   PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,   PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,   PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,   PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,   PROCESSOR_SB1, PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8,   PROCESSOR_SUPERSPARC, PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934,   PROCESSOR_HYPERSPARC, PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701,   PROCESSOR_V9, PROCESSOR_ULTRASPARC, PROCESSOR_DEFAULT, PROCESSOR_R3000,   PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100,   PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600,   PROCESSOR_R4650, PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500,   PROCESSOR_R8000, PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC,   PROCESSOR_SR71000, PROCESSOR_SB1, PROCESSOR_DEFAULT, PROCESSOR_R3000,   PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100,   PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600,   PROCESSOR_R4650, PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500,   PROCESSOR_R8000, PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC,   PROCESSOR_SR71000, PROCESSOR_SB1, PROCESSOR_EV4, PROCESSOR_EV5,   PROCESSOR_EV6, PROCESSOR_MAX, ARM_CORE, PROCESSOR_I386,   PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, PROCESSOR_K6,   PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_K8, PROCESSOR_NOCONA,   PROCESSOR_max, PROCESSOR_ITANIUM, PROCESSOR_ITANIUM2, PROCESSOR_max,   PROCESSOR_DEFAULT, PROCESSOR_IQ2000, PROCESSOR_IQ10, PROCESSOR_DEFAULT,   PROCESSOR_4KC, PROCESSOR_5KC, PROCESSOR_20KC, PROCESSOR_M4K,   PROCESSOR_R3000, PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000,   PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4130,   PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,   PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R7000, PROCESSOR_R8000,   PROCESSOR_R9000, PROCESSOR_SB1, PROCESSOR_SR71000, PROCESSOR_700,   PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_7300,   PROCESSOR_8000, PROCESSOR_RIOS1, PROCESSOR_RIOS2, PROCESSOR_RS64A,   PROCESSOR_MPCCORE, PROCESSOR_PPC403, PROCESSOR_PPC405, PROCESSOR_PPC440,   PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604, PROCESSOR_PPC604e,   PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750, PROCESSOR_PPC7400,   PROCESSOR_PPC7450, PROCESSOR_PPC8540, PROCESSOR_POWER4, PROCESSOR_POWER5,   PROCESSOR_9672_G5, PROCESSOR_9672_G6, PROCESSOR_2064_Z900, PROCESSOR_2084_Z990,   PROCESSOR_max, PROCESSOR_SH1, PROCESSOR_SH2, PROCESSOR_SH2E,   PROCESSOR_SH2A, PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4,   PROCESSOR_SH4A, PROCESSOR_SH5, PROCESSOR_V7, PROCESSOR_CYPRESS,   PROCESSOR_V8, PROCESSOR_SUPERSPARC, PROCESSOR_SPARCLITE, PROCESSOR_F930,   PROCESSOR_F934, PROCESSOR_HYPERSPARC, PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET,   PROCESSOR_TSC701, PROCESSOR_V9, PROCESSOR_ULTRASPARC, PROCESSOR_ULTRASPARC3,   PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6, PROCESSOR_MAX,   ARM_CORE, PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM,   PROCESSOR_PENTIUMPRO, PROCESSOR_K6, PROCESSOR_ATHLON, PROCESSOR_PENTIUM4,   PROCESSOR_K8, PROCESSOR_NOCONA, PROCESSOR_GENERIC32, PROCESSOR_GENERIC64,   PROCESSOR_AMDFAM10, PROCESSOR_max, PROCESSOR_ITANIUM, PROCESSOR_ITANIUM2,   PROCESSOR_max, PROCESSOR_DEFAULT, PROCESSOR_IQ2000, PROCESSOR_IQ10,   PROCESSOR_R3000, PROCESSOR_4KC, PROCESSOR_4KP, PROCESSOR_5KC,   PROCESSOR_5KF, PROCESSOR_20KC, PROCESSOR_24K, PROCESSOR_24KX,   PROCESSOR_M4K, PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000,   PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4130,   PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,   PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R7000, PROCESSOR_R8000,   PROCESSOR_R9000, PROCESSOR_SB1, PROCESSOR_SB1A, PROCESSOR_SR71000,   PROCESSOR_MAX, PROCESSOR_MN10300, PROCESSOR_AM33, PROCESSOR_AM33_2,   PROCESSOR_MS1_64_001, PROCESSOR_MS1_16_002, PROCESSOR_MS1_16_003, PROCESSOR_MS2,   PROCESSOR_700, PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200,   PROCESSOR_7300, PROCESSOR_8000, PROCESSOR_RIOS1, PROCESSOR_RIOS2,   PROCESSOR_RS64A, PROCESSOR_MPCCORE, PROCESSOR_PPC403, PROCESSOR_PPC405,   PROCESSOR_PPC440, PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604,   PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750,   PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_PPC8540, PROCESSOR_POWER4,   PROCESSOR_POWER5, PROCESSOR_9672_G5, PROCESSOR_9672_G6, PROCESSOR_2064_Z900,   PROCESSOR_2084_Z990, PROCESSOR_2094_Z9_109, PROCESSOR_max, PROCESSOR_SH1,   PROCESSOR_SH2, PROCESSOR_SH2E, PROCESSOR_SH2A, PROCESSOR_SH3,   PROCESSOR_SH3E, PROCESSOR_SH4, PROCESSOR_SH4A, PROCESSOR_SH5,   PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8, PROCESSOR_SUPERSPARC,   PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, PROCESSOR_HYPERSPARC,   PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701, PROCESSOR_V9,   PROCESSOR_ULTRASPARC, PROCESSOR_ULTRASPARC3, PROCESSOR_NIAGARA }
enum	reg_class {   NO_REGS, R2, R0_1, INDEX_REGS,   BASE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS,   CR_REGS, Q_REGS, SPECIAL_REGS, ACCUM0_REGS,   ACCUM_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R24_REG, R25_REG, R27_REG,   GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, LPCOUNT_REG, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, FPU_REGS, LO_REGS,   STACK_REG, BASE_REGS, HI_REGS, CC_REG,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REG, POINTER_X_REGS, POINTER_Y_REGS, POINTER_Z_REGS,   STACK_REG, BASE_POINTER_REGS, POINTER_REGS, ADDW_REGS,   SIMPLE_LD_REGS, LD_REGS, NO_LD_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0R1_REGS,   R2R3_REGS, EXT_LOW_REGS, EXT_REGS, ADDR_REGS,   INDEX_REGS, BK_REG, SP_REG, RC_REG,   COUNTER_REGS, INT_REGS, GENERAL_REGS, DP_REG,   ST_REG, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, S_REGS, INDEX_REGS, SP_REGS,   A_REGS, SI_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   REPEAT_REGS, CR_REGS, ACCUM_REGS, OTHER_FLAG_REGS,   F0_REGS, F1_REGS, BR_FLAG_REGS, FLAG_REGS,   EVEN_REGS, GPR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, A0H_REG, A0L_REG, A0_REG,   A1H_REG, ACCUM_HIGH_REGS, A1L_REG, ACCUM_LOW_REGS,   A1_REG, ACCUM_REGS, X_REG, X_OR_ACCUM_LOW_REGS,   X_OR_ACCUM_REGS, YH_REG, YH_OR_ACCUM_HIGH_REGS, X_OR_YH_REGS,   YL_REG, YL_OR_ACCUM_LOW_REGS, X_OR_YL_REGS, X_OR_Y_REGS,   Y_REG, ACCUM_OR_Y_REGS, PH_REG, X_OR_PH_REGS,   PL_REG, PL_OR_ACCUM_LOW_REGS, X_OR_PL_REGS, YL_OR_PL_OR_ACCUM_LOW_REGS,   P_REG, ACCUM_OR_P_REGS, YL_OR_P_REGS, ACCUM_LOW_OR_YL_OR_P_REGS,   Y_OR_P_REGS, ACCUM_Y_OR_P_REGS, NO_FRAME_Y_ADDR_REGS, Y_ADDR_REGS,   ACCUM_LOW_OR_Y_ADDR_REGS, ACCUM_OR_Y_ADDR_REGS, X_OR_Y_ADDR_REGS, Y_OR_Y_ADDR_REGS,   P_OR_Y_ADDR_REGS, NON_HIGH_YBASE_ELIGIBLE_REGS, YBASE_ELIGIBLE_REGS, J_REG,   J_OR_DAU_16_BIT_REGS, BMU_REGS, NOHIGH_NON_ADDR_REGS, NON_ADDR_REGS,   SLOW_MEM_LOAD_REGS, NOHIGH_NON_YBASE_REGS, NO_ACCUM_NON_YBASE_REGS, NON_YBASE_REGS,   YBASE_VIRT_REGS, ACCUM_LOW_OR_YBASE_REGS, ACCUM_OR_YBASE_REGS, X_OR_YBASE_REGS,   Y_OR_YBASE_REGS, ACCUM_LOW_YL_PL_OR_YBASE_REGS, P_OR_YBASE_REGS, ACCUM_Y_P_OR_YBASE_REGS,   Y_ADDR_OR_YBASE_REGS, YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS, YBASE_OR_YBASE_ELIGIBLE_REGS, NO_HIGH_ALL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG,   MULTIPLY_64_REG, LOW_REGS, HIGH_REGS, REAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,   MAC_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ADDR_REGS, DATA_REGS, FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, AREG, DREG,   CREG, BREG, SIREG, DIREG,   AD_REGS, Q_REGS, NON_Q_REGS, INDEX_REGS,   LEGACY_REGS, GENERAL_REGS, FP_TOP_REG, FP_SECOND_REG,   FLOAT_REGS, SSE_REGS, MMX_REGS, FP_TOP_SSE_REGS,   FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS, INT_SSE_REGS,   FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,   FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS,   ADDL_REGS, GR_REGS, FR_REGS, GR_AND_BR_REGS,   GR_AND_FR_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, D_REGS, X_REGS,   Y_REGS, SP_REGS, DA_REGS, DB_REGS,   Z_REGS, D8_REGS, Q_REGS, D_OR_X_REGS,   D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS, A_REGS,   X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS, A_OR_D_REGS,   A_OR_SP_REGS, H_REGS, S_REGS, D_OR_S_REGS,   X_OR_S_REGS, Y_OR_S_REGS, SP_OR_S_REGS, D_OR_X_OR_S_REGS,   D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS, A_OR_S_REGS, D_OR_A_OR_S_REGS,   TMP_REGS, D_OR_A_OR_TMP_REGS, G_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, DATA_REGS, ADDR_REGS,   FP_REGS, GENERAL_REGS, DATA_OR_FP_REGS, ADDR_OR_FP_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, AP_REG,   XRF_REGS, GENERAL_REGS, AGRF_REGS, XGRF_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, ONLYR1_REGS,   LRW_REGS, GENERAL_REGS, C_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, REMAINDER_REG,   HIMULT_REG, SYSTEM_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, DATA_REGS, ADDRESS_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,   ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,   EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS,   SP_OR_ADDRESS_OR_EXTENDED_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0,   FLOAT_REGS, FP_REGS, GEN_AND_FP_REGS, FRAME_POINTER_REG,   STACK_POINTER_REG, GEN_AND_MEM_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS,   FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,   FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, MUL_REGS,   GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, OUT_REGS,   STD_REGS, ARG_REGS, SRC_REGS, DST_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0_REGS,   R15_REGS, BASE_REGS, GENERAL_REGS, FP_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, BASE_REGS,   GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS, VRSAVE_REGS,   NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,   LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,   CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, ADDR_REGS, GENERAL_REGS,   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REGS, PR_REGS,   T_REGS, MAC_REGS, FPUL_REGS, SIBCALL_REGS,   GENERAL_REGS, FP0_REGS, FP_REGS, DF_REGS,   FPSCR_REGS, GENERAL_FP_REGS, TARGET_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, M16_NA_REGS, M16_REGS,   T_REG, M16_T_REGS, GR_REGS, FP_REGS,   HI_REG, LO_REG, HILO_REG, MD_REGS,   COP0_REGS, COP2_REGS, COP3_REGS, HI_AND_GR_REGS,   LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS,   COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS,   ST_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,   EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REGS, R1_REGS,   TWO_REGS, R2_REGS, EIGHT_REGS, R8_REGS,   ICALL_REGS, GENERAL_REGS, CARRY_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, BR_REGS, FP_REGS, ACC_REG,   SP_REG, RL_REGS, GR_REGS, AR_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,   M16_REGS, T_REG, M16_T_REGS, GR_REGS,   FP_REGS, HI_REG, LO_REG, HILO_REG,   MD_REGS, COP0_REGS, COP2_REGS, COP3_REGS,   HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS,   COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS,   ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, M16_NA_REGS, M16_REGS, T_REG,   M16_T_REGS, GR_REGS, FP_REGS, HI_REG,   LO_REG, HILO_REG, MD_REGS, COP0_REGS,   COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,   HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,   COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R2,   R0_1, INDEX_REGS, BASE_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, LR0_REGS, GENERAL_REGS,   BP_REGS, FC_REGS, CR_REGS, Q_REGS,   SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R24_REG,   R25_REG, R27_REG, GENERAL_REGS, FLOAT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   FPU_REGS, LO_REGS, STACK_REG, BASE_REGS,   HI_REGS, CC_REG, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REG, POINTER_X_REGS,   POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG, BASE_POINTER_REGS,   POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS, LD_REGS,   NO_LD_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R0R1_REGS, R2R3_REGS, EXT_LOW_REGS,   EXT_REGS, ADDR_REGS, INDEX_REGS, BK_REG,   SP_REG, RC_REG, COUNTER_REGS, INT_REGS,   GENERAL_REGS, DP_REG, ST_REG, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, FLOAT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, S_REGS,   INDEX_REGS, SP_REGS, A_REGS, SI_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, REPEAT_REGS, CR_REGS,   ACCUM_REGS, OTHER_FLAG_REGS, F0_REGS, F1_REGS,   BR_FLAG_REGS, FLAG_REGS, EVEN_REGS, GPR_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, A0H_REG,   A0L_REG, A0_REG, A1H_REG, ACCUM_HIGH_REGS,   A1L_REG, ACCUM_LOW_REGS, A1_REG, ACCUM_REGS,   X_REG, X_OR_ACCUM_LOW_REGS, X_OR_ACCUM_REGS, YH_REG,   YH_OR_ACCUM_HIGH_REGS, X_OR_YH_REGS, YL_REG, YL_OR_ACCUM_LOW_REGS,   X_OR_YL_REGS, X_OR_Y_REGS, Y_REG, ACCUM_OR_Y_REGS,   PH_REG, X_OR_PH_REGS, PL_REG, PL_OR_ACCUM_LOW_REGS,   X_OR_PL_REGS, YL_OR_PL_OR_ACCUM_LOW_REGS, P_REG, ACCUM_OR_P_REGS,   YL_OR_P_REGS, ACCUM_LOW_OR_YL_OR_P_REGS, Y_OR_P_REGS, ACCUM_Y_OR_P_REGS,   NO_FRAME_Y_ADDR_REGS, Y_ADDR_REGS, ACCUM_LOW_OR_Y_ADDR_REGS, ACCUM_OR_Y_ADDR_REGS,   X_OR_Y_ADDR_REGS, Y_OR_Y_ADDR_REGS, P_OR_Y_ADDR_REGS, NON_HIGH_YBASE_ELIGIBLE_REGS,   YBASE_ELIGIBLE_REGS, J_REG, J_OR_DAU_16_BIT_REGS, BMU_REGS,   NOHIGH_NON_ADDR_REGS, NON_ADDR_REGS, SLOW_MEM_LOAD_REGS, NOHIGH_NON_YBASE_REGS,   NO_ACCUM_NON_YBASE_REGS, NON_YBASE_REGS, YBASE_VIRT_REGS, ACCUM_LOW_OR_YBASE_REGS,   ACCUM_OR_YBASE_REGS, X_OR_YBASE_REGS, Y_OR_YBASE_REGS, ACCUM_LOW_YL_PL_OR_YBASE_REGS,   P_OR_YBASE_REGS, ACCUM_Y_P_OR_YBASE_REGS, Y_ADDR_OR_YBASE_REGS, YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS,   YBASE_OR_YBASE_ELIGIBLE_REGS, NO_HIGH_ALL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, MULTIPLY_32_REG, MULTIPLY_64_REG, LOW_REGS,   HIGH_REGS, REAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, ADDR_REGS, DATA_REGS,   FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   AREG, DREG, CREG, BREG,   SIREG, DIREG, AD_REGS, Q_REGS,   NON_Q_REGS, INDEX_REGS, LEGACY_REGS, GENERAL_REGS,   FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, SSE_REGS,   MMX_REGS, FP_TOP_SSE_REGS, FP_SECOND_SSE_REGS, FLOAT_SSE_REGS,   FLOAT_INT_REGS, INT_SSE_REGS, FLOAT_INT_SSE_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, FP_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GLOBAL_REGS,   LOCAL_REGS, LOCAL_OR_GLOBAL_REGS, FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, PR_REGS, BR_REGS,   AR_M_REGS, AR_I_REGS, ADDL_REGS, GR_REGS,   FR_REGS, GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, CARRY_REG, ACCUM_REGS,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   D_REGS, X_REGS, Y_REGS, SP_REGS,   DA_REGS, DB_REGS, Z_REGS, D8_REGS,   Q_REGS, D_OR_X_REGS, D_OR_Y_REGS, D_OR_SP_REGS,   X_OR_Y_REGS, A_REGS, X_OR_SP_REGS, Y_OR_SP_REGS,   X_OR_Y_OR_D_REGS, A_OR_D_REGS, A_OR_SP_REGS, H_REGS,   S_REGS, D_OR_S_REGS, X_OR_S_REGS, Y_OR_S_REGS,   SP_OR_S_REGS, D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS,   A_OR_S_REGS, D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS,   G_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   DATA_REGS, ADDR_REGS, FP_REGS, GENERAL_REGS,   DATA_OR_FP_REGS, ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS,   AGRF_REGS, XGRF_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, ONLYR1_REGS, LRW_REGS, GENERAL_REGS,   C_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, REMAINDER_REG, HIMULT_REG, SYSTEM_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,   ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,   DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, EXTENDED_REGS, DATA_OR_EXTENDED_REGS,   ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,   FLOAT_REG0, LONG_FLOAT_REG0, FLOAT_REGS, FP_REGS,   GEN_AND_FP_REGS, FRAME_POINTER_REG, STACK_POINTER_REG, GEN_AND_MEM_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,   GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,   SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,   GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS,   NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, OUT_REGS, STD_REGS, ARG_REGS,   SRC_REGS, DST_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R0_REGS, R15_REGS, BASE_REGS,   GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, BASE_REGS, GENERAL_REGS, FLOAT_REGS,   ALTIVEC_REGS, VRSAVE_REGS, NON_SPECIAL_REGS, MQ_REGS,   LINK_REGS, CTR_REGS, LINK_OR_CTR_REGS, SPECIAL_REGS,   SPEC_OR_GEN_REGS, CR0_REGS, CR_REGS, NON_FLOAT_REGS,   XER_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ADDR_REGS, GENERAL_REGS, FP_REGS, ADDR_FP_REGS,   GENERAL_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REGS, PR_REGS, T_REGS, MAC_REGS,   FPUL_REGS, SIBCALL_REGS, GENERAL_REGS, FP0_REGS,   FP_REGS, DF_REGS, FPSCR_REGS, GENERAL_FP_REGS,   TARGET_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   M16_NA_REGS, M16_REGS, T_REG, M16_T_REGS,   GR_REGS, FP_REGS, HI_REG, LO_REG,   HILO_REG, MD_REGS, COP0_REGS, COP2_REGS,   COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS,   HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,   ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, FPCC_REGS, I64_REGS,   GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, GENERAL_OR_FP_REGS,   GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REGS, R1_REGS, TWO_REGS, R2_REGS,   EIGHT_REGS, R8_REGS, ICALL_REGS, GENERAL_REGS,   CARRY_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, BR_REGS,   FP_REGS, ACC_REG, SP_REG, RL_REGS,   GR_REGS, AR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, M16_NA_REGS, M16_REGS, T_REG,   M16_T_REGS, GR_REGS, FP_REGS, HI_REG,   LO_REG, HILO_REG, MD_REGS, COP0_REGS,   COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,   HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,   COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,   M16_REGS, T_REG, M16_T_REGS, GR_REGS,   FP_REGS, HI_REG, LO_REG, HILO_REG,   MD_REGS, COP0_REGS, COP2_REGS, COP3_REGS,   HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS,   COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS,   ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R0_REG, R24_REG, R25_REG,   R27_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, FPA_REGS,   CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,   LO_REGS, STACK_REG, BASE_REGS, HI_REGS,   CC_REG, VFPCC_REG, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REG, POINTER_X_REGS,   POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG, BASE_POINTER_REGS,   POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS, LD_REGS,   NO_LD_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, IREGS, BREGS, LREGS,   MREGS, CIRCREGS, DAGREGS, EVEN_AREGS,   ODD_AREGS, AREGS, CCREGS, EVEN_DREGS,   ODD_DREGS, DREGS, PREGS_CLOBBERED, PREGS,   DPREGS, MOST_REGS, PROLOGUE_REGS, NON_A_CC_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0R1_REGS,   R2R3_REGS, EXT_LOW_REGS, EXT_REGS, ADDR_REGS,   INDEX_REGS, BK_REG, SP_REG, RC_REG,   COUNTER_REGS, INT_REGS, GENERAL_REGS, DP_REG,   ST_REG, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG,   MULTIPLY_64_REG, LOW_REGS, HIGH_REGS, REAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, ICC_REGS,   FCC_REGS, CC_REGS, ICR_REGS, FCR_REGS,   CR_REGS, LCR_REG, LR_REG, GR8_REGS,   GR9_REGS, GR89_REGS, FDPIC_REGS, FDPIC_FPTR_REGS,   FDPIC_CALL_REGS, SPR_REGS, QUAD_ACC_REGS, EVEN_ACC_REGS,   ACC_REGS, ACCG_REGS, QUAD_FPR_REGS, FEVEN_REGS,   FPR_REGS, QUAD_REGS, EVEN_REGS, GPR_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, COUNTER_REGS,   SOURCE_REGS, DESTINATION_REGS, GENERAL_REGS, MAC_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, AREG,   DREG, CREG, BREG, SIREG,   DIREG, AD_REGS, Q_REGS, NON_Q_REGS,   INDEX_REGS, LEGACY_REGS, GENERAL_REGS, FP_TOP_REG,   FP_SECOND_REG, FLOAT_REGS, SSE_REGS, MMX_REGS,   FP_TOP_SSE_REGS, FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS,   INT_SSE_REGS, FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, PR_REGS, BR_REGS,   AR_M_REGS, AR_I_REGS, ADDL_REGS, GR_REGS,   FR_REGS, GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, DPH_REGS, DPL_REGS,   DP_REGS, SP_REGS, IPH_REGS, IPL_REGS,   IP_REGS, DP_SP_REGS, PTR_REGS, NONPTR_REGS,   NONSP_REGS, GENERAL_REGS, ALL_REGS = GENERAL_REGS, LIM_REG_CLASSES,   NO_REGS, GR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, D_REGS,   X_REGS, Y_REGS, SP_REGS, DA_REGS,   DB_REGS, Z_REGS, D8_REGS, Q_REGS,   D_OR_X_REGS, D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS,   A_REGS, X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS,   A_OR_D_REGS, A_OR_SP_REGS, H_REGS, S_REGS,   D_OR_S_REGS, X_OR_S_REGS, Y_OR_S_REGS, Z_OR_S_REGS,   SP_OR_S_REGS, D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS,   A_OR_S_REGS, D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS,   G_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   DATA_REGS, ADDR_REGS, FP_REGS, GENERAL_REGS,   DATA_OR_FP_REGS, ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, ONLYR1_REGS, LRW_REGS, GENERAL_REGS,   C_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   M16_NA_REGS, M16_REGS, T_REG, M16_T_REGS,   PIC_FN_ADDR_REG, LEA_REGS, GR_REGS, FP_REGS,   HI_REG, LO_REG, MD_REGS, COP0_REGS,   COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,   HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,   ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, REMAINDER_REG,   HIMULT_REG, SYSTEM_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,   DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, EXTENDED_REGS, DATA_OR_EXTENDED_REGS,   ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, FP_REGS,   FP_ACC_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0,   FLOAT_REGS, LONG_REGS, FP_REGS, GEN_AND_FP_REGS,   FRAME_POINTER_REG, STACK_POINTER_REG, GEN_AND_MEM_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,   FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,   GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,   SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS,   FPU_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   BASE_REGS, GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS,   VRSAVE_REGS, VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,   NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,   LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,   CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, CC_REGS, ADDR_REGS,   GENERAL_REGS, ACCESS_REGS, ADDR_CC_REGS, GENERAL_CC_REGS,   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REGS, PR_REGS,   T_REGS, MAC_REGS, FPUL_REGS, SIBCALL_REGS,   GENERAL_REGS, FP0_REGS, FP_REGS, DF_HI_REGS,   DF_REGS, FPSCR_REGS, GENERAL_FP_REGS, TARGET_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, FPCC_REGS,   I64_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS,   GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, R0_REGS, R1_REGS, TWO_REGS,   R2_REGS, EIGHT_REGS, R8_REGS, ICALL_REGS,   GENERAL_REGS, CARRY_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   BR_REGS, FP_REGS, ACC_REG, SP_REG,   RL_REGS, GR_REGS, AR_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0_REG, R24_REG,   R25_REG, R27_REG, GENERAL_REGS, FLOAT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS,   IWMMXT_REGS, LO_REGS, STACK_REG, BASE_REGS,   HI_REGS, CC_REG, VFPCC_REG, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0_REG,   POINTER_X_REGS, POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG,   BASE_POINTER_REGS, POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS,   LD_REGS, NO_LD_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, IREGS, BREGS,   LREGS, MREGS, CIRCREGS, DAGREGS,   EVEN_AREGS, ODD_AREGS, AREGS, CCREGS,   EVEN_DREGS, ODD_DREGS, DREGS, FDPIC_REGS,   FDPIC_FPTR_REGS, PREGS_CLOBBERED, PREGS, IPREGS,   DPREGS, MOST_REGS, LT_REGS, LC_REGS,   LB_REGS, PROLOGUE_REGS, NON_A_CC_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R0R1_REGS, R2R3_REGS,   EXT_LOW_REGS, EXT_REGS, ADDR_REGS, INDEX_REGS,   BK_REG, SP_REG, RC_REG, COUNTER_REGS,   INT_REGS, GENERAL_REGS, DP_REG, ST_REG,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, MOF_REGS,   CC0_REGS, SPECIAL_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, LO_REGS, HI_REGS,   HILO_REGS, NOSP_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG, MULTIPLY_64_REG,   LOW_REGS, HIGH_REGS, REAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, ICC_REGS, FCC_REGS,   CC_REGS, ICR_REGS, FCR_REGS, CR_REGS,   LCR_REG, LR_REG, GR8_REGS, GR9_REGS,   GR89_REGS, FDPIC_REGS, FDPIC_FPTR_REGS, FDPIC_CALL_REGS,   SPR_REGS, QUAD_ACC_REGS, EVEN_ACC_REGS, ACC_REGS,   ACCG_REGS, QUAD_FPR_REGS, FEVEN_REGS, FPR_REGS,   QUAD_REGS, EVEN_REGS, GPR_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, COUNTER_REGS, SOURCE_REGS,   DESTINATION_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, AREG, DREG,   CREG, BREG, SIREG, DIREG,   AD_REGS, Q_REGS, NON_Q_REGS, INDEX_REGS,   LEGACY_REGS, GENERAL_REGS, FP_TOP_REG, FP_SECOND_REG,   FLOAT_REGS, SSE_REGS, MMX_REGS, FP_TOP_SSE_REGS,   FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS, INT_SSE_REGS,   FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS,   ADDL_REGS, GR_REGS, FP_REGS, FR_REGS,   GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, GR_REGS, ALL_REGS, LIM_REG_CLASSES,   NO_REGS, SP_REGS, FB_REGS, SB_REGS,   CR_REGS, R0_REGS, R1_REGS, R2_REGS,   R3_REGS, R02_REGS, HL_REGS, QI_REGS,   R23_REGS, R03_REGS, DI_REGS, A0_REGS,   A1_REGS, A_REGS, AD_REGS, PS_REGS,   SI_REGS, HI_REGS, RA_REGS, GENERAL_REGS,   FLG_REGS, HC_REGS, MEM_REGS, R02_A_MEM_REGS,   A_HL_MEM_REGS, R1_R3_A_MEM_REGS, R03_MEM_REGS, A_HI_MEM_REGS,   A_AD_CR_MEM_SI_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, D_REGS, X_REGS,   Y_REGS, SP_REGS, DA_REGS, DB_REGS,   Z_REGS, D8_REGS, Q_REGS, D_OR_X_REGS,   D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS, A_REGS,   X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS, A_OR_D_REGS,   A_OR_SP_REGS, H_REGS, S_REGS, D_OR_S_REGS,   X_OR_S_REGS, Y_OR_S_REGS, Z_OR_S_REGS, SP_OR_S_REGS,   D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS, A_OR_S_REGS,   D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS, G_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,   ADDR_REGS, FP_REGS, GENERAL_REGS, DATA_OR_FP_REGS,   ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ONLYR1_REGS, LRW_REGS, GENERAL_REGS, C_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,   M16_REGS, T_REG, M16_T_REGS, PIC_FN_ADDR_REG,   V1_REG, LEA_REGS, GR_REGS, FP_REGS,   HI_REG, LO_REG, MD_REGS, COP0_REGS,   COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,   HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,   ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, DSP_ACC_REGS,   ACC_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, REMAINDER_REG, HIMULT_REG, SYSTEM_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,   ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,   EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS,   SP_OR_ADDRESS_OR_EXTENDED_REGS, FP_REGS, FP_ACC_REGS, GENERAL_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,   FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,   GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,   SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS,   FPU_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   BASE_REGS, GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS,   VRSAVE_REGS, VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,   NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,   LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,   CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, CC_REGS, ADDR_REGS,   GENERAL_REGS, ACCESS_REGS, ADDR_CC_REGS, GENERAL_CC_REGS,   FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, G16_REGS, G32_REGS,   T32_REGS, HI_REG, LO_REG, CE_REGS,   CN_REG, LC_REG, SC_REG, SP_REGS,   CR_REGS, CP1_REGS, CP2_REGS, CP3_REGS,   CPA_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REGS, PR_REGS, T_REGS, MAC_REGS,   FPUL_REGS, SIBCALL_REGS, GENERAL_REGS, FP0_REGS,   FP_REGS, DF_HI_REGS, DF_REGS, FPSCR_REGS,   GENERAL_FP_REGS, GENERAL_DF_REGS, TARGET_REGS, ALL_REGS,   LIM_REG_CLASSES, NO_REGS, FPCC_REGS, I64_REGS,   GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, GENERAL_OR_FP_REGS,   GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   R0_REGS, R1_REGS, TWO_REGS, R2_REGS,   EIGHT_REGS, R8_REGS, ICALL_REGS, GENERAL_REGS,   CARRY_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,   ALL_REGS, LIM_REG_CLASSES, NO_REGS, BR_REGS,   FP_REGS, ACC_REG, SP_REG, RL_REGS,   GR_REGS, AR_REGS, ALL_REGS, LIM_REG_CLASSES }
enum	rs6000_abi {   ABI_NONE, ABI_AIX, ABI_AIX_NODESC, ABI_V4,   ABI_DARWIN, ABI_NONE, ABI_AIX, ABI_AIX_NODESC,   ABI_V4, ABI_DARWIN, ABI_NONE, ABI_AIX,   ABI_V4, ABI_DARWIN, ABI_NONE, ABI_AIX,   ABI_V4, ABI_DARWIN }
enum	rs6000_builtins {   ALTIVEC_BUILTIN_ST_INTERNAL_4si, ALTIVEC_BUILTIN_LD_INTERNAL_4si, ALTIVEC_BUILTIN_ST_INTERNAL_8hi, ALTIVEC_BUILTIN_LD_INTERNAL_8hi,   ALTIVEC_BUILTIN_ST_INTERNAL_16qi, ALTIVEC_BUILTIN_LD_INTERNAL_16qi, ALTIVEC_BUILTIN_ST_INTERNAL_4sf, ALTIVEC_BUILTIN_LD_INTERNAL_4sf,   ALTIVEC_BUILTIN_VADDUBM, ALTIVEC_BUILTIN_VADDUHM, ALTIVEC_BUILTIN_VADDUWM, ALTIVEC_BUILTIN_VADDFP,   ALTIVEC_BUILTIN_VADDCUW, ALTIVEC_BUILTIN_VADDUBS, ALTIVEC_BUILTIN_VADDSBS, ALTIVEC_BUILTIN_VADDUHS,   ALTIVEC_BUILTIN_VADDSHS, ALTIVEC_BUILTIN_VADDUWS, ALTIVEC_BUILTIN_VADDSWS, ALTIVEC_BUILTIN_VAND,   ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VAVGUB, ALTIVEC_BUILTIN_VAVGSB, ALTIVEC_BUILTIN_VAVGUH,   ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW, ALTIVEC_BUILTIN_VAVGSW, ALTIVEC_BUILTIN_VCFUX,   ALTIVEC_BUILTIN_VCFSX, ALTIVEC_BUILTIN_VCTSXS, ALTIVEC_BUILTIN_VCTUXS, ALTIVEC_BUILTIN_VCMPBFP,   ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQFP,   ALTIVEC_BUILTIN_VCMPGEFP, ALTIVEC_BUILTIN_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTUH,   ALTIVEC_BUILTIN_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTFP,   ALTIVEC_BUILTIN_VEXPTEFP, ALTIVEC_BUILTIN_VLOGEFP, ALTIVEC_BUILTIN_VMADDFP, ALTIVEC_BUILTIN_VMAXUB,   ALTIVEC_BUILTIN_VMAXSB, ALTIVEC_BUILTIN_VMAXUH, ALTIVEC_BUILTIN_VMAXSH, ALTIVEC_BUILTIN_VMAXUW,   ALTIVEC_BUILTIN_VMAXSW, ALTIVEC_BUILTIN_VMAXFP, ALTIVEC_BUILTIN_VMHADDSHS, ALTIVEC_BUILTIN_VMHRADDSHS,   ALTIVEC_BUILTIN_VMLADDUHM, ALTIVEC_BUILTIN_VMRGHB, ALTIVEC_BUILTIN_VMRGHH, ALTIVEC_BUILTIN_VMRGHW,   ALTIVEC_BUILTIN_VMRGLB, ALTIVEC_BUILTIN_VMRGLH, ALTIVEC_BUILTIN_VMRGLW, ALTIVEC_BUILTIN_VMSUMUBM,   ALTIVEC_BUILTIN_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMUHS,   ALTIVEC_BUILTIN_VMSUMSHS, ALTIVEC_BUILTIN_VMINUB, ALTIVEC_BUILTIN_VMINSB, ALTIVEC_BUILTIN_VMINUH,   ALTIVEC_BUILTIN_VMINSH, ALTIVEC_BUILTIN_VMINUW, ALTIVEC_BUILTIN_VMINSW, ALTIVEC_BUILTIN_VMINFP,   ALTIVEC_BUILTIN_VMULEUB, ALTIVEC_BUILTIN_VMULESB, ALTIVEC_BUILTIN_VMULEUH, ALTIVEC_BUILTIN_VMULESH,   ALTIVEC_BUILTIN_VMULOUB, ALTIVEC_BUILTIN_VMULOSB, ALTIVEC_BUILTIN_VMULOUH, ALTIVEC_BUILTIN_VMULOSH,   ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR, ALTIVEC_BUILTIN_VOR, ALTIVEC_BUILTIN_VSEL_4SI,   ALTIVEC_BUILTIN_VSEL_4SF, ALTIVEC_BUILTIN_VSEL_8HI, ALTIVEC_BUILTIN_VSEL_16QI, ALTIVEC_BUILTIN_VPERM_4SI,   ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI, ALTIVEC_BUILTIN_VPERM_16QI, ALTIVEC_BUILTIN_VPKUHUM,   ALTIVEC_BUILTIN_VPKUWUM, ALTIVEC_BUILTIN_VPKPX, ALTIVEC_BUILTIN_VPKUHSS, ALTIVEC_BUILTIN_VPKSHSS,   ALTIVEC_BUILTIN_VPKUWSS, ALTIVEC_BUILTIN_VPKSWSS, ALTIVEC_BUILTIN_VPKUHUS, ALTIVEC_BUILTIN_VPKSHUS,   ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS, ALTIVEC_BUILTIN_VREFP, ALTIVEC_BUILTIN_VRFIM,   ALTIVEC_BUILTIN_VRFIN, ALTIVEC_BUILTIN_VRFIP, ALTIVEC_BUILTIN_VRFIZ, ALTIVEC_BUILTIN_VRLB,   ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW, ALTIVEC_BUILTIN_VRSQRTEFP, ALTIVEC_BUILTIN_VSLB,   ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW, ALTIVEC_BUILTIN_VSL, ALTIVEC_BUILTIN_VSLO,   ALTIVEC_BUILTIN_VSPLTB, ALTIVEC_BUILTIN_VSPLTH, ALTIVEC_BUILTIN_VSPLTW, ALTIVEC_BUILTIN_VSPLTISB,   ALTIVEC_BUILTIN_VSPLTISH, ALTIVEC_BUILTIN_VSPLTISW, ALTIVEC_BUILTIN_VSRB, ALTIVEC_BUILTIN_VSRH,   ALTIVEC_BUILTIN_VSRW, ALTIVEC_BUILTIN_VSRAB, ALTIVEC_BUILTIN_VSRAH, ALTIVEC_BUILTIN_VSRAW,   ALTIVEC_BUILTIN_VSR, ALTIVEC_BUILTIN_VSRO, ALTIVEC_BUILTIN_VSUBUBM, ALTIVEC_BUILTIN_VSUBUHM,   ALTIVEC_BUILTIN_VSUBUWM, ALTIVEC_BUILTIN_VSUBFP, ALTIVEC_BUILTIN_VSUBCUW, ALTIVEC_BUILTIN_VSUBUBS,   ALTIVEC_BUILTIN_VSUBSBS, ALTIVEC_BUILTIN_VSUBUHS, ALTIVEC_BUILTIN_VSUBSHS, ALTIVEC_BUILTIN_VSUBUWS,   ALTIVEC_BUILTIN_VSUBSWS, ALTIVEC_BUILTIN_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SHS,   ALTIVEC_BUILTIN_VSUM2SWS, ALTIVEC_BUILTIN_VSUMSWS, ALTIVEC_BUILTIN_VXOR, ALTIVEC_BUILTIN_VSLDOI_16QI,   ALTIVEC_BUILTIN_VSLDOI_8HI, ALTIVEC_BUILTIN_VSLDOI_4SI, ALTIVEC_BUILTIN_VSLDOI_4SF, ALTIVEC_BUILTIN_VUPKHSB,   ALTIVEC_BUILTIN_VUPKHPX, ALTIVEC_BUILTIN_VUPKHSH, ALTIVEC_BUILTIN_VUPKLSB, ALTIVEC_BUILTIN_VUPKLPX,   ALTIVEC_BUILTIN_VUPKLSH, ALTIVEC_BUILTIN_MTVSCR, ALTIVEC_BUILTIN_MFVSCR, ALTIVEC_BUILTIN_DSSALL,   ALTIVEC_BUILTIN_DSS, ALTIVEC_BUILTIN_LVSL, ALTIVEC_BUILTIN_LVSR, ALTIVEC_BUILTIN_DSTT,   ALTIVEC_BUILTIN_DSTST, ALTIVEC_BUILTIN_DSTSTT, ALTIVEC_BUILTIN_DST, ALTIVEC_BUILTIN_LVEBX,   ALTIVEC_BUILTIN_LVEHX, ALTIVEC_BUILTIN_LVEWX, ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_LVX,   ALTIVEC_BUILTIN_STVX, ALTIVEC_BUILTIN_STVEBX, ALTIVEC_BUILTIN_STVEHX, ALTIVEC_BUILTIN_STVEWX,   ALTIVEC_BUILTIN_STVXL, ALTIVEC_BUILTIN_VCMPBFP_P, ALTIVEC_BUILTIN_VCMPEQFP_P, ALTIVEC_BUILTIN_VCMPEQUB_P,   ALTIVEC_BUILTIN_VCMPEQUH_P, ALTIVEC_BUILTIN_VCMPEQUW_P, ALTIVEC_BUILTIN_VCMPGEFP_P, ALTIVEC_BUILTIN_VCMPGTFP_P,   ALTIVEC_BUILTIN_VCMPGTSB_P, ALTIVEC_BUILTIN_VCMPGTSH_P, ALTIVEC_BUILTIN_VCMPGTSW_P, ALTIVEC_BUILTIN_VCMPGTUB_P,   ALTIVEC_BUILTIN_VCMPGTUH_P, ALTIVEC_BUILTIN_VCMPGTUW_P, ALTIVEC_BUILTIN_ABSS_V4SI, ALTIVEC_BUILTIN_ABSS_V8HI,   ALTIVEC_BUILTIN_ABSS_V16QI, ALTIVEC_BUILTIN_ABS_V4SI, ALTIVEC_BUILTIN_ABS_V4SF, ALTIVEC_BUILTIN_ABS_V8HI,   ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_ST_INTERNAL_4si, ALTIVEC_BUILTIN_LD_INTERNAL_4si, ALTIVEC_BUILTIN_ST_INTERNAL_8hi,   ALTIVEC_BUILTIN_LD_INTERNAL_8hi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi, ALTIVEC_BUILTIN_LD_INTERNAL_16qi, ALTIVEC_BUILTIN_ST_INTERNAL_4sf,   ALTIVEC_BUILTIN_LD_INTERNAL_4sf, ALTIVEC_BUILTIN_VADDUBM, ALTIVEC_BUILTIN_VADDUHM, ALTIVEC_BUILTIN_VADDUWM,   ALTIVEC_BUILTIN_VADDFP, ALTIVEC_BUILTIN_VADDCUW, ALTIVEC_BUILTIN_VADDUBS, ALTIVEC_BUILTIN_VADDSBS,   ALTIVEC_BUILTIN_VADDUHS, ALTIVEC_BUILTIN_VADDSHS, ALTIVEC_BUILTIN_VADDUWS, ALTIVEC_BUILTIN_VADDSWS,   ALTIVEC_BUILTIN_VAND, ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VAVGUB, ALTIVEC_BUILTIN_VAVGSB,   ALTIVEC_BUILTIN_VAVGUH, ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW, ALTIVEC_BUILTIN_VAVGSW,   ALTIVEC_BUILTIN_VCFUX, ALTIVEC_BUILTIN_VCFSX, ALTIVEC_BUILTIN_VCTSXS, ALTIVEC_BUILTIN_VCTUXS,   ALTIVEC_BUILTIN_VCMPBFP, ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUW,   ALTIVEC_BUILTIN_VCMPEQFP, ALTIVEC_BUILTIN_VCMPGEFP, ALTIVEC_BUILTIN_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTSB,   ALTIVEC_BUILTIN_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTSW,   ALTIVEC_BUILTIN_VCMPGTFP, ALTIVEC_BUILTIN_VEXPTEFP, ALTIVEC_BUILTIN_VLOGEFP, ALTIVEC_BUILTIN_VMADDFP,   ALTIVEC_BUILTIN_VMAXUB, ALTIVEC_BUILTIN_VMAXSB, ALTIVEC_BUILTIN_VMAXUH, ALTIVEC_BUILTIN_VMAXSH,   ALTIVEC_BUILTIN_VMAXUW, ALTIVEC_BUILTIN_VMAXSW, ALTIVEC_BUILTIN_VMAXFP, ALTIVEC_BUILTIN_VMHADDSHS,   ALTIVEC_BUILTIN_VMHRADDSHS, ALTIVEC_BUILTIN_VMLADDUHM, ALTIVEC_BUILTIN_VMRGHB, ALTIVEC_BUILTIN_VMRGHH,   ALTIVEC_BUILTIN_VMRGHW, ALTIVEC_BUILTIN_VMRGLB, ALTIVEC_BUILTIN_VMRGLH, ALTIVEC_BUILTIN_VMRGLW,   ALTIVEC_BUILTIN_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMSHM,   ALTIVEC_BUILTIN_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMSHS, ALTIVEC_BUILTIN_VMINUB, ALTIVEC_BUILTIN_VMINSB,   ALTIVEC_BUILTIN_VMINUH, ALTIVEC_BUILTIN_VMINSH, ALTIVEC_BUILTIN_VMINUW, ALTIVEC_BUILTIN_VMINSW,   ALTIVEC_BUILTIN_VMINFP, ALTIVEC_BUILTIN_VMULEUB, ALTIVEC_BUILTIN_VMULESB, ALTIVEC_BUILTIN_VMULEUH,   ALTIVEC_BUILTIN_VMULESH, ALTIVEC_BUILTIN_VMULOUB, ALTIVEC_BUILTIN_VMULOSB, ALTIVEC_BUILTIN_VMULOUH,   ALTIVEC_BUILTIN_VMULOSH, ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR, ALTIVEC_BUILTIN_VOR,   ALTIVEC_BUILTIN_VSEL_4SI, ALTIVEC_BUILTIN_VSEL_4SF, ALTIVEC_BUILTIN_VSEL_8HI, ALTIVEC_BUILTIN_VSEL_16QI,   ALTIVEC_BUILTIN_VPERM_4SI, ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI, ALTIVEC_BUILTIN_VPERM_16QI,   ALTIVEC_BUILTIN_VPKUHUM, ALTIVEC_BUILTIN_VPKUWUM, ALTIVEC_BUILTIN_VPKPX, ALTIVEC_BUILTIN_VPKUHSS,   ALTIVEC_BUILTIN_VPKSHSS, ALTIVEC_BUILTIN_VPKUWSS, ALTIVEC_BUILTIN_VPKSWSS, ALTIVEC_BUILTIN_VPKUHUS,   ALTIVEC_BUILTIN_VPKSHUS, ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS, ALTIVEC_BUILTIN_VREFP,   ALTIVEC_BUILTIN_VRFIM, ALTIVEC_BUILTIN_VRFIN, ALTIVEC_BUILTIN_VRFIP, ALTIVEC_BUILTIN_VRFIZ,   ALTIVEC_BUILTIN_VRLB, ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW, ALTIVEC_BUILTIN_VRSQRTEFP,   ALTIVEC_BUILTIN_VSLB, ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW, ALTIVEC_BUILTIN_VSL,   ALTIVEC_BUILTIN_VSLO, ALTIVEC_BUILTIN_VSPLTB, ALTIVEC_BUILTIN_VSPLTH, ALTIVEC_BUILTIN_VSPLTW,   ALTIVEC_BUILTIN_VSPLTISB, ALTIVEC_BUILTIN_VSPLTISH, ALTIVEC_BUILTIN_VSPLTISW, ALTIVEC_BUILTIN_VSRB,   ALTIVEC_BUILTIN_VSRH, ALTIVEC_BUILTIN_VSRW, ALTIVEC_BUILTIN_VSRAB, ALTIVEC_BUILTIN_VSRAH,   ALTIVEC_BUILTIN_VSRAW, ALTIVEC_BUILTIN_VSR, ALTIVEC_BUILTIN_VSRO, ALTIVEC_BUILTIN_VSUBUBM,   ALTIVEC_BUILTIN_VSUBUHM, ALTIVEC_BUILTIN_VSUBUWM, ALTIVEC_BUILTIN_VSUBFP, ALTIVEC_BUILTIN_VSUBCUW,   ALTIVEC_BUILTIN_VSUBUBS, ALTIVEC_BUILTIN_VSUBSBS, ALTIVEC_BUILTIN_VSUBUHS, ALTIVEC_BUILTIN_VSUBSHS,   ALTIVEC_BUILTIN_VSUBUWS, ALTIVEC_BUILTIN_VSUBSWS, ALTIVEC_BUILTIN_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4SBS,   ALTIVEC_BUILTIN_VSUM4SHS, ALTIVEC_BUILTIN_VSUM2SWS, ALTIVEC_BUILTIN_VSUMSWS, ALTIVEC_BUILTIN_VXOR,   ALTIVEC_BUILTIN_VSLDOI_16QI, ALTIVEC_BUILTIN_VSLDOI_8HI, ALTIVEC_BUILTIN_VSLDOI_4SI, ALTIVEC_BUILTIN_VSLDOI_4SF,   ALTIVEC_BUILTIN_VUPKHSB, ALTIVEC_BUILTIN_VUPKHPX, ALTIVEC_BUILTIN_VUPKHSH, ALTIVEC_BUILTIN_VUPKLSB,   ALTIVEC_BUILTIN_VUPKLPX, ALTIVEC_BUILTIN_VUPKLSH, ALTIVEC_BUILTIN_MTVSCR, ALTIVEC_BUILTIN_MFVSCR,   ALTIVEC_BUILTIN_DSSALL, ALTIVEC_BUILTIN_DSS, ALTIVEC_BUILTIN_LVSL, ALTIVEC_BUILTIN_LVSR,   ALTIVEC_BUILTIN_DSTT, ALTIVEC_BUILTIN_DSTST, ALTIVEC_BUILTIN_DSTSTT, ALTIVEC_BUILTIN_DST,   ALTIVEC_BUILTIN_LVEBX, ALTIVEC_BUILTIN_LVEHX, ALTIVEC_BUILTIN_LVEWX, ALTIVEC_BUILTIN_LVXL,   ALTIVEC_BUILTIN_LVX, ALTIVEC_BUILTIN_STVX, ALTIVEC_BUILTIN_STVEBX, ALTIVEC_BUILTIN_STVEHX,   ALTIVEC_BUILTIN_STVEWX, ALTIVEC_BUILTIN_STVXL, ALTIVEC_BUILTIN_VCMPBFP_P, ALTIVEC_BUILTIN_VCMPEQFP_P,   ALTIVEC_BUILTIN_VCMPEQUB_P, ALTIVEC_BUILTIN_VCMPEQUH_P, ALTIVEC_BUILTIN_VCMPEQUW_P, ALTIVEC_BUILTIN_VCMPGEFP_P,   ALTIVEC_BUILTIN_VCMPGTFP_P, ALTIVEC_BUILTIN_VCMPGTSB_P, ALTIVEC_BUILTIN_VCMPGTSH_P, ALTIVEC_BUILTIN_VCMPGTSW_P,   ALTIVEC_BUILTIN_VCMPGTUB_P, ALTIVEC_BUILTIN_VCMPGTUH_P, ALTIVEC_BUILTIN_VCMPGTUW_P, ALTIVEC_BUILTIN_ABSS_V4SI,   ALTIVEC_BUILTIN_ABSS_V8HI, ALTIVEC_BUILTIN_ABSS_V16QI, ALTIVEC_BUILTIN_ABS_V4SI, ALTIVEC_BUILTIN_ABS_V4SF,   ALTIVEC_BUILTIN_ABS_V8HI, ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_ST_INTERNAL_4si, ALTIVEC_BUILTIN_LD_INTERNAL_4si,   ALTIVEC_BUILTIN_ST_INTERNAL_8hi, ALTIVEC_BUILTIN_LD_INTERNAL_8hi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi, ALTIVEC_BUILTIN_LD_INTERNAL_16qi,   ALTIVEC_BUILTIN_ST_INTERNAL_4sf, ALTIVEC_BUILTIN_LD_INTERNAL_4sf, ALTIVEC_BUILTIN_VADDUBM, ALTIVEC_BUILTIN_VADDUHM,   ALTIVEC_BUILTIN_VADDUWM, ALTIVEC_BUILTIN_VADDFP, ALTIVEC_BUILTIN_VADDCUW, ALTIVEC_BUILTIN_VADDUBS,   ALTIVEC_BUILTIN_VADDSBS, ALTIVEC_BUILTIN_VADDUHS, ALTIVEC_BUILTIN_VADDSHS, ALTIVEC_BUILTIN_VADDUWS,   ALTIVEC_BUILTIN_VADDSWS, ALTIVEC_BUILTIN_VAND, ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VAVGUB,   ALTIVEC_BUILTIN_VAVGSB, ALTIVEC_BUILTIN_VAVGUH, ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW,   ALTIVEC_BUILTIN_VAVGSW, ALTIVEC_BUILTIN_VCFUX, ALTIVEC_BUILTIN_VCFSX, ALTIVEC_BUILTIN_VCTSXS,   ALTIVEC_BUILTIN_VCTUXS, ALTIVEC_BUILTIN_VCMPBFP, ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH,   ALTIVEC_BUILTIN_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQFP, ALTIVEC_BUILTIN_VCMPGEFP, ALTIVEC_BUILTIN_VCMPGTUB,   ALTIVEC_BUILTIN_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTUW,   ALTIVEC_BUILTIN_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTFP, ALTIVEC_BUILTIN_VEXPTEFP, ALTIVEC_BUILTIN_VLOGEFP,   ALTIVEC_BUILTIN_VMADDFP, ALTIVEC_BUILTIN_VMAXUB, ALTIVEC_BUILTIN_VMAXSB, ALTIVEC_BUILTIN_VMAXUH,   ALTIVEC_BUILTIN_VMAXSH, ALTIVEC_BUILTIN_VMAXUW, ALTIVEC_BUILTIN_VMAXSW, ALTIVEC_BUILTIN_VMAXFP,   ALTIVEC_BUILTIN_VMHADDSHS, ALTIVEC_BUILTIN_VMHRADDSHS, ALTIVEC_BUILTIN_VMLADDUHM, ALTIVEC_BUILTIN_VMRGHB,   ALTIVEC_BUILTIN_VMRGHH, ALTIVEC_BUILTIN_VMRGHW, ALTIVEC_BUILTIN_VMRGLB, ALTIVEC_BUILTIN_VMRGLH,   ALTIVEC_BUILTIN_VMRGLW, ALTIVEC_BUILTIN_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMUHM,   ALTIVEC_BUILTIN_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMSHS, ALTIVEC_BUILTIN_VMINUB,   ALTIVEC_BUILTIN_VMINSB, ALTIVEC_BUILTIN_VMINUH, ALTIVEC_BUILTIN_VMINSH, ALTIVEC_BUILTIN_VMINUW,   ALTIVEC_BUILTIN_VMINSW, ALTIVEC_BUILTIN_VMINFP, ALTIVEC_BUILTIN_VMULEUB, ALTIVEC_BUILTIN_VMULESB,   ALTIVEC_BUILTIN_VMULEUH, ALTIVEC_BUILTIN_VMULESH, ALTIVEC_BUILTIN_VMULOUB, ALTIVEC_BUILTIN_VMULOSB,   ALTIVEC_BUILTIN_VMULOUH, ALTIVEC_BUILTIN_VMULOSH, ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR,   ALTIVEC_BUILTIN_VOR, ALTIVEC_BUILTIN_VSEL_4SI, ALTIVEC_BUILTIN_VSEL_4SF, ALTIVEC_BUILTIN_VSEL_8HI,   ALTIVEC_BUILTIN_VSEL_16QI, ALTIVEC_BUILTIN_VPERM_4SI, ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI,   ALTIVEC_BUILTIN_VPERM_16QI, ALTIVEC_BUILTIN_VPKUHUM, ALTIVEC_BUILTIN_VPKUWUM, ALTIVEC_BUILTIN_VPKPX,   ALTIVEC_BUILTIN_VPKUHSS, ALTIVEC_BUILTIN_VPKSHSS, ALTIVEC_BUILTIN_VPKUWSS, ALTIVEC_BUILTIN_VPKSWSS,   ALTIVEC_BUILTIN_VPKUHUS, ALTIVEC_BUILTIN_VPKSHUS, ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS,   ALTIVEC_BUILTIN_VREFP, ALTIVEC_BUILTIN_VRFIM, ALTIVEC_BUILTIN_VRFIN, ALTIVEC_BUILTIN_VRFIP,   ALTIVEC_BUILTIN_VRFIZ, ALTIVEC_BUILTIN_VRLB, ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW,   ALTIVEC_BUILTIN_VRSQRTEFP, ALTIVEC_BUILTIN_VSLB, ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW,   ALTIVEC_BUILTIN_VSL, ALTIVEC_BUILTIN_VSLO, ALTIVEC_BUILTIN_VSPLTB, ALTIVEC_BUILTIN_VSPLTH,   ALTIVEC_BUILTIN_VSPLTW, ALTIVEC_BUILTIN_VSPLTISB, ALTIVEC_BUILTIN_VSPLTISH, ALTIVEC_BUILTIN_VSPLTISW,   ALTIVEC_BUILTIN_VSRB, ALTIVEC_BUILTIN_VSRH, ALTIVEC_BUILTIN_VSRW, ALTIVEC_BUILTIN_VSRAB,   ALTIVEC_BUILTIN_VSRAH, ALTIVEC_BUILTIN_VSRAW, ALTIVEC_BUILTIN_VSR, ALTIVEC_BUILTIN_VSRO,   ALTIVEC_BUILTIN_VSUBUBM, ALTIVEC_BUILTIN_VSUBUHM, ALTIVEC_BUILTIN_VSUBUWM, ALTIVEC_BUILTIN_VSUBFP,   ALTIVEC_BUILTIN_VSUBCUW, ALTIVEC_BUILTIN_VSUBUBS, ALTIVEC_BUILTIN_VSUBSBS, ALTIVEC_BUILTIN_VSUBUHS,   ALTIVEC_BUILTIN_VSUBSHS, ALTIVEC_BUILTIN_VSUBUWS, ALTIVEC_BUILTIN_VSUBSWS, ALTIVEC_BUILTIN_VSUM4UBS,   ALTIVEC_BUILTIN_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SHS, ALTIVEC_BUILTIN_VSUM2SWS, ALTIVEC_BUILTIN_VSUMSWS,   ALTIVEC_BUILTIN_VXOR, ALTIVEC_BUILTIN_VSLDOI_16QI, ALTIVEC_BUILTIN_VSLDOI_8HI, ALTIVEC_BUILTIN_VSLDOI_4SI,   ALTIVEC_BUILTIN_VSLDOI_4SF, ALTIVEC_BUILTIN_VUPKHSB, ALTIVEC_BUILTIN_VUPKHPX, ALTIVEC_BUILTIN_VUPKHSH,   ALTIVEC_BUILTIN_VUPKLSB, ALTIVEC_BUILTIN_VUPKLPX, ALTIVEC_BUILTIN_VUPKLSH, ALTIVEC_BUILTIN_MTVSCR,   ALTIVEC_BUILTIN_MFVSCR, ALTIVEC_BUILTIN_DSSALL, ALTIVEC_BUILTIN_DSS, ALTIVEC_BUILTIN_LVSL,   ALTIVEC_BUILTIN_LVSR, ALTIVEC_BUILTIN_DSTT, ALTIVEC_BUILTIN_DSTST, ALTIVEC_BUILTIN_DSTSTT,   ALTIVEC_BUILTIN_DST, ALTIVEC_BUILTIN_LVEBX, ALTIVEC_BUILTIN_LVEHX, ALTIVEC_BUILTIN_LVEWX,   ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_LVX, ALTIVEC_BUILTIN_STVX, ALTIVEC_BUILTIN_STVEBX,   ALTIVEC_BUILTIN_STVEHX, ALTIVEC_BUILTIN_STVEWX, ALTIVEC_BUILTIN_STVXL, ALTIVEC_BUILTIN_VCMPBFP_P,   ALTIVEC_BUILTIN_VCMPEQFP_P, ALTIVEC_BUILTIN_VCMPEQUB_P, ALTIVEC_BUILTIN_VCMPEQUH_P, ALTIVEC_BUILTIN_VCMPEQUW_P,   ALTIVEC_BUILTIN_VCMPGEFP_P, ALTIVEC_BUILTIN_VCMPGTFP_P, ALTIVEC_BUILTIN_VCMPGTSB_P, ALTIVEC_BUILTIN_VCMPGTSH_P,   ALTIVEC_BUILTIN_VCMPGTSW_P, ALTIVEC_BUILTIN_VCMPGTUB_P, ALTIVEC_BUILTIN_VCMPGTUH_P, ALTIVEC_BUILTIN_VCMPGTUW_P,   ALTIVEC_BUILTIN_ABSS_V4SI, ALTIVEC_BUILTIN_ABSS_V8HI, ALTIVEC_BUILTIN_ABSS_V16QI, ALTIVEC_BUILTIN_ABS_V4SI,   ALTIVEC_BUILTIN_ABS_V4SF, ALTIVEC_BUILTIN_ABS_V8HI, ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_COMPILETIME_ERROR,   ALTIVEC_BUILTIN_MASK_FOR_LOAD, ALTIVEC_BUILTIN_MASK_FOR_STORE, SPE_BUILTIN_EVADDW, SPE_BUILTIN_EVAND,   SPE_BUILTIN_EVANDC, SPE_BUILTIN_EVDIVWS, SPE_BUILTIN_EVDIVWU, SPE_BUILTIN_EVEQV,   SPE_BUILTIN_EVFSADD, SPE_BUILTIN_EVFSDIV, SPE_BUILTIN_EVFSMUL, SPE_BUILTIN_EVFSSUB,   SPE_BUILTIN_EVLDDX, SPE_BUILTIN_EVLDHX, SPE_BUILTIN_EVLDWX, SPE_BUILTIN_EVLHHESPLATX,   SPE_BUILTIN_EVLHHOSSPLATX, SPE_BUILTIN_EVLHHOUSPLATX, SPE_BUILTIN_EVLWHEX, SPE_BUILTIN_EVLWHOSX,   SPE_BUILTIN_EVLWHOUX, SPE_BUILTIN_EVLWHSPLATX, SPE_BUILTIN_EVLWWSPLATX, SPE_BUILTIN_EVMERGEHI,   SPE_BUILTIN_EVMERGEHILO, SPE_BUILTIN_EVMERGELO, SPE_BUILTIN_EVMERGELOHI, SPE_BUILTIN_EVMHEGSMFAA,   SPE_BUILTIN_EVMHEGSMFAN, SPE_BUILTIN_EVMHEGSMIAA, SPE_BUILTIN_EVMHEGSMIAN, SPE_BUILTIN_EVMHEGUMIAA,   SPE_BUILTIN_EVMHEGUMIAN, SPE_BUILTIN_EVMHESMF, SPE_BUILTIN_EVMHESMFA, SPE_BUILTIN_EVMHESMFAAW,   SPE_BUILTIN_EVMHESMFANW, SPE_BUILTIN_EVMHESMI, SPE_BUILTIN_EVMHESMIA, SPE_BUILTIN_EVMHESMIAAW,   SPE_BUILTIN_EVMHESMIANW, SPE_BUILTIN_EVMHESSF, SPE_BUILTIN_EVMHESSFA, SPE_BUILTIN_EVMHESSFAAW,   SPE_BUILTIN_EVMHESSFANW, SPE_BUILTIN_EVMHESSIAAW, SPE_BUILTIN_EVMHESSIANW, SPE_BUILTIN_EVMHEUMI,   SPE_BUILTIN_EVMHEUMIA, SPE_BUILTIN_EVMHEUMIAAW, SPE_BUILTIN_EVMHEUMIANW, SPE_BUILTIN_EVMHEUSIAAW,   SPE_BUILTIN_EVMHEUSIANW, SPE_BUILTIN_EVMHOGSMFAA, SPE_BUILTIN_EVMHOGSMFAN, SPE_BUILTIN_EVMHOGSMIAA,   SPE_BUILTIN_EVMHOGSMIAN, SPE_BUILTIN_EVMHOGUMIAA, SPE_BUILTIN_EVMHOGUMIAN, SPE_BUILTIN_EVMHOSMF,   SPE_BUILTIN_EVMHOSMFA, SPE_BUILTIN_EVMHOSMFAAW, SPE_BUILTIN_EVMHOSMFANW, SPE_BUILTIN_EVMHOSMI,   SPE_BUILTIN_EVMHOSMIA, SPE_BUILTIN_EVMHOSMIAAW, SPE_BUILTIN_EVMHOSMIANW, SPE_BUILTIN_EVMHOSSF,   SPE_BUILTIN_EVMHOSSFA, SPE_BUILTIN_EVMHOSSFAAW, SPE_BUILTIN_EVMHOSSFANW, SPE_BUILTIN_EVMHOSSIAAW,   SPE_BUILTIN_EVMHOSSIANW, SPE_BUILTIN_EVMHOUMI, SPE_BUILTIN_EVMHOUMIA, SPE_BUILTIN_EVMHOUMIAAW,   SPE_BUILTIN_EVMHOUMIANW, SPE_BUILTIN_EVMHOUSIAAW, SPE_BUILTIN_EVMHOUSIANW, SPE_BUILTIN_EVMWHSMF,   SPE_BUILTIN_EVMWHSMFA, SPE_BUILTIN_EVMWHSMI, SPE_BUILTIN_EVMWHSMIA, SPE_BUILTIN_EVMWHSSF,   SPE_BUILTIN_EVMWHSSFA, SPE_BUILTIN_EVMWHUMI, SPE_BUILTIN_EVMWHUMIA, SPE_BUILTIN_EVMWLSMIAAW,   SPE_BUILTIN_EVMWLSMIANW, SPE_BUILTIN_EVMWLSSIAAW, SPE_BUILTIN_EVMWLSSIANW, SPE_BUILTIN_EVMWLUMI,   SPE_BUILTIN_EVMWLUMIA, SPE_BUILTIN_EVMWLUMIAAW, SPE_BUILTIN_EVMWLUMIANW, SPE_BUILTIN_EVMWLUSIAAW,   SPE_BUILTIN_EVMWLUSIANW, SPE_BUILTIN_EVMWSMF, SPE_BUILTIN_EVMWSMFA, SPE_BUILTIN_EVMWSMFAA,   SPE_BUILTIN_EVMWSMFAN, SPE_BUILTIN_EVMWSMI, SPE_BUILTIN_EVMWSMIA, SPE_BUILTIN_EVMWSMIAA,   SPE_BUILTIN_EVMWSMIAN, SPE_BUILTIN_EVMWHSSFAA, SPE_BUILTIN_EVMWSSF, SPE_BUILTIN_EVMWSSFA,   SPE_BUILTIN_EVMWSSFAA, SPE_BUILTIN_EVMWSSFAN, SPE_BUILTIN_EVMWUMI, SPE_BUILTIN_EVMWUMIA,   SPE_BUILTIN_EVMWUMIAA, SPE_BUILTIN_EVMWUMIAN, SPE_BUILTIN_EVNAND, SPE_BUILTIN_EVNOR,   SPE_BUILTIN_EVOR, SPE_BUILTIN_EVORC, SPE_BUILTIN_EVRLW, SPE_BUILTIN_EVSLW,   SPE_BUILTIN_EVSRWS, SPE_BUILTIN_EVSRWU, SPE_BUILTIN_EVSTDDX, SPE_BUILTIN_EVSTDHX,   SPE_BUILTIN_EVSTDWX, SPE_BUILTIN_EVSTWHEX, SPE_BUILTIN_EVSTWHOX, SPE_BUILTIN_EVSTWWEX,   SPE_BUILTIN_EVSTWWOX, SPE_BUILTIN_EVSUBFW, SPE_BUILTIN_EVXOR, SPE_BUILTIN_EVABS,   SPE_BUILTIN_EVADDSMIAAW, SPE_BUILTIN_EVADDSSIAAW, SPE_BUILTIN_EVADDUMIAAW, SPE_BUILTIN_EVADDUSIAAW,   SPE_BUILTIN_EVCNTLSW, SPE_BUILTIN_EVCNTLZW, SPE_BUILTIN_EVEXTSB, SPE_BUILTIN_EVEXTSH,   SPE_BUILTIN_EVFSABS, SPE_BUILTIN_EVFSCFSF, SPE_BUILTIN_EVFSCFSI, SPE_BUILTIN_EVFSCFUF,   SPE_BUILTIN_EVFSCFUI, SPE_BUILTIN_EVFSCTSF, SPE_BUILTIN_EVFSCTSI, SPE_BUILTIN_EVFSCTSIZ,   SPE_BUILTIN_EVFSCTUF, SPE_BUILTIN_EVFSCTUI, SPE_BUILTIN_EVFSCTUIZ, SPE_BUILTIN_EVFSNABS,   SPE_BUILTIN_EVFSNEG, SPE_BUILTIN_EVMRA, SPE_BUILTIN_EVNEG, SPE_BUILTIN_EVRNDW,   SPE_BUILTIN_EVSUBFSMIAAW, SPE_BUILTIN_EVSUBFSSIAAW, SPE_BUILTIN_EVSUBFUMIAAW, SPE_BUILTIN_EVSUBFUSIAAW,   SPE_BUILTIN_EVADDIW, SPE_BUILTIN_EVLDD, SPE_BUILTIN_EVLDH, SPE_BUILTIN_EVLDW,   SPE_BUILTIN_EVLHHESPLAT, SPE_BUILTIN_EVLHHOSSPLAT, SPE_BUILTIN_EVLHHOUSPLAT, SPE_BUILTIN_EVLWHE,   SPE_BUILTIN_EVLWHOS, SPE_BUILTIN_EVLWHOU, SPE_BUILTIN_EVLWHSPLAT, SPE_BUILTIN_EVLWWSPLAT,   SPE_BUILTIN_EVRLWI, SPE_BUILTIN_EVSLWI, SPE_BUILTIN_EVSRWIS, SPE_BUILTIN_EVSRWIU,   SPE_BUILTIN_EVSTDD, SPE_BUILTIN_EVSTDH, SPE_BUILTIN_EVSTDW, SPE_BUILTIN_EVSTWHE,   SPE_BUILTIN_EVSTWHO, SPE_BUILTIN_EVSTWWE, SPE_BUILTIN_EVSTWWO, SPE_BUILTIN_EVSUBIFW,   SPE_BUILTIN_EVCMPEQ, SPE_BUILTIN_EVCMPGTS, SPE_BUILTIN_EVCMPGTU, SPE_BUILTIN_EVCMPLTS,   SPE_BUILTIN_EVCMPLTU, SPE_BUILTIN_EVFSCMPEQ, SPE_BUILTIN_EVFSCMPGT, SPE_BUILTIN_EVFSCMPLT,   SPE_BUILTIN_EVFSTSTEQ, SPE_BUILTIN_EVFSTSTGT, SPE_BUILTIN_EVFSTSTLT, SPE_BUILTIN_EVSEL_CMPEQ,   SPE_BUILTIN_EVSEL_CMPGTS, SPE_BUILTIN_EVSEL_CMPGTU, SPE_BUILTIN_EVSEL_CMPLTS, SPE_BUILTIN_EVSEL_CMPLTU,   SPE_BUILTIN_EVSEL_FSCMPEQ, SPE_BUILTIN_EVSEL_FSCMPGT, SPE_BUILTIN_EVSEL_FSCMPLT, SPE_BUILTIN_EVSEL_FSTSTEQ,   SPE_BUILTIN_EVSEL_FSTSTGT, SPE_BUILTIN_EVSEL_FSTSTLT, SPE_BUILTIN_EVSPLATFI, SPE_BUILTIN_EVSPLATI,   SPE_BUILTIN_EVMWHSSMAA, SPE_BUILTIN_EVMWHSMFAA, SPE_BUILTIN_EVMWHSMIAA, SPE_BUILTIN_EVMWHUSIAA,   SPE_BUILTIN_EVMWHUMIAA, SPE_BUILTIN_EVMWHSSFAN, SPE_BUILTIN_EVMWHSSIAN, SPE_BUILTIN_EVMWHSMFAN,   SPE_BUILTIN_EVMWHSMIAN, SPE_BUILTIN_EVMWHUSIAN, SPE_BUILTIN_EVMWHUMIAN, SPE_BUILTIN_EVMWHGSSFAA,   SPE_BUILTIN_EVMWHGSMFAA, SPE_BUILTIN_EVMWHGSMIAA, SPE_BUILTIN_EVMWHGUMIAA, SPE_BUILTIN_EVMWHGSSFAN,   SPE_BUILTIN_EVMWHGSMFAN, SPE_BUILTIN_EVMWHGSMIAN, SPE_BUILTIN_EVMWHGUMIAN, SPE_BUILTIN_MTSPEFSCR,   SPE_BUILTIN_MFSPEFSCR, SPE_BUILTIN_BRINC, ALTIVEC_BUILTIN_ST_INTERNAL_4si, ALTIVEC_BUILTIN_LD_INTERNAL_4si,   ALTIVEC_BUILTIN_ST_INTERNAL_8hi, ALTIVEC_BUILTIN_LD_INTERNAL_8hi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi, ALTIVEC_BUILTIN_LD_INTERNAL_16qi,   ALTIVEC_BUILTIN_ST_INTERNAL_4sf, ALTIVEC_BUILTIN_LD_INTERNAL_4sf, ALTIVEC_BUILTIN_VADDUBM, ALTIVEC_BUILTIN_VADDUHM,   ALTIVEC_BUILTIN_VADDUWM, ALTIVEC_BUILTIN_VADDFP, ALTIVEC_BUILTIN_VADDCUW, ALTIVEC_BUILTIN_VADDUBS,   ALTIVEC_BUILTIN_VADDSBS, ALTIVEC_BUILTIN_VADDUHS, ALTIVEC_BUILTIN_VADDSHS, ALTIVEC_BUILTIN_VADDUWS,   ALTIVEC_BUILTIN_VADDSWS, ALTIVEC_BUILTIN_VAND, ALTIVEC_BUILTIN_VANDC, ALTIVEC_BUILTIN_VAVGUB,   ALTIVEC_BUILTIN_VAVGSB, ALTIVEC_BUILTIN_VAVGUH, ALTIVEC_BUILTIN_VAVGSH, ALTIVEC_BUILTIN_VAVGUW,   ALTIVEC_BUILTIN_VAVGSW, ALTIVEC_BUILTIN_VCFUX, ALTIVEC_BUILTIN_VCFSX, ALTIVEC_BUILTIN_VCTSXS,   ALTIVEC_BUILTIN_VCTUXS, ALTIVEC_BUILTIN_VCMPBFP, ALTIVEC_BUILTIN_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUH,   ALTIVEC_BUILTIN_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQFP, ALTIVEC_BUILTIN_VCMPGEFP, ALTIVEC_BUILTIN_VCMPGTUB,   ALTIVEC_BUILTIN_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTUW,   ALTIVEC_BUILTIN_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTFP, ALTIVEC_BUILTIN_VEXPTEFP, ALTIVEC_BUILTIN_VLOGEFP,   ALTIVEC_BUILTIN_VMADDFP, ALTIVEC_BUILTIN_VMAXUB, ALTIVEC_BUILTIN_VMAXSB, ALTIVEC_BUILTIN_VMAXUH,   ALTIVEC_BUILTIN_VMAXSH, ALTIVEC_BUILTIN_VMAXUW, ALTIVEC_BUILTIN_VMAXSW, ALTIVEC_BUILTIN_VMAXFP,   ALTIVEC_BUILTIN_VMHADDSHS, ALTIVEC_BUILTIN_VMHRADDSHS, ALTIVEC_BUILTIN_VMLADDUHM, ALTIVEC_BUILTIN_VMRGHB,   ALTIVEC_BUILTIN_VMRGHH, ALTIVEC_BUILTIN_VMRGHW, ALTIVEC_BUILTIN_VMRGLB, ALTIVEC_BUILTIN_VMRGLH,   ALTIVEC_BUILTIN_VMRGLW, ALTIVEC_BUILTIN_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMUHM,   ALTIVEC_BUILTIN_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMSHS, ALTIVEC_BUILTIN_VMINUB,   ALTIVEC_BUILTIN_VMINSB, ALTIVEC_BUILTIN_VMINUH, ALTIVEC_BUILTIN_VMINSH, ALTIVEC_BUILTIN_VMINUW,   ALTIVEC_BUILTIN_VMINSW, ALTIVEC_BUILTIN_VMINFP, ALTIVEC_BUILTIN_VMULEUB, ALTIVEC_BUILTIN_VMULESB,   ALTIVEC_BUILTIN_VMULEUH, ALTIVEC_BUILTIN_VMULESH, ALTIVEC_BUILTIN_VMULOUB, ALTIVEC_BUILTIN_VMULOSB,   ALTIVEC_BUILTIN_VMULOUH, ALTIVEC_BUILTIN_VMULOSH, ALTIVEC_BUILTIN_VNMSUBFP, ALTIVEC_BUILTIN_VNOR,   ALTIVEC_BUILTIN_VOR, ALTIVEC_BUILTIN_VSEL_4SI, ALTIVEC_BUILTIN_VSEL_4SF, ALTIVEC_BUILTIN_VSEL_8HI,   ALTIVEC_BUILTIN_VSEL_16QI, ALTIVEC_BUILTIN_VPERM_4SI, ALTIVEC_BUILTIN_VPERM_4SF, ALTIVEC_BUILTIN_VPERM_8HI,   ALTIVEC_BUILTIN_VPERM_16QI, ALTIVEC_BUILTIN_VPKUHUM, ALTIVEC_BUILTIN_VPKUWUM, ALTIVEC_BUILTIN_VPKPX,   ALTIVEC_BUILTIN_VPKUHSS, ALTIVEC_BUILTIN_VPKSHSS, ALTIVEC_BUILTIN_VPKUWSS, ALTIVEC_BUILTIN_VPKSWSS,   ALTIVEC_BUILTIN_VPKUHUS, ALTIVEC_BUILTIN_VPKSHUS, ALTIVEC_BUILTIN_VPKUWUS, ALTIVEC_BUILTIN_VPKSWUS,   ALTIVEC_BUILTIN_VREFP, ALTIVEC_BUILTIN_VRFIM, ALTIVEC_BUILTIN_VRFIN, ALTIVEC_BUILTIN_VRFIP,   ALTIVEC_BUILTIN_VRFIZ, ALTIVEC_BUILTIN_VRLB, ALTIVEC_BUILTIN_VRLH, ALTIVEC_BUILTIN_VRLW,   ALTIVEC_BUILTIN_VRSQRTEFP, ALTIVEC_BUILTIN_VSLB, ALTIVEC_BUILTIN_VSLH, ALTIVEC_BUILTIN_VSLW,   ALTIVEC_BUILTIN_VSL, ALTIVEC_BUILTIN_VSLO, ALTIVEC_BUILTIN_VSPLTB, ALTIVEC_BUILTIN_VSPLTH,   ALTIVEC_BUILTIN_VSPLTW, ALTIVEC_BUILTIN_VSPLTISB, ALTIVEC_BUILTIN_VSPLTISH, ALTIVEC_BUILTIN_VSPLTISW,   ALTIVEC_BUILTIN_VSRB, ALTIVEC_BUILTIN_VSRH, ALTIVEC_BUILTIN_VSRW, ALTIVEC_BUILTIN_VSRAB,   ALTIVEC_BUILTIN_VSRAH, ALTIVEC_BUILTIN_VSRAW, ALTIVEC_BUILTIN_VSR, ALTIVEC_BUILTIN_VSRO,   ALTIVEC_BUILTIN_VSUBUBM, ALTIVEC_BUILTIN_VSUBUHM, ALTIVEC_BUILTIN_VSUBUWM, ALTIVEC_BUILTIN_VSUBFP,   ALTIVEC_BUILTIN_VSUBCUW, ALTIVEC_BUILTIN_VSUBUBS, ALTIVEC_BUILTIN_VSUBSBS, ALTIVEC_BUILTIN_VSUBUHS,   ALTIVEC_BUILTIN_VSUBSHS, ALTIVEC_BUILTIN_VSUBUWS, ALTIVEC_BUILTIN_VSUBSWS, ALTIVEC_BUILTIN_VSUM4UBS,   ALTIVEC_BUILTIN_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SHS, ALTIVEC_BUILTIN_VSUM2SWS, ALTIVEC_BUILTIN_VSUMSWS,   ALTIVEC_BUILTIN_VXOR, ALTIVEC_BUILTIN_VSLDOI_16QI, ALTIVEC_BUILTIN_VSLDOI_8HI, ALTIVEC_BUILTIN_VSLDOI_4SI,   ALTIVEC_BUILTIN_VSLDOI_4SF, ALTIVEC_BUILTIN_VUPKHSB, ALTIVEC_BUILTIN_VUPKHPX, ALTIVEC_BUILTIN_VUPKHSH,   ALTIVEC_BUILTIN_VUPKLSB, ALTIVEC_BUILTIN_VUPKLPX, ALTIVEC_BUILTIN_VUPKLSH, ALTIVEC_BUILTIN_MTVSCR,   ALTIVEC_BUILTIN_MFVSCR, ALTIVEC_BUILTIN_DSSALL, ALTIVEC_BUILTIN_DSS, ALTIVEC_BUILTIN_LVSL,   ALTIVEC_BUILTIN_LVSR, ALTIVEC_BUILTIN_DSTT, ALTIVEC_BUILTIN_DSTST, ALTIVEC_BUILTIN_DSTSTT,   ALTIVEC_BUILTIN_DST, ALTIVEC_BUILTIN_LVEBX, ALTIVEC_BUILTIN_LVEHX, ALTIVEC_BUILTIN_LVEWX,   ALTIVEC_BUILTIN_LVXL, ALTIVEC_BUILTIN_LVX, ALTIVEC_BUILTIN_STVX, ALTIVEC_BUILTIN_STVEBX,   ALTIVEC_BUILTIN_STVEHX, ALTIVEC_BUILTIN_STVEWX, ALTIVEC_BUILTIN_STVXL, ALTIVEC_BUILTIN_VCMPBFP_P,   ALTIVEC_BUILTIN_VCMPEQFP_P, ALTIVEC_BUILTIN_VCMPEQUB_P, ALTIVEC_BUILTIN_VCMPEQUH_P, ALTIVEC_BUILTIN_VCMPEQUW_P,   ALTIVEC_BUILTIN_VCMPGEFP_P, ALTIVEC_BUILTIN_VCMPGTFP_P, ALTIVEC_BUILTIN_VCMPGTSB_P, ALTIVEC_BUILTIN_VCMPGTSH_P,   ALTIVEC_BUILTIN_VCMPGTSW_P, ALTIVEC_BUILTIN_VCMPGTUB_P, ALTIVEC_BUILTIN_VCMPGTUH_P, ALTIVEC_BUILTIN_VCMPGTUW_P,   ALTIVEC_BUILTIN_ABSS_V4SI, ALTIVEC_BUILTIN_ABSS_V8HI, ALTIVEC_BUILTIN_ABSS_V16QI, ALTIVEC_BUILTIN_ABS_V4SI,   ALTIVEC_BUILTIN_ABS_V4SF, ALTIVEC_BUILTIN_ABS_V8HI, ALTIVEC_BUILTIN_ABS_V16QI, ALTIVEC_BUILTIN_MASK_FOR_LOAD,   ALTIVEC_BUILTIN_MASK_FOR_STORE, ALTIVEC_BUILTIN_VEC_INIT_V4SI, ALTIVEC_BUILTIN_VEC_INIT_V8HI, ALTIVEC_BUILTIN_VEC_INIT_V16QI,   ALTIVEC_BUILTIN_VEC_INIT_V4SF, ALTIVEC_BUILTIN_VEC_SET_V4SI, ALTIVEC_BUILTIN_VEC_SET_V8HI, ALTIVEC_BUILTIN_VEC_SET_V16QI,   ALTIVEC_BUILTIN_VEC_SET_V4SF, ALTIVEC_BUILTIN_VEC_EXT_V4SI, ALTIVEC_BUILTIN_VEC_EXT_V8HI, ALTIVEC_BUILTIN_VEC_EXT_V16QI,   ALTIVEC_BUILTIN_VEC_EXT_V4SF, ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_OVERLOADED_FIRST = ALTIVEC_BUILTIN_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPGT_P,   ALTIVEC_BUILTIN_VCMPGE_P, ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_VEC_ADD,   ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VEC_ANDC,   ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VEC_CMPEQ,   ALTIVEC_BUILTIN_VEC_CMPEQUB, ALTIVEC_BUILTIN_VEC_CMPEQUH, ALTIVEC_BUILTIN_VEC_CMPEQUW, ALTIVEC_BUILTIN_VEC_CMPGE,   ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VEC_CTF,   ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_VEC_DSTST,   ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEC_FLOOR,   ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_VEC_LOGE,   ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_VEC_LVSL,   ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VEC_MAX,   ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VEC_MLADD,   ALTIVEC_BUILTIN_VEC_MPERM, ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VEC_MRGHB, ALTIVEC_BUILTIN_VEC_MRGHH,   ALTIVEC_BUILTIN_VEC_MRGHW, ALTIVEC_BUILTIN_VEC_MRGLB, ALTIVEC_BUILTIN_VEC_MRGLH, ALTIVEC_BUILTIN_VEC_MRGLW,   ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_VEC_MULE,   ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VEC_OR,   ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VEC_PACKSU,   ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VEC_ROUND,   ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VEC_SLD,   ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VEC_SPLAT_S16,   ALTIVEC_BUILTIN_VEC_SPLAT_S32, ALTIVEC_BUILTIN_VEC_SPLAT_S8, ALTIVEC_BUILTIN_VEC_SPLAT_U16, ALTIVEC_BUILTIN_VEC_SPLAT_U32,   ALTIVEC_BUILTIN_VEC_SPLAT_U8, ALTIVEC_BUILTIN_VEC_SPLTB, ALTIVEC_BUILTIN_VEC_SPLTH, ALTIVEC_BUILTIN_VEC_SPLTW,   ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VEC_SRO,   ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_VEC_STVEBX,   ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VEC_SUBC,   ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VEC_SUMS,   ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VEC_VADDFP,   ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VEC_VADDUBM,   ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VEC_VADDUWM,   ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VEC_VAVGSW,   ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VEC_VCFSX,   ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VEC_VCMPEQUH,   ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VEC_VCMPGTSH,   ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VEC_VCMPGTUW,   ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VEC_VMAXSW,   ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VEC_VMINFP,   ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VEC_VMINUB,   ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VEC_VMRGHH,   ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VEC_VMRGLW,   ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VEC_VMSUMUBM,   ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VEC_VMULESH,   ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VEC_VMULOSH,   ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VEC_VPKSHUS,   ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VEC_VPKUHUS,   ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VEC_VRLH,   ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VEC_VSLW,   ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VEC_VSRAB,   ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VEC_VSRH,   ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VEC_VSUBSHS,   ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VEC_VSUBUHM,   ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VEC_VSUM4SBS,   ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VEC_VUPKHSB,   ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VEC_VUPKLSH,   ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VEC_STEP, ALTIVEC_BUILTIN_OVERLOADED_LAST = ALTIVEC_BUILTIN_VEC_STEP, SPE_BUILTIN_EVADDW,   SPE_BUILTIN_EVAND, SPE_BUILTIN_EVANDC, SPE_BUILTIN_EVDIVWS, SPE_BUILTIN_EVDIVWU,   SPE_BUILTIN_EVEQV, SPE_BUILTIN_EVFSADD, SPE_BUILTIN_EVFSDIV, SPE_BUILTIN_EVFSMUL,   SPE_BUILTIN_EVFSSUB, SPE_BUILTIN_EVLDDX, SPE_BUILTIN_EVLDHX, SPE_BUILTIN_EVLDWX,   SPE_BUILTIN_EVLHHESPLATX, SPE_BUILTIN_EVLHHOSSPLATX, SPE_BUILTIN_EVLHHOUSPLATX, SPE_BUILTIN_EVLWHEX,   SPE_BUILTIN_EVLWHOSX, SPE_BUILTIN_EVLWHOUX, SPE_BUILTIN_EVLWHSPLATX, SPE_BUILTIN_EVLWWSPLATX,   SPE_BUILTIN_EVMERGEHI, SPE_BUILTIN_EVMERGEHILO, SPE_BUILTIN_EVMERGELO, SPE_BUILTIN_EVMERGELOHI,   SPE_BUILTIN_EVMHEGSMFAA, SPE_BUILTIN_EVMHEGSMFAN, SPE_BUILTIN_EVMHEGSMIAA, SPE_BUILTIN_EVMHEGSMIAN,   SPE_BUILTIN_EVMHEGUMIAA, SPE_BUILTIN_EVMHEGUMIAN, SPE_BUILTIN_EVMHESMF, SPE_BUILTIN_EVMHESMFA,   SPE_BUILTIN_EVMHESMFAAW, SPE_BUILTIN_EVMHESMFANW, SPE_BUILTIN_EVMHESMI, SPE_BUILTIN_EVMHESMIA,   SPE_BUILTIN_EVMHESMIAAW, SPE_BUILTIN_EVMHESMIANW, SPE_BUILTIN_EVMHESSF, SPE_BUILTIN_EVMHESSFA,   SPE_BUILTIN_EVMHESSFAAW, SPE_BUILTIN_EVMHESSFANW, SPE_BUILTIN_EVMHESSIAAW, SPE_BUILTIN_EVMHESSIANW,   SPE_BUILTIN_EVMHEUMI, SPE_BUILTIN_EVMHEUMIA, SPE_BUILTIN_EVMHEUMIAAW, SPE_BUILTIN_EVMHEUMIANW,   SPE_BUILTIN_EVMHEUSIAAW, SPE_BUILTIN_EVMHEUSIANW, SPE_BUILTIN_EVMHOGSMFAA, SPE_BUILTIN_EVMHOGSMFAN,   SPE_BUILTIN_EVMHOGSMIAA, SPE_BUILTIN_EVMHOGSMIAN, SPE_BUILTIN_EVMHOGUMIAA, SPE_BUILTIN_EVMHOGUMIAN,   SPE_BUILTIN_EVMHOSMF, SPE_BUILTIN_EVMHOSMFA, SPE_BUILTIN_EVMHOSMFAAW, SPE_BUILTIN_EVMHOSMFANW,   SPE_BUILTIN_EVMHOSMI, SPE_BUILTIN_EVMHOSMIA, SPE_BUILTIN_EVMHOSMIAAW, SPE_BUILTIN_EVMHOSMIANW,   SPE_BUILTIN_EVMHOSSF, SPE_BUILTIN_EVMHOSSFA, SPE_BUILTIN_EVMHOSSFAAW, SPE_BUILTIN_EVMHOSSFANW,   SPE_BUILTIN_EVMHOSSIAAW, SPE_BUILTIN_EVMHOSSIANW, SPE_BUILTIN_EVMHOUMI, SPE_BUILTIN_EVMHOUMIA,   SPE_BUILTIN_EVMHOUMIAAW, SPE_BUILTIN_EVMHOUMIANW, SPE_BUILTIN_EVMHOUSIAAW, SPE_BUILTIN_EVMHOUSIANW,   SPE_BUILTIN_EVMWHSMF, SPE_BUILTIN_EVMWHSMFA, SPE_BUILTIN_EVMWHSMI, SPE_BUILTIN_EVMWHSMIA,   SPE_BUILTIN_EVMWHSSF, SPE_BUILTIN_EVMWHSSFA, SPE_BUILTIN_EVMWHUMI, SPE_BUILTIN_EVMWHUMIA,   SPE_BUILTIN_EVMWLSMIAAW, SPE_BUILTIN_EVMWLSMIANW, SPE_BUILTIN_EVMWLSSIAAW, SPE_BUILTIN_EVMWLSSIANW,   SPE_BUILTIN_EVMWLUMI, SPE_BUILTIN_EVMWLUMIA, SPE_BUILTIN_EVMWLUMIAAW, SPE_BUILTIN_EVMWLUMIANW,   SPE_BUILTIN_EVMWLUSIAAW, SPE_BUILTIN_EVMWLUSIANW, SPE_BUILTIN_EVMWSMF, SPE_BUILTIN_EVMWSMFA,   SPE_BUILTIN_EVMWSMFAA, SPE_BUILTIN_EVMWSMFAN, SPE_BUILTIN_EVMWSMI, SPE_BUILTIN_EVMWSMIA,   SPE_BUILTIN_EVMWSMIAA, SPE_BUILTIN_EVMWSMIAN, SPE_BUILTIN_EVMWHSSFAA, SPE_BUILTIN_EVMWSSF,   SPE_BUILTIN_EVMWSSFA, SPE_BUILTIN_EVMWSSFAA, SPE_BUILTIN_EVMWSSFAN, SPE_BUILTIN_EVMWUMI,   SPE_BUILTIN_EVMWUMIA, SPE_BUILTIN_EVMWUMIAA, SPE_BUILTIN_EVMWUMIAN, SPE_BUILTIN_EVNAND,   SPE_BUILTIN_EVNOR, SPE_BUILTIN_EVOR, SPE_BUILTIN_EVORC, SPE_BUILTIN_EVRLW,   SPE_BUILTIN_EVSLW, SPE_BUILTIN_EVSRWS, SPE_BUILTIN_EVSRWU, SPE_BUILTIN_EVSTDDX,   SPE_BUILTIN_EVSTDHX, SPE_BUILTIN_EVSTDWX, SPE_BUILTIN_EVSTWHEX, SPE_BUILTIN_EVSTWHOX,   SPE_BUILTIN_EVSTWWEX, SPE_BUILTIN_EVSTWWOX, SPE_BUILTIN_EVSUBFW, SPE_BUILTIN_EVXOR,   SPE_BUILTIN_EVABS, SPE_BUILTIN_EVADDSMIAAW, SPE_BUILTIN_EVADDSSIAAW, SPE_BUILTIN_EVADDUMIAAW,   SPE_BUILTIN_EVADDUSIAAW, SPE_BUILTIN_EVCNTLSW, SPE_BUILTIN_EVCNTLZW, SPE_BUILTIN_EVEXTSB,   SPE_BUILTIN_EVEXTSH, SPE_BUILTIN_EVFSABS, SPE_BUILTIN_EVFSCFSF, SPE_BUILTIN_EVFSCFSI,   SPE_BUILTIN_EVFSCFUF, SPE_BUILTIN_EVFSCFUI, SPE_BUILTIN_EVFSCTSF, SPE_BUILTIN_EVFSCTSI,   SPE_BUILTIN_EVFSCTSIZ, SPE_BUILTIN_EVFSCTUF, SPE_BUILTIN_EVFSCTUI, SPE_BUILTIN_EVFSCTUIZ,   SPE_BUILTIN_EVFSNABS, SPE_BUILTIN_EVFSNEG, SPE_BUILTIN_EVMRA, SPE_BUILTIN_EVNEG,   SPE_BUILTIN_EVRNDW, SPE_BUILTIN_EVSUBFSMIAAW, SPE_BUILTIN_EVSUBFSSIAAW, SPE_BUILTIN_EVSUBFUMIAAW,   SPE_BUILTIN_EVSUBFUSIAAW, SPE_BUILTIN_EVADDIW, SPE_BUILTIN_EVLDD, SPE_BUILTIN_EVLDH,   SPE_BUILTIN_EVLDW, SPE_BUILTIN_EVLHHESPLAT, SPE_BUILTIN_EVLHHOSSPLAT, SPE_BUILTIN_EVLHHOUSPLAT,   SPE_BUILTIN_EVLWHE, SPE_BUILTIN_EVLWHOS, SPE_BUILTIN_EVLWHOU, SPE_BUILTIN_EVLWHSPLAT,   SPE_BUILTIN_EVLWWSPLAT, SPE_BUILTIN_EVRLWI, SPE_BUILTIN_EVSLWI, SPE_BUILTIN_EVSRWIS,   SPE_BUILTIN_EVSRWIU, SPE_BUILTIN_EVSTDD, SPE_BUILTIN_EVSTDH, SPE_BUILTIN_EVSTDW,   SPE_BUILTIN_EVSTWHE, SPE_BUILTIN_EVSTWHO, SPE_BUILTIN_EVSTWWE, SPE_BUILTIN_EVSTWWO,   SPE_BUILTIN_EVSUBIFW, SPE_BUILTIN_EVCMPEQ, SPE_BUILTIN_EVCMPGTS, SPE_BUILTIN_EVCMPGTU,   SPE_BUILTIN_EVCMPLTS, SPE_BUILTIN_EVCMPLTU, SPE_BUILTIN_EVFSCMPEQ, SPE_BUILTIN_EVFSCMPGT,   SPE_BUILTIN_EVFSCMPLT, SPE_BUILTIN_EVFSTSTEQ, SPE_BUILTIN_EVFSTSTGT, SPE_BUILTIN_EVFSTSTLT,   SPE_BUILTIN_EVSEL_CMPEQ, SPE_BUILTIN_EVSEL_CMPGTS, SPE_BUILTIN_EVSEL_CMPGTU, SPE_BUILTIN_EVSEL_CMPLTS,   SPE_BUILTIN_EVSEL_CMPLTU, SPE_BUILTIN_EVSEL_FSCMPEQ, SPE_BUILTIN_EVSEL_FSCMPGT, SPE_BUILTIN_EVSEL_FSCMPLT,   SPE_BUILTIN_EVSEL_FSTSTEQ, SPE_BUILTIN_EVSEL_FSTSTGT, SPE_BUILTIN_EVSEL_FSTSTLT, SPE_BUILTIN_EVSPLATFI,   SPE_BUILTIN_EVSPLATI, SPE_BUILTIN_EVMWHSSMAA, SPE_BUILTIN_EVMWHSMFAA, SPE_BUILTIN_EVMWHSMIAA,   SPE_BUILTIN_EVMWHUSIAA, SPE_BUILTIN_EVMWHUMIAA, SPE_BUILTIN_EVMWHSSFAN, SPE_BUILTIN_EVMWHSSIAN,   SPE_BUILTIN_EVMWHSMFAN, SPE_BUILTIN_EVMWHSMIAN, SPE_BUILTIN_EVMWHUSIAN, SPE_BUILTIN_EVMWHUMIAN,   SPE_BUILTIN_EVMWHGSSFAA, SPE_BUILTIN_EVMWHGSMFAA, SPE_BUILTIN_EVMWHGSMIAA, SPE_BUILTIN_EVMWHGUMIAA,   SPE_BUILTIN_EVMWHGSSFAN, SPE_BUILTIN_EVMWHGSMFAN, SPE_BUILTIN_EVMWHGSMIAN, SPE_BUILTIN_EVMWHGUMIAN,   SPE_BUILTIN_MTSPEFSCR, SPE_BUILTIN_MFSPEFSCR, SPE_BUILTIN_BRINC, RS6000_BUILTIN_COUNT }
Variables
int	target_flags
enum processor_type	rs6000_cpu
struct rs6000_cpu_select	rs6000_select []
const char *	rs6000_debug_name
const char *	rs6000_abi_string
int	rs6000_debug_stack
int	rs6000_debug_arg
const char *	rs6000_long_double_size_string
int	rs6000_long_double_type_size
int	rs6000_altivec_abi
enum rs6000_abi	rs6000_current_abi
struct rtx_def *	rs6000_compare_op0
struct rtx_def *	rs6000_compare_op1
int	rs6000_compare_fp_p
int	toc_initialized
char	rs6000_reg_names [][8]
int	flag_pic
int	optimize
int	flag_expensive_optimizations
int	frame_pointer_needed

---

Define Documentation

#define ACCUMULATE_OUTGOING_ARGS   1

Definition at line 1437 of file rs6000.h.

#define ADDITIONAL_REGISTER_NAMES

Value:

{{"r0",    0}, {"r1",    1}, {"r2",    2}, {"r3",    3},  \
  {"r4",    4}, {"r5",    5}, {"r6",    6}, {"r7",    7}, \
  {"r8",    8}, {"r9",    9}, {"r10",  10}, {"r11",  11}, \
  {"r12",  12}, {"r13",  13}, {"r14",  14}, {"r15",  15}, \
  {"r16",  16}, {"r17",  17}, {"r18",  18}, {"r19",  19}, \
  {"r20",  20}, {"r21",  21}, {"r22",  22}, {"r23",  23}, \
  {"r24",  24}, {"r25",  25}, {"r26",  26}, {"r27",  27}, \
  {"r28",  28}, {"r29",  29}, {"r30",  30}, {"r31",  31}, \
  {"fr0",  32}, {"fr1",  33}, {"fr2",  34}, {"fr3",  35}, \
  {"fr4",  36}, {"fr5",  37}, {"fr6",  38}, {"fr7",  39}, \
  {"fr8",  40}, {"fr9",  41}, {"fr10", 42}, {"fr11", 43}, \
  {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
  {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
  {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
  {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
  {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
  {"v0",   77}, {"v1",   78}, {"v2",   79}, {"v3",   80},       \
  {"v4",   81}, {"v5",   82}, {"v6",   83}, {"v7",   84},       \
  {"v8",   85}, {"v9",   86}, {"v10",  87}, {"v11",  88},       \
  {"v12",  89}, {"v13",  90}, {"v14",  91}, {"v15",  92},       \
  {"v16",  93}, {"v17",  94}, {"v18",  95}, {"v19",  96},       \
  {"v20",  97}, {"v21",  98}, {"v22",  99}, {"v23",  100},  \
  {"v24",  101},{"v25",  102},{"v26",  103},{"v27",  104},      \
  {"v28",  105},{"v29",  106},{"v30",  107},{"v31",  108},      \
  {"vrsave", 109},            \
  /* no additional names for: mq, lr, ctr, ap */    \
  {"cr0",  68}, {"cr1",  69}, {"cr2",  70}, {"cr3",  71}, \
  {"cr4",  72}, {"cr5",  73}, {"cr6",  74}, {"cr7",  75}, \
  {"cc",   68}, {"sp",    1}, {"toc",   2} }

Definition at line 2664 of file rs6000.h.

#define ADDRESS_COST

(

RTX

)

0

Definition at line 2362 of file rs6000.h.

#define ALTIVEC_ARG_MAX_REG   (ALTIVEC_ARG_MIN_REG + 11)

Definition at line 1523 of file rs6000.h.

Referenced by function_arg(), and function_arg_advance().

#define ALTIVEC_ARG_MIN_REG   (FIRST_ALTIVEC_REGNO + 2)

Definition at line 1522 of file rs6000.h.

Referenced by compute_vrsave_mask(), init_cumulative_args(), rs6000_function_value(), and rs6000_return_in_memory().

#define ALTIVEC_ARG_NUM_REG   (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)

Definition at line 1524 of file rs6000.h.

#define ALTIVEC_ARG_RETURN   (FIRST_ALTIVEC_REGNO + 2)

Definition at line 1529 of file rs6000.h.

Referenced by compute_vrsave_mask(), is_altivec_return_reg(), rs6000_function_value(), and rs6000_libcall_value().

#define ALTIVEC_REGNO_P

(

N

)

((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)

Definition at line 839 of file rs6000.h.

Referenced by altivec_register_operand(), rs6000_dbx_register_number(), rs6000_hard_regno_mode_ok(), rs6000_hard_regno_nregs(), rs6000_secondary_reload_class(), rs6000_split_multireg_move(), and secondary_reload_class().

#define ALTIVEC_VECTOR_MODE

(

MODE

)

Value:

((MODE) == V16QImode    \
   || (MODE) == V8HImode    \
   || (MODE) == V4SFmode    \
   || (MODE) == V4SImode)

Definition at line 856 of file rs6000.h.

Referenced by easy_vector_constant(), emit_frame_save(), function_arg(), function_arg_advance(), function_arg_boundary(), init_cumulative_args(), rs6000_function_value(), rs6000_gimplify_va_arg(), rs6000_hard_regno_mode_ok(), rs6000_legitimate_address(), rs6000_legitimize_address(), rs6000_legitimize_reload_address(), rs6000_libcall_value(), rs6000_pass_by_reference(), rs6000_return_in_memory(), and rs6000_vector_mode_supported_p().

#define ARG_POINTER_CFA_OFFSET

(

FNDECL

)

0

Definition at line 1418 of file rs6000.h.

Referenced by adjust_stack_reference(), ia64_dwarf2out_def_steady_cfa(), and instantiate_virtual_regs().

#define ARG_POINTER_REGNUM   67

Definition at line 1005 of file rs6000.h.

#define ASM_APP_OFF   ""

Definition at line 2512 of file rs6000.h.

#define ASM_APP_ON   ""

Definition at line 2507 of file rs6000.h.

#define ASM_COMMENT_START   " #"

Definition at line 2408 of file rs6000.h.

#define ASM_CPU_SPEC   "%{!mcpu*: \ %{mpower: %{!mpower2: -mpwr}} \ %{mpower2: -mpwrx} \ %{mpowerpc*: -mppc} \ %{mno-power: %{!mpowerpc*: -mcom}} \ %{!mno-power: %{!mpower2: %(asm_default)}}} \%{mcpu=common: -mcom} \%{mcpu=power: -mpwr} \%{mcpu=power2: -mpwrx} \%{mcpu=powerpc: -mppc} \%{mcpu=rios: -mpwr} \%{mcpu=rios1: -mpwr} \%{mcpu=rios2: -mpwrx} \%{mcpu=rsc: -mpwr} \%{mcpu=rsc1: -mpwr} \%{mcpu=401: -mppc} \%{mcpu=403: -m403} \%{mcpu=405: -m405} \%{mcpu=505: -mppc} \%{mcpu=601: -m601} \%{mcpu=602: -mppc} \%{mcpu=603: -mppc} \%{mcpu=603e: -mppc} \%{mcpu=ec603e: -mppc} \%{mcpu=604: -mppc} \%{mcpu=604e: -mppc} \%{mcpu=620: -mppc} \%{mcpu=740: -mppc} \%{mcpu=7400: -mppc} \%{mcpu=7450: -mppc} \%{mcpu=750: -mppc} \%{mcpu=801: -mppc} \%{mcpu=821: -mppc} \%{mcpu=823: -mppc} \%{mcpu=860: -mppc} \%{maltivec: -maltivec}"

Definition at line 91 of file rs6000.h.

#define ASM_DEFAULT_SPEC   ""

Definition at line 131 of file rs6000.h.

#define ASM_FORMAT_PRIVATE_NAME	(	OUTPUT,
		NAME,
		LABELNO		)

Value:

( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10),  \
  sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))

Definition at line 2724 of file rs6000.h.

#define ASM_OUTPUT_ADDR_DIFF_ELT	(	FILE,
		BODY,
		VALUE,
		REL		)

Value:

do { char buf[100];         \
       fputs ("\t.long ", FILE);      \
       ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
       assemble_name (FILE, buf);     \
       putc ('-', FILE);        \
       ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
       assemble_name (FILE, buf);     \
       putc ('\n', FILE);       \
     } while (0)

Definition at line 2701 of file rs6000.h.

#define ASM_OUTPUT_ALIGN	(	FILE,
		LOG		)

Value:

if ((LOG) != 0)     \
    fprintf (FILE, "\t.align %d\n", (LOG))

Definition at line 2716 of file rs6000.h.

#define ASM_OUTPUT_DEF_FROM_DECLS	(	FILE,
		DECL,
		TARGET		)

Definition at line 2471 of file rs6000.h.

#define ASM_OUTPUT_SPECIAL_POOL_ENTRY	(	FILE,
		X,
		MODE,
		ALIGN,
		LABELNO,
		WIN		)

Value:

{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE))        \
    {                   \
      output_toc (FILE, X, LABELNO, MODE);          \
      goto WIN;                 \
    }                   \
}

Definition at line 2422 of file rs6000.h.

Referenced by output_constant_pool(), and output_constant_pool_1().

#define ASSEMBLER_DIALECT   (TARGET_NEW_MNEMONICS ? 1 : 0)

Definition at line 418 of file rs6000.h.

#define BASE_REG_CLASS   BASE_REGS

Definition at line 1148 of file rs6000.h.

#define BIGGEST_ALIGNMENT   128

Definition at line 624 of file rs6000.h.

#define BITS_BIG_ENDIAN   1

Definition at line 512 of file rs6000.h.

#define BITS_PER_UNIT   8

Definition at line 526 of file rs6000.h.

#define BITS_PER_WORD   (! TARGET_POWERPC64 ? 32 : 64)

Definition at line 532 of file rs6000.h.

#define BRANCH_COST   3

Definition at line 943 of file rs6000.h.

#define BUILD_VA_LIST_TYPE

(

VALIST

)

(VALIST) = rs6000_build_va_list ()

Definition at line 1711 of file rs6000.h.

#define BYTES_BIG_ENDIAN   1

Definition at line 516 of file rs6000.h.

#define CALL_LONG   0x00000008

Definition at line 1536 of file rs6000.h.

#define CALL_NORMAL   0x00000000

Definition at line 1532 of file rs6000.h.

#define CALL_REALLY_USED_REGISTERS

Value:

{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1,    \
   /* AltiVec registers.  */         \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0               \
}

Definition at line 743 of file rs6000.h.

#define CALL_USED_REGISTERS

Value:

{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1,    \
   /* AltiVec registers.  */         \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1               \
}

Definition at line 725 of file rs6000.h.

#define CALL_V4_CLEAR_FP_ARGS   0x00000002

Definition at line 1534 of file rs6000.h.

Referenced by function_arg().

#define CALL_V4_SET_FP_ARGS   0x00000004

Definition at line 1535 of file rs6000.h.

Referenced by function_arg().

#define CAN_DEBUG_WITHOUT_FP

Definition at line 482 of file rs6000.h.

#define CAN_ELIMINATE	(	FROM,
		TO		)

Value:

((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
  ? ! frame_pointer_needed          \
  : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
  : 1)

Definition at line 1832 of file rs6000.h.

#define CASE_VECTOR_MODE   SImode

Definition at line 2159 of file rs6000.h.

#define CASE_VECTOR_PC_RELATIVE   1

Definition at line 2165 of file rs6000.h.

#define CHAR_TYPE_SIZE   BITS_PER_UNIT

Definition at line 579 of file rs6000.h.

#define CLASS_CANNOT_CHANGE_MODE   FLOAT_REGS

Definition at line 1279 of file rs6000.h.

#define CLASS_CANNOT_CHANGE_MODE_P	(	FROM,
		TO		)	(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))

Definition at line 1283 of file rs6000.h.

#define CLASS_MAX_NREGS	(	CLASS,
		MODE		)

Value:

(((CLASS) == FLOAT_REGS)            \
  ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
  : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

Definition at line 1271 of file rs6000.h.

#define CONDITIONAL_REGISTER_USAGE

Definition at line 951 of file rs6000.h.

#define CONST_COSTS	(	RTX,
		CODE,
		OUTER_CODE		)

Value:

case CONST_INT:           \
  case CONST:             \
  case LABEL_REF:           \
  case SYMBOL_REF:            \
  case CONST_DOUBLE:            \
  case HIGH:              \
    return 0;

Definition at line 2233 of file rs6000.h.

#define CONST_DOUBLE_OK_FOR_LETTER_P	(	VALUE,
		C		)

Value:

(  (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE))   \
       == ((GET_MODE (VALUE) == SFmode) ? 1 : 2))   \
   : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
   : 0)

Definition at line 1200 of file rs6000.h.

#define CONST_OK_FOR_LETTER_P	(	VALUE,
		C		)

Value:

( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000  \
   : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
   : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0   \
   : (C) == 'L' ? (((VALUE) & 0xffff) == 0        \
       && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0))  \
   : (C) == 'M' ? (VALUE) > 31            \
   : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0    \
   : (C) == 'O' ? (VALUE) == 0            \
   : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
   : 0)

Definition at line 1180 of file rs6000.h.

#define CONSTANT_ADDRESS_P

(

X

)

Value:

(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF    \
   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST    \
   || GET_CODE (X) == HIGH)

Definition at line 1890 of file rs6000.h.

#define CONSTANT_ALIGNMENT	(	EXP,
		ALIGN		)

Value:

(TREE_CODE (EXP) == STRING_CST                           \
   && (ALIGN) < BITS_PER_WORD                                    \
   ? BITS_PER_WORD                                               \
   : (ALIGN))

Definition at line 643 of file rs6000.h.

#define CONSTANT_POOL_EXPR_P

(

X

)

(constant_pool_expr_p (X))

Definition at line 1961 of file rs6000.h.

Referenced by rs6000_emit_move(), rs6000_legitimize_address(), and rs6000_legitimize_reload_address().

#define COUNT_REGISTER_REGNUM   66

Definition at line 1014 of file rs6000.h.

Referenced by call_operand(), count_register_operand(), handle_syscall(), print_operand(), and rs6000_dbx_register_number().

#define CPP_CPU_SPEC   "%{!mcpu*: \ %{mpower: %{!mpower2: -D_ARCH_PWR}} \ %{mpower2: -D_ARCH_PWR2} \ %{mpowerpc*: -D_ARCH_PPC} \ %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \ %{!mno-power: %{!mpower2: %(cpp_default)}}} \%{mcpu=common: -D_ARCH_COM} \%{mcpu=power: -D_ARCH_PWR} \%{mcpu=power2: -D_ARCH_PWR2} \%{mcpu=powerpc: -D_ARCH_PPC} \%{mcpu=rios: -D_ARCH_PWR} \%{mcpu=rios1: -D_ARCH_PWR} \%{mcpu=rios2: -D_ARCH_PWR2} \%{mcpu=rsc: -D_ARCH_PWR} \%{mcpu=rsc1: -D_ARCH_PWR} \%{mcpu=401: -D_ARCH_PPC} \%{mcpu=403: -D_ARCH_PPC} \%{mcpu=405: -D_ARCH_PPC} \%{mcpu=505: -D_ARCH_PPC} \%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \%{mcpu=602: -D_ARCH_PPC} \%{mcpu=603: -D_ARCH_PPC} \%{mcpu=603e: -D_ARCH_PPC} \%{mcpu=ec603e: -D_ARCH_PPC} \%{mcpu=604: -D_ARCH_PPC} \%{mcpu=604e: -D_ARCH_PPC} \%{mcpu=620: -D_ARCH_PPC} \%{mcpu=740: -D_ARCH_PPC} \%{mcpu=7400: -D_ARCH_PPC} \%{mcpu=7450: -D_ARCH_PPC} \%{mcpu=750: -D_ARCH_PPC} \%{mcpu=801: -D_ARCH_PPC} \%{mcpu=821: -D_ARCH_PPC} \%{mcpu=823: -D_ARCH_PPC} \%{mcpu=860: -D_ARCH_PPC} \%{maltivec: -D__ALTIVEC__}"

Definition at line 51 of file rs6000.h.

#define CPP_DEFAULT_SPEC   ""

Definition at line 129 of file rs6000.h.

#define CR0_REGNO   68

Definition at line 756 of file rs6000.h.

Referenced by and64_2_operand(), and64_operand(), and_operand(), ccr_bit(), output_cbranch(), output_e500_flip_gt_bit(), print_operand(), rs6000_dbx_register_number(), rs6000_emit_epilogue(), rs6000_split_atomic_op(), rs6000_split_compare_and_swap(), rs6000_split_compare_and_swapqhi(), and rs6000_split_lock_test_and_set().

#define CR1_REGNO   69

Definition at line 757 of file rs6000.h.

Referenced by setup_incoming_varargs().

#define CR2_REGNO   70

Definition at line 758 of file rs6000.h.

Referenced by handle_syscall(), interpret_libc(), ppc_fallback_frame_state(), restore_world_operation(), rs6000_emit_epilogue(), rs6000_emit_prologue(), rs6000_stack_info(), and save_world_operation().

#define CR3_REGNO   71

Definition at line 759 of file rs6000.h.

Referenced by rs6000_stack_info().

#define CR4_REGNO   72

Definition at line 760 of file rs6000.h.

Referenced by rs6000_stack_info().

#define CR_REGNO_NOT_CR0_P

(

N

)

((N) >= 69 && (N) <= 75)

Definition at line 830 of file rs6000.h.

Referenced by cc_reg_not_cr0_operand().

#define CR_REGNO_P

(

N

)

((N) >= 68 && (N) <= 75)

Definition at line 827 of file rs6000.h.

Referenced by cc_reg_operand(), ccr_bit(), mfcr_operation(), mtcrf_operation(), output_e500_flip_gt_bit(), print_operand(), rs6000_dbx_register_number(), rs6000_hard_regno_mode_ok(), rs6000_secondary_reload_class(), and secondary_reload_class().

#define DATA_ALIGNMENT	(	TYPE,
		ALIGN		)

Value:

(TREE_CODE (TYPE) == VECTOR_TYPE ? 128  \
   : TREE_CODE (TYPE) == ARRAY_TYPE   \
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode  \
   && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))

Definition at line 651 of file rs6000.h.

#define DEBUG_REGISTER_NAMES

Value:

{                 \
     "r0", "r1",   "r2",  "r3",  "r4",  "r5",  "r6",  "r7",   \
     "r8", "r9",  "r10", "r11", "r12", "r13", "r14", "r15",   \
    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",   \
    "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",   \
     "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",   \
     "f8",  "f9", "f10", "f11", "f12", "f13", "f14", "f15",   \
    "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",   \
    "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",   \
     "mq",  "lr", "ctr",  "ap",           \
    "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",   \
  "xer",                \
     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",             \
     "v8",  "v9", "v10", "v11", "v12", "v13", "v14", "v15",             \
    "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",             \
    "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",             \
    "vrsave"                \
}

Definition at line 2642 of file rs6000.h.

#define DEFAULT_PCC_STRUCT_RETURN   0

Definition at line 1496 of file rs6000.h.

#define DEFAULT_SIGNED_CHAR   0

Definition at line 2168 of file rs6000.h.

#define DOUBLE_TYPE_SIZE   64

Definition at line 589 of file rs6000.h.

#define DRAFT_V4_STRUCT_RET   0

Definition at line 1493 of file rs6000.h.

#define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)

Definition at line 2733 of file rs6000.h.

#define EH_RETURN_DATA_REGNO

(

N

)

((N) < 4 ? (N) + 3 : INVALID_REGNUM)

Definition at line 2736 of file rs6000.h.

#define EH_RETURN_STACKADJ_RTX   gen_rtx_REG (Pmode, 10)

Definition at line 2737 of file rs6000.h.

#define ELIMINABLE_REGS

Value:

{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
 { 30, 30} }

Definition at line 1817 of file rs6000.h.

#define EMPTY_FIELD_BOUNDARY   32

Definition at line 633 of file rs6000.h.

#define EPILOGUE_USES

(

REGNO

)

Value:

((reload_completed && (REGNO) == LINK_REGISTER_REGNUM)  \
   || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO)   \
   || (current_function_calls_eh_return       \
       && TARGET_AIX            \
       && (REGNO) == TOC_REGISTER))

Definition at line 1753 of file rs6000.h.

#define EXIT_IGNORE_STACK   1

Definition at line 1746 of file rs6000.h.

#define EXPAND_BUILTIN_VA_ARG	(	valist,
		type		)	rs6000_va_arg (valist, type)

Definition at line 1719 of file rs6000.h.

#define EXPAND_BUILTIN_VA_START	(	stdarg,
		valist,
		nextarg		)	rs6000_va_start (stdarg, valist, nextarg)

Definition at line 1715 of file rs6000.h.

#define EXTRA_CC_MODES

Value:

CC(CCUNSmode,  "CCUNS") \
    CC(CCFPmode,   "CCFP")  \
    CC(CCEQmode,   "CCEQ")

Definition at line 2378 of file rs6000.h.

#define EXTRA_CONSTRAINT	(	OP,
		C		)

Value:

((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG  \
   : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP)   \
   : (C) == 'S' ? mask64_operand (OP, DImode)       \
   : (C) == 'T' ? mask_operand (OP, SImode)       \
   : (C) == 'U' ? (DEFAULT_ABI == ABI_V4        \
       && small_data_operand (OP, GET_MODE (OP)))   \
   : 0)

Definition at line 1214 of file rs6000.h.

#define EXTRA_SPECS

Value:

{ "cpp_cpu",      CPP_CPU_SPEC },       \
  { "cpp_default",    CPP_DEFAULT_SPEC },     \
  { "asm_cpu",      ASM_CPU_SPEC },       \
  { "asm_default",    ASM_DEFAULT_SPEC },     \
  SUBTARGET_EXTRA_SPECS

Definition at line 145 of file rs6000.h.

#define FIRST_ALTIVEC_REGNO   77

Definition at line 763 of file rs6000.h.

Referenced by compute_vrsave_mask(), first_altivec_reg_to_save(), generate_set_vrsave(), handle_syscall(), ppc_fallback_frame_state(), rs6000_conditional_register_usage(), rs6000_dbx_register_number(), and rs6000_memory_move_cost().

#define FIRST_PARM_OFFSET

(

FNDECL

)

RS6000_SAVE_AREA

Definition at line 1413 of file rs6000.h.

#define FIRST_PSEUDO_REGISTER   110

Definition at line 691 of file rs6000.h.

#define FIXED_REGISTERS

Value:

{0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1,    \
   /* AltiVec registers.  */         \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
   1               \
}

Definition at line 706 of file rs6000.h.

#define FLOAT_TYPE_SIZE   32

Definition at line 584 of file rs6000.h.

#define FP_ARG_AIX_MAX_REG   45

Definition at line 1513 of file rs6000.h.

#define FP_ARG_MAX_REG

Value:

((DEFAULT_ABI == ABI_AIX        \
       || DEFAULT_ABI == ABI_AIX_NODESC   \
       || DEFAULT_ABI == ABI_DARWIN)      \
      ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)

Definition at line 1515 of file rs6000.h.

Referenced by function_arg(), and rs6000_arg_partial_bytes().

#define FP_ARG_MIN_REG   33

Definition at line 1512 of file rs6000.h.

Referenced by function_arg(), init_cumulative_args(), rs6000_function_value(), rs6000_return_in_memory(), rs6000_va_start(), and setup_incoming_varargs().

#define FP_ARG_NUM_REG   (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)

Definition at line 1519 of file rs6000.h.

Referenced by rs6000_va_start(), s390_function_arg(), s390_gimplify_va_arg(), s390_register_info(), s390_va_start(), and save_fpr().

#define FP_ARG_RETURN   FP_ARG_MIN_REG

Definition at line 1528 of file rs6000.h.

Referenced by rs6000_complex_function_value(), rs6000_function_value(), and rs6000_libcall_value().

#define FP_ARG_V4_MAX_REG   40

Definition at line 1514 of file rs6000.h.

Referenced by function_arg(), function_arg_advance(), rs6000_va_start(), and setup_incoming_varargs().

#define FP_REGNO_P

(

N

)

((N) >= 32 && (N) <= 63)

Definition at line 824 of file rs6000.h.

#define FRAME_POINTER_REGNUM   31

Definition at line 996 of file rs6000.h.

#define FRAME_POINTER_REQUIRED   0

Definition at line 1002 of file rs6000.h.

#define FUNCTION_ARG	(	CUM,
		MODE,
		TYPE,
		NAMED		)	function_arg (&CUM, MODE, TYPE, NAMED)

Definition at line 1659 of file rs6000.h.

#define FUNCTION_ARG_ADVANCE	(	CUM,
		MODE,
		TYPE,
		NAMED		)	function_arg_advance (&CUM, MODE, TYPE, NAMED)

Definition at line 1622 of file rs6000.h.

#define FUNCTION_ARG_BOUNDARY	(	MODE,
		TYPE		)	function_arg_boundary (MODE, TYPE)

Definition at line 1690 of file rs6000.h.

#define FUNCTION_ARG_PADDING	(	MODE,
		TYPE		)	function_arg_padding (MODE, TYPE)

Definition at line 1684 of file rs6000.h.

#define FUNCTION_ARG_PARTIAL_NREGS	(	CUM,
		MODE,
		TYPE,
		NAMED		)	function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)

Definition at line 1666 of file rs6000.h.

#define FUNCTION_ARG_PASS_BY_REFERENCE	(	CUM,
		MODE,
		TYPE,
		NAMED		)	function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)

Definition at line 1675 of file rs6000.h.

#define FUNCTION_ARG_REGNO_P

(

N

)

Value:

(((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG))  \
   || (TARGET_ALTIVEC &&            \
       (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \
   || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))

Definition at line 1550 of file rs6000.h.

#define FUNCTION_BOUNDARY   32

Definition at line 621 of file rs6000.h.

#define FUNCTION_MODE   (TARGET_32BIT ? SImode : DImode)

Definition at line 2209 of file rs6000.h.

#define FUNCTION_PROFILER	(	FILE,
		LABELNO		)	output_function_profiler ((FILE), (LABELNO));

Definition at line 1737 of file rs6000.h.

#define FUNCTION_VALUE	(	VALTYPE,
		FUNC		)

Value:

gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE)     \
    && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD)  \
         || POINTER_TYPE_P (VALTYPE)      \
         ? word_mode : TYPE_MODE (VALTYPE),   \
         TREE_CODE (VALTYPE) == VECTOR_TYPE ? ALTIVEC_ARG_RETURN \
         : TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
               ? FP_ARG_RETURN : GP_ARG_RETURN)

Definition at line 1456 of file rs6000.h.

#define FUNCTION_VALUE_REGNO_P

(

N

)

Value:

((N) == GP_ARG_RETURN \
            || ((N) == FP_ARG_RETURN) \
            || (TARGET_ALTIVEC && \
          (N) == ALTIVEC_ARG_RETURN))

Definition at line 1542 of file rs6000.h.

#define GO_IF_LEGITIMATE_ADDRESS	(	MODE,
		X,
		ADDR		)

Value:

{ if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG))  \
    goto ADDR;              \
}

Definition at line 2022 of file rs6000.h.

#define GO_IF_MODE_DEPENDENT_ADDRESS	(	ADDR,
		LABEL		)

Value:

{ if (GET_CODE (ADDR) == PLUS         \
      && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
      && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1),  \
           (TARGET_32BIT ? 4 : 8))) \
    goto LABEL;             \
  if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC)    \
    goto LABEL;             \
  if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC)    \
    goto LABEL;             \
  if (GET_CODE (ADDR) == LO_SUM)        \
    goto LABEL;             \
}

Definition at line 2084 of file rs6000.h.

#define GP_ARG_MAX_REG   10

Definition at line 1508 of file rs6000.h.

Referenced by function_arg(), function_arg_advance(), and rs6000_spe_function_arg().

#define GP_ARG_MIN_REG   3

Definition at line 1507 of file rs6000.h.

Referenced by function_arg(), init_cumulative_args(), rs6000_darwin64_record_arg_flush(), rs6000_mixed_function_arg(), rs6000_va_start(), and setup_incoming_varargs().

#define GP_ARG_NUM_REG   (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)

Definition at line 1509 of file rs6000.h.

Referenced by function_arg(), function_arg_partial_nregs(), rs6000_arg_partial_bytes(), rs6000_darwin64_record_arg_flush(), rs6000_mixed_function_arg(), rs6000_va_start(), s390_function_arg(), s390_gimplify_va_arg(), s390_register_info(), s390_va_start(), and setup_incoming_varargs().

#define GP_ARG_RETURN   GP_ARG_MIN_REG

Definition at line 1527 of file rs6000.h.

Referenced by rs6000_complex_function_value(), rs6000_function_value(), and rs6000_libcall_value().

#define HARD_REGNO_MODE_OK	(	REGNO,
		MODE		)

Value:

(FP_REGNO_P (REGNO) ?             \
   (GET_MODE_CLASS (MODE) == MODE_FLOAT         \
    || (GET_MODE_CLASS (MODE) == MODE_INT       \
  && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD))      \
   : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE)   \
   : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC    \
   : XER_REGNO_P (REGNO) ? (MODE) == PSImode        \
   : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT   \
            && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
   : 1)

Definition at line 875 of file rs6000.h.

#define HARD_REGNO_NREGS	(	REGNO,
		MODE		)

Value:

(FP_REGNO_P (REGNO)             \
   ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
   : ALTIVEC_REGNO_P (REGNO)            \
   ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

Definition at line 849 of file rs6000.h.

#define HAVE_PRE_DECREMENT   1

Definition at line 1861 of file rs6000.h.

#define HAVE_PRE_INCREMENT   1

Definition at line 1862 of file rs6000.h.

#define INCOMING_RETURN_ADDR_RTX   gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)

Definition at line 2732 of file rs6000.h.

#define INDEX_REG_CLASS   GENERAL_REGS

Definition at line 1147 of file rs6000.h.

#define INIT_CUMULATIVE_ARGS	(	CUM,
		FNTYPE,
		LIBNAME,
		INDIRECT		)	init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)

Definition at line 1609 of file rs6000.h.

#define INIT_CUMULATIVE_INCOMING_ARGS	(	CUM,
		FNTYPE,
		LIBNAME		)	init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)

Definition at line 1615 of file rs6000.h.

#define INITIAL_ELIMINATION_OFFSET	(	FROM,
		TO,
		OFFSET		)

Value:

{                 \
  rs6000_stack_t *info = rs6000_stack_info ();        \
                  \
 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM)  \
   (OFFSET) = (info->push_p) ? 0 : - info->total_size;      \
 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
   (OFFSET) = info->total_size;           \
 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
   (OFFSET) = (info->push_p) ? info->total_size : 0;      \
  else if ((FROM) == 30)            \
    (OFFSET) = 0;             \
  else                  \
    abort ();               \
}

Definition at line 1840 of file rs6000.h.

#define INITIALIZE_TRAMPOLINE	(	ADDR,
		FNADDR,
		CXT		)	rs6000_initialize_trampoline (ADDR, FNADDR, CXT)

Definition at line 1771 of file rs6000.h.

#define INT_REG_OK_FOR_BASE_P	(	X,
		STRICT		)	(REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))

Definition at line 1937 of file rs6000.h.

Referenced by legitimate_indexed_address_p(), legitimate_indirect_address_p(), legitimate_lo_sum_address_p(), macho_lo_sum_memory_operand(), and rs6000_legitimate_offset_address_p().

#define INT_REG_OK_FOR_INDEX_P	(	X,
		STRICT		)

Value:

((! (STRICT)              \
    && (REGNO (X) <= 31           \
  || REGNO (X) == ARG_POINTER_REGNUM      \
  || REGNO (X) >= FIRST_PSEUDO_REGISTER))     \
   || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))

Definition at line 1928 of file rs6000.h.

Referenced by legitimate_indexed_address_p().

#define INT_REGNO_P

(

N

)

((N) <= 31 || (N) == ARG_POINTER_REGNUM)

Definition at line 833 of file rs6000.h.

Referenced by gpr_or_gpr_p(), mfcr_operation(), mtcrf_operation(), rs6000_hard_regno_mode_ok(), rs6000_secondary_reload_class(), rs6000_split_multireg_move(), and secondary_reload_class().

#define INT_TYPE_SIZE   32

Definition at line 562 of file rs6000.h.

#define LAST_ALTIVEC_REGNO   108

Definition at line 764 of file rs6000.h.

Referenced by compute_vrsave_mask(), debug_stack_info(), direct_return(), first_altivec_reg_to_save(), generate_set_vrsave(), rs6000_conditional_register_usage(), rs6000_emit_epilogue(), rs6000_emit_prologue(), and rs6000_stack_info().

#define LEGITIMATE_ADDRESS_INTEGER_P	(	X,
		OFFSET		)

Value:

(GET_CODE (X) == CONST_INT            \
  && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)

Definition at line 1978 of file rs6000.h.

#define LEGITIMATE_CONSTANT_P

(

X

)

Value:

(GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
   || (TARGET_POWERPC64 && GET_MODE (X) == DImode)    \
   || easy_fp_constant (X, GET_MODE (X)))

Definition at line 1902 of file rs6000.h.

#define LEGITIMATE_CONSTANT_POOL_ADDRESS_P

(

X

)

Value:

(TARGET_TOC               \
  && GET_CODE (X) == PLUS           \
  && GET_CODE (XEXP (X, 0)) == REG          \
  && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER)  \
  && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))

Definition at line 1965 of file rs6000.h.

Referenced by input_operand(), print_operand_address(), rs6000_emit_move(), and rs6000_legitimate_address().

#define LEGITIMATE_INDEXED_ADDRESS_P	(	X,
		STRICT		)

Value:

(GET_CODE (X) == PLUS           \
  && GET_CODE (XEXP (X, 0)) == REG        \
  && GET_CODE (XEXP (X, 1)) == REG        \
  && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT))    \
       && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
      || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT))   \
    && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))

Definition at line 1999 of file rs6000.h.

Referenced by print_operand(), and rs6000_legitimate_address().

#define LEGITIMATE_INDIRECT_ADDRESS_P	(	X,
		STRICT		)	(GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))

Definition at line 2008 of file rs6000.h.

Referenced by lmw_operation(), rs6000_legitimate_address(), and stmw_operation().

#define LEGITIMATE_LO_SUM_ADDRESS_P	(	MODE,
		X,
		STRICT		)

Value:

(TARGET_ELF           \
   && ! flag_pic && ! TARGET_TOC      \
   && GET_MODE_NUNITS (MODE) == 1     \
   && (GET_MODE_BITSIZE (MODE) <= 32      \
       || (TARGET_HARD_FLOAT && (MODE) == DFmode))  \
   && GET_CODE (X) == LO_SUM        \
   && GET_CODE (XEXP (X, 0)) == REG     \
   && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
   && CONSTANT_P (XEXP (X, 1)))

Definition at line 2011 of file rs6000.h.

#define LEGITIMATE_OFFSET_ADDRESS_P	(	MODE,
		X,
		STRICT		)

Value:

(GET_CODE (X) == PLUS           \
  && GET_CODE (XEXP (X, 0)) == REG        \
  && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT))    \
  && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0)    \
  && (! ALTIVEC_VECTOR_MODE (MODE)                            \
      || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \
  && (((MODE) != DFmode && (MODE) != DImode)      \
      || (TARGET_32BIT            \
    ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4)   \
    : ! (INTVAL (XEXP (X, 1)) & 3)))      \
  && ((MODE) != TImode            \
      || (TARGET_32BIT            \
    ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12)  \
    : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8)  \
       && ! (INTVAL (XEXP (X, 1)) & 3)))))

Definition at line 1982 of file rs6000.h.

#define LEGITIMATE_SMALL_DATA_P	(	MODE,
		X		)

Value:

(DEFAULT_ABI == ABI_V4            \
   && !flag_pic && !TARGET_TOC            \
   && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST)   \
   && small_data_operand (X, MODE))

Definition at line 1972 of file rs6000.h.

Referenced by rs6000_legitimate_address().

#define LEGITIMIZE_ADDRESS	(	X,
		OLDX,
		MODE,
		WIN		)

Value:

{  rtx result = rs6000_legitimize_address (X, OLDX, MODE);  \
   if (result != NULL_RTX)          \
     {                \
       (X) = result;            \
       goto WIN;            \
     }                \
}

Definition at line 2050 of file rs6000.h.

#define LEGITIMIZE_RELOAD_ADDRESS	(	X,
		MODE,
		OPNUM,
		TYPE,
		IND_LEVELS,
		WIN		)

Value:

do {                       \
  int win;                     \
  (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM),        \
      (int)(TYPE), (IND_LEVELS), &win);        \
  if ( win )                     \
    goto WIN;                    \
} while (0)

Definition at line 2066 of file rs6000.h.

#define LIBCALL_VALUE

(

MODE

)

Value:

gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN  \
         : GET_MODE_CLASS (MODE) == MODE_FLOAT    \
         && TARGET_HARD_FLOAT       \
         ? FP_ARG_RETURN : GP_ARG_RETURN)

Definition at line 1468 of file rs6000.h.

#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE   64

Definition at line 604 of file rs6000.h.

#define LINK_REGISTER_REGNUM   65

Definition at line 1011 of file rs6000.h.

Referenced by call_operand(), frob_update_context(), handle_syscall(), output_profile_hook(), ppc_fallback_frame_state(), print_operand(), rs6000_dbx_register_number(), rs6000_emit_eh_reg_restore(), rs6000_emit_epilogue(), rs6000_emit_load_toc_table(), rs6000_emit_prologue(), rs6000_output_mi_thunk(), rs6000_ra_ever_killed(), rs6000_return_addr(), and rs6000_stack_info().

#define LOAD_EXTEND_OP

(

MODE

)

ZERO_EXTEND

Definition at line 2193 of file rs6000.h.

#define LOCAL_ALIGNMENT	(	TYPE,
		ALIGN		)	((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : ALIGN)

Definition at line 629 of file rs6000.h.

#define LONG_DOUBLE_TYPE_SIZE   rs6000_long_double_type_size

Definition at line 594 of file rs6000.h.

#define LONG_LONG_TYPE_SIZE   64

Definition at line 573 of file rs6000.h.

#define LONG_TYPE_SIZE   (TARGET_32BIT ? 32 : 64)

Definition at line 567 of file rs6000.h.

#define MASK_64BIT   0x00000400

Definition at line 195 of file rs6000.h.

#define MASK_AIX_STRUCT_RET   0x00100000

Definition at line 221 of file rs6000.h.

Referenced by rs6000_override_options().

#define MASK_AIX_STRUCT_RET_SET   0x00200000

Definition at line 222 of file rs6000.h.

Referenced by rs6000_override_options().

#define MASK_ALTIVEC   0x00080000

Definition at line 218 of file rs6000.h.

Referenced by altivec_init_builtins(), and rs6000_override_options().

#define MASK_MINIMAL_TOC   0x00000200

Definition at line 192 of file rs6000.h.

Referenced by rs6000_handle_option().

#define MASK_MULTIPLE   0x00001000

Definition at line 201 of file rs6000.h.

Referenced by rs6000_handle_option(), and rs6000_override_options().

#define MASK_MULTIPLE_SET   0x00002000

Definition at line 202 of file rs6000.h.

#define MASK_NEW_MNEMONICS   0x00000040

Definition at line 175 of file rs6000.h.

Referenced by rs6000_override_options().

#define MASK_NO_FP_IN_TOC   0x00000080

Definition at line 179 of file rs6000.h.

#define MASK_NO_FUSED_MADD   0x00020000

Definition at line 212 of file rs6000.h.

#define MASK_NO_SUM_IN_TOC   0x00000100

Definition at line 183 of file rs6000.h.

#define MASK_NO_UPDATE   0x00010000

Definition at line 209 of file rs6000.h.

#define MASK_POWER   0x00000001

Definition at line 157 of file rs6000.h.

Referenced by rs6000_handle_option(), and rs6000_override_options().

#define MASK_POWER2   0x00000002

Definition at line 160 of file rs6000.h.

Referenced by rs6000_handle_option(), and rs6000_override_options().

#define MASK_POWERPC   0x00000004

Definition at line 163 of file rs6000.h.

Referenced by rs6000_handle_option(), and rs6000_override_options().

#define MASK_POWERPC64   0x00000020

Definition at line 172 of file rs6000.h.

Referenced by rs6000_handle_option(), and rs6000_override_options().

#define MASK_PPC_GFXOPT   0x00000010

Definition at line 169 of file rs6000.h.

Referenced by rs6000_handle_option(), and rs6000_override_options().

#define MASK_PPC_GPOPT   0x00000008

Definition at line 166 of file rs6000.h.

Referenced by rs6000_handle_option(), and rs6000_override_options().

#define MASK_SCHED_PROLOG   0x00040000

Definition at line 215 of file rs6000.h.

#define MASK_SOFT_FLOAT   0x00000800

Definition at line 198 of file rs6000.h.

#define MASK_STRING   0x00004000

Definition at line 205 of file rs6000.h.

Referenced by rs6000_handle_option(), and rs6000_override_options().

#define MASK_STRING_SET   0x00008000

Definition at line 206 of file rs6000.h.

#define MAX_BITS_PER_WORD   64

Definition at line 533 of file rs6000.h.

#define MAX_CR_REGNO   75

Definition at line 761 of file rs6000.h.

Referenced by mfcr_operation(), and mtcrf_operation().

#define MAX_LONG_DOUBLE_TYPE_SIZE   128

Definition at line 597 of file rs6000.h.

#define MAX_LONG_TYPE_SIZE   64

Definition at line 568 of file rs6000.h.

#define MAX_MOVE_MAX   8

Definition at line 2178 of file rs6000.h.

#define MAX_REGS_PER_ADDRESS   2

Definition at line 1886 of file rs6000.h.

#define MEMORY_MOVE_COST	(	MODE,
		CLASS,
		IN		)

Value:

((GET_MODE_CLASS (MODE) == MODE_FLOAT   \
    && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
    ? 3 : 2) \
   + 4)

Definition at line 931 of file rs6000.h.

#define MIN_UNITS_PER_WORD   4

Definition at line 537 of file rs6000.h.

#define MODES_TIEABLE_P	(	MODE1,
		MODE2		)

Value:

(GET_MODE_CLASS (MODE1) == MODE_FLOAT   \
   ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
   : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
   ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
   : GET_MODE_CLASS (MODE1) == MODE_CC    \
   ? GET_MODE_CLASS (MODE2) == MODE_CC    \
   : GET_MODE_CLASS (MODE2) == MODE_CC    \
   ? GET_MODE_CLASS (MODE1) == MODE_CC    \
   : ALTIVEC_VECTOR_MODE (MODE1)    \
   ? ALTIVEC_VECTOR_MODE (MODE2)    \
   : ALTIVEC_VECTOR_MODE (MODE2)    \
   ? ALTIVEC_VECTOR_MODE (MODE1)    \
   : 1)

Definition at line 891 of file rs6000.h.

#define MOVE_MAX   (! TARGET_POWERPC64 ? 4 : 8)

Definition at line 2177 of file rs6000.h.

#define MQ_REGNO   64

Definition at line 755 of file rs6000.h.

Referenced by gpc_reg_operand(), and rs6000_dbx_register_number().

#define N_REG_CLASSES   (int) LIM_REG_CLASSES

Definition at line 1074 of file rs6000.h.

#define NO_FUNCTION_CSE

Definition at line 2215 of file rs6000.h.

#define OBJECT_ELF   2

Definition at line 31 of file rs6000.h.

#define OBJECT_MACHO   4

Definition at line 33 of file rs6000.h.

#define OBJECT_PEF   3

Definition at line 32 of file rs6000.h.

#define OBJECT_XCOFF   1

Definition at line 30 of file rs6000.h.

#define OPTIMIZATION_OPTIONS	(	LEVEL,
		SIZE		)	optimization_options(LEVEL,SIZE)

Definition at line 479 of file rs6000.h.

#define OUTGOING_REG_PARM_STACK_SPACE

Definition at line 1427 of file rs6000.h.

#define OVERRIDE_OPTIONS   rs6000_override_options (TARGET_CPU_DEFAULT)

Definition at line 476 of file rs6000.h.

#define PAD_VARARGS_DOWN   (TYPE_MODE (type) != BLKmode)

Definition at line 1728 of file rs6000.h.

#define PARM_BOUNDARY   (TARGET_32BIT ? 32 : 64)

Definition at line 615 of file rs6000.h.

#define PCC_BITFIELD_TYPE_MATTERS   1

Definition at line 639 of file rs6000.h.

#define PIC_OFFSET_TABLE_REGNUM   (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)

Definition at line 2107 of file rs6000.h.

#define Pmode   (TARGET_32BIT ? SImode : DImode)

Definition at line 2205 of file rs6000.h.

#define POINTER_SIZE   (TARGET_32BIT ? 32 : 64)

Definition at line 612 of file rs6000.h.

#define PRE_GCC3_DWARF_FRAME_REGISTERS   77

Definition at line 694 of file rs6000.h.

Referenced by __frame_state_for().

#define PREDICATE_CODES

Definition at line 2756 of file rs6000.h.

#define PREFERRED_RELOAD_CLASS	(	X,
		CLASS		)

Value:

(((GET_CODE (X) == CONST_DOUBLE     \
     && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT)  \
    ? NO_REGS             \
    : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT  \
       && (CLASS) == NON_SPECIAL_REGS)      \
    ? GENERAL_REGS          \
    : (CLASS)))

Definition at line 1241 of file rs6000.h.

#define PRINT_OPERAND	(	FILE,
		X,
		CODE		)	print_operand (FILE, X, CODE)

Definition at line 2743 of file rs6000.h.

#define PRINT_OPERAND_ADDRESS	(	FILE,
		ADDR		)	print_operand_address (FILE, ADDR)

Definition at line 2752 of file rs6000.h.

#define PRINT_OPERAND_PUNCT_VALID_P

(

CODE

)

((CODE) == '.')

Definition at line 2747 of file rs6000.h.

#define PROCESSOR_COMMON   PROCESSOR_PPC601

Definition at line 407 of file rs6000.h.

Referenced by rs6000_override_options().

#define PROCESSOR_DEFAULT   PROCESSOR_RIOS1

Definition at line 413 of file rs6000.h.

#define PROCESSOR_DEFAULT64   PROCESSOR_RS64A

Definition at line 414 of file rs6000.h.

Referenced by rs6000_override_options().

#define PROCESSOR_POWER   PROCESSOR_RIOS1

Definition at line 408 of file rs6000.h.

Referenced by rs6000_override_options().

#define PROCESSOR_POWERPC   PROCESSOR_PPC604

Definition at line 409 of file rs6000.h.

Referenced by rs6000_override_options().

#define PROCESSOR_POWERPC64   PROCESSOR_RS64A

Definition at line 410 of file rs6000.h.

Referenced by rs6000_override_options().

#define PROMOTE_FUNCTION_ARGS

Definition at line 503 of file rs6000.h.

#define PROMOTE_FUNCTION_RETURN

Definition at line 507 of file rs6000.h.

#define PROMOTE_MODE	(	MODE,
		UNSIGNEDP,
		TYPE		)

Value:

if (GET_MODE_CLASS (MODE) == MODE_INT   \
      && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
    (MODE) = word_mode;

Definition at line 495 of file rs6000.h.

#define PTRDIFF_TYPE   "int"

Definition at line 542 of file rs6000.h.

#define REAL_ARITHMETIC

Definition at line 487 of file rs6000.h.

#define REG_ALLOC_ORDER

Value:

{32,              \
   45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34,  \
   33,              \
   63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51,  \
   50, 49, 48, 47, 46,          \
   75, 74, 69, 68, 72, 71, 70,        \
   0,             \
   9, 11, 10, 8, 7, 6, 5, 4,        \
   3,             \
   31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19,  \
   18, 17, 16, 15, 14, 13, 12,        \
   64, 66, 65,            \
   73, 1, 2, 67, 76,          \
   /* AltiVec registers.  */        \
   77, 78,            \
   90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80,    \
   79,              \
   96, 95, 94, 93, 92, 91,        \
   108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
   97, 109            \
}

Definition at line 800 of file rs6000.h.

#define REG_CLASS_CONTENTS

Value:

{                      \
  { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */      \
  { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */      \
  { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */     \
  { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */       \
  { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */     \
  { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */      \
  { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
  { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */      \
  { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */      \
  { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */       \
  { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
  { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */     \
  { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
  { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */       \
  { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */      \
  { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */   \
  { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */       \
  { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff }  /* ALL_REGS */       \
}

Definition at line 1104 of file rs6000.h.

#define REG_CLASS_FROM_LETTER

(

C

)

Value:

((C) == 'f' ? FLOAT_REGS  \
   : (C) == 'b' ? BASE_REGS \
   : (C) == 'h' ? SPECIAL_REGS  \
   : (C) == 'q' ? MQ_REGS \
   : (C) == 'c' ? CTR_REGS  \
   : (C) == 'l' ? LINK_REGS \
   : (C) == 'v' ? ALTIVEC_REGS  \
   : (C) == 'x' ? CR0_REGS  \
   : (C) == 'y' ? CR_REGS \
   : (C) == 'z' ? XER_REGS  \
   : NO_REGS)

Definition at line 1152 of file rs6000.h.

#define REG_CLASS_NAMES

Value:

{                 \
  "NO_REGS",                \
  "BASE_REGS",                \
  "GENERAL_REGS",             \
  "FLOAT_REGS",               \
  "ALTIVEC_REGS",             \
  "VRSAVE_REGS",              \
  "NON_SPECIAL_REGS",             \
  "MQ_REGS",                \
  "LINK_REGS",                \
  "CTR_REGS",               \
  "LINK_OR_CTR_REGS",             \
  "SPECIAL_REGS",             \
  "SPEC_OR_GEN_REGS",             \
  "CR0_REGS",               \
  "CR_REGS",                \
  "NON_FLOAT_REGS",             \
  "XER_REGS",               \
  "ALL_REGS"                \
}

Definition at line 1078 of file rs6000.h.

#define REG_OK_FOR_BASE_P

(

X

)

INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)

Definition at line 1941 of file rs6000.h.

#define REG_OK_FOR_INDEX_P

(

X

)

INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)

Definition at line 1940 of file rs6000.h.

#define REG_OK_STRICT_FLAG   0

Definition at line 1923 of file rs6000.h.

#define REG_PARM_STACK_SPACE

(

FNDECL

)

RS6000_REG_SAVE

Definition at line 1423 of file rs6000.h.

#define REGISTER_MOVE_COST	(	MODE,
		CLASS1,
		CLASS2		)

Value:

((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
   : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10  \
   : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10  \
   : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20  \
   : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20  \
   : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS    \
       || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS   \
       || (CLASS1) == LINK_OR_CTR_REGS)       \
      && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
    || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS  \
    || (CLASS2) == LINK_OR_CTR_REGS)) ? 10    \
   : 2)

Definition at line 912 of file rs6000.h.

#define REGISTER_NAMES

Definition at line 2519 of file rs6000.h.

#define REGNO_OK_FOR_BASE_P

(

REGNO

)

Value:

((REGNO) < FIRST_PSEUDO_REGISTER        \
 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67    \
 : (reg_renumber[REGNO] > 0         \
    && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))

Definition at line 1878 of file rs6000.h.

#define REGNO_OK_FOR_INDEX_P

(

REGNO

)

Value:

((REGNO) < FIRST_PSEUDO_REGISTER        \
 ? (REGNO) <= 31 || (REGNO) == 67       \
 : (reg_renumber[REGNO] >= 0          \
    && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))

Definition at line 1872 of file rs6000.h.

#define REGNO_REG_CLASS

(

REGNO

)

Value:

((REGNO) == 0 ? GENERAL_REGS      \
  : (REGNO) < 32 ? BASE_REGS      \
  : FP_REGNO_P (REGNO) ? FLOAT_REGS   \
  : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS  \
  : (REGNO) == CR0_REGNO ? CR0_REGS   \
  : CR_REGNO_P (REGNO) ? CR_REGS    \
  : (REGNO) == MQ_REGNO ? MQ_REGS   \
  : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
  : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
  : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
  : (REGNO) == XER_REGNO ? XER_REGS   \
  : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
  : NO_REGS)

Definition at line 1131 of file rs6000.h.

#define RETURN_ADDR_RTX	(	COUNT,
		FRAME		)	(rs6000_return_addr (COUNT, FRAME))

Definition at line 1797 of file rs6000.h.

#define RETURN_ADDRESS_OFFSET

Value:

((DEFAULT_ABI == ABI_AIX            \
   || DEFAULT_ABI == ABI_DARWIN           \
   || DEFAULT_ABI == ABI_AIX_NODESC)  ? (TARGET_32BIT ? 8 : 16) : \
  (DEFAULT_ABI == ABI_V4)   ? 4 :       \
  (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))

Definition at line 1787 of file rs6000.h.

Referenced by rs6000_return_addr().

#define RETURN_IN_MEMORY

(

TYPE

)

Value:

(AGGREGATE_TYPE_P (TYPE) && \
   (TARGET_AIX_STRUCT_RET || \
    (unsigned HOST_WIDEST_INT) int_size_in_bytes (TYPE) > 8))

Definition at line 1487 of file rs6000.h.

#define RETURN_POPS_ARGS	(	FUNDECL,
		FUNTYPE,
		SIZE		)	0

Definition at line 1446 of file rs6000.h.

#define RS6000_ALIGN	(	n,
		a		)	(((n) + (a) - 1) & ~((a) - 1))

Definition at line 1373 of file rs6000.h.

Referenced by rs6000_stack_info().

#define RS6000_ARG_SIZE	(	MODE,
		TYPE		)

Value:

((MODE) != BLKmode              \
 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)

Definition at line 1600 of file rs6000.h.

Referenced by function_arg(), function_arg_advance(), function_arg_partial_nregs(), and setup_incoming_varargs().

#define RS6000_CALL_GLUE   "cror 31,31,31"

Definition at line 2697 of file rs6000.h.

#define rs6000_cpu_attr   ((enum attr_cpu)rs6000_cpu)

Definition at line 404 of file rs6000.h.

Referenced by rs6000_adjust_cost(), rs6000_adjust_priority(), rs6000_issue_rate(), and rs6000_use_sched_lookahead().

#define RS6000_PIC_OFFSET_TABLE_REGNUM   30

Definition at line 2106 of file rs6000.h.

#define RS6000_REG_SAVE

Value:

((DEFAULT_ABI == ABI_AIX      \
        || DEFAULT_ABI == ABI_AIX_NODESC    \
        || DEFAULT_ABI == ABI_DARWIN)     \
       ? (TARGET_64BIT ? 64 : 32)     \
       : 0)

Definition at line 1353 of file rs6000.h.

#define RS6000_SAVE_AREA

Value:

(((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8)  \
   << (TARGET_64BIT ? 1 : 0))

Definition at line 1360 of file rs6000.h.

Referenced by rs6000_stack_info().

#define RS6000_SAVE_TOC

Value:

gen_rtx_MEM (Pmode, \
             plus_constant (stack_pointer_rtx, \
                (TARGET_32BIT ? 20 : 40)))

Definition at line 1365 of file rs6000.h.

#define RS6000_VARARGS_AREA   0

Definition at line 1370 of file rs6000.h.

Referenced by rs6000_stack_info().

#define RS6000_VARARGS_SIZE   ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)

Definition at line 1376 of file rs6000.h.

Referenced by rs6000_va_start(), and setup_incoming_varargs().

#define RS6000_WEAK   0

Definition at line 2433 of file rs6000.h.

#define RTX_COSTS	(	X,
		CODE,
		OUTER_CODE		)

Definition at line 2245 of file rs6000.h.

#define SECONDARY_MEMORY_NEEDED	(	CLASS1,
		CLASS2,
		MODE		)

Value:

((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS    \
         || (CLASS2) == FLOAT_REGS    \
         || (CLASS1) == ALTIVEC_REGS    \
         || (CLASS2) == ALTIVEC_REGS))

Definition at line 1260 of file rs6000.h.

#define SECONDARY_RELOAD_CLASS	(	CLASS,
		MODE,
		IN		)	secondary_reload_class (CLASS, MODE, IN)

Definition at line 1254 of file rs6000.h.

#define SELECT_CC_MODE	(	OP,
		X,
		Y		)

Value:

(GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
   : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
   : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<'   \
      ? CCEQmode : CCmode))

Definition at line 2390 of file rs6000.h.

#define SETUP_INCOMING_VARARGS	(	CUM,
		MODE,
		TYPE,
		PRETEND_SIZE,
		NO_RTL		)	setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)

Definition at line 1707 of file rs6000.h.

#define SHIFT_COUNT_TRUNCATED   (TARGET_POWER ? 1 : 0)

Definition at line 2223 of file rs6000.h.

#define SHORT_IMMEDIATES_SIGN_EXTEND

Definition at line 2196 of file rs6000.h.

#define SHORT_TYPE_SIZE   16

Definition at line 557 of file rs6000.h.

#define SIZE_TYPE   "long unsigned int"

Definition at line 545 of file rs6000.h.

#define SLOW_BYTE_ACCESS   1

Definition at line 2183 of file rs6000.h.

#define SLOW_UNALIGNED_ACCESS	(	MODE,
		ALIGN		)

Value:

(STRICT_ALIGNMENT             \
   || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
       && (ALIGN) < 32))

Definition at line 664 of file rs6000.h.

#define STACK_BOUNDARY   ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)

Definition at line 618 of file rs6000.h.

#define STACK_DYNAMIC_OFFSET

(

FUNDECL

)

Value:

(RS6000_ALIGN (current_function_outgoing_args_size,     \
     TARGET_ALTIVEC ? 16 : 8)       \
   + (STACK_POINTER_OFFSET))

Definition at line 1400 of file rs6000.h.

#define STACK_GROWS_DOWNWARD

Definition at line 1341 of file rs6000.h.

#define STACK_POINTER_OFFSET   RS6000_SAVE_AREA

Definition at line 1432 of file rs6000.h.

#define STACK_POINTER_REGNUM   1

Definition at line 993 of file rs6000.h.

#define STACK_SAVEAREA_MODE

(

LEVEL

)

Value:

(LEVEL == SAVE_FUNCTION ? VOIDmode  \
  : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)

Definition at line 1502 of file rs6000.h.

#define STARTING_FRAME_OFFSET

Value:

(RS6000_ALIGN (current_function_outgoing_args_size,     \
     TARGET_ALTIVEC ? 16 : 8)       \
   + RS6000_VARARGS_AREA            \
   + RS6000_SAVE_AREA)

Definition at line 1388 of file rs6000.h.

#define STATIC_CHAIN_REGNUM   11

Definition at line 1008 of file rs6000.h.

#define STRICT_ALIGNMENT   0

Definition at line 659 of file rs6000.h.

#define STRICT_ARGUMENT_NAMING   1

Definition at line 1732 of file rs6000.h.

#define STRUCT_VALUE   0

Definition at line 1019 of file rs6000.h.

#define STRUCTURE_SIZE_BOUNDARY   8

Definition at line 636 of file rs6000.h.

#define SUBTARGET_EXTRA_SPECS

Definition at line 143 of file rs6000.h.

#define SUBTARGET_OPTIONS

Definition at line 421 of file rs6000.h.

#define SUBTARGET_SWITCHES

Definition at line 379 of file rs6000.h.

#define TARGET_32BIT   (! TARGET_64BIT)

Definition at line 249 of file rs6000.h.

Referenced by function_arg(), function_arg_advance(), num_insns_constant(), output_function_profiler(), output_mi_thunk(), output_toc(), rs6000_aix_emit_builtin_unwind_init(), rs6000_arg_partial_bytes(), rs6000_arg_size(), rs6000_complex_function_value(), rs6000_eh_return_filter_mode(), rs6000_emit_allocate_stack(), rs6000_emit_epilogue(), rs6000_emit_load_toc_table(), rs6000_emit_prologue(), rs6000_function_value(), rs6000_initialize_trampoline(), rs6000_legitimize_address(), rs6000_libcall_value(), rs6000_move_block_from_reg(), rs6000_output_mi_thunk(), rs6000_pass_by_reference(), rs6000_return_in_memory(), rs6000_split_multireg_move(), rs6000_stack_info(), rs6000_trampoline_size(), and setup_incoming_varargs().

#define TARGET_64BIT   (target_flags & MASK_64BIT)

Definition at line 237 of file rs6000.h.

#define TARGET_AIX   0

Definition at line 41 of file rs6000.h.

#define TARGET_AIX_STRUCT_RET   (target_flags & MASK_AIX_STRUCT_RET)

Definition at line 247 of file rs6000.h.

Referenced by rs6000_return_in_memory().

#define TARGET_ALTIVEC   (target_flags & MASK_ALTIVEC)

Definition at line 246 of file rs6000.h.

Referenced by altivec_init_builtins(), compute_vrsave_mask(), easy_vector_constant(), easy_vector_constant_add_self(), expand_block_clear(), expand_block_move(), first_altivec_reg_to_save(), function_arg_advance(), get_vec_cmp_insn(), init_cumulative_args(), output_vec_const_move(), print_operand(), rs6000_builtin_mask_for_load(), rs6000_conditional_register_usage(), rs6000_cpu_cpp_builtins(), rs6000_emit_epilogue(), rs6000_emit_prologue(), rs6000_emit_vector_compare(), rs6000_emit_vector_cond_expr(), rs6000_expand_builtin(), rs6000_function_value(), rs6000_init_builtins(), rs6000_legitimate_address(), rs6000_legitimize_reload_address(), rs6000_libcall_value(), rs6000_override_options(), and rs6000_vector_mode_supported_p().

#define TARGET_ALTIVEC_ABI   rs6000_altivec_abi

Definition at line 463 of file rs6000.h.

Referenced by debug_stack_info(), emit_frame_save(), first_altivec_reg_to_save(), function_arg(), function_arg_advance(), function_arg_boundary(), init_cumulative_args(), rs6000_conditional_register_usage(), rs6000_emit_epilogue(), rs6000_emit_prologue(), rs6000_function_value(), rs6000_gimplify_va_arg(), rs6000_libcall_value(), rs6000_pass_by_reference(), rs6000_return_in_memory(), and rs6000_stack_info().

#define TARGET_CPU_DEFAULT   ((char *)0)

Definition at line 46 of file rs6000.h.

#define TARGET_DEBUG_ARG   rs6000_debug_arg

Definition at line 454 of file rs6000.h.

#define TARGET_DEBUG_STACK   rs6000_debug_stack

Definition at line 453 of file rs6000.h.

#define TARGET_DEFAULT   (MASK_POWER | MASK_MULTIPLE | MASK_STRING)

Definition at line 376 of file rs6000.h.

#define TARGET_ELF   (TARGET_OBJECT_FORMAT == OBJECT_ELF)

Definition at line 35 of file rs6000.h.

#define TARGET_FUSED_MADD   (! TARGET_NO_FUSED_MADD)

Definition at line 252 of file rs6000.h.

Referenced by recog_1(), recog_2(), and s390_rtx_costs().

#define TARGET_HARD_FLOAT   (! TARGET_SOFT_FLOAT)

Definition at line 250 of file rs6000.h.

#define TARGET_LONG_DOUBLE_128   (rs6000_long_double_type_size == 128)

Definition at line 462 of file rs6000.h.

Referenced by rs6000_cpu_cpp_builtins(), rs6000_emit_move(), rs6000_generate_compare(), rs6000_mangle_fundamental_type(), rs6000_override_options(), and sparc_override_options().

#define TARGET_MACHO   (TARGET_OBJECT_FORMAT == OBJECT_MACHO)

Definition at line 38 of file rs6000.h.

#define TARGET_MACOS   (TARGET_OBJECT_FORMAT == OBJECT_PEF)

Definition at line 37 of file rs6000.h.

#define TARGET_MEM_FUNCTIONS

Definition at line 2412 of file rs6000.h.

#define TARGET_MINIMAL_TOC   (target_flags & MASK_MINIMAL_TOC)

Definition at line 236 of file rs6000.h.

Referenced by first_reg_to_save(), legitimate_constant_pool_address_p(), output_mi_thunk(), output_toc(), print_operand_address(), rs6000_conditional_register_usage(), rs6000_emit_epilogue(), rs6000_emit_load_toc_table(), rs6000_emit_prologue(), and rs6000_stack_info().

#define TARGET_MULTIPLE   (target_flags & MASK_MULTIPLE)

Definition at line 239 of file rs6000.h.

Referenced by rs6000_emit_epilogue(), rs6000_emit_prologue(), and rs6000_override_options().

#define TARGET_MULTIPLE_SET   (target_flags & MASK_MULTIPLE_SET)

Definition at line 240 of file rs6000.h.

Referenced by rs6000_override_options().

#define TARGET_NEW_MNEMONICS   (target_flags & MASK_NEW_MNEMONICS)

Definition at line 233 of file rs6000.h.

Referenced by output_mi_thunk(), and print_operand().

#define TARGET_NO_FP_IN_TOC   (target_flags & MASK_NO_FP_IN_TOC)

Definition at line 234 of file rs6000.h.

Referenced by output_toc(), rs6000_handle_option(), and rs6000_override_options().

#define TARGET_NO_FUSED_MADD   (target_flags & MASK_NO_FUSED_MADD)

Definition at line 244 of file rs6000.h.

#define TARGET_NO_SUM_IN_TOC   (target_flags & MASK_NO_SUM_IN_TOC)

Definition at line 235 of file rs6000.h.

Referenced by rs6000_emit_move(), and rs6000_handle_option().

#define TARGET_NO_UPDATE   (target_flags & MASK_NO_UPDATE)

Definition at line 243 of file rs6000.h.

#define TARGET_OPTIONS

Value:

{                 \
   {"cpu=",  &rs6000_select[1].string,          \
    N_("Use features of and schedule code for given CPU") },    \
   {"tune=", &rs6000_select[2].string,          \
    N_("Schedule code for given CPU") },        \
   {"debug=", &rs6000_debug_name, N_("Enable debug output") },    \
   {"abi=", &rs6000_abi_string, N_("Specify ABI to use") },   \
   {"long-double-", &rs6000_long_double_size_string,      \
    N_("Specify size of long double (64 or 128 bits)") },   \
   SUBTARGET_OPTIONS              \
}

Definition at line 423 of file rs6000.h.

#define TARGET_POWER   (target_flags & MASK_POWER)

Definition at line 228 of file rs6000.h.

Referenced by rs6000_adjust_cost(), rs6000_conditional_register_usage(), rs6000_cpu_cpp_builtins(), rs6000_emit_move(), and rs6000_output_function_prologue().

#define TARGET_POWER2   (target_flags & MASK_POWER2)

Definition at line 229 of file rs6000.h.

Referenced by rs6000_cpu_cpp_builtins(), and rs6000_init_libfuncs().

#define TARGET_POWERPC   (target_flags & MASK_POWERPC)

Definition at line 230 of file rs6000.h.

Referenced by rs6000_cpu_cpp_builtins(), rs6000_emit_move(), rs6000_init_libfuncs(), and rs6000_output_function_prologue().

#define TARGET_POWERPC64   (target_flags & MASK_POWERPC64)

Definition at line 262 of file rs6000.h.

Referenced by easy_fp_constant(), expand_block_clear(), expand_block_move(), function_arg(), legitimate_lo_sum_address_p(), mask_operand(), num_insns_constant_wide(), rs6000_cpu_cpp_builtins(), rs6000_emit_epilogue(), rs6000_emit_prologue(), rs6000_emit_sCOND(), rs6000_emit_set_long_const(), rs6000_function_value(), rs6000_legitimate_address(), rs6000_legitimate_offset_address_p(), rs6000_legitimize_address(), rs6000_legitimize_reload_address(), rs6000_libcall_value(), rs6000_override_options(), rs6000_split_multireg_move(), and rs6000_stack_info().

#define TARGET_PPC_GFXOPT   (target_flags & MASK_PPC_GFXOPT)

Definition at line 232 of file rs6000.h.

Referenced by rs6000_cpu_cpp_builtins(), and rs6000_rtx_costs().

#define TARGET_PPC_GPOPT   (target_flags & MASK_PPC_GPOPT)

Definition at line 231 of file rs6000.h.

Referenced by rs6000_cpu_cpp_builtins(), and rs6000_init_libfuncs().

#define TARGET_SCHED_PROLOG   (target_flags & MASK_SCHED_PROLOG)

Definition at line 245 of file rs6000.h.

Referenced by arm_expand_prologue(), thumb_expand_epilogue(), and thumb_expand_prologue().

#define TARGET_SOFT_FLOAT   (target_flags & MASK_SOFT_FLOAT)

Definition at line 238 of file rs6000.h.

#define TARGET_STRING   (target_flags & MASK_STRING)

Definition at line 241 of file rs6000.h.

#define TARGET_STRING_SET   (target_flags & MASK_STRING_SET)

Definition at line 242 of file rs6000.h.

Referenced by rs6000_override_options().

#define TARGET_SWITCHES

Definition at line 275 of file rs6000.h.

#define TARGET_UPDATE   (! TARGET_NO_UPDATE)

Definition at line 251 of file rs6000.h.

Referenced by rs6000_emit_allocate_stack(), rs6000_legitimate_address(), rs6000_mode_dependent_address(), and rs6000_split_multireg_move().

#define TARGET_XCOFF   (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)

Definition at line 36 of file rs6000.h.

Referenced by rs6000_init_libfuncs().

#define TARGET_XL_CALL   0

Definition at line 265 of file rs6000.h.

#define TOC_REGISTER   (TARGET_MINIMAL_TOC ? 30 : 2)

Definition at line 2109 of file rs6000.h.

Referenced by create_TOC_reference(), legitimate_constant_pool_address_p(), and rs6000_legitimize_tls_address().

#define TOC_RELATIVE_EXPR_P

(

X

)

(toc_relative_expr_p (X))

Definition at line 1963 of file rs6000.h.

Referenced by input_operand(), and rs6000_emit_move().

#define TOTAL_ALTIVEC_REGS   (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)

Definition at line 765 of file rs6000.h.

Referenced by generate_set_vrsave().

#define TRAMPOLINE_SIZE   rs6000_trampoline_size ()

Definition at line 1765 of file rs6000.h.

#define TRULY_NOOP_TRUNCATION	(	OUTPREC,
		INPREC		)	1

Definition at line 2200 of file rs6000.h.

#define UNITS_PER_ALTIVEC_WORD   16

Definition at line 539 of file rs6000.h.

Referenced by rs6000_hard_regno_nregs().

#define UNITS_PER_FP_WORD   8

Definition at line 538 of file rs6000.h.

Referenced by rs6000_hard_regno_mode_ok(), rs6000_hard_regno_nregs(), and setup_incoming_varargs().

#define UNITS_PER_WORD   (! TARGET_POWERPC64 ? 4 : 8)

Definition at line 536 of file rs6000.h.

#define USE_ALTIVEC_FOR_ARG_P	(	CUM,
		MODE,
		TYPE		)

Value:

(ALTIVEC_VECTOR_MODE (MODE)     \
   && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
   && TARGET_ALTIVEC_ABI)

Definition at line 1632 of file rs6000.h.

Referenced by function_arg(), function_arg_advance(), function_arg_partial_nregs(), rs6000_arg_partial_bytes(), rs6000_darwin64_record_arg_advance_recurse(), and rs6000_darwin64_record_arg_recurse().

#define USE_FP_FOR_ARG_P	(	CUM,
		MODE,
		TYPE		)

Value:

(GET_MODE_CLASS (MODE) == MODE_FLOAT  \
   && (CUM).fregno <= FP_ARG_MAX_REG    \
   && TARGET_HARD_FLOAT)

Definition at line 1626 of file rs6000.h.

Referenced by function_arg(), function_arg_partial_nregs(), rs6000_arg_partial_bytes(), rs6000_darwin64_record_arg_advance_recurse(), and rs6000_darwin64_record_arg_recurse().

#define VECTOR_MODE_SUPPORTED_P

(

MODE

)

(TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))

Definition at line 866 of file rs6000.h.

#define VRSAVE_REGNO   109

Definition at line 766 of file rs6000.h.

Referenced by generate_set_vrsave(), handle_syscall(), ppc_fallback_frame_state(), rs6000_conditional_register_usage(), rs6000_dbx_register_number(), rs6000_emit_prologue(), and vrsave_operation().

#define WCHAR_TYPE   "short unsigned int"

Definition at line 548 of file rs6000.h.

#define WCHAR_TYPE_SIZE   16

Definition at line 551 of file rs6000.h.

#define WIDEST_HARDWARE_FP_SIZE   64

Definition at line 608 of file rs6000.h.

#define WORD_REGISTER_OPERATIONS

Definition at line 2187 of file rs6000.h.

#define WORDS_BIG_ENDIAN   1

Definition at line 523 of file rs6000.h.

#define XER_REGNO   76

Definition at line 762 of file rs6000.h.

Referenced by handle_syscall(), and rs6000_dbx_register_number().

#define XER_REGNO_P

(

N

)

((N) == XER_REGNO)

Definition at line 836 of file rs6000.h.

Referenced by gpc_reg_operand(), rs6000_hard_regno_mode_ok(), and xer_operand().

---

Typedef Documentation

typedef struct rs6000_args CUMULATIVE_ARGS

typedef struct rs6000_stack rs6000_stack_t

---

Enumeration Type Documentation

enum processor_type

Enumerator:

PROCESSOR_EV4
PROCESSOR_EV5
PROCESSOR_EV6
PROCESSOR_I386
PROCESSOR_I486
PROCESSOR_PENTIUM
PROCESSOR_PENTIUMPRO
PROCESSOR_K6
PROCESSOR_ATHLON
PROCESSOR_PENTIUM4
PROCESSOR_max
PROCESSOR_M88100
PROCESSOR_M88110
PROCESSOR_M88000
PROCESSOR_700
PROCESSOR_7100
PROCESSOR_7100LC
PROCESSOR_7200
PROCESSOR_8000
PROCESSOR_RIOS1
PROCESSOR_RIOS2
PROCESSOR_RS64A
PROCESSOR_MPCCORE
PROCESSOR_PPC403
PROCESSOR_PPC405
PROCESSOR_PPC601
PROCESSOR_PPC603
PROCESSOR_PPC604
PROCESSOR_PPC604e
PROCESSOR_PPC620
PROCESSOR_PPC630
PROCESSOR_PPC750
PROCESSOR_PPC7400
PROCESSOR_PPC7450
PROCESSOR_SH1
PROCESSOR_SH2
PROCESSOR_SH3
PROCESSOR_SH3E
PROCESSOR_SH4
PROCESSOR_SH5
PROCESSOR_DEFAULT
PROCESSOR_R3000
PROCESSOR_R3900
PROCESSOR_R6000
PROCESSOR_R4000
PROCESSOR_R4100
PROCESSOR_R4111
PROCESSOR_R4120
PROCESSOR_R4300
PROCESSOR_R4600
PROCESSOR_R4650
PROCESSOR_R5000
PROCESSOR_R5400
PROCESSOR_R5500
PROCESSOR_R8000
PROCESSOR_R4KC
PROCESSOR_R5KC
PROCESSOR_R20KC
PROCESSOR_SR71000
PROCESSOR_SB1
PROCESSOR_V7
PROCESSOR_CYPRESS
PROCESSOR_V8
PROCESSOR_SUPERSPARC
PROCESSOR_SPARCLITE
PROCESSOR_F930
PROCESSOR_F934
PROCESSOR_HYPERSPARC
PROCESSOR_SPARCLITE86X
PROCESSOR_SPARCLET
PROCESSOR_TSC701
PROCESSOR_V9
PROCESSOR_ULTRASPARC
PROCESSOR_DEFAULT
PROCESSOR_R3000
PROCESSOR_R3900
PROCESSOR_R6000
PROCESSOR_R4000
PROCESSOR_R4100
PROCESSOR_R4111
PROCESSOR_R4120
PROCESSOR_R4300
PROCESSOR_R4600
PROCESSOR_R4650
PROCESSOR_R5000
PROCESSOR_R5400
PROCESSOR_R5500
PROCESSOR_R8000
PROCESSOR_R4KC
PROCESSOR_R5KC
PROCESSOR_R20KC
PROCESSOR_SR71000
PROCESSOR_SB1
PROCESSOR_DEFAULT
PROCESSOR_R3000
PROCESSOR_R3900
PROCESSOR_R6000
PROCESSOR_R4000
PROCESSOR_R4100
PROCESSOR_R4111
PROCESSOR_R4120
PROCESSOR_R4300
PROCESSOR_R4600
PROCESSOR_R4650
PROCESSOR_R5000
PROCESSOR_R5400
PROCESSOR_R5500
PROCESSOR_R8000
PROCESSOR_R4KC
PROCESSOR_R5KC
PROCESSOR_R20KC
PROCESSOR_SR71000
PROCESSOR_SB1
PROCESSOR_EV4
PROCESSOR_EV5
PROCESSOR_EV6
PROCESSOR_I386
PROCESSOR_I486
PROCESSOR_PENTIUM
PROCESSOR_PENTIUMPRO
PROCESSOR_K6
PROCESSOR_ATHLON
PROCESSOR_PENTIUM4
PROCESSOR_max
PROCESSOR_M88100
PROCESSOR_M88110
PROCESSOR_M88000
PROCESSOR_700
PROCESSOR_7100
PROCESSOR_7100LC
PROCESSOR_7200
PROCESSOR_8000
PROCESSOR_RIOS1
PROCESSOR_RIOS2
PROCESSOR_RS64A
PROCESSOR_MPCCORE
PROCESSOR_PPC403
PROCESSOR_PPC405
PROCESSOR_PPC601
PROCESSOR_PPC603
PROCESSOR_PPC604
PROCESSOR_PPC604e
PROCESSOR_PPC620
PROCESSOR_PPC630
PROCESSOR_PPC750
PROCESSOR_PPC7400
PROCESSOR_PPC7450
PROCESSOR_SH1
PROCESSOR_SH2
PROCESSOR_SH3
PROCESSOR_SH3E
PROCESSOR_SH4
PROCESSOR_SH5
PROCESSOR_DEFAULT
PROCESSOR_R3000
PROCESSOR_R3900
PROCESSOR_R6000
PROCESSOR_R4000
PROCESSOR_R4100
PROCESSOR_R4111
PROCESSOR_R4120
PROCESSOR_R4300
PROCESSOR_R4600
PROCESSOR_R4650
PROCESSOR_R5000
PROCESSOR_R5400
PROCESSOR_R5500
PROCESSOR_R8000
PROCESSOR_R4KC
PROCESSOR_R5KC
PROCESSOR_R20KC
PROCESSOR_SR71000
PROCESSOR_SB1
PROCESSOR_V7
PROCESSOR_CYPRESS
PROCESSOR_V8
PROCESSOR_SUPERSPARC
PROCESSOR_SPARCLITE
PROCESSOR_F930
PROCESSOR_F934
PROCESSOR_HYPERSPARC
PROCESSOR_SPARCLITE86X
PROCESSOR_SPARCLET
PROCESSOR_TSC701
PROCESSOR_V9
PROCESSOR_ULTRASPARC
PROCESSOR_DEFAULT
PROCESSOR_R3000
PROCESSOR_R3900
PROCESSOR_R6000
PROCESSOR_R4000
PROCESSOR_R4100
PROCESSOR_R4111
PROCESSOR_R4120
PROCESSOR_R4300
PROCESSOR_R4600
PROCESSOR_R4650
PROCESSOR_R5000
PROCESSOR_R5400
PROCESSOR_R5500
PROCESSOR_R8000
PROCESSOR_R4KC
PROCESSOR_R5KC
PROCESSOR_R20KC
PROCESSOR_SR71000
PROCESSOR_SB1
PROCESSOR_DEFAULT
PROCESSOR_R3000
PROCESSOR_R3900
PROCESSOR_R6000
PROCESSOR_R4000
PROCESSOR_R4100
PROCESSOR_R4111
PROCESSOR_R4120
PROCESSOR_R4300
PROCESSOR_R4600
PROCESSOR_R4650
PROCESSOR_R5000
PROCESSOR_R5400
PROCESSOR_R5500
PROCESSOR_R8000
PROCESSOR_R4KC
PROCESSOR_R5KC
PROCESSOR_R20KC
PROCESSOR_SR71000
PROCESSOR_SB1
PROCESSOR_EV4
PROCESSOR_EV5
PROCESSOR_EV6
PROCESSOR_MAX
ARM_CORE
PROCESSOR_I386
PROCESSOR_I486
PROCESSOR_PENTIUM
PROCESSOR_PENTIUMPRO
PROCESSOR_K6
PROCESSOR_ATHLON
PROCESSOR_PENTIUM4
PROCESSOR_K8
PROCESSOR_NOCONA
PROCESSOR_max
PROCESSOR_ITANIUM
PROCESSOR_ITANIUM2
PROCESSOR_max
PROCESSOR_DEFAULT
PROCESSOR_IQ2000
PROCESSOR_IQ10
PROCESSOR_DEFAULT
PROCESSOR_4KC
PROCESSOR_5KC
PROCESSOR_20KC
PROCESSOR_M4K
PROCESSOR_R3000
PROCESSOR_R3900
PROCESSOR_R6000
PROCESSOR_R4000
PROCESSOR_R4100
PROCESSOR_R4111
PROCESSOR_R4120
PROCESSOR_R4130
PROCESSOR_R4300
PROCESSOR_R4600
PROCESSOR_R4650
PROCESSOR_R5000
PROCESSOR_R5400
PROCESSOR_R5500
PROCESSOR_R7000
PROCESSOR_R8000
PROCESSOR_R9000
PROCESSOR_SB1
PROCESSOR_SR71000
PROCESSOR_700
PROCESSOR_7100
PROCESSOR_7100LC
PROCESSOR_7200
PROCESSOR_7300
PROCESSOR_8000
PROCESSOR_RIOS1
PROCESSOR_RIOS2
PROCESSOR_RS64A
PROCESSOR_MPCCORE
PROCESSOR_PPC403
PROCESSOR_PPC405
PROCESSOR_PPC440
PROCESSOR_PPC601
PROCESSOR_PPC603
PROCESSOR_PPC604
PROCESSOR_PPC604e
PROCESSOR_PPC620
PROCESSOR_PPC630
PROCESSOR_PPC750
PROCESSOR_PPC7400
PROCESSOR_PPC7450
PROCESSOR_PPC8540
PROCESSOR_POWER4
PROCESSOR_POWER5
PROCESSOR_9672_G5
PROCESSOR_9672_G6
PROCESSOR_2064_Z900
PROCESSOR_2084_Z990
PROCESSOR_max
PROCESSOR_SH1
PROCESSOR_SH2
PROCESSOR_SH2E
PROCESSOR_SH2A
PROCESSOR_SH3
PROCESSOR_SH3E
PROCESSOR_SH4
PROCESSOR_SH4A
PROCESSOR_SH5
PROCESSOR_V7
PROCESSOR_CYPRESS
PROCESSOR_V8
PROCESSOR_SUPERSPARC
PROCESSOR_SPARCLITE
PROCESSOR_F930
PROCESSOR_F934
PROCESSOR_HYPERSPARC
PROCESSOR_SPARCLITE86X
PROCESSOR_SPARCLET
PROCESSOR_TSC701
PROCESSOR_V9
PROCESSOR_ULTRASPARC
PROCESSOR_ULTRASPARC3
PROCESSOR_EV4
PROCESSOR_EV5
PROCESSOR_EV6
PROCESSOR_MAX
ARM_CORE
PROCESSOR_I386
PROCESSOR_I486
PROCESSOR_PENTIUM
PROCESSOR_PENTIUMPRO
PROCESSOR_K6
PROCESSOR_ATHLON
PROCESSOR_PENTIUM4
PROCESSOR_K8
PROCESSOR_NOCONA
PROCESSOR_GENERIC32
PROCESSOR_GENERIC64
PROCESSOR_AMDFAM10
PROCESSOR_max
PROCESSOR_ITANIUM
PROCESSOR_ITANIUM2
PROCESSOR_max
PROCESSOR_DEFAULT
PROCESSOR_IQ2000
PROCESSOR_IQ10
PROCESSOR_R3000
PROCESSOR_4KC
PROCESSOR_4KP
PROCESSOR_5KC
PROCESSOR_5KF
PROCESSOR_20KC
PROCESSOR_24K
PROCESSOR_24KX
PROCESSOR_M4K
PROCESSOR_R3900
PROCESSOR_R6000
PROCESSOR_R4000
PROCESSOR_R4100
PROCESSOR_R4111
PROCESSOR_R4120
PROCESSOR_R4130
PROCESSOR_R4300
PROCESSOR_R4600
PROCESSOR_R4650
PROCESSOR_R5000
PROCESSOR_R5400
PROCESSOR_R5500
PROCESSOR_R7000
PROCESSOR_R8000
PROCESSOR_R9000
PROCESSOR_SB1
PROCESSOR_SB1A
PROCESSOR_SR71000
PROCESSOR_MAX
PROCESSOR_MN10300
PROCESSOR_AM33
PROCESSOR_AM33_2
PROCESSOR_MS1_64_001
PROCESSOR_MS1_16_002
PROCESSOR_MS1_16_003
PROCESSOR_MS2
PROCESSOR_700
PROCESSOR_7100
PROCESSOR_7100LC
PROCESSOR_7200
PROCESSOR_7300
PROCESSOR_8000
PROCESSOR_RIOS1
PROCESSOR_RIOS2
PROCESSOR_RS64A
PROCESSOR_MPCCORE
PROCESSOR_PPC403
PROCESSOR_PPC405
PROCESSOR_PPC440
PROCESSOR_PPC601
PROCESSOR_PPC603
PROCESSOR_PPC604
PROCESSOR_PPC604e
PROCESSOR_PPC620
PROCESSOR_PPC630
PROCESSOR_PPC750
PROCESSOR_PPC7400
PROCESSOR_PPC7450
PROCESSOR_PPC8540
PROCESSOR_POWER4
PROCESSOR_POWER5
PROCESSOR_9672_G5
PROCESSOR_9672_G6
PROCESSOR_2064_Z900
PROCESSOR_2084_Z990
PROCESSOR_2094_Z9_109
PROCESSOR_max
PROCESSOR_SH1
PROCESSOR_SH2
PROCESSOR_SH2E
PROCESSOR_SH2A
PROCESSOR_SH3
PROCESSOR_SH3E
PROCESSOR_SH4
PROCESSOR_SH4A
PROCESSOR_SH5
PROCESSOR_V7
PROCESSOR_CYPRESS
PROCESSOR_V8
PROCESSOR_SUPERSPARC
PROCESSOR_SPARCLITE
PROCESSOR_F930
PROCESSOR_F934
PROCESSOR_HYPERSPARC
PROCESSOR_SPARCLITE86X
PROCESSOR_SPARCLET
PROCESSOR_TSC701
PROCESSOR_V9
PROCESSOR_ULTRASPARC
PROCESSOR_ULTRASPARC3
PROCESSOR_NIAGARA

Definition at line 382 of file rs6000.h.

enum reg_class

Enumerator:

NO_REGS
R2
R0_1
INDEX_REGS
BASE_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
LR0_REGS
GENERAL_REGS
BP_REGS
FC_REGS
CR_REGS
Q_REGS
SPECIAL_REGS
ACCUM0_REGS
ACCUM_REGS
FLOAT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R24_REG
R25_REG
R27_REG
GENERAL_REGS
FLOAT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
LPCOUNT_REG
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
FPU_REGS
LO_REGS
STACK_REG
BASE_REGS
HI_REGS
CC_REG
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REG
POINTER_X_REGS
POINTER_Y_REGS
POINTER_Z_REGS
STACK_REG
BASE_POINTER_REGS
POINTER_REGS
ADDW_REGS
SIMPLE_LD_REGS
LD_REGS
NO_LD_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0R1_REGS
R2R3_REGS
EXT_LOW_REGS
EXT_REGS
ADDR_REGS
INDEX_REGS
BK_REG
SP_REG
RC_REG
COUNTER_REGS
INT_REGS
GENERAL_REGS
DP_REG
ST_REG
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
FLOAT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
S_REGS
INDEX_REGS
SP_REGS
A_REGS
SI_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
REPEAT_REGS
CR_REGS
ACCUM_REGS
OTHER_FLAG_REGS
F0_REGS
F1_REGS
BR_FLAG_REGS
FLAG_REGS
EVEN_REGS
GPR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
A0H_REG
A0L_REG
A0_REG
A1H_REG
ACCUM_HIGH_REGS
A1L_REG
ACCUM_LOW_REGS
A1_REG
ACCUM_REGS
X_REG
X_OR_ACCUM_LOW_REGS
X_OR_ACCUM_REGS
YH_REG
YH_OR_ACCUM_HIGH_REGS
X_OR_YH_REGS
YL_REG
YL_OR_ACCUM_LOW_REGS
X_OR_YL_REGS
X_OR_Y_REGS
Y_REG
ACCUM_OR_Y_REGS
PH_REG
X_OR_PH_REGS
PL_REG
PL_OR_ACCUM_LOW_REGS
X_OR_PL_REGS
YL_OR_PL_OR_ACCUM_LOW_REGS
P_REG
ACCUM_OR_P_REGS
YL_OR_P_REGS
ACCUM_LOW_OR_YL_OR_P_REGS
Y_OR_P_REGS
ACCUM_Y_OR_P_REGS
NO_FRAME_Y_ADDR_REGS
Y_ADDR_REGS
ACCUM_LOW_OR_Y_ADDR_REGS
ACCUM_OR_Y_ADDR_REGS
X_OR_Y_ADDR_REGS
Y_OR_Y_ADDR_REGS
P_OR_Y_ADDR_REGS
NON_HIGH_YBASE_ELIGIBLE_REGS
YBASE_ELIGIBLE_REGS
J_REG
J_OR_DAU_16_BIT_REGS
BMU_REGS
NOHIGH_NON_ADDR_REGS
NON_ADDR_REGS
SLOW_MEM_LOAD_REGS
NOHIGH_NON_YBASE_REGS
NO_ACCUM_NON_YBASE_REGS
NON_YBASE_REGS
YBASE_VIRT_REGS
ACCUM_LOW_OR_YBASE_REGS
ACCUM_OR_YBASE_REGS
X_OR_YBASE_REGS
Y_OR_YBASE_REGS
ACCUM_LOW_YL_PL_OR_YBASE_REGS
P_OR_YBASE_REGS
ACCUM_Y_P_OR_YBASE_REGS
Y_ADDR_OR_YBASE_REGS
YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS
YBASE_OR_YBASE_ELIGIBLE_REGS
NO_HIGH_ALL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MULTIPLY_32_REG
MULTIPLY_64_REG
LOW_REGS
HIGH_REGS
REAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
MAC_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ADDR_REGS
DATA_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
AREG
DREG
CREG
BREG
SIREG
DIREG
AD_REGS
Q_REGS
NON_Q_REGS
INDEX_REGS
LEGACY_REGS
GENERAL_REGS
FP_TOP_REG
FP_SECOND_REG
FLOAT_REGS
SSE_REGS
MMX_REGS
FP_TOP_SSE_REGS
FP_SECOND_SSE_REGS
FLOAT_SSE_REGS
FLOAT_INT_REGS
INT_SSE_REGS
FLOAT_INT_SSE_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GLOBAL_REGS
LOCAL_REGS
LOCAL_OR_GLOBAL_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
PR_REGS
BR_REGS
AR_M_REGS
AR_I_REGS
ADDL_REGS
GR_REGS
FR_REGS
GR_AND_BR_REGS
GR_AND_FR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
CARRY_REG
ACCUM_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
D_REGS
X_REGS
Y_REGS
SP_REGS
DA_REGS
DB_REGS
Z_REGS
D8_REGS
Q_REGS
D_OR_X_REGS
D_OR_Y_REGS
D_OR_SP_REGS
X_OR_Y_REGS
A_REGS
X_OR_SP_REGS
Y_OR_SP_REGS
X_OR_Y_OR_D_REGS
A_OR_D_REGS
A_OR_SP_REGS
H_REGS
S_REGS
D_OR_S_REGS
X_OR_S_REGS
Y_OR_S_REGS
SP_OR_S_REGS
D_OR_X_OR_S_REGS
D_OR_Y_OR_S_REGS
D_OR_SP_OR_S_REGS
A_OR_S_REGS
D_OR_A_OR_S_REGS
TMP_REGS
D_OR_A_OR_TMP_REGS
G_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDR_REGS
FP_REGS
GENERAL_REGS
DATA_OR_FP_REGS
ADDR_OR_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
AP_REG
XRF_REGS
GENERAL_REGS
AGRF_REGS
XGRF_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ONLYR1_REGS
LRW_REGS
GENERAL_REGS
C_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
REMAINDER_REG
HIMULT_REG
SYSTEM_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDRESS_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDRESS_REGS
SP_REGS
DATA_OR_ADDRESS_REGS
SP_OR_ADDRESS_REGS
EXTENDED_REGS
DATA_OR_EXTENDED_REGS
ADDRESS_OR_EXTENDED_REGS
SP_OR_EXTENDED_REGS
SP_OR_ADDRESS_OR_EXTENDED_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
FLOAT_REG0
LONG_FLOAT_REG0
FLOAT_REGS
FP_REGS
GEN_AND_FP_REGS
FRAME_POINTER_REG
STACK_POINTER_REG
GEN_AND_MEM_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R1_REGS
GENERAL_REGS
FPUPPER_REGS
FP_REGS
GENERAL_OR_FP_REGS
SHIFT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R1_REGS
GENERAL_REGS
FPUPPER_REGS
FP_REGS
GENERAL_OR_FP_REGS
SHIFT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MUL_REGS
GENERAL_REGS
LOAD_FPU_REGS
NO_LOAD_FPU_REGS
FPU_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
OUT_REGS
STD_REGS
ARG_REGS
SRC_REGS
DST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
R15_REGS
BASE_REGS
GENERAL_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
BASE_REGS
GENERAL_REGS
FLOAT_REGS
ALTIVEC_REGS
VRSAVE_REGS
NON_SPECIAL_REGS
MQ_REGS
LINK_REGS
CTR_REGS
LINK_OR_CTR_REGS
SPECIAL_REGS
SPEC_OR_GEN_REGS
CR0_REGS
CR_REGS
NON_FLOAT_REGS
XER_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ADDR_REGS
GENERAL_REGS
FP_REGS
ADDR_FP_REGS
GENERAL_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
PR_REGS
T_REGS
MAC_REGS
FPUL_REGS
SIBCALL_REGS
GENERAL_REGS
FP0_REGS
FP_REGS
DF_REGS
FPSCR_REGS
GENERAL_FP_REGS
TARGET_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
M16_NA_REGS
M16_REGS
T_REG
M16_T_REGS
GR_REGS
FP_REGS
HI_REG
LO_REG
HILO_REG
MD_REGS
COP0_REGS
COP2_REGS
COP3_REGS
HI_AND_GR_REGS
LO_AND_GR_REGS
HILO_AND_GR_REGS
HI_AND_FP_REGS
COP0_AND_GR_REGS
COP2_AND_GR_REGS
COP3_AND_GR_REGS
ALL_COP_REGS
ALL_COP_AND_GR_REGS
ST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
FPCC_REGS
I64_REGS
GENERAL_REGS
FP_REGS
EXTRA_FP_REGS
GENERAL_OR_FP_REGS
GENERAL_OR_EXTRA_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
R1_REGS
TWO_REGS
R2_REGS
EIGHT_REGS
R8_REGS
ICALL_REGS
GENERAL_REGS
CARRY_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
BR_REGS
FP_REGS
ACC_REG
SP_REG
RL_REGS
GR_REGS
AR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
M16_NA_REGS
M16_REGS
T_REG
M16_T_REGS
GR_REGS
FP_REGS
HI_REG
LO_REG
HILO_REG
MD_REGS
COP0_REGS
COP2_REGS
COP3_REGS
HI_AND_GR_REGS
LO_AND_GR_REGS
HILO_AND_GR_REGS
HI_AND_FP_REGS
COP0_AND_GR_REGS
COP2_AND_GR_REGS
COP3_AND_GR_REGS
ALL_COP_REGS
ALL_COP_AND_GR_REGS
ST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
M16_NA_REGS
M16_REGS
T_REG
M16_T_REGS
GR_REGS
FP_REGS
HI_REG
LO_REG
HILO_REG
MD_REGS
COP0_REGS
COP2_REGS
COP3_REGS
HI_AND_GR_REGS
LO_AND_GR_REGS
HILO_AND_GR_REGS
HI_AND_FP_REGS
COP0_AND_GR_REGS
COP2_AND_GR_REGS
COP3_AND_GR_REGS
ALL_COP_REGS
ALL_COP_AND_GR_REGS
ST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R2
R0_1
INDEX_REGS
BASE_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
LR0_REGS
GENERAL_REGS
BP_REGS
FC_REGS
CR_REGS
Q_REGS
SPECIAL_REGS
ACCUM0_REGS
ACCUM_REGS
FLOAT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R24_REG
R25_REG
R27_REG
GENERAL_REGS
FLOAT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
LPCOUNT_REG
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
FPU_REGS
LO_REGS
STACK_REG
BASE_REGS
HI_REGS
CC_REG
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REG
POINTER_X_REGS
POINTER_Y_REGS
POINTER_Z_REGS
STACK_REG
BASE_POINTER_REGS
POINTER_REGS
ADDW_REGS
SIMPLE_LD_REGS
LD_REGS
NO_LD_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0R1_REGS
R2R3_REGS
EXT_LOW_REGS
EXT_REGS
ADDR_REGS
INDEX_REGS
BK_REG
SP_REG
RC_REG
COUNTER_REGS
INT_REGS
GENERAL_REGS
DP_REG
ST_REG
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
FLOAT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
S_REGS
INDEX_REGS
SP_REGS
A_REGS
SI_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
REPEAT_REGS
CR_REGS
ACCUM_REGS
OTHER_FLAG_REGS
F0_REGS
F1_REGS
BR_FLAG_REGS
FLAG_REGS
EVEN_REGS
GPR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
A0H_REG
A0L_REG
A0_REG
A1H_REG
ACCUM_HIGH_REGS
A1L_REG
ACCUM_LOW_REGS
A1_REG
ACCUM_REGS
X_REG
X_OR_ACCUM_LOW_REGS
X_OR_ACCUM_REGS
YH_REG
YH_OR_ACCUM_HIGH_REGS
X_OR_YH_REGS
YL_REG
YL_OR_ACCUM_LOW_REGS
X_OR_YL_REGS
X_OR_Y_REGS
Y_REG
ACCUM_OR_Y_REGS
PH_REG
X_OR_PH_REGS
PL_REG
PL_OR_ACCUM_LOW_REGS
X_OR_PL_REGS
YL_OR_PL_OR_ACCUM_LOW_REGS
P_REG
ACCUM_OR_P_REGS
YL_OR_P_REGS
ACCUM_LOW_OR_YL_OR_P_REGS
Y_OR_P_REGS
ACCUM_Y_OR_P_REGS
NO_FRAME_Y_ADDR_REGS
Y_ADDR_REGS
ACCUM_LOW_OR_Y_ADDR_REGS
ACCUM_OR_Y_ADDR_REGS
X_OR_Y_ADDR_REGS
Y_OR_Y_ADDR_REGS
P_OR_Y_ADDR_REGS
NON_HIGH_YBASE_ELIGIBLE_REGS
YBASE_ELIGIBLE_REGS
J_REG
J_OR_DAU_16_BIT_REGS
BMU_REGS
NOHIGH_NON_ADDR_REGS
NON_ADDR_REGS
SLOW_MEM_LOAD_REGS
NOHIGH_NON_YBASE_REGS
NO_ACCUM_NON_YBASE_REGS
NON_YBASE_REGS
YBASE_VIRT_REGS
ACCUM_LOW_OR_YBASE_REGS
ACCUM_OR_YBASE_REGS
X_OR_YBASE_REGS
Y_OR_YBASE_REGS
ACCUM_LOW_YL_PL_OR_YBASE_REGS
P_OR_YBASE_REGS
ACCUM_Y_P_OR_YBASE_REGS
Y_ADDR_OR_YBASE_REGS
YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS
YBASE_OR_YBASE_ELIGIBLE_REGS
NO_HIGH_ALL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MULTIPLY_32_REG
MULTIPLY_64_REG
LOW_REGS
HIGH_REGS
REAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
MAC_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ADDR_REGS
DATA_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
AREG
DREG
CREG
BREG
SIREG
DIREG
AD_REGS
Q_REGS
NON_Q_REGS
INDEX_REGS
LEGACY_REGS
GENERAL_REGS
FP_TOP_REG
FP_SECOND_REG
FLOAT_REGS
SSE_REGS
MMX_REGS
FP_TOP_SSE_REGS
FP_SECOND_SSE_REGS
FLOAT_SSE_REGS
FLOAT_INT_REGS
INT_SSE_REGS
FLOAT_INT_SSE_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GLOBAL_REGS
LOCAL_REGS
LOCAL_OR_GLOBAL_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
PR_REGS
BR_REGS
AR_M_REGS
AR_I_REGS
ADDL_REGS
GR_REGS
FR_REGS
GR_AND_BR_REGS
GR_AND_FR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
CARRY_REG
ACCUM_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
D_REGS
X_REGS
Y_REGS
SP_REGS
DA_REGS
DB_REGS
Z_REGS
D8_REGS
Q_REGS
D_OR_X_REGS
D_OR_Y_REGS
D_OR_SP_REGS
X_OR_Y_REGS
A_REGS
X_OR_SP_REGS
Y_OR_SP_REGS
X_OR_Y_OR_D_REGS
A_OR_D_REGS
A_OR_SP_REGS
H_REGS
S_REGS
D_OR_S_REGS
X_OR_S_REGS
Y_OR_S_REGS
SP_OR_S_REGS
D_OR_X_OR_S_REGS
D_OR_Y_OR_S_REGS
D_OR_SP_OR_S_REGS
A_OR_S_REGS
D_OR_A_OR_S_REGS
TMP_REGS
D_OR_A_OR_TMP_REGS
G_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDR_REGS
FP_REGS
GENERAL_REGS
DATA_OR_FP_REGS
ADDR_OR_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
AP_REG
XRF_REGS
GENERAL_REGS
AGRF_REGS
XGRF_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ONLYR1_REGS
LRW_REGS
GENERAL_REGS
C_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
REMAINDER_REG
HIMULT_REG
SYSTEM_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDRESS_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDRESS_REGS
SP_REGS
DATA_OR_ADDRESS_REGS
SP_OR_ADDRESS_REGS
EXTENDED_REGS
DATA_OR_EXTENDED_REGS
ADDRESS_OR_EXTENDED_REGS
SP_OR_EXTENDED_REGS
SP_OR_ADDRESS_OR_EXTENDED_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
FLOAT_REG0
LONG_FLOAT_REG0
FLOAT_REGS
FP_REGS
GEN_AND_FP_REGS
FRAME_POINTER_REG
STACK_POINTER_REG
GEN_AND_MEM_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R1_REGS
GENERAL_REGS
FPUPPER_REGS
FP_REGS
GENERAL_OR_FP_REGS
SHIFT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R1_REGS
GENERAL_REGS
FPUPPER_REGS
FP_REGS
GENERAL_OR_FP_REGS
SHIFT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MUL_REGS
GENERAL_REGS
LOAD_FPU_REGS
NO_LOAD_FPU_REGS
FPU_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
OUT_REGS
STD_REGS
ARG_REGS
SRC_REGS
DST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
R15_REGS
BASE_REGS
GENERAL_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
BASE_REGS
GENERAL_REGS
FLOAT_REGS
ALTIVEC_REGS
VRSAVE_REGS
NON_SPECIAL_REGS
MQ_REGS
LINK_REGS
CTR_REGS
LINK_OR_CTR_REGS
SPECIAL_REGS
SPEC_OR_GEN_REGS
CR0_REGS
CR_REGS
NON_FLOAT_REGS
XER_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ADDR_REGS
GENERAL_REGS
FP_REGS
ADDR_FP_REGS
GENERAL_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
PR_REGS
T_REGS
MAC_REGS
FPUL_REGS
SIBCALL_REGS
GENERAL_REGS
FP0_REGS
FP_REGS
DF_REGS
FPSCR_REGS
GENERAL_FP_REGS
TARGET_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
M16_NA_REGS
M16_REGS
T_REG
M16_T_REGS
GR_REGS
FP_REGS
HI_REG
LO_REG
HILO_REG
MD_REGS
COP0_REGS
COP2_REGS
COP3_REGS
HI_AND_GR_REGS
LO_AND_GR_REGS
HILO_AND_GR_REGS
HI_AND_FP_REGS
COP0_AND_GR_REGS
COP2_AND_GR_REGS
COP3_AND_GR_REGS
ALL_COP_REGS
ALL_COP_AND_GR_REGS
ST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
FPCC_REGS
I64_REGS
GENERAL_REGS
FP_REGS
EXTRA_FP_REGS
GENERAL_OR_FP_REGS
GENERAL_OR_EXTRA_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
R1_REGS
TWO_REGS
R2_REGS
EIGHT_REGS
R8_REGS
ICALL_REGS
GENERAL_REGS
CARRY_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
BR_REGS
FP_REGS
ACC_REG
SP_REG
RL_REGS
GR_REGS
AR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
M16_NA_REGS
M16_REGS
T_REG
M16_T_REGS
GR_REGS
FP_REGS
HI_REG
LO_REG
HILO_REG
MD_REGS
COP0_REGS
COP2_REGS
COP3_REGS
HI_AND_GR_REGS
LO_AND_GR_REGS
HILO_AND_GR_REGS
HI_AND_FP_REGS
COP0_AND_GR_REGS
COP2_AND_GR_REGS
COP3_AND_GR_REGS
ALL_COP_REGS
ALL_COP_AND_GR_REGS
ST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
M16_NA_REGS
M16_REGS
T_REG
M16_T_REGS
GR_REGS
FP_REGS
HI_REG
LO_REG
HILO_REG
MD_REGS
COP0_REGS
COP2_REGS
COP3_REGS
HI_AND_GR_REGS
LO_AND_GR_REGS
HILO_AND_GR_REGS
HI_AND_FP_REGS
COP0_AND_GR_REGS
COP2_AND_GR_REGS
COP3_AND_GR_REGS
ALL_COP_REGS
ALL_COP_AND_GR_REGS
ST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REG
R24_REG
R25_REG
R27_REG
GENERAL_REGS
FLOAT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
LPCOUNT_REG
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
FPA_REGS
CIRRUS_REGS
VFP_REGS
IWMMXT_GR_REGS
IWMMXT_REGS
LO_REGS
STACK_REG
BASE_REGS
HI_REGS
CC_REG
VFPCC_REG
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REG
POINTER_X_REGS
POINTER_Y_REGS
POINTER_Z_REGS
STACK_REG
BASE_POINTER_REGS
POINTER_REGS
ADDW_REGS
SIMPLE_LD_REGS
LD_REGS
NO_LD_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
IREGS
BREGS
LREGS
MREGS
CIRCREGS
DAGREGS
EVEN_AREGS
ODD_AREGS
AREGS
CCREGS
EVEN_DREGS
ODD_DREGS
DREGS
PREGS_CLOBBERED
PREGS
DPREGS
MOST_REGS
PROLOGUE_REGS
NON_A_CC_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0R1_REGS
R2R3_REGS
EXT_LOW_REGS
EXT_REGS
ADDR_REGS
INDEX_REGS
BK_REG
SP_REG
RC_REG
COUNTER_REGS
INT_REGS
GENERAL_REGS
DP_REG
ST_REG
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MULTIPLY_32_REG
MULTIPLY_64_REG
LOW_REGS
HIGH_REGS
REAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ICC_REGS
FCC_REGS
CC_REGS
ICR_REGS
FCR_REGS
CR_REGS
LCR_REG
LR_REG
GR8_REGS
GR9_REGS
GR89_REGS
FDPIC_REGS
FDPIC_FPTR_REGS
FDPIC_CALL_REGS
SPR_REGS
QUAD_ACC_REGS
EVEN_ACC_REGS
ACC_REGS
ACCG_REGS
QUAD_FPR_REGS
FEVEN_REGS
FPR_REGS
QUAD_REGS
EVEN_REGS
GPR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
COUNTER_REGS
SOURCE_REGS
DESTINATION_REGS
GENERAL_REGS
MAC_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
AREG
DREG
CREG
BREG
SIREG
DIREG
AD_REGS
Q_REGS
NON_Q_REGS
INDEX_REGS
LEGACY_REGS
GENERAL_REGS
FP_TOP_REG
FP_SECOND_REG
FLOAT_REGS
SSE_REGS
MMX_REGS
FP_TOP_SSE_REGS
FP_SECOND_SSE_REGS
FLOAT_SSE_REGS
FLOAT_INT_REGS
INT_SSE_REGS
FLOAT_INT_SSE_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
PR_REGS
BR_REGS
AR_M_REGS
AR_I_REGS
ADDL_REGS
GR_REGS
FR_REGS
GR_AND_BR_REGS
GR_AND_FR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DPH_REGS
DPL_REGS
DP_REGS
SP_REGS
IPH_REGS
IPL_REGS
IP_REGS
DP_SP_REGS
PTR_REGS
NONPTR_REGS
NONSP_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
CARRY_REG
ACCUM_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
D_REGS
X_REGS
Y_REGS
SP_REGS
DA_REGS
DB_REGS
Z_REGS
D8_REGS
Q_REGS
D_OR_X_REGS
D_OR_Y_REGS
D_OR_SP_REGS
X_OR_Y_REGS
A_REGS
X_OR_SP_REGS
Y_OR_SP_REGS
X_OR_Y_OR_D_REGS
A_OR_D_REGS
A_OR_SP_REGS
H_REGS
S_REGS
D_OR_S_REGS
X_OR_S_REGS
Y_OR_S_REGS
Z_OR_S_REGS
SP_OR_S_REGS
D_OR_X_OR_S_REGS
D_OR_Y_OR_S_REGS
D_OR_SP_OR_S_REGS
A_OR_S_REGS
D_OR_A_OR_S_REGS
TMP_REGS
D_OR_A_OR_TMP_REGS
G_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDR_REGS
FP_REGS
GENERAL_REGS
DATA_OR_FP_REGS
ADDR_OR_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ONLYR1_REGS
LRW_REGS
GENERAL_REGS
C_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
M16_NA_REGS
M16_REGS
T_REG
M16_T_REGS
PIC_FN_ADDR_REG
LEA_REGS
GR_REGS
FP_REGS
HI_REG
LO_REG
MD_REGS
COP0_REGS
COP2_REGS
COP3_REGS
HI_AND_GR_REGS
LO_AND_GR_REGS
HI_AND_FP_REGS
COP0_AND_GR_REGS
COP2_AND_GR_REGS
COP3_AND_GR_REGS
ALL_COP_REGS
ALL_COP_AND_GR_REGS
ST_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
REMAINDER_REG
HIMULT_REG
SYSTEM_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDRESS_REGS
SP_REGS
DATA_OR_ADDRESS_REGS
SP_OR_ADDRESS_REGS
EXTENDED_REGS
DATA_OR_EXTENDED_REGS
ADDRESS_OR_EXTENDED_REGS
SP_OR_EXTENDED_REGS
SP_OR_ADDRESS_OR_EXTENDED_REGS
FP_REGS
FP_ACC_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
FLOAT_REG0
LONG_FLOAT_REG0
FLOAT_REGS
LONG_REGS
FP_REGS
GEN_AND_FP_REGS
FRAME_POINTER_REG
STACK_POINTER_REG
GEN_AND_MEM_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R1_REGS
GENERAL_REGS
FPUPPER_REGS
FP_REGS
GENERAL_OR_FP_REGS
SHIFT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R1_REGS
GENERAL_REGS
FPUPPER_REGS
FP_REGS
GENERAL_OR_FP_REGS
SHIFT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MUL_REGS
GENERAL_REGS
LOAD_FPU_REGS
NO_LOAD_FPU_REGS
FPU_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
BASE_REGS
GENERAL_REGS
FLOAT_REGS
ALTIVEC_REGS
VRSAVE_REGS
VSCR_REGS
SPE_ACC_REGS
SPEFSCR_REGS
NON_SPECIAL_REGS
MQ_REGS
LINK_REGS
CTR_REGS
LINK_OR_CTR_REGS
SPECIAL_REGS
SPEC_OR_GEN_REGS
CR0_REGS
CR_REGS
NON_FLOAT_REGS
XER_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
CC_REGS
ADDR_REGS
GENERAL_REGS
ACCESS_REGS
ADDR_CC_REGS
GENERAL_CC_REGS
FP_REGS
ADDR_FP_REGS
GENERAL_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
PR_REGS
T_REGS
MAC_REGS
FPUL_REGS
SIBCALL_REGS
GENERAL_REGS
FP0_REGS
FP_REGS
DF_HI_REGS
DF_REGS
FPSCR_REGS
GENERAL_FP_REGS
TARGET_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
FPCC_REGS
I64_REGS
GENERAL_REGS
FP_REGS
EXTRA_FP_REGS
GENERAL_OR_FP_REGS
GENERAL_OR_EXTRA_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
R1_REGS
TWO_REGS
R2_REGS
EIGHT_REGS
R8_REGS
ICALL_REGS
GENERAL_REGS
CARRY_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
BR_REGS
FP_REGS
ACC_REG
SP_REG
RL_REGS
GR_REGS
AR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REG
R24_REG
R25_REG
R27_REG
GENERAL_REGS
FLOAT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
LPCOUNT_REG
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
FPA_REGS
CIRRUS_REGS
VFP_REGS
IWMMXT_GR_REGS
IWMMXT_REGS
LO_REGS
STACK_REG
BASE_REGS
HI_REGS
CC_REG
VFPCC_REG
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REG
POINTER_X_REGS
POINTER_Y_REGS
POINTER_Z_REGS
STACK_REG
BASE_POINTER_REGS
POINTER_REGS
ADDW_REGS
SIMPLE_LD_REGS
LD_REGS
NO_LD_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
IREGS
BREGS
LREGS
MREGS
CIRCREGS
DAGREGS
EVEN_AREGS
ODD_AREGS
AREGS
CCREGS
EVEN_DREGS
ODD_DREGS
DREGS
FDPIC_REGS
FDPIC_FPTR_REGS
PREGS_CLOBBERED
PREGS
IPREGS
DPREGS
MOST_REGS
LT_REGS
LC_REGS
LB_REGS
PROLOGUE_REGS
NON_A_CC_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0R1_REGS
R2R3_REGS
EXT_LOW_REGS
EXT_REGS
ADDR_REGS
INDEX_REGS
BK_REG
SP_REG
RC_REG
COUNTER_REGS
INT_REGS
GENERAL_REGS
DP_REG
ST_REG
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MOF_REGS
CC0_REGS
SPECIAL_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
LO_REGS
HI_REGS
HILO_REGS
NOSP_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MULTIPLY_32_REG
MULTIPLY_64_REG
LOW_REGS
HIGH_REGS
REAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ICC_REGS
FCC_REGS
CC_REGS
ICR_REGS
FCR_REGS
CR_REGS
LCR_REG
LR_REG
GR8_REGS
GR9_REGS
GR89_REGS
FDPIC_REGS
FDPIC_FPTR_REGS
FDPIC_CALL_REGS
SPR_REGS
QUAD_ACC_REGS
EVEN_ACC_REGS
ACC_REGS
ACCG_REGS
QUAD_FPR_REGS
FEVEN_REGS
FPR_REGS
QUAD_REGS
EVEN_REGS
GPR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
COUNTER_REGS
SOURCE_REGS
DESTINATION_REGS
GENERAL_REGS
MAC_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
AREG
DREG
CREG
BREG
SIREG
DIREG
AD_REGS
Q_REGS
NON_Q_REGS
INDEX_REGS
LEGACY_REGS
GENERAL_REGS
FP_TOP_REG
FP_SECOND_REG
FLOAT_REGS
SSE_REGS
MMX_REGS
FP_TOP_SSE_REGS
FP_SECOND_SSE_REGS
FLOAT_SSE_REGS
FLOAT_INT_REGS
INT_SSE_REGS
FLOAT_INT_SSE_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
PR_REGS
BR_REGS
AR_M_REGS
AR_I_REGS
ADDL_REGS
GR_REGS
FP_REGS
FR_REGS
GR_AND_BR_REGS
GR_AND_FR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GR_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
SP_REGS
FB_REGS
SB_REGS
CR_REGS
R0_REGS
R1_REGS
R2_REGS
R3_REGS
R02_REGS
HL_REGS
QI_REGS
R23_REGS
R03_REGS
DI_REGS
A0_REGS
A1_REGS
A_REGS
AD_REGS
PS_REGS
SI_REGS
HI_REGS
RA_REGS
GENERAL_REGS
FLG_REGS
HC_REGS
MEM_REGS
R02_A_MEM_REGS
A_HL_MEM_REGS
R1_R3_A_MEM_REGS
R03_MEM_REGS
A_HI_MEM_REGS
A_AD_CR_MEM_SI_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
CARRY_REG
ACCUM_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
D_REGS
X_REGS
Y_REGS
SP_REGS
DA_REGS
DB_REGS
Z_REGS
D8_REGS
Q_REGS
D_OR_X_REGS
D_OR_Y_REGS
D_OR_SP_REGS
X_OR_Y_REGS
A_REGS
X_OR_SP_REGS
Y_OR_SP_REGS
X_OR_Y_OR_D_REGS
A_OR_D_REGS
A_OR_SP_REGS
H_REGS
S_REGS
D_OR_S_REGS
X_OR_S_REGS
Y_OR_S_REGS
Z_OR_S_REGS
SP_OR_S_REGS
D_OR_X_OR_S_REGS
D_OR_Y_OR_S_REGS
D_OR_SP_OR_S_REGS
A_OR_S_REGS
D_OR_A_OR_S_REGS
TMP_REGS
D_OR_A_OR_TMP_REGS
G_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDR_REGS
FP_REGS
GENERAL_REGS
DATA_OR_FP_REGS
ADDR_OR_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ONLYR1_REGS
LRW_REGS
GENERAL_REGS
C_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
M16_NA_REGS
M16_REGS
T_REG
M16_T_REGS
PIC_FN_ADDR_REG
V1_REG
LEA_REGS
GR_REGS
FP_REGS
HI_REG
LO_REG
MD_REGS
COP0_REGS
COP2_REGS
COP3_REGS
HI_AND_GR_REGS
LO_AND_GR_REGS
HI_AND_FP_REGS
COP0_AND_GR_REGS
COP2_AND_GR_REGS
COP3_AND_GR_REGS
ALL_COP_REGS
ALL_COP_AND_GR_REGS
ST_REGS
DSP_ACC_REGS
ACC_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
REMAINDER_REG
HIMULT_REG
SYSTEM_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
DATA_REGS
ADDRESS_REGS
SP_REGS
DATA_OR_ADDRESS_REGS
SP_OR_ADDRESS_REGS
EXTENDED_REGS
DATA_OR_EXTENDED_REGS
ADDRESS_OR_EXTENDED_REGS
SP_OR_EXTENDED_REGS
SP_OR_ADDRESS_OR_EXTENDED_REGS
FP_REGS
FP_ACC_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R1_REGS
GENERAL_REGS
FPUPPER_REGS
FP_REGS
GENERAL_OR_FP_REGS
SHIFT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R1_REGS
GENERAL_REGS
FPUPPER_REGS
FP_REGS
GENERAL_OR_FP_REGS
SHIFT_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
MUL_REGS
GENERAL_REGS
LOAD_FPU_REGS
NO_LOAD_FPU_REGS
FPU_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
BASE_REGS
GENERAL_REGS
FLOAT_REGS
ALTIVEC_REGS
VRSAVE_REGS
VSCR_REGS
SPE_ACC_REGS
SPEFSCR_REGS
NON_SPECIAL_REGS
MQ_REGS
LINK_REGS
CTR_REGS
LINK_OR_CTR_REGS
SPECIAL_REGS
SPEC_OR_GEN_REGS
CR0_REGS
CR_REGS
NON_FLOAT_REGS
XER_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
CC_REGS
ADDR_REGS
GENERAL_REGS
ACCESS_REGS
ADDR_CC_REGS
GENERAL_CC_REGS
FP_REGS
ADDR_FP_REGS
GENERAL_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
G16_REGS
G32_REGS
T32_REGS
HI_REG
LO_REG
CE_REGS
CN_REG
LC_REG
SC_REG
SP_REGS
CR_REGS
CP1_REGS
CP2_REGS
CP3_REGS
CPA_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
PR_REGS
T_REGS
MAC_REGS
FPUL_REGS
SIBCALL_REGS
GENERAL_REGS
FP0_REGS
FP_REGS
DF_HI_REGS
DF_REGS
FPSCR_REGS
GENERAL_FP_REGS
GENERAL_DF_REGS
TARGET_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
FPCC_REGS
I64_REGS
GENERAL_REGS
FP_REGS
EXTRA_FP_REGS
GENERAL_OR_FP_REGS
GENERAL_OR_EXTRA_FP_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
R0_REGS
R1_REGS
TWO_REGS
R2_REGS
EIGHT_REGS
R8_REGS
ICALL_REGS
GENERAL_REGS
CARRY_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
GENERAL_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
ALL_REGS
LIM_REG_CLASSES
NO_REGS
BR_REGS
FP_REGS
ACC_REG
SP_REG
RL_REGS
GR_REGS
AR_REGS
ALL_REGS
LIM_REG_CLASSES

Definition at line 1051 of file rs6000.h.

enum rs6000_abi

Enumerator:

ABI_NONE
ABI_AIX
ABI_AIX_NODESC
ABI_V4
ABI_DARWIN
ABI_NONE
ABI_AIX
ABI_AIX_NODESC
ABI_V4
ABI_DARWIN
ABI_NONE
ABI_AIX
ABI_V4
ABI_DARWIN
ABI_NONE
ABI_AIX
ABI_V4
ABI_DARWIN

Definition at line 1289 of file rs6000.h.

enum rs6000_builtins

Enumerator:

ALTIVEC_BUILTIN_ST_INTERNAL_4si
ALTIVEC_BUILTIN_LD_INTERNAL_4si
ALTIVEC_BUILTIN_ST_INTERNAL_8hi
ALTIVEC_BUILTIN_LD_INTERNAL_8hi
ALTIVEC_BUILTIN_ST_INTERNAL_16qi
ALTIVEC_BUILTIN_LD_INTERNAL_16qi
ALTIVEC_BUILTIN_ST_INTERNAL_4sf
ALTIVEC_BUILTIN_LD_INTERNAL_4sf
ALTIVEC_BUILTIN_VADDUBM
ALTIVEC_BUILTIN_VADDUHM
ALTIVEC_BUILTIN_VADDUWM
ALTIVEC_BUILTIN_VADDFP
ALTIVEC_BUILTIN_VADDCUW
ALTIVEC_BUILTIN_VADDUBS
ALTIVEC_BUILTIN_VADDSBS
ALTIVEC_BUILTIN_VADDUHS
ALTIVEC_BUILTIN_VADDSHS
ALTIVEC_BUILTIN_VADDUWS
ALTIVEC_BUILTIN_VADDSWS
ALTIVEC_BUILTIN_VAND
ALTIVEC_BUILTIN_VANDC
ALTIVEC_BUILTIN_VAVGUB
ALTIVEC_BUILTIN_VAVGSB
ALTIVEC_BUILTIN_VAVGUH
ALTIVEC_BUILTIN_VAVGSH
ALTIVEC_BUILTIN_VAVGUW
ALTIVEC_BUILTIN_VAVGSW
ALTIVEC_BUILTIN_VCFUX
ALTIVEC_BUILTIN_VCFSX
ALTIVEC_BUILTIN_VCTSXS
ALTIVEC_BUILTIN_VCTUXS
ALTIVEC_BUILTIN_VCMPBFP
ALTIVEC_BUILTIN_VCMPEQUB
ALTIVEC_BUILTIN_VCMPEQUH
ALTIVEC_BUILTIN_VCMPEQUW
ALTIVEC_BUILTIN_VCMPEQFP
ALTIVEC_BUILTIN_VCMPGEFP
ALTIVEC_BUILTIN_VCMPGTUB
ALTIVEC_BUILTIN_VCMPGTSB
ALTIVEC_BUILTIN_VCMPGTUH
ALTIVEC_BUILTIN_VCMPGTSH
ALTIVEC_BUILTIN_VCMPGTUW
ALTIVEC_BUILTIN_VCMPGTSW
ALTIVEC_BUILTIN_VCMPGTFP
ALTIVEC_BUILTIN_VEXPTEFP
ALTIVEC_BUILTIN_VLOGEFP
ALTIVEC_BUILTIN_VMADDFP
ALTIVEC_BUILTIN_VMAXUB
ALTIVEC_BUILTIN_VMAXSB
ALTIVEC_BUILTIN_VMAXUH
ALTIVEC_BUILTIN_VMAXSH
ALTIVEC_BUILTIN_VMAXUW
ALTIVEC_BUILTIN_VMAXSW
ALTIVEC_BUILTIN_VMAXFP
ALTIVEC_BUILTIN_VMHADDSHS
ALTIVEC_BUILTIN_VMHRADDSHS
ALTIVEC_BUILTIN_VMLADDUHM
ALTIVEC_BUILTIN_VMRGHB
ALTIVEC_BUILTIN_VMRGHH
ALTIVEC_BUILTIN_VMRGHW
ALTIVEC_BUILTIN_VMRGLB
ALTIVEC_BUILTIN_VMRGLH
ALTIVEC_BUILTIN_VMRGLW
ALTIVEC_BUILTIN_VMSUMUBM
ALTIVEC_BUILTIN_VMSUMMBM
ALTIVEC_BUILTIN_VMSUMUHM
ALTIVEC_BUILTIN_VMSUMSHM
ALTIVEC_BUILTIN_VMSUMUHS
ALTIVEC_BUILTIN_VMSUMSHS
ALTIVEC_BUILTIN_VMINUB
ALTIVEC_BUILTIN_VMINSB
ALTIVEC_BUILTIN_VMINUH
ALTIVEC_BUILTIN_VMINSH
ALTIVEC_BUILTIN_VMINUW
ALTIVEC_BUILTIN_VMINSW
ALTIVEC_BUILTIN_VMINFP
ALTIVEC_BUILTIN_VMULEUB
ALTIVEC_BUILTIN_VMULESB
ALTIVEC_BUILTIN_VMULEUH
ALTIVEC_BUILTIN_VMULESH
ALTIVEC_BUILTIN_VMULOUB
ALTIVEC_BUILTIN_VMULOSB
ALTIVEC_BUILTIN_VMULOUH
ALTIVEC_BUILTIN_VMULOSH
ALTIVEC_BUILTIN_VNMSUBFP
ALTIVEC_BUILTIN_VNOR
ALTIVEC_BUILTIN_VOR
ALTIVEC_BUILTIN_VSEL_4SI
ALTIVEC_BUILTIN_VSEL_4SF
ALTIVEC_BUILTIN_VSEL_8HI
ALTIVEC_BUILTIN_VSEL_16QI
ALTIVEC_BUILTIN_VPERM_4SI
ALTIVEC_BUILTIN_VPERM_4SF
ALTIVEC_BUILTIN_VPERM_8HI
ALTIVEC_BUILTIN_VPERM_16QI
ALTIVEC_BUILTIN_VPKUHUM
ALTIVEC_BUILTIN_VPKUWUM
ALTIVEC_BUILTIN_VPKPX
ALTIVEC_BUILTIN_VPKUHSS
ALTIVEC_BUILTIN_VPKSHSS
ALTIVEC_BUILTIN_VPKUWSS
ALTIVEC_BUILTIN_VPKSWSS
ALTIVEC_BUILTIN_VPKUHUS
ALTIVEC_BUILTIN_VPKSHUS
ALTIVEC_BUILTIN_VPKUWUS
ALTIVEC_BUILTIN_VPKSWUS
ALTIVEC_BUILTIN_VREFP
ALTIVEC_BUILTIN_VRFIM
ALTIVEC_BUILTIN_VRFIN
ALTIVEC_BUILTIN_VRFIP
ALTIVEC_BUILTIN_VRFIZ
ALTIVEC_BUILTIN_VRLB
ALTIVEC_BUILTIN_VRLH
ALTIVEC_BUILTIN_VRLW
ALTIVEC_BUILTIN_VRSQRTEFP
ALTIVEC_BUILTIN_VSLB
ALTIVEC_BUILTIN_VSLH
ALTIVEC_BUILTIN_VSLW
ALTIVEC_BUILTIN_VSL
ALTIVEC_BUILTIN_VSLO
ALTIVEC_BUILTIN_VSPLTB
ALTIVEC_BUILTIN_VSPLTH
ALTIVEC_BUILTIN_VSPLTW
ALTIVEC_BUILTIN_VSPLTISB
ALTIVEC_BUILTIN_VSPLTISH
ALTIVEC_BUILTIN_VSPLTISW
ALTIVEC_BUILTIN_VSRB
ALTIVEC_BUILTIN_VSRH
ALTIVEC_BUILTIN_VSRW
ALTIVEC_BUILTIN_VSRAB
ALTIVEC_BUILTIN_VSRAH
ALTIVEC_BUILTIN_VSRAW
ALTIVEC_BUILTIN_VSR
ALTIVEC_BUILTIN_VSRO
ALTIVEC_BUILTIN_VSUBUBM
ALTIVEC_BUILTIN_VSUBUHM
ALTIVEC_BUILTIN_VSUBUWM
ALTIVEC_BUILTIN_VSUBFP
ALTIVEC_BUILTIN_VSUBCUW
ALTIVEC_BUILTIN_VSUBUBS
ALTIVEC_BUILTIN_VSUBSBS
ALTIVEC_BUILTIN_VSUBUHS
ALTIVEC_BUILTIN_VSUBSHS
ALTIVEC_BUILTIN_VSUBUWS
ALTIVEC_BUILTIN_VSUBSWS
ALTIVEC_BUILTIN_VSUM4UBS
ALTIVEC_BUILTIN_VSUM4SBS
ALTIVEC_BUILTIN_VSUM4SHS
ALTIVEC_BUILTIN_VSUM2SWS
ALTIVEC_BUILTIN_VSUMSWS
ALTIVEC_BUILTIN_VXOR
ALTIVEC_BUILTIN_VSLDOI_16QI
ALTIVEC_BUILTIN_VSLDOI_8HI
ALTIVEC_BUILTIN_VSLDOI_4SI
ALTIVEC_BUILTIN_VSLDOI_4SF
ALTIVEC_BUILTIN_VUPKHSB
ALTIVEC_BUILTIN_VUPKHPX
ALTIVEC_BUILTIN_VUPKHSH
ALTIVEC_BUILTIN_VUPKLSB
ALTIVEC_BUILTIN_VUPKLPX
ALTIVEC_BUILTIN_VUPKLSH
ALTIVEC_BUILTIN_MTVSCR
ALTIVEC_BUILTIN_MFVSCR
ALTIVEC_BUILTIN_DSSALL
ALTIVEC_BUILTIN_DSS
ALTIVEC_BUILTIN_LVSL
ALTIVEC_BUILTIN_LVSR
ALTIVEC_BUILTIN_DSTT
ALTIVEC_BUILTIN_DSTST
ALTIVEC_BUILTIN_DSTSTT
ALTIVEC_BUILTIN_DST
ALTIVEC_BUILTIN_LVEBX
ALTIVEC_BUILTIN_LVEHX
ALTIVEC_BUILTIN_LVEWX
ALTIVEC_BUILTIN_LVXL
ALTIVEC_BUILTIN_LVX
ALTIVEC_BUILTIN_STVX
ALTIVEC_BUILTIN_STVEBX
ALTIVEC_BUILTIN_STVEHX
ALTIVEC_BUILTIN_STVEWX
ALTIVEC_BUILTIN_STVXL
ALTIVEC_BUILTIN_VCMPBFP_P
ALTIVEC_BUILTIN_VCMPEQFP_P
ALTIVEC_BUILTIN_VCMPEQUB_P
ALTIVEC_BUILTIN_VCMPEQUH_P
ALTIVEC_BUILTIN_VCMPEQUW_P
ALTIVEC_BUILTIN_VCMPGEFP_P
ALTIVEC_BUILTIN_VCMPGTFP_P
ALTIVEC_BUILTIN_VCMPGTSB_P
ALTIVEC_BUILTIN_VCMPGTSH_P
ALTIVEC_BUILTIN_VCMPGTSW_P
ALTIVEC_BUILTIN_VCMPGTUB_P
ALTIVEC_BUILTIN_VCMPGTUH_P
ALTIVEC_BUILTIN_VCMPGTUW_P
ALTIVEC_BUILTIN_ABSS_V4SI
ALTIVEC_BUILTIN_ABSS_V8HI
ALTIVEC_BUILTIN_ABSS_V16QI
ALTIVEC_BUILTIN_ABS_V4SI
ALTIVEC_BUILTIN_ABS_V4SF
ALTIVEC_BUILTIN_ABS_V8HI
ALTIVEC_BUILTIN_ABS_V16QI
ALTIVEC_BUILTIN_ST_INTERNAL_4si
ALTIVEC_BUILTIN_LD_INTERNAL_4si
ALTIVEC_BUILTIN_ST_INTERNAL_8hi
ALTIVEC_BUILTIN_LD_INTERNAL_8hi
ALTIVEC_BUILTIN_ST_INTERNAL_16qi
ALTIVEC_BUILTIN_LD_INTERNAL_16qi
ALTIVEC_BUILTIN_ST_INTERNAL_4sf
ALTIVEC_BUILTIN_LD_INTERNAL_4sf
ALTIVEC_BUILTIN_VADDUBM
ALTIVEC_BUILTIN_VADDUHM
ALTIVEC_BUILTIN_VADDUWM
ALTIVEC_BUILTIN_VADDFP
ALTIVEC_BUILTIN_VADDCUW
ALTIVEC_BUILTIN_VADDUBS
ALTIVEC_BUILTIN_VADDSBS
ALTIVEC_BUILTIN_VADDUHS
ALTIVEC_BUILTIN_VADDSHS
ALTIVEC_BUILTIN_VADDUWS
ALTIVEC_BUILTIN_VADDSWS
ALTIVEC_BUILTIN_VAND
ALTIVEC_BUILTIN_VANDC
ALTIVEC_BUILTIN_VAVGUB
ALTIVEC_BUILTIN_VAVGSB
ALTIVEC_BUILTIN_VAVGUH
ALTIVEC_BUILTIN_VAVGSH
ALTIVEC_BUILTIN_VAVGUW
ALTIVEC_BUILTIN_VAVGSW
ALTIVEC_BUILTIN_VCFUX
ALTIVEC_BUILTIN_VCFSX
ALTIVEC_BUILTIN_VCTSXS
ALTIVEC_BUILTIN_VCTUXS
ALTIVEC_BUILTIN_VCMPBFP
ALTIVEC_BUILTIN_VCMPEQUB
ALTIVEC_BUILTIN_VCMPEQUH
ALTIVEC_BUILTIN_VCMPEQUW
ALTIVEC_BUILTIN_VCMPEQFP
ALTIVEC_BUILTIN_VCMPGEFP
ALTIVEC_BUILTIN_VCMPGTUB
ALTIVEC_BUILTIN_VCMPGTSB
ALTIVEC_BUILTIN_VCMPGTUH
ALTIVEC_BUILTIN_VCMPGTSH
ALTIVEC_BUILTIN_VCMPGTUW
ALTIVEC_BUILTIN_VCMPGTSW
ALTIVEC_BUILTIN_VCMPGTFP
ALTIVEC_BUILTIN_VEXPTEFP
ALTIVEC_BUILTIN_VLOGEFP
ALTIVEC_BUILTIN_VMADDFP
ALTIVEC_BUILTIN_VMAXUB
ALTIVEC_BUILTIN_VMAXSB
ALTIVEC_BUILTIN_VMAXUH
ALTIVEC_BUILTIN_VMAXSH
ALTIVEC_BUILTIN_VMAXUW
ALTIVEC_BUILTIN_VMAXSW
ALTIVEC_BUILTIN_VMAXFP
ALTIVEC_BUILTIN_VMHADDSHS
ALTIVEC_BUILTIN_VMHRADDSHS
ALTIVEC_BUILTIN_VMLADDUHM
ALTIVEC_BUILTIN_VMRGHB
ALTIVEC_BUILTIN_VMRGHH
ALTIVEC_BUILTIN_VMRGHW
ALTIVEC_BUILTIN_VMRGLB
ALTIVEC_BUILTIN_VMRGLH
ALTIVEC_BUILTIN_VMRGLW
ALTIVEC_BUILTIN_VMSUMUBM
ALTIVEC_BUILTIN_VMSUMMBM
ALTIVEC_BUILTIN_VMSUMUHM
ALTIVEC_BUILTIN_VMSUMSHM
ALTIVEC_BUILTIN_VMSUMUHS
ALTIVEC_BUILTIN_VMSUMSHS
ALTIVEC_BUILTIN_VMINUB
ALTIVEC_BUILTIN_VMINSB
ALTIVEC_BUILTIN_VMINUH
ALTIVEC_BUILTIN_VMINSH
ALTIVEC_BUILTIN_VMINUW
ALTIVEC_BUILTIN_VMINSW
ALTIVEC_BUILTIN_VMINFP
ALTIVEC_BUILTIN_VMULEUB
ALTIVEC_BUILTIN_VMULESB
ALTIVEC_BUILTIN_VMULEUH
ALTIVEC_BUILTIN_VMULESH
ALTIVEC_BUILTIN_VMULOUB
ALTIVEC_BUILTIN_VMULOSB
ALTIVEC_BUILTIN_VMULOUH
ALTIVEC_BUILTIN_VMULOSH
ALTIVEC_BUILTIN_VNMSUBFP
ALTIVEC_BUILTIN_VNOR
ALTIVEC_BUILTIN_VOR
ALTIVEC_BUILTIN_VSEL_4SI
ALTIVEC_BUILTIN_VSEL_4SF
ALTIVEC_BUILTIN_VSEL_8HI
ALTIVEC_BUILTIN_VSEL_16QI
ALTIVEC_BUILTIN_VPERM_4SI
ALTIVEC_BUILTIN_VPERM_4SF
ALTIVEC_BUILTIN_VPERM_8HI
ALTIVEC_BUILTIN_VPERM_16QI
ALTIVEC_BUILTIN_VPKUHUM
ALTIVEC_BUILTIN_VPKUWUM
ALTIVEC_BUILTIN_VPKPX
ALTIVEC_BUILTIN_VPKUHSS
ALTIVEC_BUILTIN_VPKSHSS
ALTIVEC_BUILTIN_VPKUWSS
ALTIVEC_BUILTIN_VPKSWSS
ALTIVEC_BUILTIN_VPKUHUS
ALTIVEC_BUILTIN_VPKSHUS
ALTIVEC_BUILTIN_VPKUWUS
ALTIVEC_BUILTIN_VPKSWUS
ALTIVEC_BUILTIN_VREFP
ALTIVEC_BUILTIN_VRFIM
ALTIVEC_BUILTIN_VRFIN
ALTIVEC_BUILTIN_VRFIP
ALTIVEC_BUILTIN_VRFIZ
ALTIVEC_BUILTIN_VRLB
ALTIVEC_BUILTIN_VRLH
ALTIVEC_BUILTIN_VRLW
ALTIVEC_BUILTIN_VRSQRTEFP
ALTIVEC_BUILTIN_VSLB
ALTIVEC_BUILTIN_VSLH
ALTIVEC_BUILTIN_VSLW
ALTIVEC_BUILTIN_VSL
ALTIVEC_BUILTIN_VSLO
ALTIVEC_BUILTIN_VSPLTB
ALTIVEC_BUILTIN_VSPLTH
ALTIVEC_BUILTIN_VSPLTW
ALTIVEC_BUILTIN_VSPLTISB
ALTIVEC_BUILTIN_VSPLTISH
ALTIVEC_BUILTIN_VSPLTISW
ALTIVEC_BUILTIN_VSRB
ALTIVEC_BUILTIN_VSRH
ALTIVEC_BUILTIN_VSRW
ALTIVEC_BUILTIN_VSRAB
ALTIVEC_BUILTIN_VSRAH
ALTIVEC_BUILTIN_VSRAW
ALTIVEC_BUILTIN_VSR
ALTIVEC_BUILTIN_VSRO
ALTIVEC_BUILTIN_VSUBUBM
ALTIVEC_BUILTIN_VSUBUHM
ALTIVEC_BUILTIN_VSUBUWM
ALTIVEC_BUILTIN_VSUBFP
ALTIVEC_BUILTIN_VSUBCUW
ALTIVEC_BUILTIN_VSUBUBS
ALTIVEC_BUILTIN_VSUBSBS
ALTIVEC_BUILTIN_VSUBUHS
ALTIVEC_BUILTIN_VSUBSHS
ALTIVEC_BUILTIN_VSUBUWS
ALTIVEC_BUILTIN_VSUBSWS
ALTIVEC_BUILTIN_VSUM4UBS
ALTIVEC_BUILTIN_VSUM4SBS
ALTIVEC_BUILTIN_VSUM4SHS
ALTIVEC_BUILTIN_VSUM2SWS
ALTIVEC_BUILTIN_VSUMSWS
ALTIVEC_BUILTIN_VXOR
ALTIVEC_BUILTIN_VSLDOI_16QI
ALTIVEC_BUILTIN_VSLDOI_8HI
ALTIVEC_BUILTIN_VSLDOI_4SI
ALTIVEC_BUILTIN_VSLDOI_4SF
ALTIVEC_BUILTIN_VUPKHSB
ALTIVEC_BUILTIN_VUPKHPX
ALTIVEC_BUILTIN_VUPKHSH
ALTIVEC_BUILTIN_VUPKLSB
ALTIVEC_BUILTIN_VUPKLPX
ALTIVEC_BUILTIN_VUPKLSH
ALTIVEC_BUILTIN_MTVSCR
ALTIVEC_BUILTIN_MFVSCR
ALTIVEC_BUILTIN_DSSALL
ALTIVEC_BUILTIN_DSS
ALTIVEC_BUILTIN_LVSL
ALTIVEC_BUILTIN_LVSR
ALTIVEC_BUILTIN_DSTT
ALTIVEC_BUILTIN_DSTST
ALTIVEC_BUILTIN_DSTSTT
ALTIVEC_BUILTIN_DST
ALTIVEC_BUILTIN_LVEBX
ALTIVEC_BUILTIN_LVEHX
ALTIVEC_BUILTIN_LVEWX
ALTIVEC_BUILTIN_LVXL
ALTIVEC_BUILTIN_LVX
ALTIVEC_BUILTIN_STVX
ALTIVEC_BUILTIN_STVEBX
ALTIVEC_BUILTIN_STVEHX
ALTIVEC_BUILTIN_STVEWX
ALTIVEC_BUILTIN_STVXL
ALTIVEC_BUILTIN_VCMPBFP_P
ALTIVEC_BUILTIN_VCMPEQFP_P
ALTIVEC_BUILTIN_VCMPEQUB_P
ALTIVEC_BUILTIN_VCMPEQUH_P
ALTIVEC_BUILTIN_VCMPEQUW_P
ALTIVEC_BUILTIN_VCMPGEFP_P
ALTIVEC_BUILTIN_VCMPGTFP_P
ALTIVEC_BUILTIN_VCMPGTSB_P
ALTIVEC_BUILTIN_VCMPGTSH_P
ALTIVEC_BUILTIN_VCMPGTSW_P
ALTIVEC_BUILTIN_VCMPGTUB_P
ALTIVEC_BUILTIN_VCMPGTUH_P
ALTIVEC_BUILTIN_VCMPGTUW_P
ALTIVEC_BUILTIN_ABSS_V4SI
ALTIVEC_BUILTIN_ABSS_V8HI
ALTIVEC_BUILTIN_ABSS_V16QI
ALTIVEC_BUILTIN_ABS_V4SI
ALTIVEC_BUILTIN_ABS_V4SF
ALTIVEC_BUILTIN_ABS_V8HI
ALTIVEC_BUILTIN_ABS_V16QI
ALTIVEC_BUILTIN_ST_INTERNAL_4si
ALTIVEC_BUILTIN_LD_INTERNAL_4si
ALTIVEC_BUILTIN_ST_INTERNAL_8hi
ALTIVEC_BUILTIN_LD_INTERNAL_8hi
ALTIVEC_BUILTIN_ST_INTERNAL_16qi
ALTIVEC_BUILTIN_LD_INTERNAL_16qi
ALTIVEC_BUILTIN_ST_INTERNAL_4sf
ALTIVEC_BUILTIN_LD_INTERNAL_4sf
ALTIVEC_BUILTIN_VADDUBM
ALTIVEC_BUILTIN_VADDUHM
ALTIVEC_BUILTIN_VADDUWM
ALTIVEC_BUILTIN_VADDFP
ALTIVEC_BUILTIN_VADDCUW
ALTIVEC_BUILTIN_VADDUBS
ALTIVEC_BUILTIN_VADDSBS
ALTIVEC_BUILTIN_VADDUHS
ALTIVEC_BUILTIN_VADDSHS
ALTIVEC_BUILTIN_VADDUWS
ALTIVEC_BUILTIN_VADDSWS
ALTIVEC_BUILTIN_VAND
ALTIVEC_BUILTIN_VANDC
ALTIVEC_BUILTIN_VAVGUB
ALTIVEC_BUILTIN_VAVGSB
ALTIVEC_BUILTIN_VAVGUH
ALTIVEC_BUILTIN_VAVGSH
ALTIVEC_BUILTIN_VAVGUW
ALTIVEC_BUILTIN_VAVGSW
ALTIVEC_BUILTIN_VCFUX
ALTIVEC_BUILTIN_VCFSX
ALTIVEC_BUILTIN_VCTSXS
ALTIVEC_BUILTIN_VCTUXS
ALTIVEC_BUILTIN_VCMPBFP
ALTIVEC_BUILTIN_VCMPEQUB
ALTIVEC_BUILTIN_VCMPEQUH
ALTIVEC_BUILTIN_VCMPEQUW
ALTIVEC_BUILTIN_VCMPEQFP
ALTIVEC_BUILTIN_VCMPGEFP
ALTIVEC_BUILTIN_VCMPGTUB
ALTIVEC_BUILTIN_VCMPGTSB
ALTIVEC_BUILTIN_VCMPGTUH
ALTIVEC_BUILTIN_VCMPGTSH
ALTIVEC_BUILTIN_VCMPGTUW
ALTIVEC_BUILTIN_VCMPGTSW
ALTIVEC_BUILTIN_VCMPGTFP
ALTIVEC_BUILTIN_VEXPTEFP
ALTIVEC_BUILTIN_VLOGEFP
ALTIVEC_BUILTIN_VMADDFP
ALTIVEC_BUILTIN_VMAXUB
ALTIVEC_BUILTIN_VMAXSB
ALTIVEC_BUILTIN_VMAXUH
ALTIVEC_BUILTIN_VMAXSH
ALTIVEC_BUILTIN_VMAXUW
ALTIVEC_BUILTIN_VMAXSW
ALTIVEC_BUILTIN_VMAXFP
ALTIVEC_BUILTIN_VMHADDSHS
ALTIVEC_BUILTIN_VMHRADDSHS
ALTIVEC_BUILTIN_VMLADDUHM
ALTIVEC_BUILTIN_VMRGHB
ALTIVEC_BUILTIN_VMRGHH
ALTIVEC_BUILTIN_VMRGHW
ALTIVEC_BUILTIN_VMRGLB
ALTIVEC_BUILTIN_VMRGLH
ALTIVEC_BUILTIN_VMRGLW
ALTIVEC_BUILTIN_VMSUMUBM
ALTIVEC_BUILTIN_VMSUMMBM
ALTIVEC_BUILTIN_VMSUMUHM
ALTIVEC_BUILTIN_VMSUMSHM
ALTIVEC_BUILTIN_VMSUMUHS
ALTIVEC_BUILTIN_VMSUMSHS
ALTIVEC_BUILTIN_VMINUB
ALTIVEC_BUILTIN_VMINSB
ALTIVEC_BUILTIN_VMINUH
ALTIVEC_BUILTIN_VMINSH
ALTIVEC_BUILTIN_VMINUW
ALTIVEC_BUILTIN_VMINSW
ALTIVEC_BUILTIN_VMINFP
ALTIVEC_BUILTIN_VMULEUB
ALTIVEC_BUILTIN_VMULESB
ALTIVEC_BUILTIN_VMULEUH
ALTIVEC_BUILTIN_VMULESH
ALTIVEC_BUILTIN_VMULOUB
ALTIVEC_BUILTIN_VMULOSB
ALTIVEC_BUILTIN_VMULOUH
ALTIVEC_BUILTIN_VMULOSH
ALTIVEC_BUILTIN_VNMSUBFP
ALTIVEC_BUILTIN_VNOR
ALTIVEC_BUILTIN_VOR
ALTIVEC_BUILTIN_VSEL_4SI
ALTIVEC_BUILTIN_VSEL_4SF
ALTIVEC_BUILTIN_VSEL_8HI
ALTIVEC_BUILTIN_VSEL_16QI
ALTIVEC_BUILTIN_VPERM_4SI
ALTIVEC_BUILTIN_VPERM_4SF
ALTIVEC_BUILTIN_VPERM_8HI
ALTIVEC_BUILTIN_VPERM_16QI
ALTIVEC_BUILTIN_VPKUHUM
ALTIVEC_BUILTIN_VPKUWUM
ALTIVEC_BUILTIN_VPKPX
ALTIVEC_BUILTIN_VPKUHSS
ALTIVEC_BUILTIN_VPKSHSS
ALTIVEC_BUILTIN_VPKUWSS
ALTIVEC_BUILTIN_VPKSWSS
ALTIVEC_BUILTIN_VPKUHUS
ALTIVEC_BUILTIN_VPKSHUS
ALTIVEC_BUILTIN_VPKUWUS
ALTIVEC_BUILTIN_VPKSWUS
ALTIVEC_BUILTIN_VREFP
ALTIVEC_BUILTIN_VRFIM
ALTIVEC_BUILTIN_VRFIN
ALTIVEC_BUILTIN_VRFIP
ALTIVEC_BUILTIN_VRFIZ
ALTIVEC_BUILTIN_VRLB
ALTIVEC_BUILTIN_VRLH
ALTIVEC_BUILTIN_VRLW
ALTIVEC_BUILTIN_VRSQRTEFP
ALTIVEC_BUILTIN_VSLB
ALTIVEC_BUILTIN_VSLH
ALTIVEC_BUILTIN_VSLW
ALTIVEC_BUILTIN_VSL
ALTIVEC_BUILTIN_VSLO
ALTIVEC_BUILTIN_VSPLTB
ALTIVEC_BUILTIN_VSPLTH
ALTIVEC_BUILTIN_VSPLTW
ALTIVEC_BUILTIN_VSPLTISB
ALTIVEC_BUILTIN_VSPLTISH
ALTIVEC_BUILTIN_VSPLTISW
ALTIVEC_BUILTIN_VSRB
ALTIVEC_BUILTIN_VSRH
ALTIVEC_BUILTIN_VSRW
ALTIVEC_BUILTIN_VSRAB
ALTIVEC_BUILTIN_VSRAH
ALTIVEC_BUILTIN_VSRAW
ALTIVEC_BUILTIN_VSR
ALTIVEC_BUILTIN_VSRO
ALTIVEC_BUILTIN_VSUBUBM
ALTIVEC_BUILTIN_VSUBUHM
ALTIVEC_BUILTIN_VSUBUWM
ALTIVEC_BUILTIN_VSUBFP
ALTIVEC_BUILTIN_VSUBCUW
ALTIVEC_BUILTIN_VSUBUBS
ALTIVEC_BUILTIN_VSUBSBS
ALTIVEC_BUILTIN_VSUBUHS
ALTIVEC_BUILTIN_VSUBSHS
ALTIVEC_BUILTIN_VSUBUWS
ALTIVEC_BUILTIN_VSUBSWS
ALTIVEC_BUILTIN_VSUM4UBS
ALTIVEC_BUILTIN_VSUM4SBS
ALTIVEC_BUILTIN_VSUM4SHS
ALTIVEC_BUILTIN_VSUM2SWS
ALTIVEC_BUILTIN_VSUMSWS
ALTIVEC_BUILTIN_VXOR
ALTIVEC_BUILTIN_VSLDOI_16QI
ALTIVEC_BUILTIN_VSLDOI_8HI
ALTIVEC_BUILTIN_VSLDOI_4SI
ALTIVEC_BUILTIN_VSLDOI_4SF
ALTIVEC_BUILTIN_VUPKHSB
ALTIVEC_BUILTIN_VUPKHPX
ALTIVEC_BUILTIN_VUPKHSH
ALTIVEC_BUILTIN_VUPKLSB
ALTIVEC_BUILTIN_VUPKLPX
ALTIVEC_BUILTIN_VUPKLSH
ALTIVEC_BUILTIN_MTVSCR
ALTIVEC_BUILTIN_MFVSCR
ALTIVEC_BUILTIN_DSSALL
ALTIVEC_BUILTIN_DSS
ALTIVEC_BUILTIN_LVSL
ALTIVEC_BUILTIN_LVSR
ALTIVEC_BUILTIN_DSTT
ALTIVEC_BUILTIN_DSTST
ALTIVEC_BUILTIN_DSTSTT
ALTIVEC_BUILTIN_DST
ALTIVEC_BUILTIN_LVEBX
ALTIVEC_BUILTIN_LVEHX
ALTIVEC_BUILTIN_LVEWX
ALTIVEC_BUILTIN_LVXL
ALTIVEC_BUILTIN_LVX
ALTIVEC_BUILTIN_STVX
ALTIVEC_BUILTIN_STVEBX
ALTIVEC_BUILTIN_STVEHX
ALTIVEC_BUILTIN_STVEWX
ALTIVEC_BUILTIN_STVXL
ALTIVEC_BUILTIN_VCMPBFP_P
ALTIVEC_BUILTIN_VCMPEQFP_P
ALTIVEC_BUILTIN_VCMPEQUB_P
ALTIVEC_BUILTIN_VCMPEQUH_P
ALTIVEC_BUILTIN_VCMPEQUW_P
ALTIVEC_BUILTIN_VCMPGEFP_P
ALTIVEC_BUILTIN_VCMPGTFP_P
ALTIVEC_BUILTIN_VCMPGTSB_P
ALTIVEC_BUILTIN_VCMPGTSH_P
ALTIVEC_BUILTIN_VCMPGTSW_P
ALTIVEC_BUILTIN_VCMPGTUB_P
ALTIVEC_BUILTIN_VCMPGTUH_P
ALTIVEC_BUILTIN_VCMPGTUW_P
ALTIVEC_BUILTIN_ABSS_V4SI
ALTIVEC_BUILTIN_ABSS_V8HI
ALTIVEC_BUILTIN_ABSS_V16QI
ALTIVEC_BUILTIN_ABS_V4SI
ALTIVEC_BUILTIN_ABS_V4SF
ALTIVEC_BUILTIN_ABS_V8HI
ALTIVEC_BUILTIN_ABS_V16QI
ALTIVEC_BUILTIN_COMPILETIME_ERROR
ALTIVEC_BUILTIN_MASK_FOR_LOAD
ALTIVEC_BUILTIN_MASK_FOR_STORE
SPE_BUILTIN_EVADDW
SPE_BUILTIN_EVAND
SPE_BUILTIN_EVANDC
SPE_BUILTIN_EVDIVWS
SPE_BUILTIN_EVDIVWU
SPE_BUILTIN_EVEQV
SPE_BUILTIN_EVFSADD
SPE_BUILTIN_EVFSDIV
SPE_BUILTIN_EVFSMUL
SPE_BUILTIN_EVFSSUB
SPE_BUILTIN_EVLDDX
SPE_BUILTIN_EVLDHX
SPE_BUILTIN_EVLDWX
SPE_BUILTIN_EVLHHESPLATX
SPE_BUILTIN_EVLHHOSSPLATX
SPE_BUILTIN_EVLHHOUSPLATX
SPE_BUILTIN_EVLWHEX
SPE_BUILTIN_EVLWHOSX
SPE_BUILTIN_EVLWHOUX
SPE_BUILTIN_EVLWHSPLATX
SPE_BUILTIN_EVLWWSPLATX
SPE_BUILTIN_EVMERGEHI
SPE_BUILTIN_EVMERGEHILO
SPE_BUILTIN_EVMERGELO
SPE_BUILTIN_EVMERGELOHI
SPE_BUILTIN_EVMHEGSMFAA
SPE_BUILTIN_EVMHEGSMFAN
SPE_BUILTIN_EVMHEGSMIAA
SPE_BUILTIN_EVMHEGSMIAN
SPE_BUILTIN_EVMHEGUMIAA
SPE_BUILTIN_EVMHEGUMIAN
SPE_BUILTIN_EVMHESMF
SPE_BUILTIN_EVMHESMFA
SPE_BUILTIN_EVMHESMFAAW
SPE_BUILTIN_EVMHESMFANW
SPE_BUILTIN_EVMHESMI
SPE_BUILTIN_EVMHESMIA
SPE_BUILTIN_EVMHESMIAAW
SPE_BUILTIN_EVMHESMIANW
SPE_BUILTIN_EVMHESSF
SPE_BUILTIN_EVMHESSFA
SPE_BUILTIN_EVMHESSFAAW
SPE_BUILTIN_EVMHESSFANW
SPE_BUILTIN_EVMHESSIAAW
SPE_BUILTIN_EVMHESSIANW
SPE_BUILTIN_EVMHEUMI
SPE_BUILTIN_EVMHEUMIA
SPE_BUILTIN_EVMHEUMIAAW
SPE_BUILTIN_EVMHEUMIANW
SPE_BUILTIN_EVMHEUSIAAW
SPE_BUILTIN_EVMHEUSIANW
SPE_BUILTIN_EVMHOGSMFAA
SPE_BUILTIN_EVMHOGSMFAN
SPE_BUILTIN_EVMHOGSMIAA
SPE_BUILTIN_EVMHOGSMIAN
SPE_BUILTIN_EVMHOGUMIAA
SPE_BUILTIN_EVMHOGUMIAN
SPE_BUILTIN_EVMHOSMF
SPE_BUILTIN_EVMHOSMFA
SPE_BUILTIN_EVMHOSMFAAW
SPE_BUILTIN_EVMHOSMFANW
SPE_BUILTIN_EVMHOSMI
SPE_BUILTIN_EVMHOSMIA
SPE_BUILTIN_EVMHOSMIAAW
SPE_BUILTIN_EVMHOSMIANW
SPE_BUILTIN_EVMHOSSF
SPE_BUILTIN_EVMHOSSFA
SPE_BUILTIN_EVMHOSSFAAW
SPE_BUILTIN_EVMHOSSFANW
SPE_BUILTIN_EVMHOSSIAAW
SPE_BUILTIN_EVMHOSSIANW
SPE_BUILTIN_EVMHOUMI
SPE_BUILTIN_EVMHOUMIA
SPE_BUILTIN_EVMHOUMIAAW
SPE_BUILTIN_EVMHOUMIANW
SPE_BUILTIN_EVMHOUSIAAW
SPE_BUILTIN_EVMHOUSIANW
SPE_BUILTIN_EVMWHSMF
SPE_BUILTIN_EVMWHSMFA
SPE_BUILTIN_EVMWHSMI
SPE_BUILTIN_EVMWHSMIA
SPE_BUILTIN_EVMWHSSF
SPE_BUILTIN_EVMWHSSFA
SPE_BUILTIN_EVMWHUMI
SPE_BUILTIN_EVMWHUMIA
SPE_BUILTIN_EVMWLSMIAAW
SPE_BUILTIN_EVMWLSMIANW
SPE_BUILTIN_EVMWLSSIAAW
SPE_BUILTIN_EVMWLSSIANW
SPE_BUILTIN_EVMWLUMI
SPE_BUILTIN_EVMWLUMIA
SPE_BUILTIN_EVMWLUMIAAW
SPE_BUILTIN_EVMWLUMIANW
SPE_BUILTIN_EVMWLUSIAAW
SPE_BUILTIN_EVMWLUSIANW
SPE_BUILTIN_EVMWSMF
SPE_BUILTIN_EVMWSMFA
SPE_BUILTIN_EVMWSMFAA
SPE_BUILTIN_EVMWSMFAN
SPE_BUILTIN_EVMWSMI
SPE_BUILTIN_EVMWSMIA
SPE_BUILTIN_EVMWSMIAA
SPE_BUILTIN_EVMWSMIAN
SPE_BUILTIN_EVMWHSSFAA
SPE_BUILTIN_EVMWSSF
SPE_BUILTIN_EVMWSSFA
SPE_BUILTIN_EVMWSSFAA
SPE_BUILTIN_EVMWSSFAN
SPE_BUILTIN_EVMWUMI
SPE_BUILTIN_EVMWUMIA
SPE_BUILTIN_EVMWUMIAA
SPE_BUILTIN_EVMWUMIAN
SPE_BUILTIN_EVNAND
SPE_BUILTIN_EVNOR
SPE_BUILTIN_EVOR
SPE_BUILTIN_EVORC
SPE_BUILTIN_EVRLW
SPE_BUILTIN_EVSLW
SPE_BUILTIN_EVSRWS
SPE_BUILTIN_EVSRWU
SPE_BUILTIN_EVSTDDX
SPE_BUILTIN_EVSTDHX
SPE_BUILTIN_EVSTDWX
SPE_BUILTIN_EVSTWHEX
SPE_BUILTIN_EVSTWHOX
SPE_BUILTIN_EVSTWWEX
SPE_BUILTIN_EVSTWWOX
SPE_BUILTIN_EVSUBFW
SPE_BUILTIN_EVXOR
SPE_BUILTIN_EVABS
SPE_BUILTIN_EVADDSMIAAW
SPE_BUILTIN_EVADDSSIAAW
SPE_BUILTIN_EVADDUMIAAW
SPE_BUILTIN_EVADDUSIAAW
SPE_BUILTIN_EVCNTLSW
SPE_BUILTIN_EVCNTLZW
SPE_BUILTIN_EVEXTSB
SPE_BUILTIN_EVEXTSH
SPE_BUILTIN_EVFSABS
SPE_BUILTIN_EVFSCFSF
SPE_BUILTIN_EVFSCFSI
SPE_BUILTIN_EVFSCFUF
SPE_BUILTIN_EVFSCFUI
SPE_BUILTIN_EVFSCTSF
SPE_BUILTIN_EVFSCTSI
SPE_BUILTIN_EVFSCTSIZ
SPE_BUILTIN_EVFSCTUF
SPE_BUILTIN_EVFSCTUI
SPE_BUILTIN_EVFSCTUIZ
SPE_BUILTIN_EVFSNABS
SPE_BUILTIN_EVFSNEG
SPE_BUILTIN_EVMRA
SPE_BUILTIN_EVNEG
SPE_BUILTIN_EVRNDW
SPE_BUILTIN_EVSUBFSMIAAW
SPE_BUILTIN_EVSUBFSSIAAW
SPE_BUILTIN_EVSUBFUMIAAW
SPE_BUILTIN_EVSUBFUSIAAW
SPE_BUILTIN_EVADDIW
SPE_BUILTIN_EVLDD
SPE_BUILTIN_EVLDH
SPE_BUILTIN_EVLDW
SPE_BUILTIN_EVLHHESPLAT
SPE_BUILTIN_EVLHHOSSPLAT
SPE_BUILTIN_EVLHHOUSPLAT
SPE_BUILTIN_EVLWHE
SPE_BUILTIN_EVLWHOS
SPE_BUILTIN_EVLWHOU
SPE_BUILTIN_EVLWHSPLAT
SPE_BUILTIN_EVLWWSPLAT
SPE_BUILTIN_EVRLWI
SPE_BUILTIN_EVSLWI
SPE_BUILTIN_EVSRWIS
SPE_BUILTIN_EVSRWIU
SPE_BUILTIN_EVSTDD
SPE_BUILTIN_EVSTDH
SPE_BUILTIN_EVSTDW
SPE_BUILTIN_EVSTWHE
SPE_BUILTIN_EVSTWHO
SPE_BUILTIN_EVSTWWE
SPE_BUILTIN_EVSTWWO
SPE_BUILTIN_EVSUBIFW
SPE_BUILTIN_EVCMPEQ
SPE_BUILTIN_EVCMPGTS
SPE_BUILTIN_EVCMPGTU
SPE_BUILTIN_EVCMPLTS
SPE_BUILTIN_EVCMPLTU
SPE_BUILTIN_EVFSCMPEQ
SPE_BUILTIN_EVFSCMPGT
SPE_BUILTIN_EVFSCMPLT
SPE_BUILTIN_EVFSTSTEQ
SPE_BUILTIN_EVFSTSTGT
SPE_BUILTIN_EVFSTSTLT
SPE_BUILTIN_EVSEL_CMPEQ
SPE_BUILTIN_EVSEL_CMPGTS
SPE_BUILTIN_EVSEL_CMPGTU
SPE_BUILTIN_EVSEL_CMPLTS
SPE_BUILTIN_EVSEL_CMPLTU
SPE_BUILTIN_EVSEL_FSCMPEQ
SPE_BUILTIN_EVSEL_FSCMPGT
SPE_BUILTIN_EVSEL_FSCMPLT
SPE_BUILTIN_EVSEL_FSTSTEQ
SPE_BUILTIN_EVSEL_FSTSTGT
SPE_BUILTIN_EVSEL_FSTSTLT
SPE_BUILTIN_EVSPLATFI
SPE_BUILTIN_EVSPLATI
SPE_BUILTIN_EVMWHSSMAA
SPE_BUILTIN_EVMWHSMFAA
SPE_BUILTIN_EVMWHSMIAA
SPE_BUILTIN_EVMWHUSIAA
SPE_BUILTIN_EVMWHUMIAA
SPE_BUILTIN_EVMWHSSFAN
SPE_BUILTIN_EVMWHSSIAN
SPE_BUILTIN_EVMWHSMFAN
SPE_BUILTIN_EVMWHSMIAN
SPE_BUILTIN_EVMWHUSIAN
SPE_BUILTIN_EVMWHUMIAN
SPE_BUILTIN_EVMWHGSSFAA
SPE_BUILTIN_EVMWHGSMFAA
SPE_BUILTIN_EVMWHGSMIAA
SPE_BUILTIN_EVMWHGUMIAA
SPE_BUILTIN_EVMWHGSSFAN
SPE_BUILTIN_EVMWHGSMFAN
SPE_BUILTIN_EVMWHGSMIAN
SPE_BUILTIN_EVMWHGUMIAN
SPE_BUILTIN_MTSPEFSCR
SPE_BUILTIN_MFSPEFSCR
SPE_BUILTIN_BRINC
ALTIVEC_BUILTIN_ST_INTERNAL_4si
ALTIVEC_BUILTIN_LD_INTERNAL_4si
ALTIVEC_BUILTIN_ST_INTERNAL_8hi
ALTIVEC_BUILTIN_LD_INTERNAL_8hi
ALTIVEC_BUILTIN_ST_INTERNAL_16qi
ALTIVEC_BUILTIN_LD_INTERNAL_16qi
ALTIVEC_BUILTIN_ST_INTERNAL_4sf
ALTIVEC_BUILTIN_LD_INTERNAL_4sf
ALTIVEC_BUILTIN_VADDUBM
ALTIVEC_BUILTIN_VADDUHM
ALTIVEC_BUILTIN_VADDUWM
ALTIVEC_BUILTIN_VADDFP
ALTIVEC_BUILTIN_VADDCUW
ALTIVEC_BUILTIN_VADDUBS
ALTIVEC_BUILTIN_VADDSBS
ALTIVEC_BUILTIN_VADDUHS
ALTIVEC_BUILTIN_VADDSHS
ALTIVEC_BUILTIN_VADDUWS
ALTIVEC_BUILTIN_VADDSWS
ALTIVEC_BUILTIN_VAND
ALTIVEC_BUILTIN_VANDC
ALTIVEC_BUILTIN_VAVGUB
ALTIVEC_BUILTIN_VAVGSB
ALTIVEC_BUILTIN_VAVGUH
ALTIVEC_BUILTIN_VAVGSH
ALTIVEC_BUILTIN_VAVGUW
ALTIVEC_BUILTIN_VAVGSW
ALTIVEC_BUILTIN_VCFUX
ALTIVEC_BUILTIN_VCFSX
ALTIVEC_BUILTIN_VCTSXS
ALTIVEC_BUILTIN_VCTUXS
ALTIVEC_BUILTIN_VCMPBFP
ALTIVEC_BUILTIN_VCMPEQUB
ALTIVEC_BUILTIN_VCMPEQUH
ALTIVEC_BUILTIN_VCMPEQUW
ALTIVEC_BUILTIN_VCMPEQFP
ALTIVEC_BUILTIN_VCMPGEFP
ALTIVEC_BUILTIN_VCMPGTUB
ALTIVEC_BUILTIN_VCMPGTSB
ALTIVEC_BUILTIN_VCMPGTUH
ALTIVEC_BUILTIN_VCMPGTSH
ALTIVEC_BUILTIN_VCMPGTUW
ALTIVEC_BUILTIN_VCMPGTSW
ALTIVEC_BUILTIN_VCMPGTFP
ALTIVEC_BUILTIN_VEXPTEFP
ALTIVEC_BUILTIN_VLOGEFP
ALTIVEC_BUILTIN_VMADDFP
ALTIVEC_BUILTIN_VMAXUB
ALTIVEC_BUILTIN_VMAXSB
ALTIVEC_BUILTIN_VMAXUH
ALTIVEC_BUILTIN_VMAXSH
ALTIVEC_BUILTIN_VMAXUW
ALTIVEC_BUILTIN_VMAXSW
ALTIVEC_BUILTIN_VMAXFP
ALTIVEC_BUILTIN_VMHADDSHS
ALTIVEC_BUILTIN_VMHRADDSHS
ALTIVEC_BUILTIN_VMLADDUHM
ALTIVEC_BUILTIN_VMRGHB
ALTIVEC_BUILTIN_VMRGHH
ALTIVEC_BUILTIN_VMRGHW
ALTIVEC_BUILTIN_VMRGLB
ALTIVEC_BUILTIN_VMRGLH
ALTIVEC_BUILTIN_VMRGLW
ALTIVEC_BUILTIN_VMSUMUBM
ALTIVEC_BUILTIN_VMSUMMBM
ALTIVEC_BUILTIN_VMSUMUHM
ALTIVEC_BUILTIN_VMSUMSHM
ALTIVEC_BUILTIN_VMSUMUHS
ALTIVEC_BUILTIN_VMSUMSHS
ALTIVEC_BUILTIN_VMINUB
ALTIVEC_BUILTIN_VMINSB
ALTIVEC_BUILTIN_VMINUH
ALTIVEC_BUILTIN_VMINSH
ALTIVEC_BUILTIN_VMINUW
ALTIVEC_BUILTIN_VMINSW
ALTIVEC_BUILTIN_VMINFP
ALTIVEC_BUILTIN_VMULEUB
ALTIVEC_BUILTIN_VMULESB
ALTIVEC_BUILTIN_VMULEUH
ALTIVEC_BUILTIN_VMULESH
ALTIVEC_BUILTIN_VMULOUB
ALTIVEC_BUILTIN_VMULOSB
ALTIVEC_BUILTIN_VMULOUH
ALTIVEC_BUILTIN_VMULOSH
ALTIVEC_BUILTIN_VNMSUBFP
ALTIVEC_BUILTIN_VNOR
ALTIVEC_BUILTIN_VOR
ALTIVEC_BUILTIN_VSEL_4SI
ALTIVEC_BUILTIN_VSEL_4SF
ALTIVEC_BUILTIN_VSEL_8HI
ALTIVEC_BUILTIN_VSEL_16QI
ALTIVEC_BUILTIN_VPERM_4SI
ALTIVEC_BUILTIN_VPERM_4SF
ALTIVEC_BUILTIN_VPERM_8HI
ALTIVEC_BUILTIN_VPERM_16QI
ALTIVEC_BUILTIN_VPKUHUM
ALTIVEC_BUILTIN_VPKUWUM
ALTIVEC_BUILTIN_VPKPX
ALTIVEC_BUILTIN_VPKUHSS
ALTIVEC_BUILTIN_VPKSHSS
ALTIVEC_BUILTIN_VPKUWSS
ALTIVEC_BUILTIN_VPKSWSS
ALTIVEC_BUILTIN_VPKUHUS
ALTIVEC_BUILTIN_VPKSHUS
ALTIVEC_BUILTIN_VPKUWUS
ALTIVEC_BUILTIN_VPKSWUS
ALTIVEC_BUILTIN_VREFP
ALTIVEC_BUILTIN_VRFIM
ALTIVEC_BUILTIN_VRFIN
ALTIVEC_BUILTIN_VRFIP
ALTIVEC_BUILTIN_VRFIZ
ALTIVEC_BUILTIN_VRLB
ALTIVEC_BUILTIN_VRLH
ALTIVEC_BUILTIN_VRLW
ALTIVEC_BUILTIN_VRSQRTEFP
ALTIVEC_BUILTIN_VSLB
ALTIVEC_BUILTIN_VSLH
ALTIVEC_BUILTIN_VSLW
ALTIVEC_BUILTIN_VSL
ALTIVEC_BUILTIN_VSLO
ALTIVEC_BUILTIN_VSPLTB
ALTIVEC_BUILTIN_VSPLTH
ALTIVEC_BUILTIN_VSPLTW
ALTIVEC_BUILTIN_VSPLTISB
ALTIVEC_BUILTIN_VSPLTISH
ALTIVEC_BUILTIN_VSPLTISW
ALTIVEC_BUILTIN_VSRB
ALTIVEC_BUILTIN_VSRH
ALTIVEC_BUILTIN_VSRW
ALTIVEC_BUILTIN_VSRAB
ALTIVEC_BUILTIN_VSRAH
ALTIVEC_BUILTIN_VSRAW
ALTIVEC_BUILTIN_VSR
ALTIVEC_BUILTIN_VSRO
ALTIVEC_BUILTIN_VSUBUBM
ALTIVEC_BUILTIN_VSUBUHM
ALTIVEC_BUILTIN_VSUBUWM
ALTIVEC_BUILTIN_VSUBFP
ALTIVEC_BUILTIN_VSUBCUW
ALTIVEC_BUILTIN_VSUBUBS
ALTIVEC_BUILTIN_VSUBSBS
ALTIVEC_BUILTIN_VSUBUHS
ALTIVEC_BUILTIN_VSUBSHS
ALTIVEC_BUILTIN_VSUBUWS
ALTIVEC_BUILTIN_VSUBSWS
ALTIVEC_BUILTIN_VSUM4UBS
ALTIVEC_BUILTIN_VSUM4SBS
ALTIVEC_BUILTIN_VSUM4SHS
ALTIVEC_BUILTIN_VSUM2SWS
ALTIVEC_BUILTIN_VSUMSWS
ALTIVEC_BUILTIN_VXOR
ALTIVEC_BUILTIN_VSLDOI_16QI
ALTIVEC_BUILTIN_VSLDOI_8HI
ALTIVEC_BUILTIN_VSLDOI_4SI
ALTIVEC_BUILTIN_VSLDOI_4SF
ALTIVEC_BUILTIN_VUPKHSB
ALTIVEC_BUILTIN_VUPKHPX
ALTIVEC_BUILTIN_VUPKHSH
ALTIVEC_BUILTIN_VUPKLSB
ALTIVEC_BUILTIN_VUPKLPX
ALTIVEC_BUILTIN_VUPKLSH
ALTIVEC_BUILTIN_MTVSCR
ALTIVEC_BUILTIN_MFVSCR
ALTIVEC_BUILTIN_DSSALL
ALTIVEC_BUILTIN_DSS
ALTIVEC_BUILTIN_LVSL
ALTIVEC_BUILTIN_LVSR
ALTIVEC_BUILTIN_DSTT
ALTIVEC_BUILTIN_DSTST
ALTIVEC_BUILTIN_DSTSTT
ALTIVEC_BUILTIN_DST
ALTIVEC_BUILTIN_LVEBX
ALTIVEC_BUILTIN_LVEHX
ALTIVEC_BUILTIN_LVEWX
ALTIVEC_BUILTIN_LVXL
ALTIVEC_BUILTIN_LVX
ALTIVEC_BUILTIN_STVX
ALTIVEC_BUILTIN_STVEBX
ALTIVEC_BUILTIN_STVEHX
ALTIVEC_BUILTIN_STVEWX
ALTIVEC_BUILTIN_STVXL
ALTIVEC_BUILTIN_VCMPBFP_P
ALTIVEC_BUILTIN_VCMPEQFP_P
ALTIVEC_BUILTIN_VCMPEQUB_P
ALTIVEC_BUILTIN_VCMPEQUH_P
ALTIVEC_BUILTIN_VCMPEQUW_P
ALTIVEC_BUILTIN_VCMPGEFP_P
ALTIVEC_BUILTIN_VCMPGTFP_P
ALTIVEC_BUILTIN_VCMPGTSB_P
ALTIVEC_BUILTIN_VCMPGTSH_P
ALTIVEC_BUILTIN_VCMPGTSW_P
ALTIVEC_BUILTIN_VCMPGTUB_P
ALTIVEC_BUILTIN_VCMPGTUH_P
ALTIVEC_BUILTIN_VCMPGTUW_P
ALTIVEC_BUILTIN_ABSS_V4SI
ALTIVEC_BUILTIN_ABSS_V8HI
ALTIVEC_BUILTIN_ABSS_V16QI
ALTIVEC_BUILTIN_ABS_V4SI
ALTIVEC_BUILTIN_ABS_V4SF
ALTIVEC_BUILTIN_ABS_V8HI
ALTIVEC_BUILTIN_ABS_V16QI
ALTIVEC_BUILTIN_MASK_FOR_LOAD
ALTIVEC_BUILTIN_MASK_FOR_STORE
ALTIVEC_BUILTIN_VEC_INIT_V4SI
ALTIVEC_BUILTIN_VEC_INIT_V8HI
ALTIVEC_BUILTIN_VEC_INIT_V16QI
ALTIVEC_BUILTIN_VEC_INIT_V4SF
ALTIVEC_BUILTIN_VEC_SET_V4SI
ALTIVEC_BUILTIN_VEC_SET_V8HI
ALTIVEC_BUILTIN_VEC_SET_V16QI
ALTIVEC_BUILTIN_VEC_SET_V4SF
ALTIVEC_BUILTIN_VEC_EXT_V4SI
ALTIVEC_BUILTIN_VEC_EXT_V8HI
ALTIVEC_BUILTIN_VEC_EXT_V16QI
ALTIVEC_BUILTIN_VEC_EXT_V4SF
ALTIVEC_BUILTIN_VCMPEQ_P
ALTIVEC_BUILTIN_OVERLOADED_FIRST
ALTIVEC_BUILTIN_VCMPGT_P
ALTIVEC_BUILTIN_VCMPGE_P
ALTIVEC_BUILTIN_VEC_ABS
ALTIVEC_BUILTIN_VEC_ABSS
ALTIVEC_BUILTIN_VEC_ADD
ALTIVEC_BUILTIN_VEC_ADDC
ALTIVEC_BUILTIN_VEC_ADDS
ALTIVEC_BUILTIN_VEC_AND
ALTIVEC_BUILTIN_VEC_ANDC
ALTIVEC_BUILTIN_VEC_AVG
ALTIVEC_BUILTIN_VEC_CEIL
ALTIVEC_BUILTIN_VEC_CMPB
ALTIVEC_BUILTIN_VEC_CMPEQ
ALTIVEC_BUILTIN_VEC_CMPEQUB
ALTIVEC_BUILTIN_VEC_CMPEQUH
ALTIVEC_BUILTIN_VEC_CMPEQUW
ALTIVEC_BUILTIN_VEC_CMPGE
ALTIVEC_BUILTIN_VEC_CMPGT
ALTIVEC_BUILTIN_VEC_CMPLE
ALTIVEC_BUILTIN_VEC_CMPLT
ALTIVEC_BUILTIN_VEC_CTF
ALTIVEC_BUILTIN_VEC_CTS
ALTIVEC_BUILTIN_VEC_CTU
ALTIVEC_BUILTIN_VEC_DST
ALTIVEC_BUILTIN_VEC_DSTST
ALTIVEC_BUILTIN_VEC_DSTSTT
ALTIVEC_BUILTIN_VEC_DSTT
ALTIVEC_BUILTIN_VEC_EXPTE
ALTIVEC_BUILTIN_VEC_FLOOR
ALTIVEC_BUILTIN_VEC_LD
ALTIVEC_BUILTIN_VEC_LDE
ALTIVEC_BUILTIN_VEC_LDL
ALTIVEC_BUILTIN_VEC_LOGE
ALTIVEC_BUILTIN_VEC_LVEBX
ALTIVEC_BUILTIN_VEC_LVEHX
ALTIVEC_BUILTIN_VEC_LVEWX
ALTIVEC_BUILTIN_VEC_LVSL
ALTIVEC_BUILTIN_VEC_LVSR
ALTIVEC_BUILTIN_VEC_MADD
ALTIVEC_BUILTIN_VEC_MADDS
ALTIVEC_BUILTIN_VEC_MAX
ALTIVEC_BUILTIN_VEC_MERGEH
ALTIVEC_BUILTIN_VEC_MERGEL
ALTIVEC_BUILTIN_VEC_MIN
ALTIVEC_BUILTIN_VEC_MLADD
ALTIVEC_BUILTIN_VEC_MPERM
ALTIVEC_BUILTIN_VEC_MRADDS
ALTIVEC_BUILTIN_VEC_MRGHB
ALTIVEC_BUILTIN_VEC_MRGHH
ALTIVEC_BUILTIN_VEC_MRGHW
ALTIVEC_BUILTIN_VEC_MRGLB
ALTIVEC_BUILTIN_VEC_MRGLH
ALTIVEC_BUILTIN_VEC_MRGLW
ALTIVEC_BUILTIN_VEC_MSUM
ALTIVEC_BUILTIN_VEC_MSUMS
ALTIVEC_BUILTIN_VEC_MTVSCR
ALTIVEC_BUILTIN_VEC_MULE
ALTIVEC_BUILTIN_VEC_MULO
ALTIVEC_BUILTIN_VEC_NMSUB
ALTIVEC_BUILTIN_VEC_NOR
ALTIVEC_BUILTIN_VEC_OR
ALTIVEC_BUILTIN_VEC_PACK
ALTIVEC_BUILTIN_VEC_PACKPX
ALTIVEC_BUILTIN_VEC_PACKS
ALTIVEC_BUILTIN_VEC_PACKSU
ALTIVEC_BUILTIN_VEC_PERM
ALTIVEC_BUILTIN_VEC_RE
ALTIVEC_BUILTIN_VEC_RL
ALTIVEC_BUILTIN_VEC_ROUND
ALTIVEC_BUILTIN_VEC_RSQRTE
ALTIVEC_BUILTIN_VEC_SEL
ALTIVEC_BUILTIN_VEC_SL
ALTIVEC_BUILTIN_VEC_SLD
ALTIVEC_BUILTIN_VEC_SLL
ALTIVEC_BUILTIN_VEC_SLO
ALTIVEC_BUILTIN_VEC_SPLAT
ALTIVEC_BUILTIN_VEC_SPLAT_S16
ALTIVEC_BUILTIN_VEC_SPLAT_S32
ALTIVEC_BUILTIN_VEC_SPLAT_S8
ALTIVEC_BUILTIN_VEC_SPLAT_U16
ALTIVEC_BUILTIN_VEC_SPLAT_U32
ALTIVEC_BUILTIN_VEC_SPLAT_U8
ALTIVEC_BUILTIN_VEC_SPLTB
ALTIVEC_BUILTIN_VEC_SPLTH
ALTIVEC_BUILTIN_VEC_SPLTW
ALTIVEC_BUILTIN_VEC_SR
ALTIVEC_BUILTIN_VEC_SRA
ALTIVEC_BUILTIN_VEC_SRL
ALTIVEC_BUILTIN_VEC_SRO
ALTIVEC_BUILTIN_VEC_ST
ALTIVEC_BUILTIN_VEC_STE
ALTIVEC_BUILTIN_VEC_STL
ALTIVEC_BUILTIN_VEC_STVEBX
ALTIVEC_BUILTIN_VEC_STVEHX
ALTIVEC_BUILTIN_VEC_STVEWX
ALTIVEC_BUILTIN_VEC_SUB
ALTIVEC_BUILTIN_VEC_SUBC
ALTIVEC_BUILTIN_VEC_SUBS
ALTIVEC_BUILTIN_VEC_SUM2S
ALTIVEC_BUILTIN_VEC_SUM4S
ALTIVEC_BUILTIN_VEC_SUMS
ALTIVEC_BUILTIN_VEC_TRUNC
ALTIVEC_BUILTIN_VEC_UNPACKH
ALTIVEC_BUILTIN_VEC_UNPACKL
ALTIVEC_BUILTIN_VEC_VADDFP
ALTIVEC_BUILTIN_VEC_VADDSBS
ALTIVEC_BUILTIN_VEC_VADDSHS
ALTIVEC_BUILTIN_VEC_VADDSWS
ALTIVEC_BUILTIN_VEC_VADDUBM
ALTIVEC_BUILTIN_VEC_VADDUBS
ALTIVEC_BUILTIN_VEC_VADDUHM
ALTIVEC_BUILTIN_VEC_VADDUHS
ALTIVEC_BUILTIN_VEC_VADDUWM
ALTIVEC_BUILTIN_VEC_VADDUWS
ALTIVEC_BUILTIN_VEC_VAVGSB
ALTIVEC_BUILTIN_VEC_VAVGSH
ALTIVEC_BUILTIN_VEC_VAVGSW
ALTIVEC_BUILTIN_VEC_VAVGUB
ALTIVEC_BUILTIN_VEC_VAVGUH
ALTIVEC_BUILTIN_VEC_VAVGUW
ALTIVEC_BUILTIN_VEC_VCFSX
ALTIVEC_BUILTIN_VEC_VCFUX
ALTIVEC_BUILTIN_VEC_VCMPEQFP
ALTIVEC_BUILTIN_VEC_VCMPEQUB
ALTIVEC_BUILTIN_VEC_VCMPEQUH
ALTIVEC_BUILTIN_VEC_VCMPEQUW
ALTIVEC_BUILTIN_VEC_VCMPGTFP
ALTIVEC_BUILTIN_VEC_VCMPGTSB
ALTIVEC_BUILTIN_VEC_VCMPGTSH
ALTIVEC_BUILTIN_VEC_VCMPGTSW
ALTIVEC_BUILTIN_VEC_VCMPGTUB
ALTIVEC_BUILTIN_VEC_VCMPGTUH
ALTIVEC_BUILTIN_VEC_VCMPGTUW
ALTIVEC_BUILTIN_VEC_VMAXFP
ALTIVEC_BUILTIN_VEC_VMAXSB
ALTIVEC_BUILTIN_VEC_VMAXSH
ALTIVEC_BUILTIN_VEC_VMAXSW
ALTIVEC_BUILTIN_VEC_VMAXUB
ALTIVEC_BUILTIN_VEC_VMAXUH
ALTIVEC_BUILTIN_VEC_VMAXUW
ALTIVEC_BUILTIN_VEC_VMINFP
ALTIVEC_BUILTIN_VEC_VMINSB
ALTIVEC_BUILTIN_VEC_VMINSH
ALTIVEC_BUILTIN_VEC_VMINSW
ALTIVEC_BUILTIN_VEC_VMINUB
ALTIVEC_BUILTIN_VEC_VMINUH
ALTIVEC_BUILTIN_VEC_VMINUW
ALTIVEC_BUILTIN_VEC_VMRGHB
ALTIVEC_BUILTIN_VEC_VMRGHH
ALTIVEC_BUILTIN_VEC_VMRGHW
ALTIVEC_BUILTIN_VEC_VMRGLB
ALTIVEC_BUILTIN_VEC_VMRGLH
ALTIVEC_BUILTIN_VEC_VMRGLW
ALTIVEC_BUILTIN_VEC_VMSUMMBM
ALTIVEC_BUILTIN_VEC_VMSUMSHM
ALTIVEC_BUILTIN_VEC_VMSUMSHS
ALTIVEC_BUILTIN_VEC_VMSUMUBM
ALTIVEC_BUILTIN_VEC_VMSUMUHM
ALTIVEC_BUILTIN_VEC_VMSUMUHS
ALTIVEC_BUILTIN_VEC_VMULESB
ALTIVEC_BUILTIN_VEC_VMULESH
ALTIVEC_BUILTIN_VEC_VMULEUB
ALTIVEC_BUILTIN_VEC_VMULEUH
ALTIVEC_BUILTIN_VEC_VMULOSB
ALTIVEC_BUILTIN_VEC_VMULOSH
ALTIVEC_BUILTIN_VEC_VMULOUB
ALTIVEC_BUILTIN_VEC_VMULOUH
ALTIVEC_BUILTIN_VEC_VPKSHSS
ALTIVEC_BUILTIN_VEC_VPKSHUS
ALTIVEC_BUILTIN_VEC_VPKSWSS
ALTIVEC_BUILTIN_VEC_VPKSWUS
ALTIVEC_BUILTIN_VEC_VPKUHUM
ALTIVEC_BUILTIN_VEC_VPKUHUS
ALTIVEC_BUILTIN_VEC_VPKUWUM
ALTIVEC_BUILTIN_VEC_VPKUWUS
ALTIVEC_BUILTIN_VEC_VRLB
ALTIVEC_BUILTIN_VEC_VRLH
ALTIVEC_BUILTIN_VEC_VRLW
ALTIVEC_BUILTIN_VEC_VSLB
ALTIVEC_BUILTIN_VEC_VSLH
ALTIVEC_BUILTIN_VEC_VSLW
ALTIVEC_BUILTIN_VEC_VSPLTB
ALTIVEC_BUILTIN_VEC_VSPLTH
ALTIVEC_BUILTIN_VEC_VSPLTW
ALTIVEC_BUILTIN_VEC_VSRAB
ALTIVEC_BUILTIN_VEC_VSRAH
ALTIVEC_BUILTIN_VEC_VSRAW
ALTIVEC_BUILTIN_VEC_VSRB
ALTIVEC_BUILTIN_VEC_VSRH
ALTIVEC_BUILTIN_VEC_VSRW
ALTIVEC_BUILTIN_VEC_VSUBFP
ALTIVEC_BUILTIN_VEC_VSUBSBS
ALTIVEC_BUILTIN_VEC_VSUBSHS
ALTIVEC_BUILTIN_VEC_VSUBSWS
ALTIVEC_BUILTIN_VEC_VSUBUBM
ALTIVEC_BUILTIN_VEC_VSUBUBS
ALTIVEC_BUILTIN_VEC_VSUBUHM
ALTIVEC_BUILTIN_VEC_VSUBUHS
ALTIVEC_BUILTIN_VEC_VSUBUWM
ALTIVEC_BUILTIN_VEC_VSUBUWS
ALTIVEC_BUILTIN_VEC_VSUM4SBS
ALTIVEC_BUILTIN_VEC_VSUM4SHS
ALTIVEC_BUILTIN_VEC_VSUM4UBS
ALTIVEC_BUILTIN_VEC_VUPKHPX
ALTIVEC_BUILTIN_VEC_VUPKHSB
ALTIVEC_BUILTIN_VEC_VUPKHSH
ALTIVEC_BUILTIN_VEC_VUPKLPX
ALTIVEC_BUILTIN_VEC_VUPKLSB
ALTIVEC_BUILTIN_VEC_VUPKLSH
ALTIVEC_BUILTIN_VEC_XOR
ALTIVEC_BUILTIN_VEC_STEP
ALTIVEC_BUILTIN_OVERLOADED_LAST
SPE_BUILTIN_EVADDW
SPE_BUILTIN_EVAND
SPE_BUILTIN_EVANDC
SPE_BUILTIN_EVDIVWS
SPE_BUILTIN_EVDIVWU
SPE_BUILTIN_EVEQV
SPE_BUILTIN_EVFSADD
SPE_BUILTIN_EVFSDIV
SPE_BUILTIN_EVFSMUL
SPE_BUILTIN_EVFSSUB
SPE_BUILTIN_EVLDDX
SPE_BUILTIN_EVLDHX
SPE_BUILTIN_EVLDWX
SPE_BUILTIN_EVLHHESPLATX
SPE_BUILTIN_EVLHHOSSPLATX
SPE_BUILTIN_EVLHHOUSPLATX
SPE_BUILTIN_EVLWHEX
SPE_BUILTIN_EVLWHOSX
SPE_BUILTIN_EVLWHOUX
SPE_BUILTIN_EVLWHSPLATX
SPE_BUILTIN_EVLWWSPLATX
SPE_BUILTIN_EVMERGEHI
SPE_BUILTIN_EVMERGEHILO
SPE_BUILTIN_EVMERGELO
SPE_BUILTIN_EVMERGELOHI
SPE_BUILTIN_EVMHEGSMFAA
SPE_BUILTIN_EVMHEGSMFAN
SPE_BUILTIN_EVMHEGSMIAA
SPE_BUILTIN_EVMHEGSMIAN
SPE_BUILTIN_EVMHEGUMIAA
SPE_BUILTIN_EVMHEGUMIAN
SPE_BUILTIN_EVMHESMF
SPE_BUILTIN_EVMHESMFA
SPE_BUILTIN_EVMHESMFAAW
SPE_BUILTIN_EVMHESMFANW
SPE_BUILTIN_EVMHESMI
SPE_BUILTIN_EVMHESMIA
SPE_BUILTIN_EVMHESMIAAW
SPE_BUILTIN_EVMHESMIANW
SPE_BUILTIN_EVMHESSF
SPE_BUILTIN_EVMHESSFA
SPE_BUILTIN_EVMHESSFAAW
SPE_BUILTIN_EVMHESSFANW
SPE_BUILTIN_EVMHESSIAAW
SPE_BUILTIN_EVMHESSIANW
SPE_BUILTIN_EVMHEUMI
SPE_BUILTIN_EVMHEUMIA
SPE_BUILTIN_EVMHEUMIAAW
SPE_BUILTIN_EVMHEUMIANW
SPE_BUILTIN_EVMHEUSIAAW
SPE_BUILTIN_EVMHEUSIANW
SPE_BUILTIN_EVMHOGSMFAA
SPE_BUILTIN_EVMHOGSMFAN
SPE_BUILTIN_EVMHOGSMIAA
SPE_BUILTIN_EVMHOGSMIAN
SPE_BUILTIN_EVMHOGUMIAA
SPE_BUILTIN_EVMHOGUMIAN
SPE_BUILTIN_EVMHOSMF
SPE_BUILTIN_EVMHOSMFA
SPE_BUILTIN_EVMHOSMFAAW
SPE_BUILTIN_EVMHOSMFANW
SPE_BUILTIN_EVMHOSMI
SPE_BUILTIN_EVMHOSMIA
SPE_BUILTIN_EVMHOSMIAAW
SPE_BUILTIN_EVMHOSMIANW
SPE_BUILTIN_EVMHOSSF
SPE_BUILTIN_EVMHOSSFA
SPE_BUILTIN_EVMHOSSFAAW
SPE_BUILTIN_EVMHOSSFANW
SPE_BUILTIN_EVMHOSSIAAW
SPE_BUILTIN_EVMHOSSIANW
SPE_BUILTIN_EVMHOUMI
SPE_BUILTIN_EVMHOUMIA
SPE_BUILTIN_EVMHOUMIAAW
SPE_BUILTIN_EVMHOUMIANW
SPE_BUILTIN_EVMHOUSIAAW
SPE_BUILTIN_EVMHOUSIANW
SPE_BUILTIN_EVMWHSMF
SPE_BUILTIN_EVMWHSMFA
SPE_BUILTIN_EVMWHSMI
SPE_BUILTIN_EVMWHSMIA
SPE_BUILTIN_EVMWHSSF
SPE_BUILTIN_EVMWHSSFA
SPE_BUILTIN_EVMWHUMI
SPE_BUILTIN_EVMWHUMIA
SPE_BUILTIN_EVMWLSMIAAW
SPE_BUILTIN_EVMWLSMIANW
SPE_BUILTIN_EVMWLSSIAAW
SPE_BUILTIN_EVMWLSSIANW
SPE_BUILTIN_EVMWLUMI
SPE_BUILTIN_EVMWLUMIA
SPE_BUILTIN_EVMWLUMIAAW
SPE_BUILTIN_EVMWLUMIANW
SPE_BUILTIN_EVMWLUSIAAW
SPE_BUILTIN_EVMWLUSIANW
SPE_BUILTIN_EVMWSMF
SPE_BUILTIN_EVMWSMFA
SPE_BUILTIN_EVMWSMFAA
SPE_BUILTIN_EVMWSMFAN
SPE_BUILTIN_EVMWSMI
SPE_BUILTIN_EVMWSMIA
SPE_BUILTIN_EVMWSMIAA
SPE_BUILTIN_EVMWSMIAN
SPE_BUILTIN_EVMWHSSFAA
SPE_BUILTIN_EVMWSSF
SPE_BUILTIN_EVMWSSFA
SPE_BUILTIN_EVMWSSFAA
SPE_BUILTIN_EVMWSSFAN
SPE_BUILTIN_EVMWUMI
SPE_BUILTIN_EVMWUMIA
SPE_BUILTIN_EVMWUMIAA
SPE_BUILTIN_EVMWUMIAN
SPE_BUILTIN_EVNAND
SPE_BUILTIN_EVNOR
SPE_BUILTIN_EVOR
SPE_BUILTIN_EVORC
SPE_BUILTIN_EVRLW
SPE_BUILTIN_EVSLW
SPE_BUILTIN_EVSRWS
SPE_BUILTIN_EVSRWU
SPE_BUILTIN_EVSTDDX
SPE_BUILTIN_EVSTDHX
SPE_BUILTIN_EVSTDWX
SPE_BUILTIN_EVSTWHEX
SPE_BUILTIN_EVSTWHOX
SPE_BUILTIN_EVSTWWEX
SPE_BUILTIN_EVSTWWOX
SPE_BUILTIN_EVSUBFW
SPE_BUILTIN_EVXOR
SPE_BUILTIN_EVABS
SPE_BUILTIN_EVADDSMIAAW
SPE_BUILTIN_EVADDSSIAAW
SPE_BUILTIN_EVADDUMIAAW
SPE_BUILTIN_EVADDUSIAAW
SPE_BUILTIN_EVCNTLSW
SPE_BUILTIN_EVCNTLZW
SPE_BUILTIN_EVEXTSB
SPE_BUILTIN_EVEXTSH
SPE_BUILTIN_EVFSABS
SPE_BUILTIN_EVFSCFSF
SPE_BUILTIN_EVFSCFSI
SPE_BUILTIN_EVFSCFUF
SPE_BUILTIN_EVFSCFUI
SPE_BUILTIN_EVFSCTSF
SPE_BUILTIN_EVFSCTSI
SPE_BUILTIN_EVFSCTSIZ
SPE_BUILTIN_EVFSCTUF
SPE_BUILTIN_EVFSCTUI
SPE_BUILTIN_EVFSCTUIZ
SPE_BUILTIN_EVFSNABS
SPE_BUILTIN_EVFSNEG
SPE_BUILTIN_EVMRA
SPE_BUILTIN_EVNEG
SPE_BUILTIN_EVRNDW
SPE_BUILTIN_EVSUBFSMIAAW
SPE_BUILTIN_EVSUBFSSIAAW
SPE_BUILTIN_EVSUBFUMIAAW
SPE_BUILTIN_EVSUBFUSIAAW
SPE_BUILTIN_EVADDIW
SPE_BUILTIN_EVLDD
SPE_BUILTIN_EVLDH
SPE_BUILTIN_EVLDW
SPE_BUILTIN_EVLHHESPLAT
SPE_BUILTIN_EVLHHOSSPLAT
SPE_BUILTIN_EVLHHOUSPLAT
SPE_BUILTIN_EVLWHE
SPE_BUILTIN_EVLWHOS
SPE_BUILTIN_EVLWHOU
SPE_BUILTIN_EVLWHSPLAT
SPE_BUILTIN_EVLWWSPLAT
SPE_BUILTIN_EVRLWI
SPE_BUILTIN_EVSLWI
SPE_BUILTIN_EVSRWIS
SPE_BUILTIN_EVSRWIU
SPE_BUILTIN_EVSTDD
SPE_BUILTIN_EVSTDH
SPE_BUILTIN_EVSTDW
SPE_BUILTIN_EVSTWHE
SPE_BUILTIN_EVSTWHO
SPE_BUILTIN_EVSTWWE
SPE_BUILTIN_EVSTWWO
SPE_BUILTIN_EVSUBIFW
SPE_BUILTIN_EVCMPEQ
SPE_BUILTIN_EVCMPGTS
SPE_BUILTIN_EVCMPGTU
SPE_BUILTIN_EVCMPLTS
SPE_BUILTIN_EVCMPLTU
SPE_BUILTIN_EVFSCMPEQ
SPE_BUILTIN_EVFSCMPGT
SPE_BUILTIN_EVFSCMPLT
SPE_BUILTIN_EVFSTSTEQ
SPE_BUILTIN_EVFSTSTGT
SPE_BUILTIN_EVFSTSTLT
SPE_BUILTIN_EVSEL_CMPEQ
SPE_BUILTIN_EVSEL_CMPGTS
SPE_BUILTIN_EVSEL_CMPGTU
SPE_BUILTIN_EVSEL_CMPLTS
SPE_BUILTIN_EVSEL_CMPLTU
SPE_BUILTIN_EVSEL_FSCMPEQ
SPE_BUILTIN_EVSEL_FSCMPGT
SPE_BUILTIN_EVSEL_FSCMPLT
SPE_BUILTIN_EVSEL_FSTSTEQ
SPE_BUILTIN_EVSEL_FSTSTGT
SPE_BUILTIN_EVSEL_FSTSTLT
SPE_BUILTIN_EVSPLATFI
SPE_BUILTIN_EVSPLATI
SPE_BUILTIN_EVMWHSSMAA
SPE_BUILTIN_EVMWHSMFAA
SPE_BUILTIN_EVMWHSMIAA
SPE_BUILTIN_EVMWHUSIAA
SPE_BUILTIN_EVMWHUMIAA
SPE_BUILTIN_EVMWHSSFAN
SPE_BUILTIN_EVMWHSSIAN
SPE_BUILTIN_EVMWHSMFAN
SPE_BUILTIN_EVMWHSMIAN
SPE_BUILTIN_EVMWHUSIAN
SPE_BUILTIN_EVMWHUMIAN
SPE_BUILTIN_EVMWHGSSFAA
SPE_BUILTIN_EVMWHGSMFAA
SPE_BUILTIN_EVMWHGSMIAA
SPE_BUILTIN_EVMWHGUMIAA
SPE_BUILTIN_EVMWHGSSFAN
SPE_BUILTIN_EVMWHGSMFAN
SPE_BUILTIN_EVMWHGSMIAN
SPE_BUILTIN_EVMWHGUMIAN
SPE_BUILTIN_MTSPEFSCR
SPE_BUILTIN_MFSPEFSCR
SPE_BUILTIN_BRINC
RS6000_BUILTIN_COUNT

Definition at line 2831 of file rs6000.h.

---

Variable Documentation

int flag_expensive_optimizations

Definition at line 552 of file toplev.c.

Referenced by alpha_emit_set_const_1(), base_alias_check(), calculate_needs_all_insns(), choose_reload_regs(), combine_temp_slots(), cse_insn(), cxx_maybe_build_cleanup(), decode_options(), emit_output_reload_insns(), emit_store_flag(), find_best_addr(), gate_duplicate_computed_gotos(), gen_block_redirect(), make_extraction(), preserve_subexpressions_p(), regclass(), regmove_optimize(), reload_cse_regs(), rest_of_compilation(), rest_of_handle_gcse(), sh_can_redirect_branch(), sparc_check_64(), and try_combine().

int flag_pic

Definition at line 779 of file toplev.c.

int frame_pointer_needed

Definition at line 189 of file final.c.

int optimize

Definition at line 352 of file genattrtab.c.

const char* rs6000_abi_string

Definition at line 110 of file rs6000.c.

int rs6000_altivec_abi

Definition at line 75 of file rs6000.c.

int rs6000_compare_fp_p

Definition at line 86 of file rs6000.c.

struct rtx_def* rs6000_compare_op0

Definition at line 85 of file rs6000.c.

struct rtx_def * rs6000_compare_op1

Definition at line 85 of file rs6000.c.

enum processor_type rs6000_cpu

Definition at line 61 of file rs6000.c.

enum rs6000_abi rs6000_current_abi

Definition at line 107 of file rs6000.c.

int rs6000_debug_arg

Definition at line 115 of file rs6000.c.

const char* rs6000_debug_name

Definition at line 113 of file rs6000.c.

int rs6000_debug_stack

Definition at line 114 of file rs6000.c.

const char* rs6000_long_double_size_string

Definition at line 71 of file rs6000.c.

int rs6000_long_double_type_size

Definition at line 72 of file rs6000.c.

char rs6000_reg_names[][8]

Definition at line 183 of file rs6000.c.

struct rs6000_cpu_select rs6000_select[]

Definition at line 62 of file rs6000.c.

int target_flags

Definition at line 35 of file gensupport.c.

int toc_initialized

Definition at line 118 of file rs6000.c.