osprey-gcc-4.2.0/gcc/config/sparc/sparc.h File Reference

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Data Types

type  processor_costs
type  sparc_cpu_select
type  sparc_args

Defines

#define TARGET_CPU_CPP_BUILTINS()
#define DEFAULT_ARCH32_P   ((TARGET_DEFAULT & MASK_64BIT) == 0)
#define TARGET_ARCH32   (DEFAULT_ARCH32_P)
#define TARGET_ARCH64   (! TARGET_ARCH32)
#define TARGET_CM_MEDLOW   (sparc_cmodel == CM_MEDLOW)
#define TARGET_CM_MEDMID   (sparc_cmodel == CM_MEDMID)
#define TARGET_CM_MEDANY   (sparc_cmodel == CM_MEDANY)
#define TARGET_CM_EMBMEDANY   (sparc_cmodel == CM_EMBMEDANY)
#define SPARC_DEFAULT_CMODEL   CM_32
#define SPARC_RELAXED_ORDERING   false
#define NEED_INDICATE_EXEC_STACK   0
#define EMBMEDANY_BASE_REG   "%g4"
#define TARGET_CPU_sparc   0
#define TARGET_CPU_v7   0
#define TARGET_CPU_sparclet   1
#define TARGET_CPU_sparclite   2
#define TARGET_CPU_v8   3
#define TARGET_CPU_supersparc   4
#define TARGET_CPU_hypersparc   5
#define TARGET_CPU_sparc86x   6
#define TARGET_CPU_sparclite86x   6
#define TARGET_CPU_v9   7
#define TARGET_CPU_sparcv9   7
#define TARGET_CPU_sparc64   7
#define TARGET_CPU_ultrasparc   8
#define TARGET_CPU_ultrasparc3   9
#define TARGET_CPU_niagara   10
#define CPP_CPU64_DEFAULT_SPEC   ""
#define ASM_CPU64_DEFAULT_SPEC   ""
#define CPP_CPU32_DEFAULT_SPEC   ""
#define ASM_CPU32_DEFAULT_SPEC   ""
#define CPP_CPU_DEFAULT_SPEC   (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
#define ASM_CPU_DEFAULT_SPEC   (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
#define CPP_CPU_SPEC   "\%{msoft-float:-D_SOFT_FLOAT} \%{mcypress:} \%{msparclite:-D__sparclite__} \%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \%{mv8:-D__sparc_v8__} \%{msupersparc:-D__supersparc__ -D__sparc_v8__} \%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \%{mcpu=sparclite:-D__sparclite__} \%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \%{mcpu=v8:-D__sparc_v8__} \%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \%{mcpu=sparclite86x:-D__sparclite86x__} \%{mcpu=v9:-D__sparc_v9__} \%{mcpu=ultrasparc:-D__sparc_v9__} \%{mcpu=ultrasparc3:-D__sparc_v9__} \%{mcpu=niagara:-D__sparc_v9__} \%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \"
#define CPP_ARCH32_SPEC   ""
#define CPP_ARCH64_SPEC   "-D__arch64__"
#define CPP_ARCH_DEFAULT_SPEC   (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
#define CPP_ARCH_SPEC   "\%{m32:%(cpp_arch32)} \%{m64:%(cpp_arch64)} \%{!m32:%{!m64:%(cpp_arch_default)}} \"
#define CPP_ENDIAN_SPEC   "\%{mlittle-endian:-D__LITTLE_ENDIAN__} \%{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
#define CPP_SUBTARGET_SPEC   ""
#define CPP_SPEC   "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
#define CC1_SPEC   "\%{sun4:} %{target:} \%{mcypress:-mcpu=cypress} \%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \"
#define ASM_CPU_SPEC   "\%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \%{msparclite:-Asparclite} \%{mf930:-Asparclite} %{mf934:-Asparclite} \%{mcpu=sparclite:-Asparclite} \%{mcpu=sparclite86x:-Asparclite} \%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \%{mv8plus:-Av8plus} \%{mcpu=v9:-Av9} \%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \%{mcpu=niagara:%{!mv8plus:-Av9b}} \%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \"
#define ASM_ARCH32_SPEC   "-32"
#define ASM_ARCH64_SPEC   "-64"
#define ASM_ARCH_DEFAULT_SPEC   (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
#define ASM_ARCH_SPEC   "\%{m32:%(asm_arch32)} \%{m64:%(asm_arch64)} \%{!m32:%{!m64:%(asm_arch_default)}} \"
#define ASM_RELAX_SPEC   ""
#define ASM_SPEC   "\%{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \%(asm_cpu) %(asm_relax)"
#define AS_NEEDS_DASH_FOR_PIPED_INPUT
#define EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#define LINK_GCC_C_SEQUENCE_SPEC   "%G %L %G %L"
#define PTRDIFF_TYPE   (TARGET_ARCH64 ? "long int" : "int")
#define SIZE_TYPE   (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
#define WCHAR_TYPE   "short unsigned int"
#define WCHAR_TYPE_SIZE   16
#define CAN_DEBUG_WITHOUT_FP
#define OVERRIDE_OPTIONS   sparc_override_options ()
#define MASK_ISA   (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
#define TARGET_HARD_MUL32
#define TARGET_HARD_MUL
#define TARGET_DEFAULT   (MASK_APP_REGS + MASK_FPU)
#define sparc_cpu_attr   ((enum attr_cpu) sparc_cpu)
#define OPTION_DEFAULT_SPECS
#define BITS_BIG_ENDIAN   1
#define BYTES_BIG_ENDIAN   1
#define WORDS_BIG_ENDIAN   1
#define LIBGCC2_WORDS_BIG_ENDIAN   1
#define MAX_BITS_PER_WORD   64
#define UNITS_PER_WORD   (TARGET_ARCH64 ? 8 : 4)
#define MIN_UNITS_PER_WORD   4
#define UNITS_PER_SIMD_WORD   (TARGET_VIS ? 8 : UNITS_PER_WORD)
#define SHORT_TYPE_SIZE   16
#define INT_TYPE_SIZE   32
#define LONG_TYPE_SIZE   (TARGET_ARCH64 ? 64 : 32)
#define LONG_LONG_TYPE_SIZE   64
#define FLOAT_TYPE_SIZE   32
#define DOUBLE_TYPE_SIZE   64
#define POINTER_SIZE   (TARGET_PTR64 ? 64 : 32)
#define POINTERS_EXTEND_UNSIGNED   1
#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE)
#define PARM_BOUNDARY   (TARGET_ARCH64 ? 64 : 32)
#define STACK_BOUNDARY   (TARGET_ARCH64 ? 128 : 64)
#define SPARC_STACK_BOUNDARY_HACK   (TARGET_ARCH64 && TARGET_STACK_BIAS)
#define SPARC_STACK_ALIGN(LOC)   (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
#define FUNCTION_BOUNDARY   32
#define EMPTY_FIELD_BOUNDARY   (TARGET_ARCH64 ? 64 : 32)
#define STRUCTURE_SIZE_BOUNDARY   8
#define PCC_BITFIELD_TYPE_MATTERS   1
#define BIGGEST_ALIGNMENT   (TARGET_ARCH64 ? 128 : 64)
#define FASTEST_ALIGNMENT   64
#define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED)
#define CONSTANT_ALIGNMENT(EXP, ALIGN)
#define DATA_ALIGNMENT(TYPE, ALIGN)
#define STRICT_ALIGNMENT   1
#define MAX_TEXT_ALIGN   32
#define FIRST_PSEUDO_REGISTER   102
#define SPARC_FIRST_FP_REG   32
#define SPARC_FIRST_V9_FP_REG   64
#define SPARC_LAST_V9_FP_REG   95
#define SPARC_FIRST_V9_FCC_REG   96
#define SPARC_LAST_V9_FCC_REG   99
#define SPARC_FCC_REG   96
#define SPARC_ICC_REG   100
#define SPARC_FP_REG_P(REGNO)   ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
#define SPARC_OUTGOING_INT_ARG_FIRST   8
#define SPARC_INCOMING_INT_ARG_FIRST   24
#define SPARC_FP_ARG_FIRST   32
#define FIXED_REGISTERS
#define CALL_USED_REGISTERS
#define CONDITIONAL_REGISTER_USAGE
#define HARD_REGNO_NREGS(REGNO, MODE)
#define REGMODE_NATURAL_SIZE(MODE)   ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
#define HARD_REGNO_MODE_OK(REGNO, MODE)   ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
#define HARD_REGNO_RENAME_OK(FROM, TO)   ((FROM) != 1)
#define MODES_TIEABLE_P(MODE1, MODE2)
#define STACK_POINTER_REGNUM   14
#define SPARC_STACK_BIAS   ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
#define STACK_POINTER_OFFSET   (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
#define HARD_FRAME_POINTER_REGNUM   30
#define FRAME_POINTER_REGNUM   101
#define INIT_EXPANDERS
#define FRAME_POINTER_REQUIRED   (! (leaf_function_p () && only_leaf_regs_used ()))
#define ARG_POINTER_REGNUM   FRAME_POINTER_REGNUM
#define STATIC_CHAIN_REGNUM   (TARGET_ARCH64 ? 5 : 2)
#define PIC_OFFSET_TABLE_REGNUM   (flag_pic ? 23 : INVALID_REGNUM)
#define DEFAULT_PCC_STRUCT_RETURN   -1
#define STRUCT_VALUE_OFFSET   64
#define N_REG_CLASSES   (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES
#define REG_CLASS_CONTENTS
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS)
#define REGNO_REG_CLASS(REGNO)   sparc_regno_reg_class[(REGNO)]
#define REG_ALLOC_ORDER
#define REG_LEAF_ALLOC_ORDER
#define ORDER_REGS_FOR_LOCAL_ALLOC   order_regs_for_local_alloc ()
#define LEAF_REGISTERS   sparc_leaf_regs
#define LEAF_REG_REMAP(REGNO)   (leaf_reg_remap[REGNO])
#define INDEX_REG_CLASS   GENERAL_REGS
#define BASE_REG_CLASS   GENERAL_REGS
#define FP_REG_CLASS_P(CLASS)   ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
#define REG_CLASS_FROM_LETTER(C)
#define SPARC_SIMM10_P(X)   ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
#define SPARC_SIMM11_P(X)   ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
#define SPARC_SIMM13_P(X)   ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
#define SMALL_INT(X)   (SPARC_SIMM13_P (INTVAL (X)))
#define SPARC_SETHI_P(X)
#define SPARC_SETHI32_P(X)   (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
#define CONST_OK_FOR_LETTER_P(VALUE, C)
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)
#define PREFERRED_RELOAD_CLASS(X, CLASS)
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN)
#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN)
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)   (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
#define SECONDARY_MEMORY_NEEDED_RTX(MODE)
#define SECONDARY_MEMORY_NEEDED_MODE(MODE)
#define CLASS_MAX_NREGS(CLASS, MODE)
#define STACK_GROWS_DOWNWARD
#define FRAME_GROWS_DOWNWARD   1
#define STARTING_FRAME_OFFSET
#define FIRST_PARM_OFFSET(FNDECL)   (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
#define ARG_POINTER_CFA_OFFSET(FNDECL)   0
#define REG_PARM_STACK_SPACE(DECL)   (6 * UNITS_PER_WORD)
#define ELIMINABLE_REGS
#define CAN_ELIMINATE(FROM, TO)   ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)
#define ACCUMULATE_OUTGOING_ARGS   1
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE)   0
#define INCOMING_REGNO(OUT)   (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
#define OUTGOING_REGNO(IN)   (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
#define LOCAL_REGNO(REGNO)   ((REGNO) >= 16 && (REGNO) <= 31)
#define FUNCTION_VALUE(VALTYPE, FUNC)   function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
#define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC)   function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
#define LIBCALL_VALUE(MODE)   function_value (NULL_TREE, (MODE), 1)
#define FUNCTION_VALUE_REGNO_P(N)   ((N) == 8 || (N) == 32)
#define APPLY_RESULT_SIZE   (TARGET_ARCH64 ? 24 : 16)
#define FUNCTION_ARG_REGNO_P(N)
#define CUMULATIVE_ARGS   struct sparc_args
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)   init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)   function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)   function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED)   function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
#define FUNCTION_ARG_PADDING(MODE, TYPE)   function_arg_padding ((MODE), (TYPE))
#define FUNCTION_ARG_BOUNDARY(MODE, TYPE)
#define ASM_DECLARE_RESULT(FILE, RESULT)   fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
#define PROFILE_HOOK(LABEL)   sparc_profile_hook (LABEL)
#define FUNCTION_PROFILER(FILE, LABELNO)   do { } while (0)
#define MCOUNT_FUNCTION   "*mcount"
#define EXIT_IGNORE_STACK
#define EPILOGUE_USES(REGNO)
#define TRAMPOLINE_SIZE   (TARGET_ARCH64 ? 32 : 16)
#define TRAMPOLINE_ALIGNMENT   128
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)
#define EXPAND_BUILTIN_VA_START(valist, nextarg)   sparc_va_start (valist, nextarg)
#define SETUP_FRAME_ADDRESSES()   emit_insn (gen_flush_register_windows ())
#define DYNAMIC_CHAIN_ADDRESS(frame)   plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
#define FRAME_ADDR_RTX(frame)   plus_constant (frame, SPARC_STACK_BIAS)
#define RETURN_ADDR_IN_PREVIOUS_FRAME
#define RETURN_ADDR_OFFSET   (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
#define RETURN_ADDR_RTX(count, frame)
#define INCOMING_RETURN_ADDR_RTX   plus_constant (gen_rtx_REG (word_mode, 15), 8)
#define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (15)
#define INCOMING_FRAME_SP_OFFSET   SPARC_STACK_BIAS
#define EH_RETURN_DATA_REGNO(N)   ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX   gen_rtx_REG (Pmode, 1)
#define EH_RETURN_HANDLER_RTX   gen_rtx_REG (Pmode, 31)
#define REGNO_OK_FOR_INDEX_P(REGNO)
#define REGNO_OK_FOR_BASE_P(REGNO)   REGNO_OK_FOR_INDEX_P (REGNO)
#define REGNO_OK_FOR_FP_P(REGNO)
#define REGNO_OK_FOR_CCFP_P(REGNO)
#define FP_REG_P(X)   (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
#define IN_OR_GLOBAL_P(X)   (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
#define MAX_REGS_PER_ADDRESS   2
#define CONSTANT_ADDRESS_P(X)   constant_address_p (X)
#define LEGITIMATE_PIC_OPERAND_P(X)   legitimate_pic_operand_p (X)
#define LEGITIMATE_CONSTANT_P(X)   legitimate_constant_p (X)
#define REG_OK_FOR_INDEX_P(X)
#define REG_OK_FOR_BASE_P(X)   REG_OK_FOR_INDEX_P (X)
#define EXTRA_CONSTRAINT(OP, C)   sparc_extra_constraint_check(OP, C, 0)
#define USE_AS_OFFSETABLE_LO10   0
#define SYMBOLIC_CONST(X)   symbolic_operand (X, VOIDmode)
#define RTX_OK_FOR_BASE_P(X)
#define RTX_OK_FOR_INDEX_P(X)
#define RTX_OK_FOR_OFFSET_P(X)   (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
#define RTX_OK_FOR_OLO10_P(X)   (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)
#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
#define CASE_VECTOR_MODE   (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
#define DEFAULT_SIGNED_CHAR   1
#define MOVE_MAX   8
#define MOVE_RATIO   (optimize_size ? 3 : 8)
#define WORD_REGISTER_OPERATIONS
#define LOAD_EXTEND_OP(MODE)   ZERO_EXTEND
#define SLOW_BYTE_ACCESS   1
#define SHIFT_COUNT_TRUNCATED   1
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)   1
#define Pmode   (TARGET_ARCH64 ? DImode : SImode)
#define SELECT_CC_MODE(OP, X, Y)   select_cc_mode ((OP), (X), (Y))
#define REVERSIBLE_CC_MODE(MODE)   ((MODE) != CCFPEmode && (MODE) != CCFPmode)
#define FUNCTION_MODE   Pmode
#define NO_FUNCTION_CSE
#define SETJMP_VIA_SAVE_AREA
#define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON)   ((MODE) == TFmode)
#define TARGET_BUGGY_QP_LIB   0
#define SUN_CONVERSION_LIBFUNCS   0
#define DITF_CONVERSION_LIBFUNCS   0
#define SUN_INTEGER_MULTIPLY_64   0
#define GENERAL_OR_I64(C)   ((C) == GENERAL_REGS || (C) == I64_REGS)
#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)
#define BRANCH_COST
#define PREFETCH_BLOCK
#define SIMULTANEOUS_PREFETCHES
#define ASM_COMMENT_START   "!"
#define ASM_APP_ON   ""
#define ASM_APP_OFF   ""
#define REGISTER_NAMES
#define ADDITIONAL_REGISTER_NAMES   {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
#define DBX_CONTIN_LENGTH   1000
#define GLOBAL_ASM_OP   "\t.global "
#define USER_LABEL_PREFIX   "_"
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)   sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
#define ASM_OUTPUT_ADDR_VEC(LAB, VEC)   sparc_defer_case_vector ((LAB),(VEC), 0)
#define ASM_OUTPUT_ADDR_DIFF_VEC(LAB, VEC)   sparc_defer_case_vector ((LAB),(VEC), 1)
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)
#define ASM_OUTPUT_ALIGN(FILE, LOG)
#define ASM_OUTPUT_ALIGN_WITH_NOP(FILE, LOG)
#define ASM_OUTPUT_SKIP(FILE, SIZE)   fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED)
#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED)
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)
#define IDENT_ASM_OP   "\t.ident\t"
#define ASM_OUTPUT_IDENT(FILE, NAME)   fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
#define ASM_OUTPUT_OPCODE(FILE, PTR)
#define SPARC_SYMBOL_REF_TLS_P(RTX)   (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR)
#define PRINT_OPERAND(FILE, X, CODE)   print_operand (FILE, X, CODE)
#define PRINT_OPERAND_ADDRESS(FILE, ADDR)
#define TARGET_TLS   0
#define TARGET_SUN_TLS   TARGET_TLS
#define TARGET_GNU_TLS   0
#define JMP_BUF_SIZE   12

Enumerations

enum  cmodel {
  CM_32, CM_SMALL, CM_KERNEL, CM_MEDIUM,
  CM_LARGE, CM_SMALL_PIC, CM_32, CM_MEDLOW,
  CM_MEDMID, CM_MEDANY, CM_EMBMEDANY, CM_32,
  CM_SMALL, CM_KERNEL, CM_MEDIUM, CM_LARGE,
  CM_SMALL_PIC, CM_32, CM_MEDLOW, CM_MEDMID,
  CM_MEDANY, CM_EMBMEDANY, CM_32, CM_SMALL,
  CM_KERNEL, CM_MEDIUM, CM_LARGE, CM_SMALL_PIC,
  CM_32, CM_MEDLOW, CM_MEDMID, CM_MEDANY,
  CM_EMBMEDANY, CM_32, CM_SMALL, CM_KERNEL,
  CM_MEDIUM, CM_LARGE, CM_SMALL_PIC, CM_MEDIUM_PIC,
  CM_32, CM_MEDLOW, CM_MEDMID, CM_MEDANY,
  CM_EMBMEDANY
}
enum  processor_type {
  PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6, PROCESSOR_I386,
  PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, PROCESSOR_K6,
  PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_max, PROCESSOR_M88100,
  PROCESSOR_M88110, PROCESSOR_M88000, PROCESSOR_700, PROCESSOR_7100,
  PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_8000, PROCESSOR_RIOS1,
  PROCESSOR_RIOS2, PROCESSOR_RS64A, PROCESSOR_MPCCORE, PROCESSOR_PPC403,
  PROCESSOR_PPC405, PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604,
  PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750,
  PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_SH1, PROCESSOR_SH2,
  PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4, PROCESSOR_SH5,
  PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900, PROCESSOR_R6000,
  PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120,
  PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,
  PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000, PROCESSOR_R4KC,
  PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000, PROCESSOR_SB1,
  PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8, PROCESSOR_SUPERSPARC,
  PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, PROCESSOR_HYPERSPARC,
  PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701, PROCESSOR_V9,
  PROCESSOR_ULTRASPARC, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,
  PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,
  PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,
  PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,
  PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,
  PROCESSOR_SB1, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,
  PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,
  PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,
  PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,
  PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,
  PROCESSOR_SB1, PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6,
  PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO,
  PROCESSOR_K6, PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_max,
  PROCESSOR_M88100, PROCESSOR_M88110, PROCESSOR_M88000, PROCESSOR_700,
  PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_8000,
  PROCESSOR_RIOS1, PROCESSOR_RIOS2, PROCESSOR_RS64A, PROCESSOR_MPCCORE,
  PROCESSOR_PPC403, PROCESSOR_PPC405, PROCESSOR_PPC601, PROCESSOR_PPC603,
  PROCESSOR_PPC604, PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630,
  PROCESSOR_PPC750, PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_SH1,
  PROCESSOR_SH2, PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4,
  PROCESSOR_SH5, PROCESSOR_DEFAULT, PROCESSOR_R3000, PROCESSOR_R3900,
  PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100, PROCESSOR_R4111,
  PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650,
  PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R8000,
  PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC, PROCESSOR_SR71000,
  PROCESSOR_SB1, PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8,
  PROCESSOR_SUPERSPARC, PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934,
  PROCESSOR_HYPERSPARC, PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701,
  PROCESSOR_V9, PROCESSOR_ULTRASPARC, PROCESSOR_DEFAULT, PROCESSOR_R3000,
  PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100,
  PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600,
  PROCESSOR_R4650, PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500,
  PROCESSOR_R8000, PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC,
  PROCESSOR_SR71000, PROCESSOR_SB1, PROCESSOR_DEFAULT, PROCESSOR_R3000,
  PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000, PROCESSOR_R4100,
  PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4300, PROCESSOR_R4600,
  PROCESSOR_R4650, PROCESSOR_R5000, PROCESSOR_R5400, PROCESSOR_R5500,
  PROCESSOR_R8000, PROCESSOR_R4KC, PROCESSOR_R5KC, PROCESSOR_R20KC,
  PROCESSOR_SR71000, PROCESSOR_SB1, PROCESSOR_EV4, PROCESSOR_EV5,
  PROCESSOR_EV6, PROCESSOR_MAX, ARM_CORE, PROCESSOR_I386,
  PROCESSOR_I486, PROCESSOR_PENTIUM, PROCESSOR_PENTIUMPRO, PROCESSOR_K6,
  PROCESSOR_ATHLON, PROCESSOR_PENTIUM4, PROCESSOR_K8, PROCESSOR_NOCONA,
  PROCESSOR_max, PROCESSOR_ITANIUM, PROCESSOR_ITANIUM2, PROCESSOR_max,
  PROCESSOR_DEFAULT, PROCESSOR_IQ2000, PROCESSOR_IQ10, PROCESSOR_DEFAULT,
  PROCESSOR_4KC, PROCESSOR_5KC, PROCESSOR_20KC, PROCESSOR_M4K,
  PROCESSOR_R3000, PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000,
  PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4130,
  PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,
  PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R7000, PROCESSOR_R8000,
  PROCESSOR_R9000, PROCESSOR_SB1, PROCESSOR_SR71000, PROCESSOR_700,
  PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200, PROCESSOR_7300,
  PROCESSOR_8000, PROCESSOR_RIOS1, PROCESSOR_RIOS2, PROCESSOR_RS64A,
  PROCESSOR_MPCCORE, PROCESSOR_PPC403, PROCESSOR_PPC405, PROCESSOR_PPC440,
  PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604, PROCESSOR_PPC604e,
  PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750, PROCESSOR_PPC7400,
  PROCESSOR_PPC7450, PROCESSOR_PPC8540, PROCESSOR_POWER4, PROCESSOR_POWER5,
  PROCESSOR_9672_G5, PROCESSOR_9672_G6, PROCESSOR_2064_Z900, PROCESSOR_2084_Z990,
  PROCESSOR_max, PROCESSOR_SH1, PROCESSOR_SH2, PROCESSOR_SH2E,
  PROCESSOR_SH2A, PROCESSOR_SH3, PROCESSOR_SH3E, PROCESSOR_SH4,
  PROCESSOR_SH4A, PROCESSOR_SH5, PROCESSOR_V7, PROCESSOR_CYPRESS,
  PROCESSOR_V8, PROCESSOR_SUPERSPARC, PROCESSOR_SPARCLITE, PROCESSOR_F930,
  PROCESSOR_F934, PROCESSOR_HYPERSPARC, PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET,
  PROCESSOR_TSC701, PROCESSOR_V9, PROCESSOR_ULTRASPARC, PROCESSOR_ULTRASPARC3,
  PROCESSOR_EV4, PROCESSOR_EV5, PROCESSOR_EV6, PROCESSOR_MAX,
  ARM_CORE, PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM,
  PROCESSOR_PENTIUMPRO, PROCESSOR_K6, PROCESSOR_ATHLON, PROCESSOR_PENTIUM4,
  PROCESSOR_K8, PROCESSOR_NOCONA, PROCESSOR_GENERIC32, PROCESSOR_GENERIC64,
  PROCESSOR_AMDFAM10, PROCESSOR_max, PROCESSOR_ITANIUM, PROCESSOR_ITANIUM2,
  PROCESSOR_max, PROCESSOR_DEFAULT, PROCESSOR_IQ2000, PROCESSOR_IQ10,
  PROCESSOR_R3000, PROCESSOR_4KC, PROCESSOR_4KP, PROCESSOR_5KC,
  PROCESSOR_5KF, PROCESSOR_20KC, PROCESSOR_24K, PROCESSOR_24KX,
  PROCESSOR_M4K, PROCESSOR_R3900, PROCESSOR_R6000, PROCESSOR_R4000,
  PROCESSOR_R4100, PROCESSOR_R4111, PROCESSOR_R4120, PROCESSOR_R4130,
  PROCESSOR_R4300, PROCESSOR_R4600, PROCESSOR_R4650, PROCESSOR_R5000,
  PROCESSOR_R5400, PROCESSOR_R5500, PROCESSOR_R7000, PROCESSOR_R8000,
  PROCESSOR_R9000, PROCESSOR_SB1, PROCESSOR_SB1A, PROCESSOR_SR71000,
  PROCESSOR_MAX, PROCESSOR_MN10300, PROCESSOR_AM33, PROCESSOR_AM33_2,
  PROCESSOR_MS1_64_001, PROCESSOR_MS1_16_002, PROCESSOR_MS1_16_003, PROCESSOR_MS2,
  PROCESSOR_700, PROCESSOR_7100, PROCESSOR_7100LC, PROCESSOR_7200,
  PROCESSOR_7300, PROCESSOR_8000, PROCESSOR_RIOS1, PROCESSOR_RIOS2,
  PROCESSOR_RS64A, PROCESSOR_MPCCORE, PROCESSOR_PPC403, PROCESSOR_PPC405,
  PROCESSOR_PPC440, PROCESSOR_PPC601, PROCESSOR_PPC603, PROCESSOR_PPC604,
  PROCESSOR_PPC604e, PROCESSOR_PPC620, PROCESSOR_PPC630, PROCESSOR_PPC750,
  PROCESSOR_PPC7400, PROCESSOR_PPC7450, PROCESSOR_PPC8540, PROCESSOR_POWER4,
  PROCESSOR_POWER5, PROCESSOR_9672_G5, PROCESSOR_9672_G6, PROCESSOR_2064_Z900,
  PROCESSOR_2084_Z990, PROCESSOR_2094_Z9_109, PROCESSOR_max, PROCESSOR_SH1,
  PROCESSOR_SH2, PROCESSOR_SH2E, PROCESSOR_SH2A, PROCESSOR_SH3,
  PROCESSOR_SH3E, PROCESSOR_SH4, PROCESSOR_SH4A, PROCESSOR_SH5,
  PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8, PROCESSOR_SUPERSPARC,
  PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, PROCESSOR_HYPERSPARC,
  PROCESSOR_SPARCLITE86X, PROCESSOR_SPARCLET, PROCESSOR_TSC701, PROCESSOR_V9,
  PROCESSOR_ULTRASPARC, PROCESSOR_ULTRASPARC3, PROCESSOR_NIAGARA
}
enum  reg_class {
  NO_REGS, R2, R0_1, INDEX_REGS,
  BASE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  LR0_REGS, GENERAL_REGS, BP_REGS, FC_REGS,
  CR_REGS, Q_REGS, SPECIAL_REGS, ACCUM0_REGS,
  ACCUM_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, R24_REG, R25_REG, R27_REG,
  GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, LPCOUNT_REG, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, FPU_REGS, LO_REGS,
  STACK_REG, BASE_REGS, HI_REGS, CC_REG,
  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  R0_REG, POINTER_X_REGS, POINTER_Y_REGS, POINTER_Z_REGS,
  STACK_REG, BASE_POINTER_REGS, POINTER_REGS, ADDW_REGS,
  SIMPLE_LD_REGS, LD_REGS, NO_LD_REGS, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0R1_REGS,
  R2R3_REGS, EXT_LOW_REGS, EXT_REGS, ADDR_REGS,
  INDEX_REGS, BK_REG, SP_REG, RC_REG,
  COUNTER_REGS, INT_REGS, GENERAL_REGS, DP_REG,
  ST_REG, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, S_REGS, INDEX_REGS, SP_REGS,
  A_REGS, SI_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  REPEAT_REGS, CR_REGS, ACCUM_REGS, OTHER_FLAG_REGS,
  F0_REGS, F1_REGS, BR_FLAG_REGS, FLAG_REGS,
  EVEN_REGS, GPR_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, A0H_REG, A0L_REG, A0_REG,
  A1H_REG, ACCUM_HIGH_REGS, A1L_REG, ACCUM_LOW_REGS,
  A1_REG, ACCUM_REGS, X_REG, X_OR_ACCUM_LOW_REGS,
  X_OR_ACCUM_REGS, YH_REG, YH_OR_ACCUM_HIGH_REGS, X_OR_YH_REGS,
  YL_REG, YL_OR_ACCUM_LOW_REGS, X_OR_YL_REGS, X_OR_Y_REGS,
  Y_REG, ACCUM_OR_Y_REGS, PH_REG, X_OR_PH_REGS,
  PL_REG, PL_OR_ACCUM_LOW_REGS, X_OR_PL_REGS, YL_OR_PL_OR_ACCUM_LOW_REGS,
  P_REG, ACCUM_OR_P_REGS, YL_OR_P_REGS, ACCUM_LOW_OR_YL_OR_P_REGS,
  Y_OR_P_REGS, ACCUM_Y_OR_P_REGS, NO_FRAME_Y_ADDR_REGS, Y_ADDR_REGS,
  ACCUM_LOW_OR_Y_ADDR_REGS, ACCUM_OR_Y_ADDR_REGS, X_OR_Y_ADDR_REGS, Y_OR_Y_ADDR_REGS,
  P_OR_Y_ADDR_REGS, NON_HIGH_YBASE_ELIGIBLE_REGS, YBASE_ELIGIBLE_REGS, J_REG,
  J_OR_DAU_16_BIT_REGS, BMU_REGS, NOHIGH_NON_ADDR_REGS, NON_ADDR_REGS,
  SLOW_MEM_LOAD_REGS, NOHIGH_NON_YBASE_REGS, NO_ACCUM_NON_YBASE_REGS, NON_YBASE_REGS,
  YBASE_VIRT_REGS, ACCUM_LOW_OR_YBASE_REGS, ACCUM_OR_YBASE_REGS, X_OR_YBASE_REGS,
  Y_OR_YBASE_REGS, ACCUM_LOW_YL_PL_OR_YBASE_REGS, P_OR_YBASE_REGS, ACCUM_Y_P_OR_YBASE_REGS,
  Y_ADDR_OR_YBASE_REGS, YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS, YBASE_OR_YBASE_ELIGIBLE_REGS, NO_HIGH_ALL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG,
  MULTIPLY_64_REG, LOW_REGS, HIGH_REGS, REAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,
  MAC_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  ADDR_REGS, DATA_REGS, FP_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, AREG, DREG,
  CREG, BREG, SIREG, DIREG,
  AD_REGS, Q_REGS, NON_Q_REGS, INDEX_REGS,
  LEGACY_REGS, GENERAL_REGS, FP_TOP_REG, FP_SECOND_REG,
  FLOAT_REGS, SSE_REGS, MMX_REGS, FP_TOP_SSE_REGS,
  FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS, INT_SSE_REGS,
  FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,
  FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS,
  ADDL_REGS, GR_REGS, FR_REGS, GR_AND_BR_REGS,
  GR_AND_FR_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, D_REGS, X_REGS,
  Y_REGS, SP_REGS, DA_REGS, DB_REGS,
  Z_REGS, D8_REGS, Q_REGS, D_OR_X_REGS,
  D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS, A_REGS,
  X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS, A_OR_D_REGS,
  A_OR_SP_REGS, H_REGS, S_REGS, D_OR_S_REGS,
  X_OR_S_REGS, Y_OR_S_REGS, SP_OR_S_REGS, D_OR_X_OR_S_REGS,
  D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS, A_OR_S_REGS, D_OR_A_OR_S_REGS,
  TMP_REGS, D_OR_A_OR_TMP_REGS, G_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, DATA_REGS, ADDR_REGS,
  FP_REGS, GENERAL_REGS, DATA_OR_FP_REGS, ADDR_OR_FP_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, AP_REG,
  XRF_REGS, GENERAL_REGS, AGRF_REGS, XGRF_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, ONLYR1_REGS,
  LRW_REGS, GENERAL_REGS, C_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, REMAINDER_REG,
  HIMULT_REG, SYSTEM_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, DATA_REGS, ADDRESS_REGS, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,
  ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
  EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS,
  SP_OR_ADDRESS_OR_EXTENDED_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0,
  FLOAT_REGS, FP_REGS, GEN_AND_FP_REGS, FRAME_POINTER_REG,
  STACK_POINTER_REG, GEN_AND_MEM_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS,
  FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,
  FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, MUL_REGS,
  GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, OUT_REGS,
  STD_REGS, ARG_REGS, SRC_REGS, DST_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0_REGS,
  R15_REGS, BASE_REGS, GENERAL_REGS, FP_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, BASE_REGS,
  GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS, VRSAVE_REGS,
  NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,
  LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,
  CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, ADDR_REGS, GENERAL_REGS,
  FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R0_REGS, PR_REGS,
  T_REGS, MAC_REGS, FPUL_REGS, SIBCALL_REGS,
  GENERAL_REGS, FP0_REGS, FP_REGS, DF_REGS,
  FPSCR_REGS, GENERAL_FP_REGS, TARGET_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, M16_NA_REGS, M16_REGS,
  T_REG, M16_T_REGS, GR_REGS, FP_REGS,
  HI_REG, LO_REG, HILO_REG, MD_REGS,
  COP0_REGS, COP2_REGS, COP3_REGS, HI_AND_GR_REGS,
  LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS,
  COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS,
  ST_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
  EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R0_REGS, R1_REGS,
  TWO_REGS, R2_REGS, EIGHT_REGS, R8_REGS,
  ICALL_REGS, GENERAL_REGS, CARRY_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, BR_REGS, FP_REGS, ACC_REG,
  SP_REG, RL_REGS, GR_REGS, AR_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,
  M16_REGS, T_REG, M16_T_REGS, GR_REGS,
  FP_REGS, HI_REG, LO_REG, HILO_REG,
  MD_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
  HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS,
  COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS,
  ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, M16_NA_REGS, M16_REGS, T_REG,
  M16_T_REGS, GR_REGS, FP_REGS, HI_REG,
  LO_REG, HILO_REG, MD_REGS, COP0_REGS,
  COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,
  HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,
  COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R2,
  R0_1, INDEX_REGS, BASE_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, LR0_REGS, GENERAL_REGS,
  BP_REGS, FC_REGS, CR_REGS, Q_REGS,
  SPECIAL_REGS, ACCUM0_REGS, ACCUM_REGS, FLOAT_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R24_REG,
  R25_REG, R27_REG, GENERAL_REGS, FLOAT_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG,
  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  FPU_REGS, LO_REGS, STACK_REG, BASE_REGS,
  HI_REGS, CC_REG, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R0_REG, POINTER_X_REGS,
  POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG, BASE_POINTER_REGS,
  POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS, LD_REGS,
  NO_LD_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, R0R1_REGS, R2R3_REGS, EXT_LOW_REGS,
  EXT_REGS, ADDR_REGS, INDEX_REGS, BK_REG,
  SP_REG, RC_REG, COUNTER_REGS, INT_REGS,
  GENERAL_REGS, DP_REG, ST_REG, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, FLOAT_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, S_REGS,
  INDEX_REGS, SP_REGS, A_REGS, SI_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, REPEAT_REGS, CR_REGS,
  ACCUM_REGS, OTHER_FLAG_REGS, F0_REGS, F1_REGS,
  BR_FLAG_REGS, FLAG_REGS, EVEN_REGS, GPR_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, A0H_REG,
  A0L_REG, A0_REG, A1H_REG, ACCUM_HIGH_REGS,
  A1L_REG, ACCUM_LOW_REGS, A1_REG, ACCUM_REGS,
  X_REG, X_OR_ACCUM_LOW_REGS, X_OR_ACCUM_REGS, YH_REG,
  YH_OR_ACCUM_HIGH_REGS, X_OR_YH_REGS, YL_REG, YL_OR_ACCUM_LOW_REGS,
  X_OR_YL_REGS, X_OR_Y_REGS, Y_REG, ACCUM_OR_Y_REGS,
  PH_REG, X_OR_PH_REGS, PL_REG, PL_OR_ACCUM_LOW_REGS,
  X_OR_PL_REGS, YL_OR_PL_OR_ACCUM_LOW_REGS, P_REG, ACCUM_OR_P_REGS,
  YL_OR_P_REGS, ACCUM_LOW_OR_YL_OR_P_REGS, Y_OR_P_REGS, ACCUM_Y_OR_P_REGS,
  NO_FRAME_Y_ADDR_REGS, Y_ADDR_REGS, ACCUM_LOW_OR_Y_ADDR_REGS, ACCUM_OR_Y_ADDR_REGS,
  X_OR_Y_ADDR_REGS, Y_OR_Y_ADDR_REGS, P_OR_Y_ADDR_REGS, NON_HIGH_YBASE_ELIGIBLE_REGS,
  YBASE_ELIGIBLE_REGS, J_REG, J_OR_DAU_16_BIT_REGS, BMU_REGS,
  NOHIGH_NON_ADDR_REGS, NON_ADDR_REGS, SLOW_MEM_LOAD_REGS, NOHIGH_NON_YBASE_REGS,
  NO_ACCUM_NON_YBASE_REGS, NON_YBASE_REGS, YBASE_VIRT_REGS, ACCUM_LOW_OR_YBASE_REGS,
  ACCUM_OR_YBASE_REGS, X_OR_YBASE_REGS, Y_OR_YBASE_REGS, ACCUM_LOW_YL_PL_OR_YBASE_REGS,
  P_OR_YBASE_REGS, ACCUM_Y_P_OR_YBASE_REGS, Y_ADDR_OR_YBASE_REGS, YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS,
  YBASE_OR_YBASE_ELIGIBLE_REGS, NO_HIGH_ALL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, MULTIPLY_32_REG, MULTIPLY_64_REG, LOW_REGS,
  HIGH_REGS, REAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, ADDR_REGS, DATA_REGS,
  FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  AREG, DREG, CREG, BREG,
  SIREG, DIREG, AD_REGS, Q_REGS,
  NON_Q_REGS, INDEX_REGS, LEGACY_REGS, GENERAL_REGS,
  FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, SSE_REGS,
  MMX_REGS, FP_TOP_SSE_REGS, FP_SECOND_SSE_REGS, FLOAT_SSE_REGS,
  FLOAT_INT_REGS, INT_SSE_REGS, FLOAT_INT_SSE_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, FP_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, GLOBAL_REGS,
  LOCAL_REGS, LOCAL_OR_GLOBAL_REGS, FP_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, PR_REGS, BR_REGS,
  AR_M_REGS, AR_I_REGS, ADDL_REGS, GR_REGS,
  FR_REGS, GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, CARRY_REG, ACCUM_REGS,
  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  D_REGS, X_REGS, Y_REGS, SP_REGS,
  DA_REGS, DB_REGS, Z_REGS, D8_REGS,
  Q_REGS, D_OR_X_REGS, D_OR_Y_REGS, D_OR_SP_REGS,
  X_OR_Y_REGS, A_REGS, X_OR_SP_REGS, Y_OR_SP_REGS,
  X_OR_Y_OR_D_REGS, A_OR_D_REGS, A_OR_SP_REGS, H_REGS,
  S_REGS, D_OR_S_REGS, X_OR_S_REGS, Y_OR_S_REGS,
  SP_OR_S_REGS, D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS,
  A_OR_S_REGS, D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS,
  G_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  DATA_REGS, ADDR_REGS, FP_REGS, GENERAL_REGS,
  DATA_OR_FP_REGS, ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS,
  AGRF_REGS, XGRF_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, ONLYR1_REGS, LRW_REGS, GENERAL_REGS,
  C_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  GENERAL_REGS, REMAINDER_REG, HIMULT_REG, SYSTEM_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,
  ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
  DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, EXTENDED_REGS, DATA_OR_EXTENDED_REGS,
  ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,
  FLOAT_REG0, LONG_FLOAT_REG0, FLOAT_REGS, FP_REGS,
  GEN_AND_FP_REGS, FRAME_POINTER_REG, STACK_POINTER_REG, GEN_AND_MEM_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,
  GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,
  SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
  GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS,
  NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, OUT_REGS, STD_REGS, ARG_REGS,
  SRC_REGS, DST_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, R0_REGS, R15_REGS, BASE_REGS,
  GENERAL_REGS, FP_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, BASE_REGS, GENERAL_REGS, FLOAT_REGS,
  ALTIVEC_REGS, VRSAVE_REGS, NON_SPECIAL_REGS, MQ_REGS,
  LINK_REGS, CTR_REGS, LINK_OR_CTR_REGS, SPECIAL_REGS,
  SPEC_OR_GEN_REGS, CR0_REGS, CR_REGS, NON_FLOAT_REGS,
  XER_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  ADDR_REGS, GENERAL_REGS, FP_REGS, ADDR_FP_REGS,
  GENERAL_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  R0_REGS, PR_REGS, T_REGS, MAC_REGS,
  FPUL_REGS, SIBCALL_REGS, GENERAL_REGS, FP0_REGS,
  FP_REGS, DF_REGS, FPSCR_REGS, GENERAL_FP_REGS,
  TARGET_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  M16_NA_REGS, M16_REGS, T_REG, M16_T_REGS,
  GR_REGS, FP_REGS, HI_REG, LO_REG,
  HILO_REG, MD_REGS, COP0_REGS, COP2_REGS,
  COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS,
  HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,
  ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, FPCC_REGS, I64_REGS,
  GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, GENERAL_OR_FP_REGS,
  GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  R0_REGS, R1_REGS, TWO_REGS, R2_REGS,
  EIGHT_REGS, R8_REGS, ICALL_REGS, GENERAL_REGS,
  CARRY_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, BR_REGS,
  FP_REGS, ACC_REG, SP_REG, RL_REGS,
  GR_REGS, AR_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, M16_NA_REGS, M16_REGS, T_REG,
  M16_T_REGS, GR_REGS, FP_REGS, HI_REG,
  LO_REG, HILO_REG, MD_REGS, COP0_REGS,
  COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,
  HILO_AND_GR_REGS, HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS,
  COP3_AND_GR_REGS, ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,
  M16_REGS, T_REG, M16_T_REGS, GR_REGS,
  FP_REGS, HI_REG, LO_REG, HILO_REG,
  MD_REGS, COP0_REGS, COP2_REGS, COP3_REGS,
  HI_AND_GR_REGS, LO_AND_GR_REGS, HILO_AND_GR_REGS, HI_AND_FP_REGS,
  COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS, ALL_COP_REGS,
  ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, R0_REG, R24_REG, R25_REG,
  R27_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, FPA_REGS,
  CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,
  LO_REGS, STACK_REG, BASE_REGS, HI_REGS,
  CC_REG, VFPCC_REG, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R0_REG, POINTER_X_REGS,
  POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG, BASE_POINTER_REGS,
  POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS, LD_REGS,
  NO_LD_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, IREGS, BREGS, LREGS,
  MREGS, CIRCREGS, DAGREGS, EVEN_AREGS,
  ODD_AREGS, AREGS, CCREGS, EVEN_DREGS,
  ODD_DREGS, DREGS, PREGS_CLOBBERED, PREGS,
  DPREGS, MOST_REGS, PROLOGUE_REGS, NON_A_CC_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0R1_REGS,
  R2R3_REGS, EXT_LOW_REGS, EXT_REGS, ADDR_REGS,
  INDEX_REGS, BK_REG, SP_REG, RC_REG,
  COUNTER_REGS, INT_REGS, GENERAL_REGS, DP_REG,
  ST_REG, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG,
  MULTIPLY_64_REG, LOW_REGS, HIGH_REGS, REAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, ICC_REGS,
  FCC_REGS, CC_REGS, ICR_REGS, FCR_REGS,
  CR_REGS, LCR_REG, LR_REG, GR8_REGS,
  GR9_REGS, GR89_REGS, FDPIC_REGS, FDPIC_FPTR_REGS,
  FDPIC_CALL_REGS, SPR_REGS, QUAD_ACC_REGS, EVEN_ACC_REGS,
  ACC_REGS, ACCG_REGS, QUAD_FPR_REGS, FEVEN_REGS,
  FPR_REGS, QUAD_REGS, EVEN_REGS, GPR_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, COUNTER_REGS,
  SOURCE_REGS, DESTINATION_REGS, GENERAL_REGS, MAC_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, AREG,
  DREG, CREG, BREG, SIREG,
  DIREG, AD_REGS, Q_REGS, NON_Q_REGS,
  INDEX_REGS, LEGACY_REGS, GENERAL_REGS, FP_TOP_REG,
  FP_SECOND_REG, FLOAT_REGS, SSE_REGS, MMX_REGS,
  FP_TOP_SSE_REGS, FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS,
  INT_SSE_REGS, FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GENERAL_REGS, FP_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, PR_REGS, BR_REGS,
  AR_M_REGS, AR_I_REGS, ADDL_REGS, GR_REGS,
  FR_REGS, GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, DPH_REGS, DPL_REGS,
  DP_REGS, SP_REGS, IPH_REGS, IPL_REGS,
  IP_REGS, DP_SP_REGS, PTR_REGS, NONPTR_REGS,
  NONSP_REGS, GENERAL_REGS, ALL_REGS = GENERAL_REGS, LIM_REG_CLASSES,
  NO_REGS, GR_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, D_REGS,
  X_REGS, Y_REGS, SP_REGS, DA_REGS,
  DB_REGS, Z_REGS, D8_REGS, Q_REGS,
  D_OR_X_REGS, D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS,
  A_REGS, X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS,
  A_OR_D_REGS, A_OR_SP_REGS, H_REGS, S_REGS,
  D_OR_S_REGS, X_OR_S_REGS, Y_OR_S_REGS, Z_OR_S_REGS,
  SP_OR_S_REGS, D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS,
  A_OR_S_REGS, D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS,
  G_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  DATA_REGS, ADDR_REGS, FP_REGS, GENERAL_REGS,
  DATA_OR_FP_REGS, ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, ONLYR1_REGS, LRW_REGS, GENERAL_REGS,
  C_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  M16_NA_REGS, M16_REGS, T_REG, M16_T_REGS,
  PIC_FN_ADDR_REG, LEA_REGS, GR_REGS, FP_REGS,
  HI_REG, LO_REG, MD_REGS, COP0_REGS,
  COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,
  HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,
  ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, GENERAL_REGS, REMAINDER_REG,
  HIMULT_REG, SYSTEM_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
  DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, EXTENDED_REGS, DATA_OR_EXTENDED_REGS,
  ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, FP_REGS,
  FP_ACC_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0,
  FLOAT_REGS, LONG_REGS, FP_REGS, GEN_AND_FP_REGS,
  FRAME_POINTER_REG, STACK_POINTER_REG, GEN_AND_MEM_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,
  FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,
  GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,
  SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS,
  FPU_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  BASE_REGS, GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS,
  VRSAVE_REGS, VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,
  NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,
  LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,
  CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, CC_REGS, ADDR_REGS,
  GENERAL_REGS, ACCESS_REGS, ADDR_CC_REGS, GENERAL_CC_REGS,
  FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R0_REGS, PR_REGS,
  T_REGS, MAC_REGS, FPUL_REGS, SIBCALL_REGS,
  GENERAL_REGS, FP0_REGS, FP_REGS, DF_HI_REGS,
  DF_REGS, FPSCR_REGS, GENERAL_FP_REGS, TARGET_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, FPCC_REGS,
  I64_REGS, GENERAL_REGS, FP_REGS, EXTRA_FP_REGS,
  GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, R0_REGS, R1_REGS, TWO_REGS,
  R2_REGS, EIGHT_REGS, R8_REGS, ICALL_REGS,
  GENERAL_REGS, CARRY_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  BR_REGS, FP_REGS, ACC_REG, SP_REG,
  RL_REGS, GR_REGS, AR_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R0_REG, R24_REG,
  R25_REG, R27_REG, GENERAL_REGS, FLOAT_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, LPCOUNT_REG,
  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS,
  IWMMXT_REGS, LO_REGS, STACK_REG, BASE_REGS,
  HI_REGS, CC_REG, VFPCC_REG, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R0_REG,
  POINTER_X_REGS, POINTER_Y_REGS, POINTER_Z_REGS, STACK_REG,
  BASE_POINTER_REGS, POINTER_REGS, ADDW_REGS, SIMPLE_LD_REGS,
  LD_REGS, NO_LD_REGS, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, IREGS, BREGS,
  LREGS, MREGS, CIRCREGS, DAGREGS,
  EVEN_AREGS, ODD_AREGS, AREGS, CCREGS,
  EVEN_DREGS, ODD_DREGS, DREGS, FDPIC_REGS,
  FDPIC_FPTR_REGS, PREGS_CLOBBERED, PREGS, IPREGS,
  DPREGS, MOST_REGS, LT_REGS, LC_REGS,
  LB_REGS, PROLOGUE_REGS, NON_A_CC_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R0R1_REGS, R2R3_REGS,
  EXT_LOW_REGS, EXT_REGS, ADDR_REGS, INDEX_REGS,
  BK_REG, SP_REG, RC_REG, COUNTER_REGS,
  INT_REGS, GENERAL_REGS, DP_REG, ST_REG,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, MOF_REGS,
  CC0_REGS, SPECIAL_REGS, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, LO_REGS, HI_REGS,
  HILO_REGS, NOSP_REGS, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, MULTIPLY_32_REG, MULTIPLY_64_REG,
  LOW_REGS, HIGH_REGS, REAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, ICC_REGS, FCC_REGS,
  CC_REGS, ICR_REGS, FCR_REGS, CR_REGS,
  LCR_REG, LR_REG, GR8_REGS, GR9_REGS,
  GR89_REGS, FDPIC_REGS, FDPIC_FPTR_REGS, FDPIC_CALL_REGS,
  SPR_REGS, QUAD_ACC_REGS, EVEN_ACC_REGS, ACC_REGS,
  ACCG_REGS, QUAD_FPR_REGS, FEVEN_REGS, FPR_REGS,
  QUAD_REGS, EVEN_REGS, GPR_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, COUNTER_REGS, SOURCE_REGS,
  DESTINATION_REGS, GENERAL_REGS, MAC_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, AREG, DREG,
  CREG, BREG, SIREG, DIREG,
  AD_REGS, Q_REGS, NON_Q_REGS, INDEX_REGS,
  LEGACY_REGS, GENERAL_REGS, FP_TOP_REG, FP_SECOND_REG,
  FLOAT_REGS, SSE_REGS, MMX_REGS, FP_TOP_SSE_REGS,
  FP_SECOND_SSE_REGS, FLOAT_SSE_REGS, FLOAT_INT_REGS, INT_SSE_REGS,
  FLOAT_INT_SSE_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  PR_REGS, BR_REGS, AR_M_REGS, AR_I_REGS,
  ADDL_REGS, GR_REGS, FP_REGS, FR_REGS,
  GR_AND_BR_REGS, GR_AND_FR_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, GR_REGS, ALL_REGS, LIM_REG_CLASSES,
  NO_REGS, SP_REGS, FB_REGS, SB_REGS,
  CR_REGS, R0_REGS, R1_REGS, R2_REGS,
  R3_REGS, R02_REGS, HL_REGS, QI_REGS,
  R23_REGS, R03_REGS, DI_REGS, A0_REGS,
  A1_REGS, A_REGS, AD_REGS, PS_REGS,
  SI_REGS, HI_REGS, RA_REGS, GENERAL_REGS,
  FLG_REGS, HC_REGS, MEM_REGS, R02_A_MEM_REGS,
  A_HL_MEM_REGS, R1_R3_A_MEM_REGS, R03_MEM_REGS, A_HI_MEM_REGS,
  A_AD_CR_MEM_SI_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, D_REGS, X_REGS,
  Y_REGS, SP_REGS, DA_REGS, DB_REGS,
  Z_REGS, D8_REGS, Q_REGS, D_OR_X_REGS,
  D_OR_Y_REGS, D_OR_SP_REGS, X_OR_Y_REGS, A_REGS,
  X_OR_SP_REGS, Y_OR_SP_REGS, X_OR_Y_OR_D_REGS, A_OR_D_REGS,
  A_OR_SP_REGS, H_REGS, S_REGS, D_OR_S_REGS,
  X_OR_S_REGS, Y_OR_S_REGS, Z_OR_S_REGS, SP_OR_S_REGS,
  D_OR_X_OR_S_REGS, D_OR_Y_OR_S_REGS, D_OR_SP_OR_S_REGS, A_OR_S_REGS,
  D_OR_A_OR_S_REGS, TMP_REGS, D_OR_A_OR_TMP_REGS, G_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,
  ADDR_REGS, FP_REGS, GENERAL_REGS, DATA_OR_FP_REGS,
  ADDR_OR_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  ONLYR1_REGS, LRW_REGS, GENERAL_REGS, C_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, M16_NA_REGS,
  M16_REGS, T_REG, M16_T_REGS, PIC_FN_ADDR_REG,
  V1_REG, LEA_REGS, GR_REGS, FP_REGS,
  HI_REG, LO_REG, MD_REGS, COP0_REGS,
  COP2_REGS, COP3_REGS, HI_AND_GR_REGS, LO_AND_GR_REGS,
  HI_AND_FP_REGS, COP0_AND_GR_REGS, COP2_AND_GR_REGS, COP3_AND_GR_REGS,
  ALL_COP_REGS, ALL_COP_AND_GR_REGS, ST_REGS, DSP_ACC_REGS,
  ACC_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  GENERAL_REGS, REMAINDER_REG, HIMULT_REG, SYSTEM_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, DATA_REGS,
  ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
  EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS, SP_OR_EXTENDED_REGS,
  SP_OR_ADDRESS_OR_EXTENDED_REGS, FP_REGS, FP_ACC_REGS, GENERAL_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, R1_REGS, GENERAL_REGS,
  FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS, SHIFT_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, R1_REGS,
  GENERAL_REGS, FPUPPER_REGS, FP_REGS, GENERAL_OR_FP_REGS,
  SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS,
  FPU_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  BASE_REGS, GENERAL_REGS, FLOAT_REGS, ALTIVEC_REGS,
  VRSAVE_REGS, VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS,
  NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS,
  LINK_OR_CTR_REGS, SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS,
  CR_REGS, NON_FLOAT_REGS, XER_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, CC_REGS, ADDR_REGS,
  GENERAL_REGS, ACCESS_REGS, ADDR_CC_REGS, GENERAL_CC_REGS,
  FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, G16_REGS, G32_REGS,
  T32_REGS, HI_REG, LO_REG, CE_REGS,
  CN_REG, LC_REG, SC_REG, SP_REGS,
  CR_REGS, CP1_REGS, CP2_REGS, CP3_REGS,
  CPA_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  R0_REGS, PR_REGS, T_REGS, MAC_REGS,
  FPUL_REGS, SIBCALL_REGS, GENERAL_REGS, FP0_REGS,
  FP_REGS, DF_HI_REGS, DF_REGS, FPSCR_REGS,
  GENERAL_FP_REGS, GENERAL_DF_REGS, TARGET_REGS, ALL_REGS,
  LIM_REG_CLASSES, NO_REGS, FPCC_REGS, I64_REGS,
  GENERAL_REGS, FP_REGS, EXTRA_FP_REGS, GENERAL_OR_FP_REGS,
  GENERAL_OR_EXTRA_FP_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  R0_REGS, R1_REGS, TWO_REGS, R2_REGS,
  EIGHT_REGS, R8_REGS, ICALL_REGS, GENERAL_REGS,
  CARRY_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES, NO_REGS,
  ALL_REGS, LIM_REG_CLASSES, NO_REGS, BR_REGS,
  FP_REGS, ACC_REG, SP_REG, RL_REGS,
  GR_REGS, AR_REGS, ALL_REGS, LIM_REG_CLASSES
}

Functions/Subroutines

 GTY (()) rtx sparc_compare_op0

Variables

struct processor_costs * sparc_costs
enum cmodel sparc_cmodel
enum processor_type sparc_cpu
struct sparc_cpu_select sparc_select []
const int * hard_regno_mode_classes
int sparc_mode_class []
enum reg_class sparc_regno_reg_class [FIRST_PSEUDO_REGISTER]
char sparc_leaf_regs []
char leaf_reg_remap []
int sparc_indent_opcode

Define Documentation

#define ACCUMULATE_OUTGOING_ARGS   1

Definition at line 1443 of file sparc.h.

#define ADDITIONAL_REGISTER_NAMES   {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}

Definition at line 2229 of file sparc.h.

#define APPLY_RESULT_SIZE   (TARGET_ARCH64 ? 24 : 16)

Definition at line 1508 of file sparc.h.

#define ARG_POINTER_CFA_OFFSET ( FNDECL   )     0

Definition at line 1401 of file sparc.h.

#define ARG_POINTER_REGNUM   FRAME_POINTER_REGNUM

Definition at line 957 of file sparc.h.

#define AS_NEEDS_DASH_FOR_PIPED_INPUT

Definition at line 445 of file sparc.h.

#define ASM_APP_OFF   ""

Definition at line 2207 of file sparc.h.

#define ASM_APP_ON   ""

Definition at line 2202 of file sparc.h.

#define ASM_ARCH32_SPEC   "-32"

Definition at line 418 of file sparc.h.

#define ASM_ARCH64_SPEC   "-64"

Definition at line 422 of file sparc.h.

#define ASM_ARCH_DEFAULT_SPEC   (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)

Definition at line 424 of file sparc.h.

#define ASM_ARCH_SPEC   "\%{m32:%(asm_arch32)} \%{m64:%(asm_arch64)} \%{!m32:%{!m64:%(asm_arch_default)}} \"

Definition at line 427 of file sparc.h.

#define ASM_COMMENT_START   "!"

Definition at line 2197 of file sparc.h.

#define ASM_CPU32_DEFAULT_SPEC   ""

Definition at line 280 of file sparc.h.

#define ASM_CPU64_DEFAULT_SPEC   ""

Definition at line 275 of file sparc.h.

#define ASM_CPU_DEFAULT_SPEC   (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)

Definition at line 336 of file sparc.h.

#define ASM_CPU_SPEC   "\%{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \%{msparclite:-Asparclite} \%{mf930:-Asparclite} %{mf934:-Asparclite} \%{mcpu=sparclite:-Asparclite} \%{mcpu=sparclite86x:-Asparclite} \%{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \%{mv8plus:-Av8plus} \%{mcpu=v9:-Av9} \%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \%{mcpu=niagara:%{!mv8plus:-Av9b}} \%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \"

Definition at line 400 of file sparc.h.

#define ASM_DECLARE_RESULT ( FILE,
RESULT   )     fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))

Definition at line 1609 of file sparc.h.

#define ASM_GENERATE_INTERNAL_LABEL ( LABEL,
PREFIX,
NUM   )     sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))

Definition at line 2255 of file sparc.h.

#define ASM_OUTPUT_ADDR_DIFF_ELT ( FILE,
BODY,
VALUE,
REL   ) 

Value:

do {                  \
  char label[30];             \
  ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE));      \
  if (CASE_VECTOR_MODE == SImode)         \
    fprintf (FILE, "\t.word\t");          \
  else                  \
    fprintf (FILE, "\t.xword\t");         \
  assemble_name (FILE, label);            \
  ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL));      \
  fputc ('-', FILE);              \
  assemble_name (FILE, label);            \
  fputc ('\n', FILE);             \
} while (0)

Definition at line 2283 of file sparc.h.

#define ASM_OUTPUT_ADDR_DIFF_VEC ( LAB,
VEC   )     sparc_defer_case_vector ((LAB),(VEC), 1)

Definition at line 2263 of file sparc.h.

#define ASM_OUTPUT_ADDR_VEC ( LAB,
VEC   )     sparc_defer_case_vector ((LAB),(VEC), 0)

Definition at line 2260 of file sparc.h.

#define ASM_OUTPUT_ADDR_VEC_ELT ( FILE,
VALUE   ) 

Value:

do {                  \
  char label[30];             \
  ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE);      \
  if (CASE_VECTOR_MODE == SImode)         \
    fprintf (FILE, "\t.word\t");          \
  else                  \
    fprintf (FILE, "\t.xword\t");         \
  assemble_name (FILE, label);            \
  fputc ('\n', FILE);             \
} while (0)

Definition at line 2268 of file sparc.h.

#define ASM_OUTPUT_ALIGN ( FILE,
LOG   ) 

Value:

if ((LOG) != 0)     \
    fprintf (FILE, "\t.align %d\n", (1<<(LOG)))

Definition at line 2316 of file sparc.h.

#define ASM_OUTPUT_ALIGN_WITH_NOP ( FILE,
LOG   ) 

Value:

if ((LOG) != 0)                             \
    fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))

Definition at line 2323 of file sparc.h.

#define ASM_OUTPUT_ALIGNED_BSS ( FILE,
DECL,
NAME,
SIZE,
ALIGN   ) 

Value:

do {                \
    ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN);   \
  } while (0)

Definition at line 2352 of file sparc.h.

#define ASM_OUTPUT_ALIGNED_LOCAL ( FILE,
NAME,
SIZE,
ALIGNED   ) 

Value:

( fputs ("\t.reserve ", (FILE)),          \
  assemble_name ((FILE), (NAME)),         \
  fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n",  \
     (SIZE), ((ALIGNED) / BITS_PER_UNIT)))

Definition at line 2341 of file sparc.h.

#define ASM_OUTPUT_COMMON ( FILE,
NAME,
SIZE,
ROUNDED   ) 

Value:

( fputs ("\t.common ", (FILE)),   \
  assemble_name ((FILE), (NAME)),   \
  fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))

Definition at line 2333 of file sparc.h.

#define ASM_OUTPUT_IDENT ( FILE,
NAME   )     fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);

Definition at line 2361 of file sparc.h.

#define ASM_OUTPUT_OPCODE ( FILE,
PTR   ) 

Value:

do {          \
    if (sparc_indent_opcode)    \
      {         \
  putc (' ', FILE);   \
  sparc_indent_opcode = 0;  \
      }         \
  } while (0)

Definition at line 2368 of file sparc.h.

#define ASM_OUTPUT_SKIP ( FILE,
SIZE   )     fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))

Definition at line 2327 of file sparc.h.

#define ASM_RELAX_SPEC   ""

Definition at line 436 of file sparc.h.

#define ASM_SPEC   "\%{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \%(asm_cpu) %(asm_relax)"

Definition at line 441 of file sparc.h.

#define BASE_REG_CLASS   GENERAL_REGS

Definition at line 1174 of file sparc.h.

#define BIGGEST_ALIGNMENT   (TARGET_ARCH64 ? 128 : 64)

Definition at line 659 of file sparc.h.

#define BITS_BIG_ENDIAN   1

Definition at line 571 of file sparc.h.

#define BRANCH_COST

Value:

((sparc_cpu == PROCESSOR_V9 \
    || sparc_cpu == PROCESSOR_ULTRASPARC) \
   ? 7 \
         : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
            ? 9 \
   : (sparc_cpu == PROCESSOR_NIAGARA \
      ? 4 \
   : 3)))

Definition at line 2168 of file sparc.h.

#define BYTES_BIG_ENDIAN   1

Definition at line 574 of file sparc.h.

#define CALL_USED_REGISTERS

Value:

{1, 1, 1, 1, 1, 1, 1, 1,  \
  1, 1, 1, 1, 1, 1, 1, 1, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 1, 1, \
        \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
        \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
        \
  1, 1, 1, 1, 1, 1}

Definition at line 793 of file sparc.h.

#define CAN_DEBUG_WITHOUT_FP

Definition at line 490 of file sparc.h.

#define CAN_ELIMINATE ( FROM,
TO   )     ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)

Definition at line 1424 of file sparc.h.

#define CANNOT_CHANGE_MODE_CLASS ( FROM,
TO,
CLASS   ) 

Value:

(TARGET_ARCH64            \
   && (FROM) == SImode            \
   && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)    \
   ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)

Definition at line 1072 of file sparc.h.

#define CASE_VECTOR_MODE   (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)

Definition at line 2061 of file sparc.h.

#define CC1_SPEC   "\%{sun4:} %{target:} \%{mcypress:-mcpu=cypress} \%{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \%{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \"

Definition at line 392 of file sparc.h.

#define CLASS_MAX_NREGS ( CLASS,
MODE   ) 

Value:

(FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

Definition at line 1365 of file sparc.h.

#define CONDITIONAL_REGISTER_USAGE

Definition at line 814 of file sparc.h.

#define CONST_DOUBLE_OK_FOR_LETTER_P ( VALUE,
C   ) 

Value:

((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE))  \
   : (C) == 'H' ? arith_double_operand (VALUE, DImode)    \
   : 0)

Definition at line 1254 of file sparc.h.

#define CONST_OK_FOR_LETTER_P ( VALUE,
C   ) 

Value:

((C) == 'I' ? SPARC_SIMM13_P (VALUE)      \
   : (C) == 'J' ? (VALUE) == 0        \
   : (C) == 'K' ? SPARC_SETHI32_P (VALUE)   \
   : (C) == 'L' ? SPARC_SIMM11_P (VALUE)    \
   : (C) == 'M' ? SPARC_SIMM10_P (VALUE)    \
   : (C) == 'N' ? SPARC_SETHI_P (VALUE)     \
   : (C) == 'O' ? (VALUE) == 4096     \
   : 0)

Definition at line 1241 of file sparc.h.

#define CONSTANT_ADDRESS_P ( X   )     constant_address_p (X)

Definition at line 1835 of file sparc.h.

#define CONSTANT_ALIGNMENT ( EXP,
ALIGN   ) 

Value:

((TREE_CODE (EXP) == STRING_CST \
    && (ALIGN) < FASTEST_ALIGNMENT) \
   ? FASTEST_ALIGNMENT : (ALIGN))

Definition at line 682 of file sparc.h.

#define CPP_ARCH32_SPEC   ""

Definition at line 364 of file sparc.h.

#define CPP_ARCH64_SPEC   "-D__arch64__"

Definition at line 365 of file sparc.h.

#define CPP_ARCH_DEFAULT_SPEC   (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)

Definition at line 367 of file sparc.h.

#define CPP_ARCH_SPEC   "\%{m32:%(cpp_arch32)} \%{m64:%(cpp_arch64)} \%{!m32:%{!m64:%(cpp_arch_default)}} \"

Definition at line 370 of file sparc.h.

#define CPP_CPU32_DEFAULT_SPEC   ""

Definition at line 279 of file sparc.h.

#define CPP_CPU64_DEFAULT_SPEC   ""

Definition at line 274 of file sparc.h.

#define CPP_CPU_DEFAULT_SPEC   (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)

Definition at line 335 of file sparc.h.

#define CPP_CPU_SPEC   "\%{msoft-float:-D_SOFT_FLOAT} \%{mcypress:} \%{msparclite:-D__sparclite__} \%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \%{mv8:-D__sparc_v8__} \%{msupersparc:-D__supersparc__ -D__sparc_v8__} \%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \%{mcpu=sparclite:-D__sparclite__} \%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \%{mcpu=v8:-D__sparc_v8__} \%{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \%{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \%{mcpu=sparclite86x:-D__sparclite86x__} \%{mcpu=v9:-D__sparc_v9__} \%{mcpu=ultrasparc:-D__sparc_v9__} \%{mcpu=ultrasparc3:-D__sparc_v9__} \%{mcpu=niagara:-D__sparc_v9__} \%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \"

Definition at line 344 of file sparc.h.

#define CPP_ENDIAN_SPEC   "\%{mlittle-endian:-D__LITTLE_ENDIAN__} \%{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"

Definition at line 377 of file sparc.h.

#define CPP_SPEC   "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"

Definition at line 384 of file sparc.h.

#define CPP_SUBTARGET_SPEC   ""

Definition at line 382 of file sparc.h.

#define CUMULATIVE_ARGS   struct sparc_args

Definition at line 1536 of file sparc.h.

#define DATA_ALIGNMENT ( TYPE,
ALIGN   ) 

Value:

(TREE_CODE (TYPE) == ARRAY_TYPE   \
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode  \
   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))

Definition at line 688 of file sparc.h.

#define DBX_CONTIN_LENGTH   1000

Definition at line 2238 of file sparc.h.

#define DEFAULT_ARCH32_P   ((TARGET_DEFAULT & MASK_64BIT) == 0)

Definition at line 130 of file sparc.h.

#define DEFAULT_PCC_STRUCT_RETURN   -1

Definition at line 972 of file sparc.h.

#define DEFAULT_SIGNED_CHAR   1

Definition at line 2066 of file sparc.h.

#define DITF_CONVERSION_LIBFUNCS   0

Definition at line 2141 of file sparc.h.

#define DOUBLE_TYPE_SIZE   64

Definition at line 607 of file sparc.h.

#define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (15)

Definition at line 1737 of file sparc.h.

#define DYNAMIC_CHAIN_ADDRESS ( frame   )     plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)

Definition at line 1701 of file sparc.h.

#define EH_RETURN_DATA_REGNO ( N   )     ((N) < 4 ? (N) + 24 : INVALID_REGNUM)

Definition at line 1745 of file sparc.h.

#define EH_RETURN_HANDLER_RTX   gen_rtx_REG (Pmode, 31)

Definition at line 1747 of file sparc.h.

#define EH_RETURN_STACKADJ_RTX   gen_rtx_REG (Pmode, 1)

Definition at line 1746 of file sparc.h.

#define ELIMINABLE_REGS

Value:

{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }

Definition at line 1416 of file sparc.h.

#define EMBMEDANY_BASE_REG   "%g4"

Definition at line 220 of file sparc.h.

#define EMPTY_FIELD_BOUNDARY   (TARGET_ARCH64 ? 64 : 32)

Definition at line 650 of file sparc.h.

#define EPILOGUE_USES ( REGNO   ) 

Value:

((REGNO) == 31 \
  || (current_function_calls_eh_return && (REGNO) == 1))

Definition at line 1670 of file sparc.h.

#define EXIT_IGNORE_STACK

Value:

(get_frame_size () != 0 \
  || current_function_calls_alloca || current_function_outgoing_args_size)

Definition at line 1665 of file sparc.h.

#define EXPAND_BUILTIN_VA_START ( valist,
nextarg   )     sparc_va_start (valist, nextarg)

Definition at line 1690 of file sparc.h.

#define EXTRA_CONSTRAINT ( OP,
C   )     sparc_extra_constraint_check(OP, C, 0)

Definition at line 1902 of file sparc.h.

#define EXTRA_SPECS

Value:

{ "cpp_cpu",    CPP_CPU_SPEC },   \
  { "cpp_cpu_default",  CPP_CPU_DEFAULT_SPEC }, \
  { "cpp_arch32", CPP_ARCH32_SPEC },  \
  { "cpp_arch64", CPP_ARCH64_SPEC },  \
  { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
  { "cpp_arch",   CPP_ARCH_SPEC },  \
  { "cpp_endian", CPP_ENDIAN_SPEC },  \
  { "cpp_subtarget",  CPP_SUBTARGET_SPEC }, \
  { "asm_cpu",    ASM_CPU_SPEC },   \
  { "asm_cpu_default",  ASM_CPU_DEFAULT_SPEC }, \
  { "asm_arch32", ASM_ARCH32_SPEC },  \
  { "asm_arch64", ASM_ARCH64_SPEC },  \
  { "asm_relax",  ASM_RELAX_SPEC }, \
  { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
  { "asm_arch",   ASM_ARCH_SPEC },  \
  SUBTARGET_EXTRA_SPECS

Definition at line 457 of file sparc.h.

#define FASTEST_ALIGNMENT   64

Definition at line 662 of file sparc.h.

#define FIRST_PARM_OFFSET ( FNDECL   )     (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)

Definition at line 1395 of file sparc.h.

#define FIRST_PSEUDO_REGISTER   102

Definition at line 718 of file sparc.h.

#define FIXED_REGISTERS

Value:

{1, 0, 2, 2, 2, 2, 1, 1,  \
  0, 0, 0, 0, 0, 0, 1, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 1, 1, \
        \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
        \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
        \
  0, 0, 0, 0, 0, 1}

Definition at line 768 of file sparc.h.

#define FLOAT_LIB_COMPARE_RETURNS_BOOL ( MODE,
COMPARISON   )     ((MODE) == TFmode)

Definition at line 2130 of file sparc.h.

#define FLOAT_TYPE_SIZE   32

Definition at line 606 of file sparc.h.

#define FP_REG_CLASS_P ( CLASS   )     ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)

Definition at line 1177 of file sparc.h.

#define FP_REG_P ( X   )     (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))

Definition at line 1822 of file sparc.h.

#define FRAME_ADDR_RTX ( frame   )     plus_constant (frame, SPARC_STACK_BIAS)

Definition at line 1706 of file sparc.h.

Referenced by expand_builtin_return_addr().

#define FRAME_GROWS_DOWNWARD   1

Definition at line 1379 of file sparc.h.

#define FRAME_POINTER_REGNUM   101

Definition at line 937 of file sparc.h.

#define FRAME_POINTER_REQUIRED   (! (leaf_function_p () && only_leaf_regs_used ()))

Definition at line 953 of file sparc.h.

#define FUNCTION_ARG ( CUM,
MODE,
TYPE,
NAMED   )     function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)

Definition at line 1565 of file sparc.h.

#define FUNCTION_ARG_ADVANCE ( CUM,
MODE,
TYPE,
NAMED   )     function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))

Definition at line 1549 of file sparc.h.

#define FUNCTION_ARG_BOUNDARY ( MODE,
TYPE   ) 

Value:

((TARGET_ARCH64         \
  && (GET_MODE_ALIGNMENT (MODE) == 128    \
      || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
 ? 128 : PARM_BOUNDARY)

Definition at line 1587 of file sparc.h.

#define FUNCTION_ARG_PADDING ( MODE,
TYPE   )     function_arg_padding ((MODE), (TYPE))

Definition at line 1579 of file sparc.h.

#define FUNCTION_ARG_REGNO_P ( N   ) 

Value:

(TARGET_ARCH64 \
 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
 : ((N) >= 8 && (N) <= 13))

Definition at line 1513 of file sparc.h.

#define FUNCTION_BOUNDARY   32

Definition at line 647 of file sparc.h.

#define FUNCTION_INCOMING_ARG ( CUM,
MODE,
TYPE,
NAMED   )     function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)

Definition at line 1571 of file sparc.h.

#define FUNCTION_MODE   Pmode

Definition at line 2118 of file sparc.h.

#define FUNCTION_OUTGOING_VALUE ( VALTYPE,
FUNC   )     function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)

Definition at line 1489 of file sparc.h.

#define FUNCTION_PROFILER ( FILE,
LABELNO   )     do { } while (0)

Definition at line 1655 of file sparc.h.

#define FUNCTION_VALUE ( VALTYPE,
FUNC   )     function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)

Definition at line 1484 of file sparc.h.

#define FUNCTION_VALUE_REGNO_P ( N   )     ((N) == 8 || (N) == 32)

Definition at line 1503 of file sparc.h.

#define GENERAL_OR_I64 ( C   )     ((C) == GENERAL_REGS || (C) == I64_REGS)

Definition at line 2146 of file sparc.h.

#define GLOBAL_ASM_OP   "\t.global "

Definition at line 2244 of file sparc.h.

#define GO_IF_LEGITIMATE_ADDRESS ( MODE,
X,
ADDR   ) 

Value:

{             \
  if (legitimate_address_p (MODE, X, 0))    \
    goto ADDR;            \
}

Definition at line 1962 of file sparc.h.

#define GO_IF_MODE_DEPENDENT_ADDRESS ( ADDR,
LABEL   ) 

Value:

{             \
  if (flag_pic == 1)          \
    {             \
      if (GET_CODE (ADDR) == PLUS)      \
  {           \
    rtx op0 = XEXP (ADDR, 0);     \
    rtx op1 = XEXP (ADDR, 1);     \
    if (op0 == pic_offset_table_rtx   \
        && SYMBOLIC_CONST (op1))      \
      goto LABEL;         \
  }           \
    }             \
}

Definition at line 1982 of file sparc.h.

#define HARD_FRAME_POINTER_REGNUM   30

Definition at line 934 of file sparc.h.

#define HARD_REGNO_MODE_OK ( REGNO,
MODE   )     ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)

Definition at line 893 of file sparc.h.

#define HARD_REGNO_NREGS ( REGNO,
MODE   ) 

Value:

(TARGET_ARCH64              \
   ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM     \
      ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD  \
      : (GET_MODE_SIZE (MODE) + 3) / 4)         \
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

Definition at line 873 of file sparc.h.

#define HARD_REGNO_RENAME_OK ( FROM,
TO   )     ((FROM) != 1)

Definition at line 899 of file sparc.h.

#define IDENT_ASM_OP   "\t.ident\t"

Definition at line 2357 of file sparc.h.

#define IN_OR_GLOBAL_P ( X   )     (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))

Definition at line 1825 of file sparc.h.

#define INCOMING_FRAME_SP_OFFSET   SPARC_STACK_BIAS

Definition at line 1742 of file sparc.h.

#define INCOMING_REGNO ( OUT   )     (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)

Definition at line 1459 of file sparc.h.

#define INCOMING_RETURN_ADDR_RTX   plus_constant (gen_rtx_REG (word_mode, 15), 8)

Definition at line 1735 of file sparc.h.

#define INDEX_REG_CLASS   GENERAL_REGS

Definition at line 1173 of file sparc.h.

#define INIT_CUMULATIVE_ARGS ( CUM,
FNTYPE,
LIBNAME,
FNDECL,
N_NAMED_ARGS   )     init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));

Definition at line 1542 of file sparc.h.

#define INIT_EXPANDERS

Value:

do {                   \
    if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS)   \
      {                  \
  REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT;  \
  REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
      }                  \
  } while (0)

Definition at line 940 of file sparc.h.

#define INITIAL_ELIMINATION_OFFSET ( FROM,
TO,
OFFSET   ) 

Value:

do {                  \
    if ((TO) == STACK_POINTER_REGNUM)         \
      (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
    else                \
      (OFFSET) = 0;             \
    (OFFSET) += SPARC_STACK_BIAS;         \
  } while (0)

Definition at line 1430 of file sparc.h.

#define INITIALIZE_TRAMPOLINE ( TRAMP,
FNADDR,
CXT   ) 

Value:

if (TARGET_ARCH64)            \
      sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
    else              \
      sparc_initialize_trampoline (TRAMP, FNADDR, CXT)

Definition at line 1683 of file sparc.h.

#define INT_TYPE_SIZE   32

Definition at line 603 of file sparc.h.

#define JMP_BUF_SIZE   12

Definition at line 2480 of file sparc.h.

#define LEAF_REG_REMAP ( REGNO   )     (leaf_reg_remap[REGNO])

Definition at line 1170 of file sparc.h.

#define LEAF_REGISTERS   sparc_leaf_regs

Definition at line 1167 of file sparc.h.

#define LEGITIMATE_CONSTANT_P ( X   )     legitimate_constant_p (X)

Definition at line 1846 of file sparc.h.

#define LEGITIMATE_PIC_OPERAND_P ( X   )     legitimate_pic_operand_p (X)

Definition at line 1840 of file sparc.h.

#define LEGITIMIZE_ADDRESS ( X,
OLDX,
MODE,
WIN   ) 

Value:

{           \
  (X) = legitimize_address (X, OLDX, MODE); \
  if (memory_address_p (MODE, X))   \
    goto WIN;         \
}

Definition at line 2011 of file sparc.h.

#define LEGITIMIZE_RELOAD_ADDRESS ( X,
MODE,
OPNUM,
TYPE,
IND_LEVELS,
WIN   ) 

Value:

do {                                                                    \
  /* Decompose SImode constants into hi+lo_sum.  We do have to    \
     rerecognize what we produce, so be careful.  */      \
  if (CONSTANT_P (X)              \
      && (MODE != TFmode || TARGET_ARCH64)        \
      && GET_MODE (X) == SImode           \
      && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH     \
      && ! (flag_pic              \
      && (symbolic_operand (X, Pmode)       \
    || pic_address_needs_scratch (X)))      \
      && sparc_cmodel <= CM_MEDLOW)         \
    {                 \
      X = gen_rtx_LO_SUM (GET_MODE (X),         \
        gen_rtx_HIGH (GET_MODE (X), X), X);   \
      push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL,   \
                   BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0,  \
                   OPNUM, TYPE);          \
      goto WIN;               \
    }                 \
  /* ??? 64-bit reloads.  */            \
} while (0)

Definition at line 2029 of file sparc.h.

#define LIBCALL_VALUE ( MODE   )     function_value (NULL_TREE, (MODE), 1)

Definition at line 1495 of file sparc.h.

#define LIBGCC2_WORDS_BIG_ENDIAN   1

Definition at line 585 of file sparc.h.

#define LINK_GCC_C_SEQUENCE_SPEC   "%G %L %G %L"

Definition at line 479 of file sparc.h.

#define LOAD_EXTEND_OP ( MODE   )     ZERO_EXTEND

Definition at line 2085 of file sparc.h.

#define LOCAL_REGNO ( REGNO   )     ((REGNO) >= 16 && (REGNO) <= 31)

Definition at line 1474 of file sparc.h.

#define LONG_LONG_TYPE_SIZE   64

Definition at line 605 of file sparc.h.

#define LONG_TYPE_SIZE   (TARGET_ARCH64 ? 64 : 32)

Definition at line 604 of file sparc.h.

#define MASK_ISA   (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)

Definition at line 497 of file sparc.h.

#define MAX_BITS_PER_WORD   64

Definition at line 588 of file sparc.h.

#define MAX_REGS_PER_ADDRESS   2

Definition at line 1829 of file sparc.h.

#define MAX_TEXT_ALIGN   32

Definition at line 700 of file sparc.h.

#define MCOUNT_FUNCTION   "*mcount"

Definition at line 1658 of file sparc.h.

#define MIN_UNITS_PER_WORD   4

Definition at line 595 of file sparc.h.

#define MODES_TIEABLE_P ( MODE1,
MODE2   ) 

Value:

((MODE1) == (MODE2)           \
   || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)   \
       && (! TARGET_V9            \
     || (GET_MODE_CLASS (MODE1) != MODE_FLOAT   \
         || (MODE1 != SFmode && MODE2 != SFmode)))))

Definition at line 909 of file sparc.h.

#define MOVE_MAX   8

Definition at line 2070 of file sparc.h.

#define MOVE_RATIO   (optimize_size ? 3 : 8)

Definition at line 2075 of file sparc.h.

#define N_REG_CLASSES   (int) LIM_REG_CLASSES

Definition at line 1040 of file sparc.h.

#define NEED_INDICATE_EXEC_STACK   0

Definition at line 216 of file sparc.h.

#define NO_FUNCTION_CSE

Definition at line 2124 of file sparc.h.

#define OPTION_DEFAULT_SPECS

Value:

{"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
  {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }

Definition at line 551 of file sparc.h.

#define ORDER_REGS_FOR_LOCAL_ALLOC   order_regs_for_local_alloc ()

Definition at line 1164 of file sparc.h.

#define OUTGOING_REGNO ( IN   )     (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)

Definition at line 1467 of file sparc.h.

#define OVERRIDE_OPTIONS   sparc_override_options ()

Definition at line 494 of file sparc.h.

#define PARM_BOUNDARY   (TARGET_ARCH64 ? 64 : 32)

Definition at line 632 of file sparc.h.

#define PCC_BITFIELD_TYPE_MATTERS   1

Definition at line 656 of file sparc.h.

#define PIC_OFFSET_TABLE_REGNUM   (flag_pic ? 23 : INVALID_REGNUM)

Definition at line 966 of file sparc.h.

#define Pmode   (TARGET_ARCH64 ? DImode : SImode)

Definition at line 2102 of file sparc.h.

#define POINTER_SIZE   (TARGET_PTR64 ? 64 : 32)

Definition at line 614 of file sparc.h.

#define POINTERS_EXTEND_UNSIGNED   1

Definition at line 619 of file sparc.h.

#define PREFERRED_RELOAD_CLASS ( X,
CLASS   ) 

Value:

(CONSTANT_P (X)         \
   ? ((FP_REG_CLASS_P (CLASS)       \
       || (CLASS) == GENERAL_OR_FP_REGS     \
       || (CLASS) == GENERAL_OR_EXTRA_FP_REGS   \
       || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT  \
     && ! TARGET_FPU)       \
       || (GET_MODE (X) == TFmode     \
     && ! const_zero_operand (X, TFmode)))  \
      ? NO_REGS           \
      : (!FP_REG_CLASS_P (CLASS)      \
         && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT)  \
      ? GENERAL_REGS          \
      : (CLASS))          \
   : (CLASS))

Definition at line 1271 of file sparc.h.

#define PREFETCH_BLOCK

Value:

((sparc_cpu == PROCESSOR_ULTRASPARC \
          || sparc_cpu == PROCESSOR_ULTRASPARC3 \
    || sparc_cpu == PROCESSOR_NIAGARA) \
         ? 64 : 32)

Definition at line 2178 of file sparc.h.

#define PRINT_OPERAND ( FILE,
X,
CODE   )     print_operand (FILE, X, CODE)

Definition at line 2388 of file sparc.h.

#define PRINT_OPERAND_ADDRESS ( FILE,
ADDR   ) 

Definition at line 2392 of file sparc.h.

#define PRINT_OPERAND_PUNCT_VALID_P ( CHAR   ) 

Value:

((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '('    \
   || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')

Definition at line 2380 of file sparc.h.

#define PROFILE_HOOK ( LABEL   )     sparc_profile_hook (LABEL)

Definition at line 1652 of file sparc.h.

#define PROMOTE_FUNCTION_MODE ( MODE,
UNSIGNEDP,
TYPE   ) 

Value:

if (TARGET_ARCH64       \
    && GET_MODE_CLASS (MODE) == MODE_INT  \
    && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
  (MODE) = word_mode;

Definition at line 625 of file sparc.h.

#define PTRDIFF_TYPE   (TARGET_ARCH64 ? "long int" : "int")

Definition at line 482 of file sparc.h.

#define REG_ALLOC_ORDER

Value:

{ 1, 2, 3, 4, 5, 6, 7,      /* %g1-%g7 */ \
  13, 12, 11, 10, 9, 8,     /* %o5-%o0 */ \
  15,         /* %o7 */ \
  16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */   \
  29, 28, 27, 26, 25, 24, 31,   /* %i5-%i0,%i7 */\
  40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */  \
  48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
  56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
  64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
  72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
  80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
  88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
  39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */   \
  96, 97, 98, 99,     /* %fcc0-3 */   \
  100, 0, 14, 30, 101}

Definition at line 1108 of file sparc.h.

#define REG_CLASS_CONTENTS

Value:

{{0, 0, 0, 0},  /* NO_REGS */     \
   {0, 0, 0, 0xf},  /* FPCC_REGS */     \
   {0xffff, 0, 0, 0}, /* I64_REGS */      \
   {-1, 0, 0, 0x20},  /* GENERAL_REGS */    \
   {0, -1, 0, 0}, /* FP_REGS */     \
   {0, -1, -1, 0},  /* EXTRA_FP_REGS */   \
   {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */  \
   {-1, -1, -1, 0x20},  /* GENERAL_OR_EXTRA_FP_REGS */  \
   {-1, -1, -1, 0x3f}}

Definition at line 1053 of file sparc.h.

#define REG_CLASS_FROM_LETTER ( C   ) 

Value:

(TARGET_V9          \
 ? ((C) == 'f' ? FP_REGS      \
    : (C) == 'e' ? EXTRA_FP_REGS    \
    : (C) == 'c' ? FPCC_REGS      \
    : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
    : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
    : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
    : NO_REGS)          \
 : ((C) == 'f' ? FP_REGS      \
    : (C) == 'e' ? FP_REGS      \
    : (C) == 'c' ? FPCC_REGS      \
    : NO_REGS))

Definition at line 1186 of file sparc.h.

#define REG_CLASS_NAMES

Value:

{ "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS",  \
     "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
     "ALL_REGS" }

Definition at line 1044 of file sparc.h.

#define REG_LEAF_ALLOC_ORDER

Value:

{ 1, 2, 3, 4, 5, 6, 7,      /* %g1-%g7 */ \
  29, 28, 27, 26, 25, 24,   /* %i5-%i0 */ \
  15,         /* %o7 */ \
  13, 12, 11, 10, 9, 8,     /* %o5-%o0 */ \
  16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
  40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */  \
  48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
  56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
  64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
  72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
  80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
  88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
  39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
  96, 97, 98, 99,     /* %fcc0-3 */ \
  100, 0, 14, 30, 31, 101}

Definition at line 1147 of file sparc.h.

#define REG_OK_FOR_BASE_P ( X   )     REG_OK_FOR_INDEX_P (X)

Definition at line 1894 of file sparc.h.

#define REG_OK_FOR_INDEX_P ( X   ) 

Value:

(REGNO (X) < 32       \
   || REGNO (X) == FRAME_POINTER_REGNUM   \
   || REGNO (X) >= FIRST_PSEUDO_REGISTER)

Definition at line 1887 of file sparc.h.

#define REG_PARM_STACK_SPACE ( DECL   )     (6 * UNITS_PER_WORD)

Definition at line 1412 of file sparc.h.

#define REGISTER_MOVE_COST ( MODE,
CLASS1,
CLASS2   ) 

Value:

(((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
    || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
    || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS)    \
   ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
       || sparc_cpu == PROCESSOR_ULTRASPARC3 \
       || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2)

Definition at line 2147 of file sparc.h.

#define REGISTER_NAMES

Value:

{"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7",    \
 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7",    \
 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7",    \
 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7",    \
 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",    \
 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",    \
 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",  \
 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",  \
 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39",  \
 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47",  \
 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55",  \
 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63",  \
 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }

Definition at line 2212 of file sparc.h.

#define REGMODE_NATURAL_SIZE ( MODE   )     ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)

Definition at line 882 of file sparc.h.

#define REGNO_OK_FOR_BASE_P ( REGNO   )     REGNO_OK_FOR_INDEX_P (REGNO)

Definition at line 1803 of file sparc.h.

#define REGNO_OK_FOR_CCFP_P ( REGNO   ) 

Value:

(TARGET_V9 \
  && (((unsigned) (REGNO) - 96 < (unsigned)4) \
      || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))

Definition at line 1808 of file sparc.h.

#define REGNO_OK_FOR_FP_P ( REGNO   ) 

Value:

(((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
   || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))

Definition at line 1805 of file sparc.h.

#define REGNO_OK_FOR_INDEX_P ( REGNO   ) 

Value:

((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32  \
 || (REGNO) == FRAME_POINTER_REGNUM       \
 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)

Definition at line 1798 of file sparc.h.

#define REGNO_REG_CLASS ( REGNO   )     sparc_regno_reg_class[(REGNO)]

Definition at line 1085 of file sparc.h.

#define RETURN_ADDR_IN_PREVIOUS_FRAME

Definition at line 1712 of file sparc.h.

#define RETURN_ADDR_OFFSET   (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))

Definition at line 1716 of file sparc.h.

#define RETURN_ADDR_RTX ( count,
frame   ) 

Value:

((count == -1)        \
   ? gen_rtx_REG (Pmode, 31)      \
   : gen_rtx_MEM (Pmode,      \
      memory_address (Pmode, plus_constant (frame, \
              15 * UNITS_PER_WORD \
              + SPARC_STACK_BIAS))))

Definition at line 1723 of file sparc.h.

#define RETURN_POPS_ARGS ( FUNDECL,
FUNTYPE,
SIZE   )     0

Definition at line 1452 of file sparc.h.

#define REVERSIBLE_CC_MODE ( MODE   )     ((MODE) != CCFPEmode && (MODE) != CCFPmode)

Definition at line 2115 of file sparc.h.

#define ROUND_TYPE_ALIGN ( STRUCT,
COMPUTED,
SPECIFIED   ) 

Value:

(TARGET_FASTER_STRUCTS ?        \
  ((TREE_CODE (STRUCT) == RECORD_TYPE     \
    || TREE_CODE (STRUCT) == UNION_TYPE                 \
    || TREE_CODE (STRUCT) == QUAL_UNION_TYPE)           \
   && TYPE_FIELDS (STRUCT) != 0                         \
     ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
     : MAX ((COMPUTED), (SPECIFIED)))     \
   :  MAX ((COMPUTED), (SPECIFIED)))

Definition at line 671 of file sparc.h.

#define RTX_OK_FOR_BASE_P ( X   ) 

Value:

((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))     \
  || (GET_CODE (X) == SUBREG            \
      && GET_CODE (SUBREG_REG (X)) == REG       \
      && REG_OK_FOR_BASE_P (SUBREG_REG (X))))

Definition at line 1937 of file sparc.h.

#define RTX_OK_FOR_INDEX_P ( X   ) 

Value:

((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))      \
  || (GET_CODE (X) == SUBREG            \
      && GET_CODE (SUBREG_REG (X)) == REG       \
      && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))

Definition at line 1943 of file sparc.h.

#define RTX_OK_FOR_OFFSET_P ( X   )     (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)

Definition at line 1949 of file sparc.h.

#define RTX_OK_FOR_OLO10_P ( X   )     (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)

Definition at line 1952 of file sparc.h.

#define SECONDARY_INPUT_RELOAD_CLASS ( CLASS,
MODE,
IN   ) 

Value:

((FP_REG_CLASS_P (CLASS)          \
    && ((MODE) == HImode || (MODE) == QImode)     \
    && (GET_CODE (IN) == MEM          \
        || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
            && true_regnum (IN) == -1)))      \
   ? GENERAL_REGS           \
   : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode    \
      && GET_CODE (IN) == MEM && TARGET_ARCH32      \
      && ! mem_min_alignment ((IN), 8))       \
     ? FP_REGS              \
     : (((TARGET_CM_MEDANY          \
    && symbolic_operand ((IN), (MODE)))     \
   || (TARGET_CM_EMBMEDANY        \
       && text_segment_operand ((IN), (MODE))))   \
  && !flag_pic)           \
       ? GENERAL_REGS           \
       : NO_REGS)

Definition at line 1297 of file sparc.h.

#define SECONDARY_MEMORY_NEEDED ( CLASS1,
CLASS2,
MODE   )     (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))

Definition at line 1337 of file sparc.h.

#define SECONDARY_MEMORY_NEEDED_MODE ( MODE   ) 

Value:

(TARGET_ARCH64            \
   ? (GET_MODE_BITSIZE (MODE) < 32        \
      ? mode_for_size (32, GET_MODE_CLASS (MODE), 0)    \
      : MODE)             \
   : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD     \
      ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
      : MODE))

Definition at line 1353 of file sparc.h.

#define SECONDARY_MEMORY_NEEDED_RTX ( MODE   ) 

Value:

(get_frame_size () == 0           \
   ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0)     \
   : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx,   \
               STARTING_FRAME_OFFSET)))

Definition at line 1344 of file sparc.h.

#define SECONDARY_OUTPUT_RELOAD_CLASS ( CLASS,
MODE,
IN   ) 

Value:

((FP_REG_CLASS_P (CLASS)          \
     && ((MODE) == HImode || (MODE) == QImode)      \
     && (GET_CODE (IN) == MEM         \
         || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG)  \
             && true_regnum (IN) == -1)))     \
   ? GENERAL_REGS           \
   : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode    \
      && GET_CODE (IN) == MEM && TARGET_ARCH32      \
      && ! mem_min_alignment ((IN), 8))       \
     ? FP_REGS              \
     : (((TARGET_CM_MEDANY          \
    && symbolic_operand ((IN), (MODE)))     \
   || (TARGET_CM_EMBMEDANY        \
       && text_segment_operand ((IN), (MODE))))   \
  && !flag_pic)           \
       ? GENERAL_REGS           \
       : NO_REGS)

Definition at line 1316 of file sparc.h.

#define SELECT_CC_MODE ( OP,
X,
Y   )     select_cc_mode ((OP), (X), (Y))

Definition at line 2109 of file sparc.h.

#define SETJMP_VIA_SAVE_AREA

Definition at line 2127 of file sparc.h.

 
#define SETUP_FRAME_ADDRESSES (  )     emit_insn (gen_flush_register_windows ())

Definition at line 1695 of file sparc.h.

#define SHIFT_COUNT_TRUNCATED   1

Definition at line 2095 of file sparc.h.

#define SHORT_TYPE_SIZE   16

Definition at line 602 of file sparc.h.

#define SIMULTANEOUS_PREFETCHES

Value:

((sparc_cpu == PROCESSOR_ULTRASPARC \
    || sparc_cpu == PROCESSOR_NIAGARA) \
         ? 2 \
         : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
            ? 8 : 3))

Definition at line 2184 of file sparc.h.

#define SIZE_TYPE   (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")

Definition at line 483 of file sparc.h.

#define SLOW_BYTE_ACCESS   1

Definition at line 2091 of file sparc.h.

#define SMALL_INT ( X   )     (SPARC_SIMM13_P (INTVAL (X)))

Definition at line 1222 of file sparc.h.

#define sparc_cpu_attr   ((enum attr_cpu) sparc_cpu)

Definition at line 544 of file sparc.h.

#define SPARC_DEFAULT_CMODEL   CM_32

Definition at line 203 of file sparc.h.

#define SPARC_FCC_REG   96

Definition at line 728 of file sparc.h.

#define SPARC_FIRST_FP_REG   32

Definition at line 720 of file sparc.h.

#define SPARC_FIRST_V9_FCC_REG   96

Definition at line 725 of file sparc.h.

#define SPARC_FIRST_V9_FP_REG   64

Definition at line 722 of file sparc.h.

#define SPARC_FP_ARG_FIRST   32

Definition at line 739 of file sparc.h.

#define SPARC_FP_REG_P ( REGNO   )     ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)

Definition at line 733 of file sparc.h.

#define SPARC_ICC_REG   100

Definition at line 730 of file sparc.h.

#define SPARC_INCOMING_INT_ARG_FIRST   24

Definition at line 738 of file sparc.h.

#define SPARC_LAST_V9_FCC_REG   99

Definition at line 726 of file sparc.h.

#define SPARC_LAST_V9_FP_REG   95

Definition at line 723 of file sparc.h.

#define SPARC_OUTGOING_INT_ARG_FIRST   8

Definition at line 737 of file sparc.h.

#define SPARC_RELAXED_ORDERING   false

Definition at line 213 of file sparc.h.

#define SPARC_SETHI32_P ( X   )     (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))

Definition at line 1238 of file sparc.h.

#define SPARC_SETHI_P ( X   ) 

Value:

(((unsigned HOST_WIDE_INT) (X) \
    & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)

Definition at line 1233 of file sparc.h.

#define SPARC_SIMM10_P ( X   )     ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)

Definition at line 1216 of file sparc.h.

#define SPARC_SIMM11_P ( X   )     ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)

Definition at line 1217 of file sparc.h.

#define SPARC_SIMM13_P ( X   )     ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)

Definition at line 1218 of file sparc.h.

#define SPARC_STACK_ALIGN ( LOC   )     (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))

Definition at line 643 of file sparc.h.

#define SPARC_STACK_BIAS   ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)

Definition at line 923 of file sparc.h.

#define SPARC_STACK_BOUNDARY_HACK   (TARGET_ARCH64 && TARGET_STACK_BIAS)

Definition at line 639 of file sparc.h.

#define SPARC_SYMBOL_REF_TLS_P ( RTX   )     (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)

Definition at line 2377 of file sparc.h.

Referenced by legitimate_address_p(), legitimate_constant_p(), legitimate_pic_operand_p(), legitimize_address(), sparc_expand_move(), and sparc_tls_symbol_ref_1().

#define STACK_BOUNDARY   (TARGET_ARCH64 ? 128 : 64)

Definition at line 637 of file sparc.h.

#define STACK_GROWS_DOWNWARD

Definition at line 1373 of file sparc.h.

#define STACK_POINTER_OFFSET   (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)

Definition at line 931 of file sparc.h.

#define STACK_POINTER_REGNUM   14

Definition at line 920 of file sparc.h.

#define STARTING_FRAME_OFFSET

Value:

(TARGET_ARCH64 ? -16 \
   : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))

Definition at line 1387 of file sparc.h.

#define STATIC_CHAIN_REGNUM   (TARGET_ARCH64 ? 5 : 2)

Definition at line 961 of file sparc.h.

#define STRICT_ALIGNMENT   1

Definition at line 695 of file sparc.h.

#define STRUCT_VALUE_OFFSET   64

Definition at line 979 of file sparc.h.

#define STRUCTURE_SIZE_BOUNDARY   8

Definition at line 653 of file sparc.h.

#define SUBTARGET_EXTRA_SPECS

Definition at line 475 of file sparc.h.

#define SUN_CONVERSION_LIBFUNCS   0

Definition at line 2140 of file sparc.h.

#define SUN_INTEGER_MULTIPLY_64   0

Definition at line 2142 of file sparc.h.

#define SYMBOLIC_CONST ( X   )     symbolic_operand (X, VOIDmode)

Definition at line 1935 of file sparc.h.

#define TARGET_ARCH32   (DEFAULT_ARCH32_P)

Definition at line 145 of file sparc.h.

#define TARGET_ARCH64   (! TARGET_ARCH32)

Definition at line 148 of file sparc.h.

#define TARGET_BUGGY_QP_LIB   0

Definition at line 2135 of file sparc.h.

#define TARGET_CM_EMBMEDANY   (sparc_cmodel == CM_EMBMEDANY)

Definition at line 201 of file sparc.h.

#define TARGET_CM_MEDANY   (sparc_cmodel == CM_MEDANY)

Definition at line 200 of file sparc.h.

#define TARGET_CM_MEDLOW   (sparc_cmodel == CM_MEDLOW)

Definition at line 198 of file sparc.h.

#define TARGET_CM_MEDMID   (sparc_cmodel == CM_MEDMID)

Definition at line 199 of file sparc.h.

 
#define TARGET_CPU_CPP_BUILTINS (  ) 

Value:

do            \
    {           \
  builtin_define_std ("sparc");   \
  if (TARGET_64BIT)     \
    {           \
      builtin_assert ("cpu=sparc64"); \
      builtin_assert ("machine=sparc64"); \
    }         \
  else          \
    {           \
      builtin_assert ("cpu=sparc"); \
      builtin_assert ("machine=sparc"); \
    }         \
    }           \
  while (0)

Definition at line 109 of file sparc.h.

#define TARGET_CPU_hypersparc   5

Definition at line 233 of file sparc.h.

#define TARGET_CPU_niagara   10

Definition at line 241 of file sparc.h.

Referenced by sparc_override_options().

#define TARGET_CPU_sparc   0

Definition at line 227 of file sparc.h.

#define TARGET_CPU_sparc64   7

Definition at line 238 of file sparc.h.

#define TARGET_CPU_sparc86x   6

Definition at line 234 of file sparc.h.

#define TARGET_CPU_sparclet   1

Definition at line 229 of file sparc.h.

#define TARGET_CPU_sparclite   2

Definition at line 230 of file sparc.h.

#define TARGET_CPU_sparclite86x   6

Definition at line 235 of file sparc.h.

#define TARGET_CPU_sparcv9   7

Definition at line 237 of file sparc.h.

#define TARGET_CPU_supersparc   4

Definition at line 232 of file sparc.h.

#define TARGET_CPU_ultrasparc   8

Definition at line 239 of file sparc.h.

#define TARGET_CPU_ultrasparc3   9

Definition at line 240 of file sparc.h.

#define TARGET_CPU_v7   0

Definition at line 228 of file sparc.h.

#define TARGET_CPU_v8   3

Definition at line 231 of file sparc.h.

#define TARGET_CPU_v9   7

Definition at line 236 of file sparc.h.

#define TARGET_DEFAULT   (MASK_APP_REGS + MASK_FPU)

Definition at line 517 of file sparc.h.

#define TARGET_GNU_TLS   0

Definition at line 2477 of file sparc.h.

#define TARGET_HARD_MUL

Value:

(TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
   || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)

Definition at line 510 of file sparc.h.

#define TARGET_HARD_MUL32

Value:

((TARGET_V8 || TARGET_SPARCLITE     \
    || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
   && ! TARGET_V8PLUS && TARGET_ARCH32)

Definition at line 505 of file sparc.h.

#define TARGET_SUN_TLS   TARGET_TLS

Definition at line 2476 of file sparc.h.

#define TARGET_TLS   0

Definition at line 2473 of file sparc.h.

#define TRAMPOLINE_ALIGNMENT   128

Definition at line 1677 of file sparc.h.

#define TRAMPOLINE_SIZE   (TARGET_ARCH64 ? 32 : 16)

Definition at line 1675 of file sparc.h.

#define TRULY_NOOP_TRUNCATION ( OUTPREC,
INPREC   )     1

Definition at line 2099 of file sparc.h.

#define UNITS_PER_SIMD_WORD   (TARGET_VIS ? 8 : UNITS_PER_WORD)

Definition at line 598 of file sparc.h.

#define UNITS_PER_WORD   (TARGET_ARCH64 ? 8 : 4)

Definition at line 591 of file sparc.h.

#define USE_AS_OFFSETABLE_LO10   0

Definition at line 1922 of file sparc.h.

#define USER_LABEL_PREFIX   "_"

Definition at line 2248 of file sparc.h.

#define WCHAR_TYPE   "short unsigned int"

Definition at line 486 of file sparc.h.

#define WCHAR_TYPE_SIZE   16

Definition at line 487 of file sparc.h.

#define WORD_REGISTER_OPERATIONS

Definition at line 2079 of file sparc.h.

#define WORDS_BIG_ENDIAN   1

Definition at line 578 of file sparc.h.

Enumeration Type Documentation

enum cmodel

Enumerator:
CM_32 
CM_SMALL 
CM_KERNEL 
CM_MEDIUM 
CM_LARGE 
CM_SMALL_PIC 
CM_32 
CM_MEDLOW 
CM_MEDMID 
CM_MEDANY 
CM_EMBMEDANY 
CM_32 
CM_SMALL 
CM_KERNEL 
CM_MEDIUM 
CM_LARGE 
CM_SMALL_PIC 
CM_32 
CM_MEDLOW 
CM_MEDMID 
CM_MEDANY 
CM_EMBMEDANY 
CM_32 
CM_SMALL 
CM_KERNEL 
CM_MEDIUM 
CM_LARGE 
CM_SMALL_PIC 
CM_32 
CM_MEDLOW 
CM_MEDMID 
CM_MEDANY 
CM_EMBMEDANY 
CM_32 
CM_SMALL 
CM_KERNEL 
CM_MEDIUM 
CM_LARGE 
CM_SMALL_PIC 
CM_MEDIUM_PIC 
CM_32 
CM_MEDLOW 
CM_MEDMID 
CM_MEDANY 
CM_EMBMEDANY 

Definition at line 186 of file sparc.h.

enum processor_type

Enumerator:
PROCESSOR_EV4 
PROCESSOR_EV5 
PROCESSOR_EV6 
PROCESSOR_I386 
PROCESSOR_I486 
PROCESSOR_PENTIUM 
PROCESSOR_PENTIUMPRO 
PROCESSOR_K6 
PROCESSOR_ATHLON 
PROCESSOR_PENTIUM4 
PROCESSOR_max 
PROCESSOR_M88100 
PROCESSOR_M88110 
PROCESSOR_M88000 
PROCESSOR_700 
PROCESSOR_7100 
PROCESSOR_7100LC 
PROCESSOR_7200 
PROCESSOR_8000 
PROCESSOR_RIOS1 
PROCESSOR_RIOS2 
PROCESSOR_RS64A 
PROCESSOR_MPCCORE 
PROCESSOR_PPC403 
PROCESSOR_PPC405 
PROCESSOR_PPC601 
PROCESSOR_PPC603 
PROCESSOR_PPC604 
PROCESSOR_PPC604e 
PROCESSOR_PPC620 
PROCESSOR_PPC630 
PROCESSOR_PPC750 
PROCESSOR_PPC7400 
PROCESSOR_PPC7450 
PROCESSOR_SH1 
PROCESSOR_SH2 
PROCESSOR_SH3 
PROCESSOR_SH3E 
PROCESSOR_SH4 
PROCESSOR_SH5 
PROCESSOR_DEFAULT 
PROCESSOR_R3000 
PROCESSOR_R3900 
PROCESSOR_R6000 
PROCESSOR_R4000 
PROCESSOR_R4100 
PROCESSOR_R4111 
PROCESSOR_R4120 
PROCESSOR_R4300 
PROCESSOR_R4600 
PROCESSOR_R4650 
PROCESSOR_R5000 
PROCESSOR_R5400 
PROCESSOR_R5500 
PROCESSOR_R8000 
PROCESSOR_R4KC 
PROCESSOR_R5KC 
PROCESSOR_R20KC 
PROCESSOR_SR71000 
PROCESSOR_SB1 
PROCESSOR_V7 
PROCESSOR_CYPRESS 
PROCESSOR_V8 
PROCESSOR_SUPERSPARC 
PROCESSOR_SPARCLITE 
PROCESSOR_F930 
PROCESSOR_F934 
PROCESSOR_HYPERSPARC 
PROCESSOR_SPARCLITE86X 
PROCESSOR_SPARCLET 
PROCESSOR_TSC701 
PROCESSOR_V9 
PROCESSOR_ULTRASPARC 
PROCESSOR_DEFAULT 
PROCESSOR_R3000 
PROCESSOR_R3900 
PROCESSOR_R6000 
PROCESSOR_R4000 
PROCESSOR_R4100 
PROCESSOR_R4111 
PROCESSOR_R4120 
PROCESSOR_R4300 
PROCESSOR_R4600 
PROCESSOR_R4650 
PROCESSOR_R5000 
PROCESSOR_R5400 
PROCESSOR_R5500 
PROCESSOR_R8000 
PROCESSOR_R4KC 
PROCESSOR_R5KC 
PROCESSOR_R20KC 
PROCESSOR_SR71000 
PROCESSOR_SB1 
PROCESSOR_DEFAULT 
PROCESSOR_R3000 
PROCESSOR_R3900 
PROCESSOR_R6000 
PROCESSOR_R4000 
PROCESSOR_R4100 
PROCESSOR_R4111 
PROCESSOR_R4120 
PROCESSOR_R4300 
PROCESSOR_R4600 
PROCESSOR_R4650 
PROCESSOR_R5000 
PROCESSOR_R5400 
PROCESSOR_R5500 
PROCESSOR_R8000 
PROCESSOR_R4KC 
PROCESSOR_R5KC 
PROCESSOR_R20KC 
PROCESSOR_SR71000 
PROCESSOR_SB1 
PROCESSOR_EV4 
PROCESSOR_EV5 
PROCESSOR_EV6 
PROCESSOR_I386 
PROCESSOR_I486 
PROCESSOR_PENTIUM 
PROCESSOR_PENTIUMPRO 
PROCESSOR_K6 
PROCESSOR_ATHLON 
PROCESSOR_PENTIUM4 
PROCESSOR_max 
PROCESSOR_M88100 
PROCESSOR_M88110 
PROCESSOR_M88000 
PROCESSOR_700 
PROCESSOR_7100 
PROCESSOR_7100LC 
PROCESSOR_7200 
PROCESSOR_8000 
PROCESSOR_RIOS1 
PROCESSOR_RIOS2 
PROCESSOR_RS64A 
PROCESSOR_MPCCORE 
PROCESSOR_PPC403 
PROCESSOR_PPC405 
PROCESSOR_PPC601 
PROCESSOR_PPC603 
PROCESSOR_PPC604 
PROCESSOR_PPC604e 
PROCESSOR_PPC620 
PROCESSOR_PPC630 
PROCESSOR_PPC750 
PROCESSOR_PPC7400 
PROCESSOR_PPC7450 
PROCESSOR_SH1 
PROCESSOR_SH2 
PROCESSOR_SH3 
PROCESSOR_SH3E 
PROCESSOR_SH4 
PROCESSOR_SH5 
PROCESSOR_DEFAULT 
PROCESSOR_R3000 
PROCESSOR_R3900 
PROCESSOR_R6000 
PROCESSOR_R4000 
PROCESSOR_R4100 
PROCESSOR_R4111 
PROCESSOR_R4120 
PROCESSOR_R4300 
PROCESSOR_R4600 
PROCESSOR_R4650 
PROCESSOR_R5000 
PROCESSOR_R5400 
PROCESSOR_R5500 
PROCESSOR_R8000 
PROCESSOR_R4KC 
PROCESSOR_R5KC 
PROCESSOR_R20KC 
PROCESSOR_SR71000 
PROCESSOR_SB1 
PROCESSOR_V7 
PROCESSOR_CYPRESS 
PROCESSOR_V8 
PROCESSOR_SUPERSPARC 
PROCESSOR_SPARCLITE 
PROCESSOR_F930 
PROCESSOR_F934 
PROCESSOR_HYPERSPARC 
PROCESSOR_SPARCLITE86X 
PROCESSOR_SPARCLET 
PROCESSOR_TSC701 
PROCESSOR_V9 
PROCESSOR_ULTRASPARC 
PROCESSOR_DEFAULT 
PROCESSOR_R3000 
PROCESSOR_R3900 
PROCESSOR_R6000 
PROCESSOR_R4000 
PROCESSOR_R4100 
PROCESSOR_R4111 
PROCESSOR_R4120 
PROCESSOR_R4300 
PROCESSOR_R4600 
PROCESSOR_R4650 
PROCESSOR_R5000 
PROCESSOR_R5400 
PROCESSOR_R5500 
PROCESSOR_R8000 
PROCESSOR_R4KC 
PROCESSOR_R5KC 
PROCESSOR_R20KC 
PROCESSOR_SR71000 
PROCESSOR_SB1 
PROCESSOR_DEFAULT 
PROCESSOR_R3000 
PROCESSOR_R3900 
PROCESSOR_R6000 
PROCESSOR_R4000 
PROCESSOR_R4100 
PROCESSOR_R4111 
PROCESSOR_R4120 
PROCESSOR_R4300 
PROCESSOR_R4600 
PROCESSOR_R4650 
PROCESSOR_R5000 
PROCESSOR_R5400 
PROCESSOR_R5500 
PROCESSOR_R8000 
PROCESSOR_R4KC 
PROCESSOR_R5KC 
PROCESSOR_R20KC 
PROCESSOR_SR71000 
PROCESSOR_SB1 
PROCESSOR_EV4 
PROCESSOR_EV5 
PROCESSOR_EV6 
PROCESSOR_MAX 
ARM_CORE 
PROCESSOR_I386 
PROCESSOR_I486 
PROCESSOR_PENTIUM 
PROCESSOR_PENTIUMPRO 
PROCESSOR_K6 
PROCESSOR_ATHLON 
PROCESSOR_PENTIUM4 
PROCESSOR_K8 
PROCESSOR_NOCONA 
PROCESSOR_max 
PROCESSOR_ITANIUM 
PROCESSOR_ITANIUM2 
PROCESSOR_max 
PROCESSOR_DEFAULT 
PROCESSOR_IQ2000 
PROCESSOR_IQ10 
PROCESSOR_DEFAULT 
PROCESSOR_4KC 
PROCESSOR_5KC 
PROCESSOR_20KC 
PROCESSOR_M4K 
PROCESSOR_R3000 
PROCESSOR_R3900 
PROCESSOR_R6000 
PROCESSOR_R4000 
PROCESSOR_R4100 
PROCESSOR_R4111 
PROCESSOR_R4120 
PROCESSOR_R4130 
PROCESSOR_R4300 
PROCESSOR_R4600 
PROCESSOR_R4650 
PROCESSOR_R5000 
PROCESSOR_R5400 
PROCESSOR_R5500 
PROCESSOR_R7000 
PROCESSOR_R8000 
PROCESSOR_R9000 
PROCESSOR_SB1 
PROCESSOR_SR71000 
PROCESSOR_700 
PROCESSOR_7100 
PROCESSOR_7100LC 
PROCESSOR_7200 
PROCESSOR_7300 
PROCESSOR_8000 
PROCESSOR_RIOS1 
PROCESSOR_RIOS2 
PROCESSOR_RS64A 
PROCESSOR_MPCCORE 
PROCESSOR_PPC403 
PROCESSOR_PPC405 
PROCESSOR_PPC440 
PROCESSOR_PPC601 
PROCESSOR_PPC603 
PROCESSOR_PPC604 
PROCESSOR_PPC604e 
PROCESSOR_PPC620 
PROCESSOR_PPC630 
PROCESSOR_PPC750 
PROCESSOR_PPC7400 
PROCESSOR_PPC7450 
PROCESSOR_PPC8540 
PROCESSOR_POWER4 
PROCESSOR_POWER5 
PROCESSOR_9672_G5 
PROCESSOR_9672_G6 
PROCESSOR_2064_Z900 
PROCESSOR_2084_Z990 
PROCESSOR_max 
PROCESSOR_SH1 
PROCESSOR_SH2 
PROCESSOR_SH2E 
PROCESSOR_SH2A 
PROCESSOR_SH3 
PROCESSOR_SH3E 
PROCESSOR_SH4 
PROCESSOR_SH4A 
PROCESSOR_SH5 
PROCESSOR_V7 
PROCESSOR_CYPRESS 
PROCESSOR_V8 
PROCESSOR_SUPERSPARC 
PROCESSOR_SPARCLITE 
PROCESSOR_F930 
PROCESSOR_F934 
PROCESSOR_HYPERSPARC 
PROCESSOR_SPARCLITE86X 
PROCESSOR_SPARCLET 
PROCESSOR_TSC701 
PROCESSOR_V9 
PROCESSOR_ULTRASPARC 
PROCESSOR_ULTRASPARC3 
PROCESSOR_EV4 
PROCESSOR_EV5 
PROCESSOR_EV6 
PROCESSOR_MAX 
ARM_CORE 
PROCESSOR_I386 
PROCESSOR_I486 
PROCESSOR_PENTIUM 
PROCESSOR_PENTIUMPRO 
PROCESSOR_K6 
PROCESSOR_ATHLON 
PROCESSOR_PENTIUM4 
PROCESSOR_K8 
PROCESSOR_NOCONA 
PROCESSOR_GENERIC32 
PROCESSOR_GENERIC64 
PROCESSOR_AMDFAM10 
PROCESSOR_max 
PROCESSOR_ITANIUM 
PROCESSOR_ITANIUM2 
PROCESSOR_max 
PROCESSOR_DEFAULT 
PROCESSOR_IQ2000 
PROCESSOR_IQ10 
PROCESSOR_R3000 
PROCESSOR_4KC 
PROCESSOR_4KP 
PROCESSOR_5KC 
PROCESSOR_5KF 
PROCESSOR_20KC 
PROCESSOR_24K 
PROCESSOR_24KX 
PROCESSOR_M4K 
PROCESSOR_R3900 
PROCESSOR_R6000 
PROCESSOR_R4000 
PROCESSOR_R4100 
PROCESSOR_R4111 
PROCESSOR_R4120 
PROCESSOR_R4130 
PROCESSOR_R4300 
PROCESSOR_R4600 
PROCESSOR_R4650 
PROCESSOR_R5000 
PROCESSOR_R5400 
PROCESSOR_R5500 
PROCESSOR_R7000 
PROCESSOR_R8000 
PROCESSOR_R9000 
PROCESSOR_SB1 
PROCESSOR_SB1A 
PROCESSOR_SR71000 
PROCESSOR_MAX 
PROCESSOR_MN10300 
PROCESSOR_AM33 
PROCESSOR_AM33_2 
PROCESSOR_MS1_64_001 
PROCESSOR_MS1_16_002 
PROCESSOR_MS1_16_003 
PROCESSOR_MS2 
PROCESSOR_700 
PROCESSOR_7100 
PROCESSOR_7100LC 
PROCESSOR_7200 
PROCESSOR_7300 
PROCESSOR_8000 
PROCESSOR_RIOS1 
PROCESSOR_RIOS2 
PROCESSOR_RS64A 
PROCESSOR_MPCCORE 
PROCESSOR_PPC403 
PROCESSOR_PPC405 
PROCESSOR_PPC440 
PROCESSOR_PPC601 
PROCESSOR_PPC603 
PROCESSOR_PPC604 
PROCESSOR_PPC604e 
PROCESSOR_PPC620 
PROCESSOR_PPC630 
PROCESSOR_PPC750 
PROCESSOR_PPC7400 
PROCESSOR_PPC7450 
PROCESSOR_PPC8540 
PROCESSOR_POWER4 
PROCESSOR_POWER5 
PROCESSOR_9672_G5 
PROCESSOR_9672_G6 
PROCESSOR_2064_Z900 
PROCESSOR_2084_Z990 
PROCESSOR_2094_Z9_109 
PROCESSOR_max 
PROCESSOR_SH1 
PROCESSOR_SH2 
PROCESSOR_SH2E 
PROCESSOR_SH2A 
PROCESSOR_SH3 
PROCESSOR_SH3E 
PROCESSOR_SH4 
PROCESSOR_SH4A 
PROCESSOR_SH5 
PROCESSOR_V7 
PROCESSOR_CYPRESS 
PROCESSOR_V8 
PROCESSOR_SUPERSPARC 
PROCESSOR_SPARCLITE 
PROCESSOR_F930 
PROCESSOR_F934 
PROCESSOR_HYPERSPARC 
PROCESSOR_SPARCLITE86X 
PROCESSOR_SPARCLET 
PROCESSOR_TSC701 
PROCESSOR_V9 
PROCESSOR_ULTRASPARC 
PROCESSOR_ULTRASPARC3 
PROCESSOR_NIAGARA 

Definition at line 521 of file sparc.h.

enum reg_class

Enumerator:
NO_REGS 
R2 
R0_1 
INDEX_REGS 
BASE_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
LR0_REGS 
GENERAL_REGS 
BP_REGS 
FC_REGS 
CR_REGS 
Q_REGS 
SPECIAL_REGS 
ACCUM0_REGS 
ACCUM_REGS 
FLOAT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R24_REG 
R25_REG 
R27_REG 
GENERAL_REGS 
FLOAT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
LPCOUNT_REG 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
FPU_REGS 
LO_REGS 
STACK_REG 
BASE_REGS 
HI_REGS 
CC_REG 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REG 
POINTER_X_REGS 
POINTER_Y_REGS 
POINTER_Z_REGS 
STACK_REG 
BASE_POINTER_REGS 
POINTER_REGS 
ADDW_REGS 
SIMPLE_LD_REGS 
LD_REGS 
NO_LD_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0R1_REGS 
R2R3_REGS 
EXT_LOW_REGS 
EXT_REGS 
ADDR_REGS 
INDEX_REGS 
BK_REG 
SP_REG 
RC_REG 
COUNTER_REGS 
INT_REGS 
GENERAL_REGS 
DP_REG 
ST_REG 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
FLOAT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
S_REGS 
INDEX_REGS 
SP_REGS 
A_REGS 
SI_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
REPEAT_REGS 
CR_REGS 
ACCUM_REGS 
OTHER_FLAG_REGS 
F0_REGS 
F1_REGS 
BR_FLAG_REGS 
FLAG_REGS 
EVEN_REGS 
GPR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
A0H_REG 
A0L_REG 
A0_REG 
A1H_REG 
ACCUM_HIGH_REGS 
A1L_REG 
ACCUM_LOW_REGS 
A1_REG 
ACCUM_REGS 
X_REG 
X_OR_ACCUM_LOW_REGS 
X_OR_ACCUM_REGS 
YH_REG 
YH_OR_ACCUM_HIGH_REGS 
X_OR_YH_REGS 
YL_REG 
YL_OR_ACCUM_LOW_REGS 
X_OR_YL_REGS 
X_OR_Y_REGS 
Y_REG 
ACCUM_OR_Y_REGS 
PH_REG 
X_OR_PH_REGS 
PL_REG 
PL_OR_ACCUM_LOW_REGS 
X_OR_PL_REGS 
YL_OR_PL_OR_ACCUM_LOW_REGS 
P_REG 
ACCUM_OR_P_REGS 
YL_OR_P_REGS 
ACCUM_LOW_OR_YL_OR_P_REGS 
Y_OR_P_REGS 
ACCUM_Y_OR_P_REGS 
NO_FRAME_Y_ADDR_REGS 
Y_ADDR_REGS 
ACCUM_LOW_OR_Y_ADDR_REGS 
ACCUM_OR_Y_ADDR_REGS 
X_OR_Y_ADDR_REGS 
Y_OR_Y_ADDR_REGS 
P_OR_Y_ADDR_REGS 
NON_HIGH_YBASE_ELIGIBLE_REGS 
YBASE_ELIGIBLE_REGS 
J_REG 
J_OR_DAU_16_BIT_REGS 
BMU_REGS 
NOHIGH_NON_ADDR_REGS 
NON_ADDR_REGS 
SLOW_MEM_LOAD_REGS 
NOHIGH_NON_YBASE_REGS 
NO_ACCUM_NON_YBASE_REGS 
NON_YBASE_REGS 
YBASE_VIRT_REGS 
ACCUM_LOW_OR_YBASE_REGS 
ACCUM_OR_YBASE_REGS 
X_OR_YBASE_REGS 
Y_OR_YBASE_REGS 
ACCUM_LOW_YL_PL_OR_YBASE_REGS 
P_OR_YBASE_REGS 
ACCUM_Y_P_OR_YBASE_REGS 
Y_ADDR_OR_YBASE_REGS 
YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS 
YBASE_OR_YBASE_ELIGIBLE_REGS 
NO_HIGH_ALL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MULTIPLY_32_REG 
MULTIPLY_64_REG 
LOW_REGS 
HIGH_REGS 
REAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
MAC_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ADDR_REGS 
DATA_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
AREG 
DREG 
CREG 
BREG 
SIREG 
DIREG 
AD_REGS 
Q_REGS 
NON_Q_REGS 
INDEX_REGS 
LEGACY_REGS 
GENERAL_REGS 
FP_TOP_REG 
FP_SECOND_REG 
FLOAT_REGS 
SSE_REGS 
MMX_REGS 
FP_TOP_SSE_REGS 
FP_SECOND_SSE_REGS 
FLOAT_SSE_REGS 
FLOAT_INT_REGS 
INT_SSE_REGS 
FLOAT_INT_SSE_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GLOBAL_REGS 
LOCAL_REGS 
LOCAL_OR_GLOBAL_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
PR_REGS 
BR_REGS 
AR_M_REGS 
AR_I_REGS 
ADDL_REGS 
GR_REGS 
FR_REGS 
GR_AND_BR_REGS 
GR_AND_FR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
CARRY_REG 
ACCUM_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
D_REGS 
X_REGS 
Y_REGS 
SP_REGS 
DA_REGS 
DB_REGS 
Z_REGS 
D8_REGS 
Q_REGS 
D_OR_X_REGS 
D_OR_Y_REGS 
D_OR_SP_REGS 
X_OR_Y_REGS 
A_REGS 
X_OR_SP_REGS 
Y_OR_SP_REGS 
X_OR_Y_OR_D_REGS 
A_OR_D_REGS 
A_OR_SP_REGS 
H_REGS 
S_REGS 
D_OR_S_REGS 
X_OR_S_REGS 
Y_OR_S_REGS 
SP_OR_S_REGS 
D_OR_X_OR_S_REGS 
D_OR_Y_OR_S_REGS 
D_OR_SP_OR_S_REGS 
A_OR_S_REGS 
D_OR_A_OR_S_REGS 
TMP_REGS 
D_OR_A_OR_TMP_REGS 
G_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDR_REGS 
FP_REGS 
GENERAL_REGS 
DATA_OR_FP_REGS 
ADDR_OR_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
AP_REG 
XRF_REGS 
GENERAL_REGS 
AGRF_REGS 
XGRF_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ONLYR1_REGS 
LRW_REGS 
GENERAL_REGS 
C_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
REMAINDER_REG 
HIMULT_REG 
SYSTEM_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDRESS_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDRESS_REGS 
SP_REGS 
DATA_OR_ADDRESS_REGS 
SP_OR_ADDRESS_REGS 
EXTENDED_REGS 
DATA_OR_EXTENDED_REGS 
ADDRESS_OR_EXTENDED_REGS 
SP_OR_EXTENDED_REGS 
SP_OR_ADDRESS_OR_EXTENDED_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
FLOAT_REG0 
LONG_FLOAT_REG0 
FLOAT_REGS 
FP_REGS 
GEN_AND_FP_REGS 
FRAME_POINTER_REG 
STACK_POINTER_REG 
GEN_AND_MEM_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R1_REGS 
GENERAL_REGS 
FPUPPER_REGS 
FP_REGS 
GENERAL_OR_FP_REGS 
SHIFT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R1_REGS 
GENERAL_REGS 
FPUPPER_REGS 
FP_REGS 
GENERAL_OR_FP_REGS 
SHIFT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MUL_REGS 
GENERAL_REGS 
LOAD_FPU_REGS 
NO_LOAD_FPU_REGS 
FPU_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
OUT_REGS 
STD_REGS 
ARG_REGS 
SRC_REGS 
DST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
R15_REGS 
BASE_REGS 
GENERAL_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
BASE_REGS 
GENERAL_REGS 
FLOAT_REGS 
ALTIVEC_REGS 
VRSAVE_REGS 
NON_SPECIAL_REGS 
MQ_REGS 
LINK_REGS 
CTR_REGS 
LINK_OR_CTR_REGS 
SPECIAL_REGS 
SPEC_OR_GEN_REGS 
CR0_REGS 
CR_REGS 
NON_FLOAT_REGS 
XER_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ADDR_REGS 
GENERAL_REGS 
FP_REGS 
ADDR_FP_REGS 
GENERAL_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
PR_REGS 
T_REGS 
MAC_REGS 
FPUL_REGS 
SIBCALL_REGS 
GENERAL_REGS 
FP0_REGS 
FP_REGS 
DF_REGS 
FPSCR_REGS 
GENERAL_FP_REGS 
TARGET_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
M16_NA_REGS 
M16_REGS 
T_REG 
M16_T_REGS 
GR_REGS 
FP_REGS 
HI_REG 
LO_REG 
HILO_REG 
MD_REGS 
COP0_REGS 
COP2_REGS 
COP3_REGS 
HI_AND_GR_REGS 
LO_AND_GR_REGS 
HILO_AND_GR_REGS 
HI_AND_FP_REGS 
COP0_AND_GR_REGS 
COP2_AND_GR_REGS 
COP3_AND_GR_REGS 
ALL_COP_REGS 
ALL_COP_AND_GR_REGS 
ST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
FPCC_REGS 
I64_REGS 
GENERAL_REGS 
FP_REGS 
EXTRA_FP_REGS 
GENERAL_OR_FP_REGS 
GENERAL_OR_EXTRA_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
R1_REGS 
TWO_REGS 
R2_REGS 
EIGHT_REGS 
R8_REGS 
ICALL_REGS 
GENERAL_REGS 
CARRY_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
BR_REGS 
FP_REGS 
ACC_REG 
SP_REG 
RL_REGS 
GR_REGS 
AR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
M16_NA_REGS 
M16_REGS 
T_REG 
M16_T_REGS 
GR_REGS 
FP_REGS 
HI_REG 
LO_REG 
HILO_REG 
MD_REGS 
COP0_REGS 
COP2_REGS 
COP3_REGS 
HI_AND_GR_REGS 
LO_AND_GR_REGS 
HILO_AND_GR_REGS 
HI_AND_FP_REGS 
COP0_AND_GR_REGS 
COP2_AND_GR_REGS 
COP3_AND_GR_REGS 
ALL_COP_REGS 
ALL_COP_AND_GR_REGS 
ST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
M16_NA_REGS 
M16_REGS 
T_REG 
M16_T_REGS 
GR_REGS 
FP_REGS 
HI_REG 
LO_REG 
HILO_REG 
MD_REGS 
COP0_REGS 
COP2_REGS 
COP3_REGS 
HI_AND_GR_REGS 
LO_AND_GR_REGS 
HILO_AND_GR_REGS 
HI_AND_FP_REGS 
COP0_AND_GR_REGS 
COP2_AND_GR_REGS 
COP3_AND_GR_REGS 
ALL_COP_REGS 
ALL_COP_AND_GR_REGS 
ST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R2 
R0_1 
INDEX_REGS 
BASE_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
LR0_REGS 
GENERAL_REGS 
BP_REGS 
FC_REGS 
CR_REGS 
Q_REGS 
SPECIAL_REGS 
ACCUM0_REGS 
ACCUM_REGS 
FLOAT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R24_REG 
R25_REG 
R27_REG 
GENERAL_REGS 
FLOAT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
LPCOUNT_REG 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
FPU_REGS 
LO_REGS 
STACK_REG 
BASE_REGS 
HI_REGS 
CC_REG 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REG 
POINTER_X_REGS 
POINTER_Y_REGS 
POINTER_Z_REGS 
STACK_REG 
BASE_POINTER_REGS 
POINTER_REGS 
ADDW_REGS 
SIMPLE_LD_REGS 
LD_REGS 
NO_LD_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0R1_REGS 
R2R3_REGS 
EXT_LOW_REGS 
EXT_REGS 
ADDR_REGS 
INDEX_REGS 
BK_REG 
SP_REG 
RC_REG 
COUNTER_REGS 
INT_REGS 
GENERAL_REGS 
DP_REG 
ST_REG 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
FLOAT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
S_REGS 
INDEX_REGS 
SP_REGS 
A_REGS 
SI_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
REPEAT_REGS 
CR_REGS 
ACCUM_REGS 
OTHER_FLAG_REGS 
F0_REGS 
F1_REGS 
BR_FLAG_REGS 
FLAG_REGS 
EVEN_REGS 
GPR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
A0H_REG 
A0L_REG 
A0_REG 
A1H_REG 
ACCUM_HIGH_REGS 
A1L_REG 
ACCUM_LOW_REGS 
A1_REG 
ACCUM_REGS 
X_REG 
X_OR_ACCUM_LOW_REGS 
X_OR_ACCUM_REGS 
YH_REG 
YH_OR_ACCUM_HIGH_REGS 
X_OR_YH_REGS 
YL_REG 
YL_OR_ACCUM_LOW_REGS 
X_OR_YL_REGS 
X_OR_Y_REGS 
Y_REG 
ACCUM_OR_Y_REGS 
PH_REG 
X_OR_PH_REGS 
PL_REG 
PL_OR_ACCUM_LOW_REGS 
X_OR_PL_REGS 
YL_OR_PL_OR_ACCUM_LOW_REGS 
P_REG 
ACCUM_OR_P_REGS 
YL_OR_P_REGS 
ACCUM_LOW_OR_YL_OR_P_REGS 
Y_OR_P_REGS 
ACCUM_Y_OR_P_REGS 
NO_FRAME_Y_ADDR_REGS 
Y_ADDR_REGS 
ACCUM_LOW_OR_Y_ADDR_REGS 
ACCUM_OR_Y_ADDR_REGS 
X_OR_Y_ADDR_REGS 
Y_OR_Y_ADDR_REGS 
P_OR_Y_ADDR_REGS 
NON_HIGH_YBASE_ELIGIBLE_REGS 
YBASE_ELIGIBLE_REGS 
J_REG 
J_OR_DAU_16_BIT_REGS 
BMU_REGS 
NOHIGH_NON_ADDR_REGS 
NON_ADDR_REGS 
SLOW_MEM_LOAD_REGS 
NOHIGH_NON_YBASE_REGS 
NO_ACCUM_NON_YBASE_REGS 
NON_YBASE_REGS 
YBASE_VIRT_REGS 
ACCUM_LOW_OR_YBASE_REGS 
ACCUM_OR_YBASE_REGS 
X_OR_YBASE_REGS 
Y_OR_YBASE_REGS 
ACCUM_LOW_YL_PL_OR_YBASE_REGS 
P_OR_YBASE_REGS 
ACCUM_Y_P_OR_YBASE_REGS 
Y_ADDR_OR_YBASE_REGS 
YBASE_OR_NOHIGH_YBASE_ELIGIBLE_REGS 
YBASE_OR_YBASE_ELIGIBLE_REGS 
NO_HIGH_ALL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MULTIPLY_32_REG 
MULTIPLY_64_REG 
LOW_REGS 
HIGH_REGS 
REAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
MAC_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ADDR_REGS 
DATA_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
AREG 
DREG 
CREG 
BREG 
SIREG 
DIREG 
AD_REGS 
Q_REGS 
NON_Q_REGS 
INDEX_REGS 
LEGACY_REGS 
GENERAL_REGS 
FP_TOP_REG 
FP_SECOND_REG 
FLOAT_REGS 
SSE_REGS 
MMX_REGS 
FP_TOP_SSE_REGS 
FP_SECOND_SSE_REGS 
FLOAT_SSE_REGS 
FLOAT_INT_REGS 
INT_SSE_REGS 
FLOAT_INT_SSE_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GLOBAL_REGS 
LOCAL_REGS 
LOCAL_OR_GLOBAL_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
PR_REGS 
BR_REGS 
AR_M_REGS 
AR_I_REGS 
ADDL_REGS 
GR_REGS 
FR_REGS 
GR_AND_BR_REGS 
GR_AND_FR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
CARRY_REG 
ACCUM_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
D_REGS 
X_REGS 
Y_REGS 
SP_REGS 
DA_REGS 
DB_REGS 
Z_REGS 
D8_REGS 
Q_REGS 
D_OR_X_REGS 
D_OR_Y_REGS 
D_OR_SP_REGS 
X_OR_Y_REGS 
A_REGS 
X_OR_SP_REGS 
Y_OR_SP_REGS 
X_OR_Y_OR_D_REGS 
A_OR_D_REGS 
A_OR_SP_REGS 
H_REGS 
S_REGS 
D_OR_S_REGS 
X_OR_S_REGS 
Y_OR_S_REGS 
SP_OR_S_REGS 
D_OR_X_OR_S_REGS 
D_OR_Y_OR_S_REGS 
D_OR_SP_OR_S_REGS 
A_OR_S_REGS 
D_OR_A_OR_S_REGS 
TMP_REGS 
D_OR_A_OR_TMP_REGS 
G_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDR_REGS 
FP_REGS 
GENERAL_REGS 
DATA_OR_FP_REGS 
ADDR_OR_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
AP_REG 
XRF_REGS 
GENERAL_REGS 
AGRF_REGS 
XGRF_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ONLYR1_REGS 
LRW_REGS 
GENERAL_REGS 
C_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
REMAINDER_REG 
HIMULT_REG 
SYSTEM_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDRESS_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDRESS_REGS 
SP_REGS 
DATA_OR_ADDRESS_REGS 
SP_OR_ADDRESS_REGS 
EXTENDED_REGS 
DATA_OR_EXTENDED_REGS 
ADDRESS_OR_EXTENDED_REGS 
SP_OR_EXTENDED_REGS 
SP_OR_ADDRESS_OR_EXTENDED_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
FLOAT_REG0 
LONG_FLOAT_REG0 
FLOAT_REGS 
FP_REGS 
GEN_AND_FP_REGS 
FRAME_POINTER_REG 
STACK_POINTER_REG 
GEN_AND_MEM_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R1_REGS 
GENERAL_REGS 
FPUPPER_REGS 
FP_REGS 
GENERAL_OR_FP_REGS 
SHIFT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R1_REGS 
GENERAL_REGS 
FPUPPER_REGS 
FP_REGS 
GENERAL_OR_FP_REGS 
SHIFT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MUL_REGS 
GENERAL_REGS 
LOAD_FPU_REGS 
NO_LOAD_FPU_REGS 
FPU_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
OUT_REGS 
STD_REGS 
ARG_REGS 
SRC_REGS 
DST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
R15_REGS 
BASE_REGS 
GENERAL_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
BASE_REGS 
GENERAL_REGS 
FLOAT_REGS 
ALTIVEC_REGS 
VRSAVE_REGS 
NON_SPECIAL_REGS 
MQ_REGS 
LINK_REGS 
CTR_REGS 
LINK_OR_CTR_REGS 
SPECIAL_REGS 
SPEC_OR_GEN_REGS 
CR0_REGS 
CR_REGS 
NON_FLOAT_REGS 
XER_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ADDR_REGS 
GENERAL_REGS 
FP_REGS 
ADDR_FP_REGS 
GENERAL_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
PR_REGS 
T_REGS 
MAC_REGS 
FPUL_REGS 
SIBCALL_REGS 
GENERAL_REGS 
FP0_REGS 
FP_REGS 
DF_REGS 
FPSCR_REGS 
GENERAL_FP_REGS 
TARGET_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
M16_NA_REGS 
M16_REGS 
T_REG 
M16_T_REGS 
GR_REGS 
FP_REGS 
HI_REG 
LO_REG 
HILO_REG 
MD_REGS 
COP0_REGS 
COP2_REGS 
COP3_REGS 
HI_AND_GR_REGS 
LO_AND_GR_REGS 
HILO_AND_GR_REGS 
HI_AND_FP_REGS 
COP0_AND_GR_REGS 
COP2_AND_GR_REGS 
COP3_AND_GR_REGS 
ALL_COP_REGS 
ALL_COP_AND_GR_REGS 
ST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
FPCC_REGS 
I64_REGS 
GENERAL_REGS 
FP_REGS 
EXTRA_FP_REGS 
GENERAL_OR_FP_REGS 
GENERAL_OR_EXTRA_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
R1_REGS 
TWO_REGS 
R2_REGS 
EIGHT_REGS 
R8_REGS 
ICALL_REGS 
GENERAL_REGS 
CARRY_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
BR_REGS 
FP_REGS 
ACC_REG 
SP_REG 
RL_REGS 
GR_REGS 
AR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
M16_NA_REGS 
M16_REGS 
T_REG 
M16_T_REGS 
GR_REGS 
FP_REGS 
HI_REG 
LO_REG 
HILO_REG 
MD_REGS 
COP0_REGS 
COP2_REGS 
COP3_REGS 
HI_AND_GR_REGS 
LO_AND_GR_REGS 
HILO_AND_GR_REGS 
HI_AND_FP_REGS 
COP0_AND_GR_REGS 
COP2_AND_GR_REGS 
COP3_AND_GR_REGS 
ALL_COP_REGS 
ALL_COP_AND_GR_REGS 
ST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
M16_NA_REGS 
M16_REGS 
T_REG 
M16_T_REGS 
GR_REGS 
FP_REGS 
HI_REG 
LO_REG 
HILO_REG 
MD_REGS 
COP0_REGS 
COP2_REGS 
COP3_REGS 
HI_AND_GR_REGS 
LO_AND_GR_REGS 
HILO_AND_GR_REGS 
HI_AND_FP_REGS 
COP0_AND_GR_REGS 
COP2_AND_GR_REGS 
COP3_AND_GR_REGS 
ALL_COP_REGS 
ALL_COP_AND_GR_REGS 
ST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REG 
R24_REG 
R25_REG 
R27_REG 
GENERAL_REGS 
FLOAT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
LPCOUNT_REG 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
FPA_REGS 
CIRRUS_REGS 
VFP_REGS 
IWMMXT_GR_REGS 
IWMMXT_REGS 
LO_REGS 
STACK_REG 
BASE_REGS 
HI_REGS 
CC_REG 
VFPCC_REG 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REG 
POINTER_X_REGS 
POINTER_Y_REGS 
POINTER_Z_REGS 
STACK_REG 
BASE_POINTER_REGS 
POINTER_REGS 
ADDW_REGS 
SIMPLE_LD_REGS 
LD_REGS 
NO_LD_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
IREGS 
BREGS 
LREGS 
MREGS 
CIRCREGS 
DAGREGS 
EVEN_AREGS 
ODD_AREGS 
AREGS 
CCREGS 
EVEN_DREGS 
ODD_DREGS 
DREGS 
PREGS_CLOBBERED 
PREGS 
DPREGS 
MOST_REGS 
PROLOGUE_REGS 
NON_A_CC_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0R1_REGS 
R2R3_REGS 
EXT_LOW_REGS 
EXT_REGS 
ADDR_REGS 
INDEX_REGS 
BK_REG 
SP_REG 
RC_REG 
COUNTER_REGS 
INT_REGS 
GENERAL_REGS 
DP_REG 
ST_REG 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MULTIPLY_32_REG 
MULTIPLY_64_REG 
LOW_REGS 
HIGH_REGS 
REAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ICC_REGS 
FCC_REGS 
CC_REGS 
ICR_REGS 
FCR_REGS 
CR_REGS 
LCR_REG 
LR_REG 
GR8_REGS 
GR9_REGS 
GR89_REGS 
FDPIC_REGS 
FDPIC_FPTR_REGS 
FDPIC_CALL_REGS 
SPR_REGS 
QUAD_ACC_REGS 
EVEN_ACC_REGS 
ACC_REGS 
ACCG_REGS 
QUAD_FPR_REGS 
FEVEN_REGS 
FPR_REGS 
QUAD_REGS 
EVEN_REGS 
GPR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
COUNTER_REGS 
SOURCE_REGS 
DESTINATION_REGS 
GENERAL_REGS 
MAC_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
AREG 
DREG 
CREG 
BREG 
SIREG 
DIREG 
AD_REGS 
Q_REGS 
NON_Q_REGS 
INDEX_REGS 
LEGACY_REGS 
GENERAL_REGS 
FP_TOP_REG 
FP_SECOND_REG 
FLOAT_REGS 
SSE_REGS 
MMX_REGS 
FP_TOP_SSE_REGS 
FP_SECOND_SSE_REGS 
FLOAT_SSE_REGS 
FLOAT_INT_REGS 
INT_SSE_REGS 
FLOAT_INT_SSE_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
PR_REGS 
BR_REGS 
AR_M_REGS 
AR_I_REGS 
ADDL_REGS 
GR_REGS 
FR_REGS 
GR_AND_BR_REGS 
GR_AND_FR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DPH_REGS 
DPL_REGS 
DP_REGS 
SP_REGS 
IPH_REGS 
IPL_REGS 
IP_REGS 
DP_SP_REGS 
PTR_REGS 
NONPTR_REGS 
NONSP_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
CARRY_REG 
ACCUM_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
D_REGS 
X_REGS 
Y_REGS 
SP_REGS 
DA_REGS 
DB_REGS 
Z_REGS 
D8_REGS 
Q_REGS 
D_OR_X_REGS 
D_OR_Y_REGS 
D_OR_SP_REGS 
X_OR_Y_REGS 
A_REGS 
X_OR_SP_REGS 
Y_OR_SP_REGS 
X_OR_Y_OR_D_REGS 
A_OR_D_REGS 
A_OR_SP_REGS 
H_REGS 
S_REGS 
D_OR_S_REGS 
X_OR_S_REGS 
Y_OR_S_REGS 
Z_OR_S_REGS 
SP_OR_S_REGS 
D_OR_X_OR_S_REGS 
D_OR_Y_OR_S_REGS 
D_OR_SP_OR_S_REGS 
A_OR_S_REGS 
D_OR_A_OR_S_REGS 
TMP_REGS 
D_OR_A_OR_TMP_REGS 
G_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDR_REGS 
FP_REGS 
GENERAL_REGS 
DATA_OR_FP_REGS 
ADDR_OR_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ONLYR1_REGS 
LRW_REGS 
GENERAL_REGS 
C_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
M16_NA_REGS 
M16_REGS 
T_REG 
M16_T_REGS 
PIC_FN_ADDR_REG 
LEA_REGS 
GR_REGS 
FP_REGS 
HI_REG 
LO_REG 
MD_REGS 
COP0_REGS 
COP2_REGS 
COP3_REGS 
HI_AND_GR_REGS 
LO_AND_GR_REGS 
HI_AND_FP_REGS 
COP0_AND_GR_REGS 
COP2_AND_GR_REGS 
COP3_AND_GR_REGS 
ALL_COP_REGS 
ALL_COP_AND_GR_REGS 
ST_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
REMAINDER_REG 
HIMULT_REG 
SYSTEM_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDRESS_REGS 
SP_REGS 
DATA_OR_ADDRESS_REGS 
SP_OR_ADDRESS_REGS 
EXTENDED_REGS 
DATA_OR_EXTENDED_REGS 
ADDRESS_OR_EXTENDED_REGS 
SP_OR_EXTENDED_REGS 
SP_OR_ADDRESS_OR_EXTENDED_REGS 
FP_REGS 
FP_ACC_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
FLOAT_REG0 
LONG_FLOAT_REG0 
FLOAT_REGS 
LONG_REGS 
FP_REGS 
GEN_AND_FP_REGS 
FRAME_POINTER_REG 
STACK_POINTER_REG 
GEN_AND_MEM_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R1_REGS 
GENERAL_REGS 
FPUPPER_REGS 
FP_REGS 
GENERAL_OR_FP_REGS 
SHIFT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R1_REGS 
GENERAL_REGS 
FPUPPER_REGS 
FP_REGS 
GENERAL_OR_FP_REGS 
SHIFT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MUL_REGS 
GENERAL_REGS 
LOAD_FPU_REGS 
NO_LOAD_FPU_REGS 
FPU_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
BASE_REGS 
GENERAL_REGS 
FLOAT_REGS 
ALTIVEC_REGS 
VRSAVE_REGS 
VSCR_REGS 
SPE_ACC_REGS 
SPEFSCR_REGS 
NON_SPECIAL_REGS 
MQ_REGS 
LINK_REGS 
CTR_REGS 
LINK_OR_CTR_REGS 
SPECIAL_REGS 
SPEC_OR_GEN_REGS 
CR0_REGS 
CR_REGS 
NON_FLOAT_REGS 
XER_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
CC_REGS 
ADDR_REGS 
GENERAL_REGS 
ACCESS_REGS 
ADDR_CC_REGS 
GENERAL_CC_REGS 
FP_REGS 
ADDR_FP_REGS 
GENERAL_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
PR_REGS 
T_REGS 
MAC_REGS 
FPUL_REGS 
SIBCALL_REGS 
GENERAL_REGS 
FP0_REGS 
FP_REGS 
DF_HI_REGS 
DF_REGS 
FPSCR_REGS 
GENERAL_FP_REGS 
TARGET_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
FPCC_REGS 
I64_REGS 
GENERAL_REGS 
FP_REGS 
EXTRA_FP_REGS 
GENERAL_OR_FP_REGS 
GENERAL_OR_EXTRA_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
R1_REGS 
TWO_REGS 
R2_REGS 
EIGHT_REGS 
R8_REGS 
ICALL_REGS 
GENERAL_REGS 
CARRY_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
BR_REGS 
FP_REGS 
ACC_REG 
SP_REG 
RL_REGS 
GR_REGS 
AR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REG 
R24_REG 
R25_REG 
R27_REG 
GENERAL_REGS 
FLOAT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
LPCOUNT_REG 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
FPA_REGS 
CIRRUS_REGS 
VFP_REGS 
IWMMXT_GR_REGS 
IWMMXT_REGS 
LO_REGS 
STACK_REG 
BASE_REGS 
HI_REGS 
CC_REG 
VFPCC_REG 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REG 
POINTER_X_REGS 
POINTER_Y_REGS 
POINTER_Z_REGS 
STACK_REG 
BASE_POINTER_REGS 
POINTER_REGS 
ADDW_REGS 
SIMPLE_LD_REGS 
LD_REGS 
NO_LD_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
IREGS 
BREGS 
LREGS 
MREGS 
CIRCREGS 
DAGREGS 
EVEN_AREGS 
ODD_AREGS 
AREGS 
CCREGS 
EVEN_DREGS 
ODD_DREGS 
DREGS 
FDPIC_REGS 
FDPIC_FPTR_REGS 
PREGS_CLOBBERED 
PREGS 
IPREGS 
DPREGS 
MOST_REGS 
LT_REGS 
LC_REGS 
LB_REGS 
PROLOGUE_REGS 
NON_A_CC_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0R1_REGS 
R2R3_REGS 
EXT_LOW_REGS 
EXT_REGS 
ADDR_REGS 
INDEX_REGS 
BK_REG 
SP_REG 
RC_REG 
COUNTER_REGS 
INT_REGS 
GENERAL_REGS 
DP_REG 
ST_REG 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MOF_REGS 
CC0_REGS 
SPECIAL_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
LO_REGS 
HI_REGS 
HILO_REGS 
NOSP_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MULTIPLY_32_REG 
MULTIPLY_64_REG 
LOW_REGS 
HIGH_REGS 
REAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ICC_REGS 
FCC_REGS 
CC_REGS 
ICR_REGS 
FCR_REGS 
CR_REGS 
LCR_REG 
LR_REG 
GR8_REGS 
GR9_REGS 
GR89_REGS 
FDPIC_REGS 
FDPIC_FPTR_REGS 
FDPIC_CALL_REGS 
SPR_REGS 
QUAD_ACC_REGS 
EVEN_ACC_REGS 
ACC_REGS 
ACCG_REGS 
QUAD_FPR_REGS 
FEVEN_REGS 
FPR_REGS 
QUAD_REGS 
EVEN_REGS 
GPR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
COUNTER_REGS 
SOURCE_REGS 
DESTINATION_REGS 
GENERAL_REGS 
MAC_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
AREG 
DREG 
CREG 
BREG 
SIREG 
DIREG 
AD_REGS 
Q_REGS 
NON_Q_REGS 
INDEX_REGS 
LEGACY_REGS 
GENERAL_REGS 
FP_TOP_REG 
FP_SECOND_REG 
FLOAT_REGS 
SSE_REGS 
MMX_REGS 
FP_TOP_SSE_REGS 
FP_SECOND_SSE_REGS 
FLOAT_SSE_REGS 
FLOAT_INT_REGS 
INT_SSE_REGS 
FLOAT_INT_SSE_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
PR_REGS 
BR_REGS 
AR_M_REGS 
AR_I_REGS 
ADDL_REGS 
GR_REGS 
FP_REGS 
FR_REGS 
GR_AND_BR_REGS 
GR_AND_FR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GR_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
SP_REGS 
FB_REGS 
SB_REGS 
CR_REGS 
R0_REGS 
R1_REGS 
R2_REGS 
R3_REGS 
R02_REGS 
HL_REGS 
QI_REGS 
R23_REGS 
R03_REGS 
DI_REGS 
A0_REGS 
A1_REGS 
A_REGS 
AD_REGS 
PS_REGS 
SI_REGS 
HI_REGS 
RA_REGS 
GENERAL_REGS 
FLG_REGS 
HC_REGS 
MEM_REGS 
R02_A_MEM_REGS 
A_HL_MEM_REGS 
R1_R3_A_MEM_REGS 
R03_MEM_REGS 
A_HI_MEM_REGS 
A_AD_CR_MEM_SI_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
CARRY_REG 
ACCUM_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
D_REGS 
X_REGS 
Y_REGS 
SP_REGS 
DA_REGS 
DB_REGS 
Z_REGS 
D8_REGS 
Q_REGS 
D_OR_X_REGS 
D_OR_Y_REGS 
D_OR_SP_REGS 
X_OR_Y_REGS 
A_REGS 
X_OR_SP_REGS 
Y_OR_SP_REGS 
X_OR_Y_OR_D_REGS 
A_OR_D_REGS 
A_OR_SP_REGS 
H_REGS 
S_REGS 
D_OR_S_REGS 
X_OR_S_REGS 
Y_OR_S_REGS 
Z_OR_S_REGS 
SP_OR_S_REGS 
D_OR_X_OR_S_REGS 
D_OR_Y_OR_S_REGS 
D_OR_SP_OR_S_REGS 
A_OR_S_REGS 
D_OR_A_OR_S_REGS 
TMP_REGS 
D_OR_A_OR_TMP_REGS 
G_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDR_REGS 
FP_REGS 
GENERAL_REGS 
DATA_OR_FP_REGS 
ADDR_OR_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ONLYR1_REGS 
LRW_REGS 
GENERAL_REGS 
C_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
M16_NA_REGS 
M16_REGS 
T_REG 
M16_T_REGS 
PIC_FN_ADDR_REG 
V1_REG 
LEA_REGS 
GR_REGS 
FP_REGS 
HI_REG 
LO_REG 
MD_REGS 
COP0_REGS 
COP2_REGS 
COP3_REGS 
HI_AND_GR_REGS 
LO_AND_GR_REGS 
HI_AND_FP_REGS 
COP0_AND_GR_REGS 
COP2_AND_GR_REGS 
COP3_AND_GR_REGS 
ALL_COP_REGS 
ALL_COP_AND_GR_REGS 
ST_REGS 
DSP_ACC_REGS 
ACC_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
REMAINDER_REG 
HIMULT_REG 
SYSTEM_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
DATA_REGS 
ADDRESS_REGS 
SP_REGS 
DATA_OR_ADDRESS_REGS 
SP_OR_ADDRESS_REGS 
EXTENDED_REGS 
DATA_OR_EXTENDED_REGS 
ADDRESS_OR_EXTENDED_REGS 
SP_OR_EXTENDED_REGS 
SP_OR_ADDRESS_OR_EXTENDED_REGS 
FP_REGS 
FP_ACC_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R1_REGS 
GENERAL_REGS 
FPUPPER_REGS 
FP_REGS 
GENERAL_OR_FP_REGS 
SHIFT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R1_REGS 
GENERAL_REGS 
FPUPPER_REGS 
FP_REGS 
GENERAL_OR_FP_REGS 
SHIFT_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
MUL_REGS 
GENERAL_REGS 
LOAD_FPU_REGS 
NO_LOAD_FPU_REGS 
FPU_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
BASE_REGS 
GENERAL_REGS 
FLOAT_REGS 
ALTIVEC_REGS 
VRSAVE_REGS 
VSCR_REGS 
SPE_ACC_REGS 
SPEFSCR_REGS 
NON_SPECIAL_REGS 
MQ_REGS 
LINK_REGS 
CTR_REGS 
LINK_OR_CTR_REGS 
SPECIAL_REGS 
SPEC_OR_GEN_REGS 
CR0_REGS 
CR_REGS 
NON_FLOAT_REGS 
XER_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
CC_REGS 
ADDR_REGS 
GENERAL_REGS 
ACCESS_REGS 
ADDR_CC_REGS 
GENERAL_CC_REGS 
FP_REGS 
ADDR_FP_REGS 
GENERAL_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
G16_REGS 
G32_REGS 
T32_REGS 
HI_REG 
LO_REG 
CE_REGS 
CN_REG 
LC_REG 
SC_REG 
SP_REGS 
CR_REGS 
CP1_REGS 
CP2_REGS 
CP3_REGS 
CPA_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
PR_REGS 
T_REGS 
MAC_REGS 
FPUL_REGS 
SIBCALL_REGS 
GENERAL_REGS 
FP0_REGS 
FP_REGS 
DF_HI_REGS 
DF_REGS 
FPSCR_REGS 
GENERAL_FP_REGS 
GENERAL_DF_REGS 
TARGET_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
FPCC_REGS 
I64_REGS 
GENERAL_REGS 
FP_REGS 
EXTRA_FP_REGS 
GENERAL_OR_FP_REGS 
GENERAL_OR_EXTRA_FP_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
R0_REGS 
R1_REGS 
TWO_REGS 
R2_REGS 
EIGHT_REGS 
R8_REGS 
ICALL_REGS 
GENERAL_REGS 
CARRY_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
GENERAL_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
ALL_REGS 
LIM_REG_CLASSES 
NO_REGS 
BR_REGS 
FP_REGS 
ACC_REG 
SP_REG 
RL_REGS 
GR_REGS 
AR_REGS 
ALL_REGS 
LIM_REG_CLASSES 

Definition at line 1036 of file sparc.h.

Function Documentation

GTY ( ()   )  [read, write]

Definition at line 94 of file hashtab.h.

Variable Documentation

const int* hard_regno_mode_classes

Definition at line 3459 of file sparc.c.

char leaf_reg_remap[]

enum cmodel sparc_cmodel

Definition at line 193 of file sparc.c.

struct processor_costs* sparc_costs

Definition at line 199 of file sparc.c.

enum processor_type sparc_cpu

Definition at line 207 of file sparc.c.

int sparc_indent_opcode

Definition at line 297 of file sparc.c.

char sparc_leaf_regs[]

Definition at line 256 of file sparc.c.

int sparc_mode_class[]

Definition at line 3511 of file sparc.c.

enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]

Definition at line 3513 of file sparc.c.

struct sparc_cpu_select sparc_select[]

Definition at line 197 of file sparc.c.

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