Open64: osprey/cygnus/opcodes/m32r-opc.c Source File

00001 /*
00002  * Copyright 2003, 2004, 2005, 2006 PathScale, Inc.  All Rights Reserved.
00003  */
00004 
00005 /* Instruction opcode table for m32r.
00006 
00007 THIS FILE IS MACHINE GENERATED WITH CGEN.
00008 
00009 Copyright 1996-2005 Free Software Foundation, Inc.
00010 
00011 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00012 
00013 This program is free software; you can redistribute it and/or modify
00014 it under the terms of the GNU General Public License as published by
00015 the Free Software Foundation; either version 2, or (at your option)
00016 any later version.
00017 
00018 This program is distributed in the hope that it will be useful,
00019 but WITHOUT ANY WARRANTY; without even the implied warranty of
00020 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00021 GNU General Public License for more details.
00022 
00023 You should have received a copy of the GNU General Public License along
00024 with this program; if not, write to the Free Software Foundation, Inc.,
00025 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00026 
00027 */
00028 
00029 #include "sysdep.h"
00030 #include "ansidecl.h"
00031 #include "bfd.h"
00032 #include "symcat.h"
00033 #include "m32r-desc.h"
00034 #include "m32r-opc.h"
00035 #include "libiberty.h"
00036 
00037 /* -- opc.c */
00038 unsigned int
00039 m32r_cgen_dis_hash (buf, value)
00040      const char * buf ATTRIBUTE_UNUSED;
00041      CGEN_INSN_INT value;
00042 {
00043   unsigned int x;
00044                                                                                 
00045   if (value & 0xffff0000) /* 32bit instructions */
00046     value = (value >> 16) & 0xffff;
00047                                                                                 
00048   x = (value>>8) & 0xf0;
00049   if (x == 0x40 || x == 0xe0 || x == 0x60 || x == 0x50)
00050     return x;
00051                                                                                 
00052   if (x == 0x70 || x == 0xf0)
00053     return x | ((value>>8) & 0x0f);
00054                                                                                 
00055   if (x == 0x30)
00056     return x | ((value & 0x70) >> 4);
00057   else
00058     return x | ((value & 0xf0) >> 4);
00059 }
00060                                                                                 
00061 /* -- */
00062 /* The hash functions are recorded here to help keep assembler code out of
00063    the disassembler and vice versa.  */
00064 
00065 static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
00066 static unsigned int asm_hash_insn PARAMS ((const char *));
00067 static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
00068 static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
00069 
00070 /* Instruction formats.  */
00071 
00072 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00073 #define F(f) & m32r_cgen_ifld_table[M32R_##f]
00074 #else
00075 #define F(f) & m32r_cgen_ifld_table[M32R_f]
00076 #endif
00077 static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
00078   0, 0, 0x0, { { 0 } }
00079 };
00080 
00081 static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = {
00082   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00083 };
00084 
00085 static const CGEN_IFMT ifmt_add3 ATTRIBUTE_UNUSED = {
00086   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00087 };
00088 
00089 static const CGEN_IFMT ifmt_and3 ATTRIBUTE_UNUSED = {
00090   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
00091 };
00092 
00093 static const CGEN_IFMT ifmt_or3 ATTRIBUTE_UNUSED = {
00094   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
00095 };
00096 
00097 static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = {
00098   16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
00099 };
00100 
00101 static const CGEN_IFMT ifmt_addv3 ATTRIBUTE_UNUSED = {
00102   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00103 };
00104 
00105 static const CGEN_IFMT ifmt_bc8 ATTRIBUTE_UNUSED = {
00106   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
00107 };
00108 
00109 static const CGEN_IFMT ifmt_bc24 ATTRIBUTE_UNUSED = {
00110   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
00111 };
00112 
00113 static const CGEN_IFMT ifmt_beq ATTRIBUTE_UNUSED = {
00114   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
00115 };
00116 
00117 static const CGEN_IFMT ifmt_beqz ATTRIBUTE_UNUSED = {
00118   32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_DISP16) }, { 0 } }
00119 };
00120 
00121 static const CGEN_IFMT ifmt_cmp ATTRIBUTE_UNUSED = {
00122   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00123 };
00124 
00125 static const CGEN_IFMT ifmt_cmpi ATTRIBUTE_UNUSED = {
00126   32, 32, 0xfff00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00127 };
00128 
00129 static const CGEN_IFMT ifmt_cmpz ATTRIBUTE_UNUSED = {
00130   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00131 };
00132 
00133 static const CGEN_IFMT ifmt_div ATTRIBUTE_UNUSED = {
00134   32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00135 };
00136 
00137 static const CGEN_IFMT ifmt_jc ATTRIBUTE_UNUSED = {
00138   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00139 };
00140 
00141 static const CGEN_IFMT ifmt_ld24 ATTRIBUTE_UNUSED = {
00142   32, 32, 0xf0000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM24) }, { 0 } }
00143 };
00144 
00145 static const CGEN_IFMT ifmt_ldi16 ATTRIBUTE_UNUSED = {
00146   32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00147 };
00148 
00149 static const CGEN_IFMT ifmt_machi_a ATTRIBUTE_UNUSED = {
00150   16, 16, 0xf070, { { F (F_OP1) }, { F (F_R1) }, { F (F_ACC) }, { F (F_OP23) }, { F (F_R2) }, { 0 } }
00151 };
00152 
00153 static const CGEN_IFMT ifmt_mvfachi ATTRIBUTE_UNUSED = {
00154   16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00155 };
00156 
00157 static const CGEN_IFMT ifmt_mvfachi_a ATTRIBUTE_UNUSED = {
00158   16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
00159 };
00160 
00161 static const CGEN_IFMT ifmt_mvfc ATTRIBUTE_UNUSED = {
00162   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00163 };
00164 
00165 static const CGEN_IFMT ifmt_mvtachi ATTRIBUTE_UNUSED = {
00166   16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00167 };
00168 
00169 static const CGEN_IFMT ifmt_mvtachi_a ATTRIBUTE_UNUSED = {
00170   16, 16, 0xf0f3, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_OP3) }, { 0 } }
00171 };
00172 
00173 static const CGEN_IFMT ifmt_mvtc ATTRIBUTE_UNUSED = {
00174   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00175 };
00176 
00177 static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = {
00178   16, 16, 0xffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00179 };
00180 
00181 static const CGEN_IFMT ifmt_rac_dsi ATTRIBUTE_UNUSED = {
00182   16, 16, 0xf3f2, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
00183 };
00184 
00185 static const CGEN_IFMT ifmt_seth ATTRIBUTE_UNUSED = {
00186   32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_HI16) }, { 0 } }
00187 };
00188 
00189 static const CGEN_IFMT ifmt_slli ATTRIBUTE_UNUSED = {
00190   16, 16, 0xf0e0, { { F (F_OP1) }, { F (F_R1) }, { F (F_SHIFT_OP2) }, { F (F_UIMM5) }, { 0 } }
00191 };
00192 
00193 static const CGEN_IFMT ifmt_st_d ATTRIBUTE_UNUSED = {
00194   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00195 };
00196 
00197 static const CGEN_IFMT ifmt_trap ATTRIBUTE_UNUSED = {
00198   16, 16, 0xfff0, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_UIMM4) }, { 0 } }
00199 };
00200 
00201 static const CGEN_IFMT ifmt_satb ATTRIBUTE_UNUSED = {
00202   32, 32, 0xf0f0ffff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_UIMM16) }, { 0 } }
00203 };
00204 
00205 static const CGEN_IFMT ifmt_clrpsw ATTRIBUTE_UNUSED = {
00206   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_UIMM8) }, { 0 } }
00207 };
00208 
00209 static const CGEN_IFMT ifmt_bset ATTRIBUTE_UNUSED = {
00210   32, 32, 0xf8f00000, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
00211 };
00212 
00213 static const CGEN_IFMT ifmt_btst ATTRIBUTE_UNUSED = {
00214   16, 16, 0xf8f0, { { F (F_OP1) }, { F (F_BIT4) }, { F (F_UIMM3) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
00215 };
00216 
00217 #undef F
00218 
00219 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00220 #define A(a) (1 << CGEN_INSN_##a)
00221 #else
00222 #define A(a) (1 << CGEN_INSN_a)
00223 #endif
00224 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00225 #define OPERAND(op) M32R_OPERAND_##op
00226 #else
00227 #define OPERAND(op) M32R_OPERAND_op
00228 #endif
00229 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
00230 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00231 
00232 /* The instruction table.  */
00233 
00234 static const CGEN_OPCODE m32r_cgen_insn_opcode_table[MAX_INSNS] =
00235 {
00236   /* Special null first entry.
00237      A `num' value of zero is thus invalid.
00238      Also, the special `invalid' insn resides here.  */
00239   { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
00240 /* add $dr,$sr */
00241   {
00242     { 0, 0, 0, 0 },
00243     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00244     & ifmt_add, { 0xa0 }
00245   },
00246 /* add3 $dr,$sr,$hash$slo16 */
00247   {
00248     { 0, 0, 0, 0 },
00249     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } },
00250     & ifmt_add3, { 0x80a00000 }
00251   },
00252 /* and $dr,$sr */
00253   {
00254     { 0, 0, 0, 0 },
00255     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00256     & ifmt_add, { 0xc0 }
00257   },
00258 /* and3 $dr,$sr,$uimm16 */
00259   {
00260     { 0, 0, 0, 0 },
00261     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
00262     & ifmt_and3, { 0x80c00000 }
00263   },
00264 /* or $dr,$sr */
00265   {
00266     { 0, 0, 0, 0 },
00267     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00268     & ifmt_add, { 0xe0 }
00269   },
00270 /* or3 $dr,$sr,$hash$ulo16 */
00271   {
00272     { 0, 0, 0, 0 },
00273     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (ULO16), 0 } },
00274     & ifmt_or3, { 0x80e00000 }
00275   },
00276 /* xor $dr,$sr */
00277   {
00278     { 0, 0, 0, 0 },
00279     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00280     & ifmt_add, { 0xd0 }
00281   },
00282 /* xor3 $dr,$sr,$uimm16 */
00283   {
00284     { 0, 0, 0, 0 },
00285     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } },
00286     & ifmt_and3, { 0x80d00000 }
00287   },
00288 /* addi $dr,$simm8 */
00289   {
00290     { 0, 0, 0, 0 },
00291     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
00292     & ifmt_addi, { 0x4000 }
00293   },
00294 /* addv $dr,$sr */
00295   {
00296     { 0, 0, 0, 0 },
00297     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00298     & ifmt_add, { 0x80 }
00299   },
00300 /* addv3 $dr,$sr,$simm16 */
00301   {
00302     { 0, 0, 0, 0 },
00303     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
00304     & ifmt_addv3, { 0x80800000 }
00305   },
00306 /* addx $dr,$sr */
00307   {
00308     { 0, 0, 0, 0 },
00309     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00310     & ifmt_add, { 0x90 }
00311   },
00312 /* bc.s $disp8 */
00313   {
00314     { 0, 0, 0, 0 },
00315     { { MNEM, ' ', OP (DISP8), 0 } },
00316     & ifmt_bc8, { 0x7c00 }
00317   },
00318 /* bc.l $disp24 */
00319   {
00320     { 0, 0, 0, 0 },
00321     { { MNEM, ' ', OP (DISP24), 0 } },
00322     & ifmt_bc24, { 0xfc000000 }
00323   },
00324 /* beq $src1,$src2,$disp16 */
00325   {
00326     { 0, 0, 0, 0 },
00327     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
00328     & ifmt_beq, { 0xb0000000 }
00329   },
00330 /* beqz $src2,$disp16 */
00331   {
00332     { 0, 0, 0, 0 },
00333     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00334     & ifmt_beqz, { 0xb0800000 }
00335   },
00336 /* bgez $src2,$disp16 */
00337   {
00338     { 0, 0, 0, 0 },
00339     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00340     & ifmt_beqz, { 0xb0b00000 }
00341   },
00342 /* bgtz $src2,$disp16 */
00343   {
00344     { 0, 0, 0, 0 },
00345     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00346     & ifmt_beqz, { 0xb0d00000 }
00347   },
00348 /* blez $src2,$disp16 */
00349   {
00350     { 0, 0, 0, 0 },
00351     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00352     & ifmt_beqz, { 0xb0c00000 }
00353   },
00354 /* bltz $src2,$disp16 */
00355   {
00356     { 0, 0, 0, 0 },
00357     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00358     & ifmt_beqz, { 0xb0a00000 }
00359   },
00360 /* bnez $src2,$disp16 */
00361   {
00362     { 0, 0, 0, 0 },
00363     { { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 } },
00364     & ifmt_beqz, { 0xb0900000 }
00365   },
00366 /* bl.s $disp8 */
00367   {
00368     { 0, 0, 0, 0 },
00369     { { MNEM, ' ', OP (DISP8), 0 } },
00370     & ifmt_bc8, { 0x7e00 }
00371   },
00372 /* bl.l $disp24 */
00373   {
00374     { 0, 0, 0, 0 },
00375     { { MNEM, ' ', OP (DISP24), 0 } },
00376     & ifmt_bc24, { 0xfe000000 }
00377   },
00378 /* bcl.s $disp8 */
00379   {
00380     { 0, 0, 0, 0 },
00381     { { MNEM, ' ', OP (DISP8), 0 } },
00382     & ifmt_bc8, { 0x7800 }
00383   },
00384 /* bcl.l $disp24 */
00385   {
00386     { 0, 0, 0, 0 },
00387     { { MNEM, ' ', OP (DISP24), 0 } },
00388     & ifmt_bc24, { 0xf8000000 }
00389   },
00390 /* bnc.s $disp8 */
00391   {
00392     { 0, 0, 0, 0 },
00393     { { MNEM, ' ', OP (DISP8), 0 } },
00394     & ifmt_bc8, { 0x7d00 }
00395   },
00396 /* bnc.l $disp24 */
00397   {
00398     { 0, 0, 0, 0 },
00399     { { MNEM, ' ', OP (DISP24), 0 } },
00400     & ifmt_bc24, { 0xfd000000 }
00401   },
00402 /* bne $src1,$src2,$disp16 */
00403   {
00404     { 0, 0, 0, 0 },
00405     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 } },
00406     & ifmt_beq, { 0xb0100000 }
00407   },
00408 /* bra.s $disp8 */
00409   {
00410     { 0, 0, 0, 0 },
00411     { { MNEM, ' ', OP (DISP8), 0 } },
00412     & ifmt_bc8, { 0x7f00 }
00413   },
00414 /* bra.l $disp24 */
00415   {
00416     { 0, 0, 0, 0 },
00417     { { MNEM, ' ', OP (DISP24), 0 } },
00418     & ifmt_bc24, { 0xff000000 }
00419   },
00420 /* bncl.s $disp8 */
00421   {
00422     { 0, 0, 0, 0 },
00423     { { MNEM, ' ', OP (DISP8), 0 } },
00424     & ifmt_bc8, { 0x7900 }
00425   },
00426 /* bncl.l $disp24 */
00427   {
00428     { 0, 0, 0, 0 },
00429     { { MNEM, ' ', OP (DISP24), 0 } },
00430     & ifmt_bc24, { 0xf9000000 }
00431   },
00432 /* cmp $src1,$src2 */
00433   {
00434     { 0, 0, 0, 0 },
00435     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00436     & ifmt_cmp, { 0x40 }
00437   },
00438 /* cmpi $src2,$simm16 */
00439   {
00440     { 0, 0, 0, 0 },
00441     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
00442     & ifmt_cmpi, { 0x80400000 }
00443   },
00444 /* cmpu $src1,$src2 */
00445   {
00446     { 0, 0, 0, 0 },
00447     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00448     & ifmt_cmp, { 0x50 }
00449   },
00450 /* cmpui $src2,$simm16 */
00451   {
00452     { 0, 0, 0, 0 },
00453     { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
00454     & ifmt_cmpi, { 0x80500000 }
00455   },
00456 /* cmpeq $src1,$src2 */
00457   {
00458     { 0, 0, 0, 0 },
00459     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00460     & ifmt_cmp, { 0x60 }
00461   },
00462 /* cmpz $src2 */
00463   {
00464     { 0, 0, 0, 0 },
00465     { { MNEM, ' ', OP (SRC2), 0 } },
00466     & ifmt_cmpz, { 0x70 }
00467   },
00468 /* div $dr,$sr */
00469   {
00470     { 0, 0, 0, 0 },
00471     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00472     & ifmt_div, { 0x90000000 }
00473   },
00474 /* divu $dr,$sr */
00475   {
00476     { 0, 0, 0, 0 },
00477     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00478     & ifmt_div, { 0x90100000 }
00479   },
00480 /* rem $dr,$sr */
00481   {
00482     { 0, 0, 0, 0 },
00483     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00484     & ifmt_div, { 0x90200000 }
00485   },
00486 /* remu $dr,$sr */
00487   {
00488     { 0, 0, 0, 0 },
00489     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00490     & ifmt_div, { 0x90300000 }
00491   },
00492 /* remh $dr,$sr */
00493   {
00494     { 0, 0, 0, 0 },
00495     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00496     & ifmt_div, { 0x90200010 }
00497   },
00498 /* remuh $dr,$sr */
00499   {
00500     { 0, 0, 0, 0 },
00501     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00502     & ifmt_div, { 0x90300010 }
00503   },
00504 /* remb $dr,$sr */
00505   {
00506     { 0, 0, 0, 0 },
00507     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00508     & ifmt_div, { 0x90200018 }
00509   },
00510 /* remub $dr,$sr */
00511   {
00512     { 0, 0, 0, 0 },
00513     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00514     & ifmt_div, { 0x90300018 }
00515   },
00516 /* divuh $dr,$sr */
00517   {
00518     { 0, 0, 0, 0 },
00519     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00520     & ifmt_div, { 0x90100010 }
00521   },
00522 /* divb $dr,$sr */
00523   {
00524     { 0, 0, 0, 0 },
00525     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00526     & ifmt_div, { 0x90000018 }
00527   },
00528 /* divub $dr,$sr */
00529   {
00530     { 0, 0, 0, 0 },
00531     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00532     & ifmt_div, { 0x90100018 }
00533   },
00534 /* divh $dr,$sr */
00535   {
00536     { 0, 0, 0, 0 },
00537     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00538     & ifmt_div, { 0x90000010 }
00539   },
00540 /* jc $sr */
00541   {
00542     { 0, 0, 0, 0 },
00543     { { MNEM, ' ', OP (SR), 0 } },
00544     & ifmt_jc, { 0x1cc0 }
00545   },
00546 /* jnc $sr */
00547   {
00548     { 0, 0, 0, 0 },
00549     { { MNEM, ' ', OP (SR), 0 } },
00550     & ifmt_jc, { 0x1dc0 }
00551   },
00552 /* jl $sr */
00553   {
00554     { 0, 0, 0, 0 },
00555     { { MNEM, ' ', OP (SR), 0 } },
00556     & ifmt_jc, { 0x1ec0 }
00557   },
00558 /* jmp $sr */
00559   {
00560     { 0, 0, 0, 0 },
00561     { { MNEM, ' ', OP (SR), 0 } },
00562     & ifmt_jc, { 0x1fc0 }
00563   },
00564 /* ld $dr,@$sr */
00565   {
00566     { 0, 0, 0, 0 },
00567     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00568     & ifmt_add, { 0x20c0 }
00569   },
00570 /* ld $dr,@($slo16,$sr) */
00571   {
00572     { 0, 0, 0, 0 },
00573     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00574     & ifmt_add3, { 0xa0c00000 }
00575   },
00576 /* ldb $dr,@$sr */
00577   {
00578     { 0, 0, 0, 0 },
00579     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00580     & ifmt_add, { 0x2080 }
00581   },
00582 /* ldb $dr,@($slo16,$sr) */
00583   {
00584     { 0, 0, 0, 0 },
00585     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00586     & ifmt_add3, { 0xa0800000 }
00587   },
00588 /* ldh $dr,@$sr */
00589   {
00590     { 0, 0, 0, 0 },
00591     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00592     & ifmt_add, { 0x20a0 }
00593   },
00594 /* ldh $dr,@($slo16,$sr) */
00595   {
00596     { 0, 0, 0, 0 },
00597     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00598     & ifmt_add3, { 0xa0a00000 }
00599   },
00600 /* ldub $dr,@$sr */
00601   {
00602     { 0, 0, 0, 0 },
00603     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00604     & ifmt_add, { 0x2090 }
00605   },
00606 /* ldub $dr,@($slo16,$sr) */
00607   {
00608     { 0, 0, 0, 0 },
00609     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00610     & ifmt_add3, { 0xa0900000 }
00611   },
00612 /* lduh $dr,@$sr */
00613   {
00614     { 0, 0, 0, 0 },
00615     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00616     & ifmt_add, { 0x20b0 }
00617   },
00618 /* lduh $dr,@($slo16,$sr) */
00619   {
00620     { 0, 0, 0, 0 },
00621     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
00622     & ifmt_add3, { 0xa0b00000 }
00623   },
00624 /* ld $dr,@$sr+ */
00625   {
00626     { 0, 0, 0, 0 },
00627     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 } },
00628     & ifmt_add, { 0x20e0 }
00629   },
00630 /* ld24 $dr,$uimm24 */
00631   {
00632     { 0, 0, 0, 0 },
00633     { { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 } },
00634     & ifmt_ld24, { 0xe0000000 }
00635   },
00636 /* ldi8 $dr,$simm8 */
00637   {
00638     { 0, 0, 0, 0 },
00639     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
00640     & ifmt_addi, { 0x6000 }
00641   },
00642 /* ldi16 $dr,$hash$slo16 */
00643   {
00644     { 0, 0, 0, 0 },
00645     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
00646     & ifmt_ldi16, { 0x90f00000 }
00647   },
00648 /* lock $dr,@$sr */
00649   {
00650     { 0, 0, 0, 0 },
00651     { { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 } },
00652     & ifmt_add, { 0x20d0 }
00653   },
00654 /* machi $src1,$src2 */
00655   {
00656     { 0, 0, 0, 0 },
00657     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00658     & ifmt_cmp, { 0x3040 }
00659   },
00660 /* machi $src1,$src2,$acc */
00661   {
00662     { 0, 0, 0, 0 },
00663     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00664     & ifmt_machi_a, { 0x3040 }
00665   },
00666 /* maclo $src1,$src2 */
00667   {
00668     { 0, 0, 0, 0 },
00669     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00670     & ifmt_cmp, { 0x3050 }
00671   },
00672 /* maclo $src1,$src2,$acc */
00673   {
00674     { 0, 0, 0, 0 },
00675     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00676     & ifmt_machi_a, { 0x3050 }
00677   },
00678 /* macwhi $src1,$src2 */
00679   {
00680     { 0, 0, 0, 0 },
00681     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00682     & ifmt_cmp, { 0x3060 }
00683   },
00684 /* macwhi $src1,$src2,$acc */
00685   {
00686     { 0, 0, 0, 0 },
00687     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00688     & ifmt_machi_a, { 0x3060 }
00689   },
00690 /* macwlo $src1,$src2 */
00691   {
00692     { 0, 0, 0, 0 },
00693     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00694     & ifmt_cmp, { 0x3070 }
00695   },
00696 /* macwlo $src1,$src2,$acc */
00697   {
00698     { 0, 0, 0, 0 },
00699     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00700     & ifmt_machi_a, { 0x3070 }
00701   },
00702 /* mul $dr,$sr */
00703   {
00704     { 0, 0, 0, 0 },
00705     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00706     & ifmt_add, { 0x1060 }
00707   },
00708 /* mulhi $src1,$src2 */
00709   {
00710     { 0, 0, 0, 0 },
00711     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00712     & ifmt_cmp, { 0x3000 }
00713   },
00714 /* mulhi $src1,$src2,$acc */
00715   {
00716     { 0, 0, 0, 0 },
00717     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00718     & ifmt_machi_a, { 0x3000 }
00719   },
00720 /* mullo $src1,$src2 */
00721   {
00722     { 0, 0, 0, 0 },
00723     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00724     & ifmt_cmp, { 0x3010 }
00725   },
00726 /* mullo $src1,$src2,$acc */
00727   {
00728     { 0, 0, 0, 0 },
00729     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00730     & ifmt_machi_a, { 0x3010 }
00731   },
00732 /* mulwhi $src1,$src2 */
00733   {
00734     { 0, 0, 0, 0 },
00735     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00736     & ifmt_cmp, { 0x3020 }
00737   },
00738 /* mulwhi $src1,$src2,$acc */
00739   {
00740     { 0, 0, 0, 0 },
00741     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00742     & ifmt_machi_a, { 0x3020 }
00743   },
00744 /* mulwlo $src1,$src2 */
00745   {
00746     { 0, 0, 0, 0 },
00747     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
00748     & ifmt_cmp, { 0x3030 }
00749   },
00750 /* mulwlo $src1,$src2,$acc */
00751   {
00752     { 0, 0, 0, 0 },
00753     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
00754     & ifmt_machi_a, { 0x3030 }
00755   },
00756 /* mv $dr,$sr */
00757   {
00758     { 0, 0, 0, 0 },
00759     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00760     & ifmt_add, { 0x1080 }
00761   },
00762 /* mvfachi $dr */
00763   {
00764     { 0, 0, 0, 0 },
00765     { { MNEM, ' ', OP (DR), 0 } },
00766     & ifmt_mvfachi, { 0x50f0 }
00767   },
00768 /* mvfachi $dr,$accs */
00769   {
00770     { 0, 0, 0, 0 },
00771     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
00772     & ifmt_mvfachi_a, { 0x50f0 }
00773   },
00774 /* mvfaclo $dr */
00775   {
00776     { 0, 0, 0, 0 },
00777     { { MNEM, ' ', OP (DR), 0 } },
00778     & ifmt_mvfachi, { 0x50f1 }
00779   },
00780 /* mvfaclo $dr,$accs */
00781   {
00782     { 0, 0, 0, 0 },
00783     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
00784     & ifmt_mvfachi_a, { 0x50f1 }
00785   },
00786 /* mvfacmi $dr */
00787   {
00788     { 0, 0, 0, 0 },
00789     { { MNEM, ' ', OP (DR), 0 } },
00790     & ifmt_mvfachi, { 0x50f2 }
00791   },
00792 /* mvfacmi $dr,$accs */
00793   {
00794     { 0, 0, 0, 0 },
00795     { { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 } },
00796     & ifmt_mvfachi_a, { 0x50f2 }
00797   },
00798 /* mvfc $dr,$scr */
00799   {
00800     { 0, 0, 0, 0 },
00801     { { MNEM, ' ', OP (DR), ',', OP (SCR), 0 } },
00802     & ifmt_mvfc, { 0x1090 }
00803   },
00804 /* mvtachi $src1 */
00805   {
00806     { 0, 0, 0, 0 },
00807     { { MNEM, ' ', OP (SRC1), 0 } },
00808     & ifmt_mvtachi, { 0x5070 }
00809   },
00810 /* mvtachi $src1,$accs */
00811   {
00812     { 0, 0, 0, 0 },
00813     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
00814     & ifmt_mvtachi_a, { 0x5070 }
00815   },
00816 /* mvtaclo $src1 */
00817   {
00818     { 0, 0, 0, 0 },
00819     { { MNEM, ' ', OP (SRC1), 0 } },
00820     & ifmt_mvtachi, { 0x5071 }
00821   },
00822 /* mvtaclo $src1,$accs */
00823   {
00824     { 0, 0, 0, 0 },
00825     { { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 } },
00826     & ifmt_mvtachi_a, { 0x5071 }
00827   },
00828 /* mvtc $sr,$dcr */
00829   {
00830     { 0, 0, 0, 0 },
00831     { { MNEM, ' ', OP (SR), ',', OP (DCR), 0 } },
00832     & ifmt_mvtc, { 0x10a0 }
00833   },
00834 /* neg $dr,$sr */
00835   {
00836     { 0, 0, 0, 0 },
00837     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00838     & ifmt_add, { 0x30 }
00839   },
00840 /* nop */
00841   {
00842     { 0, 0, 0, 0 },
00843     { { MNEM, 0 } },
00844     & ifmt_nop, { 0x7000 }
00845   },
00846 /* not $dr,$sr */
00847   {
00848     { 0, 0, 0, 0 },
00849     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00850     & ifmt_add, { 0xb0 }
00851   },
00852 /* rac */
00853   {
00854     { 0, 0, 0, 0 },
00855     { { MNEM, 0 } },
00856     & ifmt_nop, { 0x5090 }
00857   },
00858 /* rac $accd,$accs,$imm1 */
00859   {
00860     { 0, 0, 0, 0 },
00861     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
00862     & ifmt_rac_dsi, { 0x5090 }
00863   },
00864 /* rach */
00865   {
00866     { 0, 0, 0, 0 },
00867     { { MNEM, 0 } },
00868     & ifmt_nop, { 0x5080 }
00869   },
00870 /* rach $accd,$accs,$imm1 */
00871   {
00872     { 0, 0, 0, 0 },
00873     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', OP (IMM1), 0 } },
00874     & ifmt_rac_dsi, { 0x5080 }
00875   },
00876 /* rte */
00877   {
00878     { 0, 0, 0, 0 },
00879     { { MNEM, 0 } },
00880     & ifmt_nop, { 0x10d6 }
00881   },
00882 /* seth $dr,$hash$hi16 */
00883   {
00884     { 0, 0, 0, 0 },
00885     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (HI16), 0 } },
00886     & ifmt_seth, { 0xd0c00000 }
00887   },
00888 /* sll $dr,$sr */
00889   {
00890     { 0, 0, 0, 0 },
00891     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00892     & ifmt_add, { 0x1040 }
00893   },
00894 /* sll3 $dr,$sr,$simm16 */
00895   {
00896     { 0, 0, 0, 0 },
00897     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
00898     & ifmt_addv3, { 0x90c00000 }
00899   },
00900 /* slli $dr,$uimm5 */
00901   {
00902     { 0, 0, 0, 0 },
00903     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
00904     & ifmt_slli, { 0x5040 }
00905   },
00906 /* sra $dr,$sr */
00907   {
00908     { 0, 0, 0, 0 },
00909     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00910     & ifmt_add, { 0x1020 }
00911   },
00912 /* sra3 $dr,$sr,$simm16 */
00913   {
00914     { 0, 0, 0, 0 },
00915     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
00916     & ifmt_addv3, { 0x90a00000 }
00917   },
00918 /* srai $dr,$uimm5 */
00919   {
00920     { 0, 0, 0, 0 },
00921     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
00922     & ifmt_slli, { 0x5020 }
00923   },
00924 /* srl $dr,$sr */
00925   {
00926     { 0, 0, 0, 0 },
00927     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
00928     & ifmt_add, { 0x1000 }
00929   },
00930 /* srl3 $dr,$sr,$simm16 */
00931   {
00932     { 0, 0, 0, 0 },
00933     { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
00934     & ifmt_addv3, { 0x90800000 }
00935   },
00936 /* srli $dr,$uimm5 */
00937   {
00938     { 0, 0, 0, 0 },
00939     { { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 } },
00940     & ifmt_slli, { 0x5000 }
00941   },
00942 /* st $src1,@$src2 */
00943   {
00944     { 0, 0, 0, 0 },
00945     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
00946     & ifmt_cmp, { 0x2040 }
00947   },
00948 /* st $src1,@($slo16,$src2) */
00949   {
00950     { 0, 0, 0, 0 },
00951     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
00952     & ifmt_st_d, { 0xa0400000 }
00953   },
00954 /* stb $src1,@$src2 */
00955   {
00956     { 0, 0, 0, 0 },
00957     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
00958     & ifmt_cmp, { 0x2000 }
00959   },
00960 /* stb $src1,@($slo16,$src2) */
00961   {
00962     { 0, 0, 0, 0 },
00963     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
00964     & ifmt_st_d, { 0xa0000000 }
00965   },
00966 /* sth $src1,@$src2 */
00967   {
00968     { 0, 0, 0, 0 },
00969     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
00970     & ifmt_cmp, { 0x2020 }
00971   },
00972 /* sth $src1,@($slo16,$src2) */
00973   {
00974     { 0, 0, 0, 0 },
00975     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 } },
00976     & ifmt_st_d, { 0xa0200000 }
00977   },
00978 /* st $src1,@+$src2 */
00979   {
00980     { 0, 0, 0, 0 },
00981     { { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 } },
00982     & ifmt_cmp, { 0x2060 }
00983   },
00984 /* sth $src1,@$src2+ */
00985   {
00986     { 0, 0, 0, 0 },
00987     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
00988     & ifmt_cmp, { 0x2030 }
00989   },
00990 /* stb $src1,@$src2+ */
00991   {
00992     { 0, 0, 0, 0 },
00993     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), '+', 0 } },
00994     & ifmt_cmp, { 0x2010 }
00995   },
00996 /* st $src1,@-$src2 */
00997   {
00998     { 0, 0, 0, 0 },
00999     { { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 } },
01000     & ifmt_cmp, { 0x2070 }
01001   },
01002 /* sub $dr,$sr */
01003   {
01004     { 0, 0, 0, 0 },
01005     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01006     & ifmt_add, { 0x20 }
01007   },
01008 /* subv $dr,$sr */
01009   {
01010     { 0, 0, 0, 0 },
01011     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01012     & ifmt_add, { 0x0 }
01013   },
01014 /* subx $dr,$sr */
01015   {
01016     { 0, 0, 0, 0 },
01017     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01018     & ifmt_add, { 0x10 }
01019   },
01020 /* trap $uimm4 */
01021   {
01022     { 0, 0, 0, 0 },
01023     { { MNEM, ' ', OP (UIMM4), 0 } },
01024     & ifmt_trap, { 0x10f0 }
01025   },
01026 /* unlock $src1,@$src2 */
01027   {
01028     { 0, 0, 0, 0 },
01029     { { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 } },
01030     & ifmt_cmp, { 0x2050 }
01031   },
01032 /* satb $dr,$sr */
01033   {
01034     { 0, 0, 0, 0 },
01035     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01036     & ifmt_satb, { 0x80600300 }
01037   },
01038 /* sath $dr,$sr */
01039   {
01040     { 0, 0, 0, 0 },
01041     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01042     & ifmt_satb, { 0x80600200 }
01043   },
01044 /* sat $dr,$sr */
01045   {
01046     { 0, 0, 0, 0 },
01047     { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
01048     & ifmt_satb, { 0x80600000 }
01049   },
01050 /* pcmpbz $src2 */
01051   {
01052     { 0, 0, 0, 0 },
01053     { { MNEM, ' ', OP (SRC2), 0 } },
01054     & ifmt_cmpz, { 0x370 }
01055   },
01056 /* sadd */
01057   {
01058     { 0, 0, 0, 0 },
01059     { { MNEM, 0 } },
01060     & ifmt_nop, { 0x50e4 }
01061   },
01062 /* macwu1 $src1,$src2 */
01063   {
01064     { 0, 0, 0, 0 },
01065     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
01066     & ifmt_cmp, { 0x50b0 }
01067   },
01068 /* msblo $src1,$src2 */
01069   {
01070     { 0, 0, 0, 0 },
01071     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
01072     & ifmt_cmp, { 0x50d0 }
01073   },
01074 /* mulwu1 $src1,$src2 */
01075   {
01076     { 0, 0, 0, 0 },
01077     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
01078     & ifmt_cmp, { 0x50a0 }
01079   },
01080 /* maclh1 $src1,$src2 */
01081   {
01082     { 0, 0, 0, 0 },
01083     { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
01084     & ifmt_cmp, { 0x50c0 }
01085   },
01086 /* sc */
01087   {
01088     { 0, 0, 0, 0 },
01089     { { MNEM, 0 } },
01090     & ifmt_nop, { 0x7401 }
01091   },
01092 /* snc */
01093   {
01094     { 0, 0, 0, 0 },
01095     { { MNEM, 0 } },
01096     & ifmt_nop, { 0x7501 }
01097   },
01098 /* clrpsw $uimm8 */
01099   {
01100     { 0, 0, 0, 0 },
01101     { { MNEM, ' ', OP (UIMM8), 0 } },
01102     & ifmt_clrpsw, { 0x7200 }
01103   },
01104 /* setpsw $uimm8 */
01105   {
01106     { 0, 0, 0, 0 },
01107     { { MNEM, ' ', OP (UIMM8), 0 } },
01108     & ifmt_clrpsw, { 0x7100 }
01109   },
01110 /* bset $uimm3,@($slo16,$sr) */
01111   {
01112     { 0, 0, 0, 0 },
01113     { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
01114     & ifmt_bset, { 0xa0600000 }
01115   },
01116 /* bclr $uimm3,@($slo16,$sr) */
01117   {
01118     { 0, 0, 0, 0 },
01119     { { MNEM, ' ', OP (UIMM3), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 } },
01120     & ifmt_bset, { 0xa0700000 }
01121   },
01122 /* btst $uimm3,$sr */
01123   {
01124     { 0, 0, 0, 0 },
01125     { { MNEM, ' ', OP (UIMM3), ',', OP (SR), 0 } },
01126     & ifmt_btst, { 0xf0 }
01127   },
01128 };
01129 
01130 #undef A
01131 #undef OPERAND
01132 #undef MNEM
01133 #undef OP
01134 
01135 /* Formats for ALIAS macro-insns.  */
01136 
01137 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
01138 #define F(f) & m32r_cgen_ifld_table[M32R_##f]
01139 #else
01140 #define F(f) & m32r_cgen_ifld_table[M32R_f]
01141 #endif
01142 static const CGEN_IFMT ifmt_bc8r ATTRIBUTE_UNUSED = {
01143   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01144 };
01145 
01146 static const CGEN_IFMT ifmt_bc24r ATTRIBUTE_UNUSED = {
01147   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01148 };
01149 
01150 static const CGEN_IFMT ifmt_bl8r ATTRIBUTE_UNUSED = {
01151   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01152 };
01153 
01154 static const CGEN_IFMT ifmt_bl24r ATTRIBUTE_UNUSED = {
01155   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01156 };
01157 
01158 static const CGEN_IFMT ifmt_bcl8r ATTRIBUTE_UNUSED = {
01159   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01160 };
01161 
01162 static const CGEN_IFMT ifmt_bcl24r ATTRIBUTE_UNUSED = {
01163   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01164 };
01165 
01166 static const CGEN_IFMT ifmt_bnc8r ATTRIBUTE_UNUSED = {
01167   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01168 };
01169 
01170 static const CGEN_IFMT ifmt_bnc24r ATTRIBUTE_UNUSED = {
01171   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01172 };
01173 
01174 static const CGEN_IFMT ifmt_bra8r ATTRIBUTE_UNUSED = {
01175   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01176 };
01177 
01178 static const CGEN_IFMT ifmt_bra24r ATTRIBUTE_UNUSED = {
01179   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01180 };
01181 
01182 static const CGEN_IFMT ifmt_bncl8r ATTRIBUTE_UNUSED = {
01183   16, 16, 0xff00, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP8) }, { 0 } }
01184 };
01185 
01186 static const CGEN_IFMT ifmt_bncl24r ATTRIBUTE_UNUSED = {
01187   32, 32, 0xff000000, { { F (F_OP1) }, { F (F_R1) }, { F (F_DISP24) }, { 0 } }
01188 };
01189 
01190 static const CGEN_IFMT ifmt_ld_2 ATTRIBUTE_UNUSED = {
01191   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01192 };
01193 
01194 static const CGEN_IFMT ifmt_ld_d2 ATTRIBUTE_UNUSED = {
01195   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01196 };
01197 
01198 static const CGEN_IFMT ifmt_ldb_2 ATTRIBUTE_UNUSED = {
01199   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01200 };
01201 
01202 static const CGEN_IFMT ifmt_ldb_d2 ATTRIBUTE_UNUSED = {
01203   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01204 };
01205 
01206 static const CGEN_IFMT ifmt_ldh_2 ATTRIBUTE_UNUSED = {
01207   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01208 };
01209 
01210 static const CGEN_IFMT ifmt_ldh_d2 ATTRIBUTE_UNUSED = {
01211   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01212 };
01213 
01214 static const CGEN_IFMT ifmt_ldub_2 ATTRIBUTE_UNUSED = {
01215   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01216 };
01217 
01218 static const CGEN_IFMT ifmt_ldub_d2 ATTRIBUTE_UNUSED = {
01219   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01220 };
01221 
01222 static const CGEN_IFMT ifmt_lduh_2 ATTRIBUTE_UNUSED = {
01223   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01224 };
01225 
01226 static const CGEN_IFMT ifmt_lduh_d2 ATTRIBUTE_UNUSED = {
01227   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01228 };
01229 
01230 static const CGEN_IFMT ifmt_pop ATTRIBUTE_UNUSED = {
01231   16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_R1) }, { F (F_OP2) }, { F (F_R2) }, { 0 } }
01232 };
01233 
01234 static const CGEN_IFMT ifmt_ldi8a ATTRIBUTE_UNUSED = {
01235   16, 16, 0xf000, { { F (F_OP1) }, { F (F_R1) }, { F (F_SIMM8) }, { 0 } }
01236 };
01237 
01238 static const CGEN_IFMT ifmt_ldi16a ATTRIBUTE_UNUSED = {
01239   32, 32, 0xf0ff0000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R2) }, { F (F_R1) }, { F (F_SIMM16) }, { 0 } }
01240 };
01241 
01242 static const CGEN_IFMT ifmt_rac_d ATTRIBUTE_UNUSED = {
01243   16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
01244 };
01245 
01246 static const CGEN_IFMT ifmt_rac_ds ATTRIBUTE_UNUSED = {
01247   16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
01248 };
01249 
01250 static const CGEN_IFMT ifmt_rach_d ATTRIBUTE_UNUSED = {
01251   16, 16, 0xf3ff, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
01252 };
01253 
01254 static const CGEN_IFMT ifmt_rach_ds ATTRIBUTE_UNUSED = {
01255   16, 16, 0xf3f3, { { F (F_OP1) }, { F (F_ACCD) }, { F (F_BITS67) }, { F (F_OP2) }, { F (F_ACCS) }, { F (F_BIT14) }, { F (F_IMM1) }, { 0 } }
01256 };
01257 
01258 static const CGEN_IFMT ifmt_st_2 ATTRIBUTE_UNUSED = {
01259   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01260 };
01261 
01262 static const CGEN_IFMT ifmt_st_d2 ATTRIBUTE_UNUSED = {
01263   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01264 };
01265 
01266 static const CGEN_IFMT ifmt_stb_2 ATTRIBUTE_UNUSED = {
01267   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01268 };
01269 
01270 static const CGEN_IFMT ifmt_stb_d2 ATTRIBUTE_UNUSED = {
01271   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01272 };
01273 
01274 static const CGEN_IFMT ifmt_sth_2 ATTRIBUTE_UNUSED = {
01275   16, 16, 0xf0f0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01276 };
01277 
01278 static const CGEN_IFMT ifmt_sth_d2 ATTRIBUTE_UNUSED = {
01279   32, 32, 0xf0f00000, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { F (F_SIMM16) }, { 0 } }
01280 };
01281 
01282 static const CGEN_IFMT ifmt_push ATTRIBUTE_UNUSED = {
01283   16, 16, 0xf0ff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_R1) }, { F (F_R2) }, { 0 } }
01284 };
01285 
01286 #undef F
01287 
01288 /* Each non-simple macro entry points to an array of expansion possibilities.  */
01289 
01290 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
01291 #define A(a) (1 << CGEN_INSN_##a)
01292 #else
01293 #define A(a) (1 << CGEN_INSN_a)
01294 #endif
01295 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
01296 #define OPERAND(op) M32R_OPERAND_##op
01297 #else
01298 #define OPERAND(op) M32R_OPERAND_op
01299 #endif
01300 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
01301 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
01302 
01303 /* The macro instruction table.  */
01304 
01305 static const CGEN_IBASE m32r_cgen_macro_insn_table[] =
01306 {
01307 /* bc $disp8 */
01308   {
01309     -1, "bc8r", "bc", 16,
01310     { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01311   },
01312 /* bc $disp24 */
01313   {
01314     -1, "bc24r", "bc", 32,
01315     { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01316   },
01317 /* bl $disp8 */
01318   {
01319     -1, "bl8r", "bl", 16,
01320     { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01321   },
01322 /* bl $disp24 */
01323   {
01324     -1, "bl24r", "bl", 32,
01325     { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01326   },
01327 /* bcl $disp8 */
01328   {
01329     -1, "bcl8r", "bcl", 16,
01330     { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
01331   },
01332 /* bcl $disp24 */
01333   {
01334     -1, "bcl24r", "bcl", 32,
01335     { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
01336   },
01337 /* bnc $disp8 */
01338   {
01339     -1, "bnc8r", "bnc", 16,
01340     { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01341   },
01342 /* bnc $disp24 */
01343   {
01344     -1, "bnc24r", "bnc", 32,
01345     { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01346   },
01347 /* bra $disp8 */
01348   {
01349     -1, "bra8r", "bra", 16,
01350     { 0|A(RELAXABLE)|A(FILL_SLOT)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01351   },
01352 /* bra $disp24 */
01353   {
01354     -1, "bra24r", "bra", 32,
01355     { 0|A(RELAXED)|A(UNCOND_CTI)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01356   },
01357 /* bncl $disp8 */
01358   {
01359     -1, "bncl8r", "bncl", 16,
01360     { 0|A(RELAXABLE)|A(FILL_SLOT)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_O } }
01361   },
01362 /* bncl $disp24 */
01363   {
01364     -1, "bncl24r", "bncl", 32,
01365     { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_NONE } }
01366   },
01367 /* ld $dr,@($sr) */
01368   {
01369     -1, "ld-2", "ld", 16,
01370     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01371   },
01372 /* ld $dr,@($sr,$slo16) */
01373   {
01374     -1, "ld-d2", "ld", 32,
01375     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01376   },
01377 /* ldb $dr,@($sr) */
01378   {
01379     -1, "ldb-2", "ldb", 16,
01380     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01381   },
01382 /* ldb $dr,@($sr,$slo16) */
01383   {
01384     -1, "ldb-d2", "ldb", 32,
01385     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01386   },
01387 /* ldh $dr,@($sr) */
01388   {
01389     -1, "ldh-2", "ldh", 16,
01390     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01391   },
01392 /* ldh $dr,@($sr,$slo16) */
01393   {
01394     -1, "ldh-d2", "ldh", 32,
01395     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01396   },
01397 /* ldub $dr,@($sr) */
01398   {
01399     -1, "ldub-2", "ldub", 16,
01400     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01401   },
01402 /* ldub $dr,@($sr,$slo16) */
01403   {
01404     -1, "ldub-d2", "ldub", 32,
01405     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01406   },
01407 /* lduh $dr,@($sr) */
01408   {
01409     -1, "lduh-2", "lduh", 16,
01410     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01411   },
01412 /* lduh $dr,@($sr,$slo16) */
01413   {
01414     -1, "lduh-d2", "lduh", 32,
01415     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01416   },
01417 /* pop $dr */
01418   {
01419     -1, "pop", "pop", 16,
01420     { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01421   },
01422 /* ldi $dr,$simm8 */
01423   {
01424     -1, "ldi8a", "ldi", 16,
01425     { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_OS } }
01426   },
01427 /* ldi $dr,$hash$slo16 */
01428   {
01429     -1, "ldi16a", "ldi", 32,
01430     { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01431   },
01432 /* rac $accd */
01433   {
01434     -1, "rac-d", "rac", 16,
01435     { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01436   },
01437 /* rac $accd,$accs */
01438   {
01439     -1, "rac-ds", "rac", 16,
01440     { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01441   },
01442 /* rach $accd */
01443   {
01444     -1, "rach-d", "rach", 16,
01445     { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01446   },
01447 /* rach $accd,$accs */
01448   {
01449     -1, "rach-ds", "rach", 16,
01450     { 0|A(ALIAS), { (1<<MACH_M32RX)|(1<<MACH_M32R2), PIPE_S } }
01451   },
01452 /* st $src1,@($src2) */
01453   {
01454     -1, "st-2", "st", 16,
01455     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01456   },
01457 /* st $src1,@($src2,$slo16) */
01458   {
01459     -1, "st-d2", "st", 32,
01460     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01461   },
01462 /* stb $src1,@($src2) */
01463   {
01464     -1, "stb-2", "stb", 16,
01465     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01466   },
01467 /* stb $src1,@($src2,$slo16) */
01468   {
01469     -1, "stb-d2", "stb", 32,
01470     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01471   },
01472 /* sth $src1,@($src2) */
01473   {
01474     -1, "sth-2", "sth", 16,
01475     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01476   },
01477 /* sth $src1,@($src2,$slo16) */
01478   {
01479     -1, "sth-d2", "sth", 32,
01480     { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), PIPE_NONE } }
01481   },
01482 /* push $src1 */
01483   {
01484     -1, "push", "push", 16,
01485     { 0|A(ALIAS), { (1<<MACH_BASE), PIPE_O } }
01486   },
01487 };
01488 
01489 /* The macro instruction opcode table.  */
01490 
01491 static const CGEN_OPCODE m32r_cgen_macro_insn_opcode_table[] =
01492 {
01493 /* bc $disp8 */
01494   {
01495     { 0, 0, 0, 0 },
01496     { { MNEM, ' ', OP (DISP8), 0 } },
01497     & ifmt_bc8r, { 0x7c00 }
01498   },
01499 /* bc $disp24 */
01500   {
01501     { 0, 0, 0, 0 },
01502     { { MNEM, ' ', OP (DISP24), 0 } },
01503     & ifmt_bc24r, { 0xfc000000 }
01504   },
01505 /* bl $disp8 */
01506   {
01507     { 0, 0, 0, 0 },
01508     { { MNEM, ' ', OP (DISP8), 0 } },
01509     & ifmt_bl8r, { 0x7e00 }
01510   },
01511 /* bl $disp24 */
01512   {
01513     { 0, 0, 0, 0 },
01514     { { MNEM, ' ', OP (DISP24), 0 } },
01515     & ifmt_bl24r, { 0xfe000000 }
01516   },
01517 /* bcl $disp8 */
01518   {
01519     { 0, 0, 0, 0 },
01520     { { MNEM, ' ', OP (DISP8), 0 } },
01521     & ifmt_bcl8r, { 0x7800 }
01522   },
01523 /* bcl $disp24 */
01524   {
01525     { 0, 0, 0, 0 },
01526     { { MNEM, ' ', OP (DISP24), 0 } },
01527     & ifmt_bcl24r, { 0xf8000000 }
01528   },
01529 /* bnc $disp8 */
01530   {
01531     { 0, 0, 0, 0 },
01532     { { MNEM, ' ', OP (DISP8), 0 } },
01533     & ifmt_bnc8r, { 0x7d00 }
01534   },
01535 /* bnc $disp24 */
01536   {
01537     { 0, 0, 0, 0 },
01538     { { MNEM, ' ', OP (DISP24), 0 } },
01539     & ifmt_bnc24r, { 0xfd000000 }
01540   },
01541 /* bra $disp8 */
01542   {
01543     { 0, 0, 0, 0 },
01544     { { MNEM, ' ', OP (DISP8), 0 } },
01545     & ifmt_bra8r, { 0x7f00 }
01546   },
01547 /* bra $disp24 */
01548   {
01549     { 0, 0, 0, 0 },
01550     { { MNEM, ' ', OP (DISP24), 0 } },
01551     & ifmt_bra24r, { 0xff000000 }
01552   },
01553 /* bncl $disp8 */
01554   {
01555     { 0, 0, 0, 0 },
01556     { { MNEM, ' ', OP (DISP8), 0 } },
01557     & ifmt_bncl8r, { 0x7900 }
01558   },
01559 /* bncl $disp24 */
01560   {
01561     { 0, 0, 0, 0 },
01562     { { MNEM, ' ', OP (DISP24), 0 } },
01563     & ifmt_bncl24r, { 0xf9000000 }
01564   },
01565 /* ld $dr,@($sr) */
01566   {
01567     { 0, 0, 0, 0 },
01568     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01569     & ifmt_ld_2, { 0x20c0 }
01570   },
01571 /* ld $dr,@($sr,$slo16) */
01572   {
01573     { 0, 0, 0, 0 },
01574     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01575     & ifmt_ld_d2, { 0xa0c00000 }
01576   },
01577 /* ldb $dr,@($sr) */
01578   {
01579     { 0, 0, 0, 0 },
01580     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01581     & ifmt_ldb_2, { 0x2080 }
01582   },
01583 /* ldb $dr,@($sr,$slo16) */
01584   {
01585     { 0, 0, 0, 0 },
01586     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01587     & ifmt_ldb_d2, { 0xa0800000 }
01588   },
01589 /* ldh $dr,@($sr) */
01590   {
01591     { 0, 0, 0, 0 },
01592     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01593     & ifmt_ldh_2, { 0x20a0 }
01594   },
01595 /* ldh $dr,@($sr,$slo16) */
01596   {
01597     { 0, 0, 0, 0 },
01598     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01599     & ifmt_ldh_d2, { 0xa0a00000 }
01600   },
01601 /* ldub $dr,@($sr) */
01602   {
01603     { 0, 0, 0, 0 },
01604     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01605     & ifmt_ldub_2, { 0x2090 }
01606   },
01607 /* ldub $dr,@($sr,$slo16) */
01608   {
01609     { 0, 0, 0, 0 },
01610     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01611     & ifmt_ldub_d2, { 0xa0900000 }
01612   },
01613 /* lduh $dr,@($sr) */
01614   {
01615     { 0, 0, 0, 0 },
01616     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 } },
01617     & ifmt_lduh_2, { 0x20b0 }
01618   },
01619 /* lduh $dr,@($sr,$slo16) */
01620   {
01621     { 0, 0, 0, 0 },
01622     { { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 } },
01623     & ifmt_lduh_d2, { 0xa0b00000 }
01624   },
01625 /* pop $dr */
01626   {
01627     { 0, 0, 0, 0 },
01628     { { MNEM, ' ', OP (DR), 0 } },
01629     & ifmt_pop, { 0x20ef }
01630   },
01631 /* ldi $dr,$simm8 */
01632   {
01633     { 0, 0, 0, 0 },
01634     { { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 } },
01635     & ifmt_ldi8a, { 0x6000 }
01636   },
01637 /* ldi $dr,$hash$slo16 */
01638   {
01639     { 0, 0, 0, 0 },
01640     { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (SLO16), 0 } },
01641     & ifmt_ldi16a, { 0x90f00000 }
01642   },
01643 /* rac $accd */
01644   {
01645     { 0, 0, 0, 0 },
01646     { { MNEM, ' ', OP (ACCD), 0 } },
01647     & ifmt_rac_d, { 0x5090 }
01648   },
01649 /* rac $accd,$accs */
01650   {
01651     { 0, 0, 0, 0 },
01652     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
01653     & ifmt_rac_ds, { 0x5090 }
01654   },
01655 /* rach $accd */
01656   {
01657     { 0, 0, 0, 0 },
01658     { { MNEM, ' ', OP (ACCD), 0 } },
01659     & ifmt_rach_d, { 0x5080 }
01660   },
01661 /* rach $accd,$accs */
01662   {
01663     { 0, 0, 0, 0 },
01664     { { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 } },
01665     & ifmt_rach_ds, { 0x5080 }
01666   },
01667 /* st $src1,@($src2) */
01668   {
01669     { 0, 0, 0, 0 },
01670     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
01671     & ifmt_st_2, { 0x2040 }
01672   },
01673 /* st $src1,@($src2,$slo16) */
01674   {
01675     { 0, 0, 0, 0 },
01676     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
01677     & ifmt_st_d2, { 0xa0400000 }
01678   },
01679 /* stb $src1,@($src2) */
01680   {
01681     { 0, 0, 0, 0 },
01682     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
01683     & ifmt_stb_2, { 0x2000 }
01684   },
01685 /* stb $src1,@($src2,$slo16) */
01686   {
01687     { 0, 0, 0, 0 },
01688     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
01689     & ifmt_stb_d2, { 0xa0000000 }
01690   },
01691 /* sth $src1,@($src2) */
01692   {
01693     { 0, 0, 0, 0 },
01694     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 } },
01695     & ifmt_sth_2, { 0x2020 }
01696   },
01697 /* sth $src1,@($src2,$slo16) */
01698   {
01699     { 0, 0, 0, 0 },
01700     { { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 } },
01701     & ifmt_sth_d2, { 0xa0200000 }
01702   },
01703 /* push $src1 */
01704   {
01705     { 0, 0, 0, 0 },
01706     { { MNEM, ' ', OP (SRC1), 0 } },
01707     & ifmt_push, { 0x207f }
01708   },
01709 };
01710 
01711 #undef A
01712 #undef OPERAND
01713 #undef MNEM
01714 #undef OP
01715 
01716 #ifndef CGEN_ASM_HASH_P
01717 #define CGEN_ASM_HASH_P(insn) 1
01718 #endif
01719 
01720 #ifndef CGEN_DIS_HASH_P
01721 #define CGEN_DIS_HASH_P(insn) 1
01722 #endif
01723 
01724 /* Return non-zero if INSN is to be added to the hash table.
01725    Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
01726 
01727 static int
01728 asm_hash_insn_p (insn)
01729      const CGEN_INSN *insn ATTRIBUTE_UNUSED;
01730 {
01731   return CGEN_ASM_HASH_P (insn);
01732 }
01733 
01734 static int
01735 dis_hash_insn_p (insn)
01736      const CGEN_INSN *insn;
01737 {
01738   /* If building the hash table and the NO-DIS attribute is present,
01739      ignore.  */
01740   if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
01741     return 0;
01742   return CGEN_DIS_HASH_P (insn);
01743 }
01744 
01745 #ifndef CGEN_ASM_HASH
01746 #define CGEN_ASM_HASH_SIZE 127
01747 #ifdef CGEN_MNEMONIC_OPERANDS
01748 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
01749 #else
01750 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
01751 #endif
01752 #endif
01753 
01754 /* It doesn't make much sense to provide a default here,
01755    but while this is under development we do.
01756    BUFFER is a pointer to the bytes of the insn, target order.
01757    VALUE is the first base_insn_bitsize bits as an int in host order.  */
01758 
01759 #ifndef CGEN_DIS_HASH
01760 #define CGEN_DIS_HASH_SIZE 256
01761 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
01762 #endif
01763 
01764 /* The result is the hash value of the insn.
01765    Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
01766 
01767 static unsigned int
01768 asm_hash_insn (mnem)
01769      const char * mnem;
01770 {
01771   return CGEN_ASM_HASH (mnem);
01772 }
01773 
01774 /* BUF is a pointer to the bytes of the insn, target order.
01775    VALUE is the first base_insn_bitsize bits as an int in host order.  */
01776 
01777 static unsigned int
01778 dis_hash_insn (buf, value)
01779      const char * buf ATTRIBUTE_UNUSED;
01780      CGEN_INSN_INT value ATTRIBUTE_UNUSED;
01781 {
01782   return CGEN_DIS_HASH (buf, value);
01783 }
01784 
01785 static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
01786 
01787 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
01788 
01789 static void
01790 set_fields_bitsize (fields, size)
01791      CGEN_FIELDS *fields;
01792      int size;
01793 {
01794   CGEN_FIELDS_BITSIZE (fields) = size;
01795 }
01796 
01797 /* Function to call before using the operand instance table.
01798    This plugs the opcode entries and macro instructions into the cpu table.  */
01799 
01800 void
01801 m32r_cgen_init_opcode_table (cd)
01802      CGEN_CPU_DESC cd;
01803 {
01804   int i;
01805   int num_macros = (sizeof (m32r_cgen_macro_insn_table) /
01806         sizeof (m32r_cgen_macro_insn_table[0]));
01807   const CGEN_IBASE *ib = & m32r_cgen_macro_insn_table[0];
01808   const CGEN_OPCODE *oc = & m32r_cgen_macro_insn_opcode_table[0];
01809   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (num_macros * sizeof (CGEN_INSN));
01810   memset (insns, 0, num_macros * sizeof (CGEN_INSN));
01811   for (i = 0; i < num_macros; ++i)
01812     {
01813       insns[i].base = &ib[i];
01814       insns[i].opcode = &oc[i];
01815       m32r_cgen_build_insn_regex (& insns[i]);
01816     }
01817   cd->macro_insn_table.init_entries = insns;
01818   cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
01819   cd->macro_insn_table.num_init_entries = num_macros;
01820 
01821   oc = & m32r_cgen_insn_opcode_table[0];
01822   insns = (CGEN_INSN *) cd->insn_table.init_entries;
01823   for (i = 0; i < MAX_INSNS; ++i)
01824     {
01825       insns[i].opcode = &oc[i];
01826       m32r_cgen_build_insn_regex (& insns[i]);
01827     }
01828 
01829   cd->sizeof_fields = sizeof (CGEN_FIELDS);
01830   cd->set_fields_bitsize = set_fields_bitsize;
01831 
01832   cd->asm_hash_p = asm_hash_insn_p;
01833   cd->asm_hash = asm_hash_insn;
01834   cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
01835 
01836   cd->dis_hash_p = dis_hash_insn_p;
01837   cd->dis_hash = dis_hash_insn;
01838   cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
01839 }