Open64: osprey/be/cg/MIPS/cgtarget.cxx Source File

00001 /*
00002  * Copyright 2002, 2003, 2004 PathScale, Inc.  All Rights Reserved.
00003  */
00004 
00005 /*
00006 
00007   Copyright (C) 2000, 2001 Silicon Graphics, Inc.  All Rights Reserved.
00008 
00009   This program is free software; you can redistribute it and/or modify it
00010   under the terms of version 2 of the GNU General Public License as
00011   published by the Free Software Foundation.
00012 
00013   This program is distributed in the hope that it would be useful, but
00014   WITHOUT ANY WARRANTY; without even the implied warranty of
00015   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
00016 
00017   Further, this software is distributed without any warranty that it is
00018   free of the rightful claim of any third person regarding infringement 
00019   or the like.  Any license provided herein, whether implied or 
00020   otherwise, applies only to this software file.  Patent licenses, if 
00021   any, provided herein do not apply to combinations of this program with 
00022   other software, or any other product whatsoever.  
00023 
00024   You should have received a copy of the GNU General Public License along
00025   with this program; if not, write the Free Software Foundation, Inc., 59
00026   Temple Place - Suite 330, Boston MA 02111-1307, USA.
00027 
00028   Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pky,
00029   Mountain View, CA 94043, or:
00030 
00031   http://www.sgi.com
00032 
00033   For further information regarding this notice, see:
00034 
00035   http://oss.sgi.com/projects/GenInfo/NoticeExplan
00036 
00037 */
00038 
00039 
00040 /* ====================================================================
00041  * ====================================================================
00042  *
00043  * Module: cgtarget.cxx
00044  * $Revision: 1.4 $
00045  * $Date: 2006/06/13 02:11:08 $
00046  * $Author: weitang $
00047  * $Source: /depot/CVSROOT/javi/src/sw/cmplr/be/cg/MIPS/cgtarget.cxx,v $
00048  *
00049  * Description:
00050  *
00051  * Support routines for target-specific code generator functionality.
00052  *
00053  * ====================================================================
00054  * ====================================================================
00055  */
00056 
00057 #include <ctype.h>
00058 
00059 #include "defs.h"
00060 #include "util.h"
00061 #include "config.h"
00062 #include "config_targ_opt.h"
00063 #include "erglob.h"
00064 #include "tracing.h"
00065 #include "data_layout.h"
00066 #include "const.h"
00067 #include "wn.h"
00068 #include "import.h"
00069 #include "opt_alias_interface.h"
00070 #include "opt_alias_mgr.h"
00071 #include "cgir.h"
00072 #include "cg.h"
00073 #include "void_list.h"
00074 #include "cg_dep_graph.h"
00075 #include "cg_spill.h"
00076 #include "cg_vector.h"
00077 #include "whirl2ops.h"
00078 #include "ti_errors.h"
00079 #include "ti_latency.h"
00080 #include "w2op.h"
00081 #include "cgexp.h"
00082 #include "cg_loop_recur.h"
00083 #include "targ_proc_properties.h"
00084 #include "ti_bundle.h"
00085 #include "hb_sched.h"
00086 #include "hb_hazards.h"
00087 #include "bb.h"
00088 #include "op.h"
00089 #include "op_list.h"
00090 #include "cg_grouping.h"
00091 #include "calls.h"
00092 #include "cgtarget.h"
00093 #include "calls.h"
00094 
00095 UINT32 CGTARG_branch_taken_penalty;
00096 BOOL CGTARG_branch_taken_penalty_overridden = FALSE;
00097 
00098 TOP CGTARG_Invert_Table[TOP_count+1];
00099 TOP CGTARG_Immed_To_Reg_Table[TOP_count+1];
00100 
00101 OPCODE CGTARG_Assoc_Base_Opr_Table[TOP_count];
00102 mTOP CGTARG_Assoc_Base_Top_Table[TOP_count];
00103 mTOP CGTARG_Assoc_Base_Fnc_Table[TOP_count];
00104 
00105 mTOP CGTARG_Inter_RegClass_Copy_Table[ISA_REGISTER_CLASS_MAX+1][ISA_REGISTER_CLASS_MAX+1][2];
00106 
00107 /* Trace flags: */
00108 BOOL Trace_TD = FALSE;  /* Target-dependent prep trace */
00109 BOOL Trace_Eager = FALSE; /* gcm used to set this... */
00110 extern BOOL Trace_Call_Exp; /* Trace call expansion, from cgexp */
00111 
00112 
00113 UINT32 CGTARG_Mem_Ref_Bytes(const OP *memop)
00114 /* -----------------------------------------------------------------------
00115  * Requires: OP_load(memop) || OP_store(memop)
00116  * See interface description.
00117  * -----------------------------------------------------------------------
00118  */
00119 {
00120   FmtAssert(OP_load(memop) || OP_store(memop), ("not a load or store"));
00121 
00122   TOP topcode = OP_code(memop);
00123 
00124   Is_True(topcode < TOP_count, ("unexpected topcode %d\n", topcode));
00125 
00126   if (topcode < TOP_count)
00127   {
00128     switch (topcode)
00129     {
00130     case TOP_lb:
00131     case TOP_lbu:
00132     case TOP_sb:
00133       return 1;
00134       
00135     case TOP_lh:
00136     case TOP_lhu:
00137     case TOP_sh:
00138       return 2;
00139     
00140 #ifdef TARG_SL
00141     case TOP_ldw16:
00142     case TOP_stw16:
00143     case TOP_push16:
00144     case TOP_pop16:
00145       return 4;
00146 
00147     case TOP_ldub16_rs:
00148       return 1;
00149     case TOP_lduh16_rs:
00150       return 2;
00151 
00152     case TOP_c3_ld:
00153     case TOP_c3_st:
00154     case TOP_c3_dmac_a:
00155     case TOP_c3_dmacn_a:
00156     case TOP_c3_dmula_a:
00157     case TOP_c3_dmulan_a:
00158     case TOP_c3_mac_a:
00159     case TOP_c3_mac_ar:
00160     case TOP_c3_macn_a:
00161     case TOP_c3_macn_ar:
00162     case TOP_c3_mula_a:
00163     case TOP_c3_mula_ar:
00164     case TOP_c3_saadd_a:
00165     case TOP_c3_saaddh_a:
00166     case TOP_c3_saddha_a:
00167     case TOP_c3_samulh_a:
00168     case TOP_c3_sasub_a:
00169     case TOP_c3_sasubh_a:
00170     case TOP_c3_viterbi:
00171     case TOP_c3_trback:
00172     case TOP_c3_fft:
00173     case TOP_c3_fftld:
00174     case TOP_c3_fftst:
00175     // new C3   
00176     case TOP_C3_dmac_a:            
00177     case TOP_C3_dmacn_a:           
00178     case TOP_C3_dmula_a:           
00179     case TOP_C3_dmulan_a:          
00180     case TOP_C3_ffe:               
00181     case TOP_C3_fftld:             
00182     case TOP_C3_ld:                
00183     case TOP_C3_fftst:             
00184     case TOP_C3_st:                
00185     case TOP_C3_mac_a:             
00186     case TOP_C3_macn_a:            
00187     case TOP_C3_mac_ar:            
00188     case TOP_C3_macn_ar:           
00189     case TOP_C3_mula_a:            
00190     case TOP_C3_mula_ar:           
00191     case TOP_C3_saadd_a:           
00192     case TOP_C3_sasub_a:           
00193     case TOP_C3_saaddh_a:          
00194     case TOP_C3_sasubh_a:          
00195     case TOP_C3_sadda_a:           
00196     case TOP_C3_samulh_a:          
00197     // end 
00198       return 4;
00199 #endif
00200 
00201 #ifdef TARG_SL2
00202     //ld_v:  vbuf->rf
00203     case TOP_c2_ld_v_b_u:
00204     case  TOP_c2_ld_v_b:
00205     case  TOP_c2_ldi_v_b_u:
00206     case  TOP_c2_ldi_v_b:
00207       return 16;
00208     
00209     case  TOP_c2_ld_v_h:
00210     case  TOP_c2_ldi_v_h:
00211       return 32;
00212     
00213     case  TOP_c2_ld_v_w:
00214     case  TOP_c2_ldi_v_w:
00215       return 64;
00216 
00217     case  TOP_c2_ld_v_sw:
00218     case  TOP_c2_ld_v_m_b_u:
00219     case  TOP_c2_ld_v_m_b:
00220     case  TOP_c2_ld_v_m_h:
00221     case  TOP_c2_ld_v_m_w:
00222     case  TOP_c2_ldi_v_m_b_u:
00223     case  TOP_c2_ldi_v_m_b:
00224     case  TOP_c2_ldi_v_m_h:
00225     case  TOP_c2_ldi_v_m_w:
00226       return 32768;
00227 
00228     //ld_g: sbuf->gpr
00229     case  TOP_c2_ld_s_h_u_p:
00230     case  TOP_c2_ld_s_h_u:
00231     case  TOP_c2_ld_s_h_p:
00232     case  TOP_c2_ld_s_h:
00233     case  TOP_c2_ldi_s_h_u:
00234     case  TOP_c2_ldi_s_h:
00235       return 2;
00236 
00237     case  TOP_c2_ld_s_w_p:
00238     case  TOP_c2_ld_s_w:
00239     case  TOP_c2_ldi_s_w:
00240       return 4;
00241 
00242     //ld_v2g: vbuf->gpr
00243     case  TOP_c2_ld_v2g_b_u:
00244     case  TOP_c2_ld_v2g_b:
00245     case  TOP_c2_ldi_v2g_b_u:
00246     case  TOP_c2_ldi_v2g_b:
00247       return 1;
00248 
00249     case  TOP_c2_ld_v2g_h_u:
00250     case  TOP_c2_ld_v2g_h:
00251     case  TOP_c2_ldi_v2g_h_u:
00252     case  TOP_c2_ldi_v2g_h:
00253       return 17;
00254 
00255     case  TOP_c2_ld_v2g_w:
00256     case  TOP_c2_ldi_v2g_w:
00257       return 49;
00258 
00259     //ld_c_imm: sbuf->cr
00260     case  TOP_c2_ldi_c:
00261       return 4;
00262     
00263     //st_v: rf->vbuf    
00264     case  TOP_c2_st_v_b:
00265     case  TOP_c2_sti_v_b:
00266       return 16;
00267     
00268     case  TOP_c2_st_v_h:
00269     case  TOP_c2_sti_v_h:
00270       return 32;
00271     
00272     case  TOP_c2_st_v_w:
00273     case  TOP_c2_sti_v_w:
00274       return 64;
00275     
00276     case  TOP_c2_st_v_m_b:
00277     case  TOP_c2_st_v_m_h:
00278     case  TOP_c2_st_v_m_w:
00279     case  TOP_c2_sti_v_m_b:
00280     case  TOP_c2_sti_v_m_h:
00281     case  TOP_c2_sti_v_m_w:
00282       return 32768;
00283 
00284     //st_g: gpr->sbuf
00285     case  TOP_c2_st_s_h:
00286     case  TOP_c2_st_s_h_p:
00287     case  TOP_c2_sti_s_h:
00288       return 2;
00289     
00290     case  TOP_c2_st_s_w:
00291     case  TOP_c2_st_s_w_p:
00292     case  TOP_c2_sti_s_w:
00293       return 4;
00294     
00295     case  TOP_c2_sti_c:
00296       return 4;
00297 
00298 
00299     //st_g2v: gpr->vbuf
00300     case  TOP_c2_st_g2v_b:
00301     case  TOP_c2_sti_g2v_b:
00302       return 1;
00303     case  TOP_c2_st_g2v_h:
00304     case  TOP_c2_sti_g2v_h:
00305       return 17;
00306     case  TOP_c2_st_g2v_w:
00307     case  TOP_c2_sti_g2v_w:   
00308       return 49;
00309 
00310 #endif 
00311     case TOP_lw:
00312     case TOP_ll:
00313     case TOP_lwu:
00314     case TOP_lwc1:
00315     case TOP_lwxc1:
00316     case TOP_sw:
00317     case TOP_sc:
00318     case TOP_swc1:
00319     case TOP_swxc1:
00320       return 4;
00321 
00322     case TOP_ld:
00323     case TOP_lld:
00324     case TOP_ldc1:
00325     case TOP_ldxc1:
00326     case TOP_sd:
00327     case TOP_scd:
00328     case TOP_sdc1:
00329     case TOP_sdxc1:
00330       return 8;
00331     }
00332   }
00333   
00334   return 0;
00335 }
00336 
00337 /* ====================================================================
00338  *
00339  * CGTARG_Is_OP_Speculative
00340  *
00341  * See interface description
00342  *
00343  * ====================================================================
00344  */
00345 BOOL
00346 CGTARG_Is_OP_Speculative(OP *op)
00347 {
00348   if (!OP_load(op)) return FALSE;
00349 
00350   // speculative and advanced loads are safe to speculate.
00351   if (CGTARG_Is_OP_Advanced_Load(op) || CGTARG_Is_OP_Speculative_Load(op))
00352     return TRUE;
00353 
00354   return FALSE;
00355 }
00356 
00357 /* ====================================================================
00358  *
00359  * CGTARG_Perform_THR_Code_Generation
00360  *
00361  * See interface description
00362  *
00363  * ====================================================================
00364  */
00365 void CGTARG_Perform_THR_Code_Generation (OP *load_op, OP *chk_load,
00366            THR_TYPE type)
00367 {
00368   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
00369 }
00370 
00371 /* ====================================================================
00372  *
00373  * CGTARG_ARC_Sched_Latency
00374  *
00375  * See interface description
00376  *
00377  * ====================================================================
00378  */
00379 INT CGTARG_ARC_Sched_Latency(
00380   ARC *arc
00381 )
00382 {
00383   if ( ARC_kind(arc) == CG_DEP_PREBR && 
00384       PROC_has_same_cycle_branch_shadow() )
00385     return 0;
00386   else
00387     return ARC_latency(arc);
00388 }
00389 
00390 
00391 /* ====================================================================
00392  *
00393  * CGTARG_Bundle_Slot_Available
00394  *
00395  * See interface description
00396  *
00397  * ====================================================================
00398  */
00399 BOOL 
00400 CGTARG_Bundle_Slot_Available(TI_BUNDLE              *bundle,
00401            OP                     *op,
00402            INT                     slot,
00403            ISA_EXEC_UNIT_PROPERTY *prop, 
00404            BOOL                    stop_bit_reqd,
00405            const CG_GROUPING      *grouping)
00406 {
00407   return FALSE;
00408 }
00409 
00410 /* ====================================================================
00411  *
00412  * CGTARG_Bundle_Stop_Bit_Available
00413  *
00414  * See interface description
00415  *
00416  * ====================================================================
00417  */
00418 BOOL 
00419 CGTARG_Bundle_Stop_Bit_Available(TI_BUNDLE *bundle, INT slot)
00420 {
00421   // Return TRUE the stop-bit is already set.
00422   if (TI_BUNDLE_stop_bit(bundle, slot)) return TRUE;
00423 
00424   return TI_BUNDLE_Stop_Bit_Available(bundle, slot);
00425 }
00426 
00427 /* ====================================================================
00428  *
00429  * CGTARG_Handle_Bundle_Hazard
00430  *
00431  * See interface description
00432  *
00433  * ====================================================================
00434  */
00435 void
00436 CGTARG_Handle_Bundle_Hazard (OP                          *op, 
00437            TI_BUNDLE                   *bundle, 
00438            VECTOR                      *bundle_vector,
00439            BOOL                        can_fill, 
00440            INT                         slot_pos, 
00441            INT                         max_pos,
00442            BOOL                        stop_bit_reqd,
00443            ISA_EXEC_UNIT_PROPERTY      prop) 
00444 {
00445   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
00446 }
00447 
00448 /* ====================================================================
00449  *
00450  * CGTARG_Handle_Errata_Hazard
00451  *
00452  * See interface description
00453  *
00454  * ====================================================================
00455  */
00456 void
00457 CGTARG_Handle_Errata_Hazard (OP *op, INT erratnum, INT ops_to_check)
00458 {
00459   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
00460 }
00461 
00462 /* ====================================================================
00463  *
00464  * Reduce_Fraction
00465  *
00466  * Half hearted attempt to reduce a fraction. If we don't succeed
00467  * the only problem will be that we might round incorrectly on a
00468  * instruction rate.
00469  *
00470  * The algorithm is to first try the denominator as a factor and
00471  * then a few small primes.
00472  *
00473  * ====================================================================
00474  */
00475 static void
00476 Reduce_Fraction(INT frac[2])
00477 {
00478   INT i;
00479   static const INT primes[] = {2, 3, 5, 7, 11, 13};
00480   INT n = frac[0];
00481   INT d = frac[1];
00482   INT p = d;
00483 
00484   if (d < -1 || d > 1) {
00485     for (i = sizeof(primes) / sizeof(primes[0]); ; p = primes[--i]) {
00486       while (n % p == 0 && d % p == 0) {
00487   n = n / p;
00488   d = d / p;
00489       }
00490       if (i == 0) break;
00491     }
00492   }
00493 
00494   frac[0] = n;
00495   frac[1] = d;
00496 }
00497 
00498 
00499 /* ====================================================================
00500  *
00501  * Harmonic_Mean
00502  *
00503  * Compute the harmonic weighted mean of two rates as follows:
00504  *
00505  *    1        a                    b
00506  *  ---- = ( ----- * a_rate ) + ( ----- * b_rate )
00507  *  mean     a + b                a + b
00508  *
00509  * Where:
00510  *
00511  *  "a" is the number of operations of class "a"
00512  *  "b" is the number of operations of class "b"
00513  *
00514  * ====================================================================
00515  */
00516 static void
00517 Harmonic_Mean(
00518   INT mean[2],
00519   INT a,
00520   const INT a_rate[2],
00521   INT b,
00522   const INT b_rate[2]
00523 ) {
00524   if (a == 0) {
00525     mean[0] = b_rate[0];
00526     mean[1] = b_rate[1];
00527   } else if (b == 0) {
00528     mean[0] = a_rate[0];
00529     mean[1] = a_rate[1];
00530   } else {
00531     mean[1] =   (a * a_rate[1] * b_rate[0]) 
00532         + (b * b_rate[1] * a_rate[0]);
00533     mean[0] = (a + b) * a_rate[0] * b_rate[0];
00534     Reduce_Fraction(mean);
00535   }
00536 }
00537 
00538 
00539 /* ====================================================================
00540  *
00541  * CGTARG_Peak_Rate
00542  *
00543  * See interface description
00544  *
00545  * ====================================================================
00546  */
00547 void CGTARG_Peak_Rate( PEAK_RATE_CLASS prc, PRC_INFO *info, INT ratio[2] )
00548 {
00549   ratio[0] = 1;
00550   ratio[1] = 1;
00551   
00552   switch (prc) {
00553   case PRC_INST:
00554     ratio[0] = 4;
00555     break;
00556   case PRC_MADD:
00557   case PRC_MEMREF:
00558     ratio[0] = 2;
00559     break;
00560   case PRC_FLOP:
00561   case PRC_FADD:
00562   case PRC_FMUL:
00563     ratio[0] = 2;
00564     break;
00565   case PRC_IOP:
00566     ratio[0] = 2;
00567     break;
00568   default:
00569     ratio[0] = 2;
00570     break;
00571   }
00572 }
00573 
00574 /* =======================================================================
00575  *
00576  *  Plural
00577  *
00578  *  Return "s" if i != 1, "" otherwise.  Used to get the number of nouns
00579  *  right when printing.
00580  *
00581  * =======================================================================
00582  */
00583 #define Plural(i) ((i) != 1 ? "s" : "")
00584 
00585 
00586 /* =======================================================================
00587  *
00588  *  Percent_Of_Peak
00589  *
00590  *  Compute the percentage of peak instructions executed. Both the
00591  *  actual number of instructions executed and the peak attainable
00592  *  are expressed as a fraction of insts/cycle.
00593  *
00594  * =======================================================================
00595  */
00596 static INT
00597 Percent_Of_Peak(INT numer, INT denom, INT peak[2])
00598 {
00599   if (numer == 0) return 0;
00600   return (numer * peak[1] * 100) / ((denom * peak[0]) + peak[1] - 1);
00601 }
00602 
00603 
00604 /* =======================================================================
00605  *
00606  *  CGTARG_Print_PRC_INFO
00607  *
00608  *  Print statistics for the PRC_INFO to a 'file'.
00609  *
00610  * =======================================================================
00611  */
00612 void
00613 CGTARG_Print_PRC_INFO(
00614   FILE       *file,
00615   PRC_INFO   *info,
00616   INT32      ii,
00617   const char *prefix,
00618   const char *suffix
00619 )
00620 {
00621   char *s;
00622   INT madds_per_cycle[2];
00623   INT memrefs_per_cycle[2];
00624   INT flops_per_cycle[2];
00625   INT fadds_per_cycle[2];
00626   INT fmuls_per_cycle[2];
00627   INT iops_per_cycle[2];
00628   INT insts_per_cycle[2];
00629   INT insts = info->refs[PRC_INST];
00630   INT memrefs = info->refs[PRC_MEMREF];
00631   INT flops = info->refs[PRC_FLOP];
00632   INT madds = info->refs[PRC_MADD];
00633   INT fadds = info->refs[PRC_FADD];
00634   INT fmuls = info->refs[PRC_FMUL];
00635   INT iops = info->refs[PRC_IOP];
00636 
00637   CGTARG_Peak_Rate(PRC_INST, info, insts_per_cycle);
00638   CGTARG_Peak_Rate(PRC_MEMREF, info, memrefs_per_cycle);
00639   CGTARG_Peak_Rate(PRC_FLOP, info, flops_per_cycle);
00640   CGTARG_Peak_Rate(PRC_MADD, info, madds_per_cycle);
00641   CGTARG_Peak_Rate(PRC_FADD, info, fadds_per_cycle);
00642   CGTARG_Peak_Rate(PRC_FMUL, info, fmuls_per_cycle);
00643   CGTARG_Peak_Rate(PRC_IOP, info, iops_per_cycle);
00644 
00645   if (flops != 0) {
00646     BOOL unbalanced_fpu = FALSE;
00647 
00648     if ( madds_per_cycle[0] != 0 ) {
00649       fprintf(file,"%s%5d flop%1s        (%3d%% of peak) (madds count as 2)%s"
00650                    "%s%5d flop%1s        (%3d%% of peak) (madds count as 1)%s"
00651                    "%s%5d madd%1s        (%3d%% of peak)%s",
00652      prefix,
00653      flops + madds,
00654      Plural(flops + madds),
00655      Percent_Of_Peak(flops + madds, ii * 2, madds_per_cycle),
00656      suffix,
00657      prefix,
00658      flops,
00659      Plural(flops),
00660      Percent_Of_Peak(flops, ii, flops_per_cycle),
00661      suffix,
00662      prefix,
00663      madds,
00664      Plural(madds),
00665      Percent_Of_Peak(madds, ii, madds_per_cycle),
00666      suffix);
00667     }
00668     else {
00669       fprintf(file,"%s%5d flop%1s        (%3d%% of peak)%s",
00670      prefix,
00671      flops,
00672      Plural(flops),
00673      Percent_Of_Peak(flops, ii, flops_per_cycle),
00674      suffix);
00675     }
00676 
00677     if ( unbalanced_fpu ) {
00678       INT fmuls2_per_cycle[2]; /* combined fmul/madd peak rate */
00679       INT fadds2_per_cycle[2]; /* combined fadd/madd peak rate */
00680       INT fadds2 = fadds + madds;
00681       INT fmuls2 = fmuls + madds;
00682 
00683       Harmonic_Mean(fmuls2_per_cycle,
00684         fmuls, fmuls_per_cycle,
00685         madds, madds_per_cycle);
00686       Harmonic_Mean(fadds2_per_cycle,
00687         fadds, fadds_per_cycle,
00688         madds, madds_per_cycle);
00689 
00690       fprintf(file,"%s%5d fmul%1s        (%3d%% of peak)%s%s",
00691      prefix,
00692      fmuls2,
00693      Plural(fmuls2),
00694      Percent_Of_Peak(fmuls2, ii, fmuls2_per_cycle),
00695      madds_per_cycle[0] ? " (madds count as 1)" : "",
00696      suffix);
00697       fprintf(file,"%s%5d fadd%1s        (%3d%% of peak)%s%s",
00698      prefix,
00699      fadds2,
00700      Plural(fadds2),
00701      Percent_Of_Peak(fadds2, ii, fadds2_per_cycle),
00702      madds_per_cycle[0] ? " (madds count as 1)" : "",
00703      suffix);
00704     }
00705   }
00706 
00707   s = "";
00708   if (FALSE) {
00709     iops += memrefs;
00710     s = " (mem refs included)";
00711   }
00712 
00713   fprintf(file,"%s%5d mem ref%1s     (%3d%% of peak)%s"
00714                "%s%5d integer op%1s  (%3d%% of peak)%s%s"
00715                "%s%5d instruction%1s (%3d%% of peak)%s",
00716                prefix,
00717                memrefs,
00718                Plural(memrefs),
00719                Percent_Of_Peak(memrefs, ii, memrefs_per_cycle),
00720          suffix,
00721                prefix,
00722                iops,
00723                Plural(iops),
00724                Percent_Of_Peak(iops, ii, iops_per_cycle),
00725          s,
00726          suffix,
00727                prefix,
00728                insts,
00729                Plural(insts),
00730                Percent_Of_Peak(insts, ii, insts_per_cycle),
00731          suffix);
00732 }
00733 
00734 
00735 
00736 /* =======================================================================
00737  *
00738  *  CGTARG_Compute_PRC_INFO
00739  *
00740  *  Compute some basic information about the given 'bb'. 
00741  *
00742  * =======================================================================
00743  */
00744 void
00745 CGTARG_Compute_PRC_INFO(
00746   BB *bb,
00747   PRC_INFO *info
00748 )
00749 {
00750   OP *op;
00751 
00752   bzero (info, sizeof (PRC_INFO));
00753 
00754   for ( op = BB_first_op(bb); op != NULL; op = OP_next(op) ) {
00755     INT num_insts = OP_Real_Ops (op);
00756 
00757     if (num_insts == 0) continue;
00758 
00759     info->refs[PRC_INST] += num_insts;
00760 
00761     if ( OP_flop(op) ) {
00762       BOOL is_single = (OP_result_size(op,0) == 32);
00763 
00764       ++info->refs[PRC_FLOP];
00765       info->refs[PRC_FLOP_S] += is_single;
00766       if (OP_madd(op)) {
00767         ++info->refs[PRC_MADD];
00768   info->refs[PRC_MADD_S] += is_single;
00769       }
00770       else if (OP_fadd(op) || OP_fsub(op)) {
00771   ++info->refs[PRC_FADD];
00772   info->refs[PRC_FADD_S] += is_single;
00773       }
00774       else if (OP_fmul(op)) {
00775   ++info->refs[PRC_FMUL];
00776   info->refs[PRC_FMUL_S] += is_single;
00777       }
00778     }
00779     else if (OP_memory(op))
00780       ++info->refs[PRC_MEMREF];
00781     else {
00782       INT k;
00783 
00784       /* Conditional moves and m[tf]c1 are not tagged as flops.
00785        * We certainly don't want to call them integer ops, so assume
00786        * anything that uses FP regs isn't an integer instruction.
00787        */
00788       if (OP_has_result(op) && TN_is_float(OP_result(op,0))) goto not_iop;
00789 
00790       for (k = 0; k < OP_opnds(op); k++) {
00791   if (TN_is_float(OP_opnd(op,k))) goto not_iop;
00792       }
00793 
00794       info->refs[PRC_IOP] += num_insts;
00795 
00796     not_iop:
00797       ;
00798     }
00799   }
00800 }
00801 
00802 
00803 /* ====================================================================
00804  *
00805  * CG_TARG_Branch_Info
00806  *
00807  * See interface description
00808  *
00809  * ====================================================================
00810  */
00811 void
00812 CGTARG_Branch_Info ( const OP  *op,
00813                     INT *tfirst,  /* Which operand is the first target? */
00814                     INT *tcount ) /* How many target operands are there? */
00815 {
00816   INT i;
00817   TN *tn;
00818 
00819   /* Initialize results: */
00820   *tfirst = -1;
00821   *tcount = 0;
00822 
00823   /* Find the first target: */
00824   for ( i = 0; ; i++ ) {
00825     if ( i >= OP_opnds(op) ) return;
00826     tn = OP_opnd(op,i);
00827     if ( tn != NULL && TN_is_label(tn) ) break;
00828   }
00829   *tfirst = i;
00830 
00831   /* Count the targets: */
00832   *tcount = 1;
00833   for ( i++; i < OP_opnds(op); i++ ) {
00834     tn = OP_opnd(op,i);
00835     if ( tn == NULL || ! TN_is_label(tn) ) return;
00836     (*tcount)++;
00837   }
00838   return;
00839 }
00840 
00841 
00842 /* ====================================================================
00843  *
00844  * CGTARG_Can_Be_Speculative
00845  *
00846  * See interface description
00847  *
00848  * ====================================================================
00849  */
00850 BOOL
00851 CGTARG_Can_Be_Speculative( OP *op )
00852 {
00853   WN *wn;
00854 
00855   /* not allowed to speculate anything. */
00856   if (Eager_Level == EAGER_NONE) return FALSE;
00857 
00858   /* don't speculate volatile memory references. */
00859   if (OP_volatile(op)) return FALSE;
00860 
00861   if (TOP_Can_Be_Speculative(OP_code(op))) return TRUE;
00862 
00863   if (!OP_load(op)) return FALSE;
00864 
00865   /* Try to identify simple scalar loads than can be safely speculated:
00866    *  a) read only loads (literals, GOT-loads, etc.)
00867    *  b) load of a fixed variable (directly referenced)
00868    *  c) load of a fixed variable (base address is constant or
00869    *     known to be in bounds)
00870    *  d) speculative, advanced and advanced-speculative loads are safe.
00871    */
00872 
00873   /*  a) read only loads (literals, GOT-loads, etc.)
00874    */
00875   if (OP_no_alias(op)) goto scalar_load;
00876 
00877   /*  b) load of a fixed variable (directly referenced); this
00878    *     includes spill-restores.
00879    *  b') exclude cases of direct loads of weak symbols (#622949).
00880    */
00881   if (TN_is_symbol(OP_opnd(op, 1)) &&
00882       !ST_is_weak_symbol(TN_var(OP_opnd(op, 1)))) goto scalar_load;
00883 
00884   /*  c) load of a fixed variable (base address is constant or
00885    *     known to be in bounds), comment out the rematerizable bit check 
00886    *     since it doesn;t guarantee safeness all the time.
00887    */
00888   if (/*   TN_is_rematerializable(OP_opnd(op, 0)) || */
00889       (   (wn = Get_WN_From_Memory_OP(op))
00890     && Alias_Manager->Safe_to_speculate(wn))) goto scalar_load;
00891 
00892   /* d) speculative, advanced, speculative-advanced loads are safe to 
00893    *    speculate. 
00894    */
00895   if (CGTARG_Is_OP_Speculative(op)) goto scalar_load;
00896 
00897   /* If we got to here, we couldn't convince ourself that we have
00898    * a scalar load -- no speculation this time...
00899    */
00900   return FALSE;
00901 
00902   /* We now know we have a scalar load of some form. Determine if they
00903    * are allowed to be speculated.
00904    */
00905 scalar_load:
00906   return TRUE; 
00907 }
00908 
00909 /* ====================================================================
00910  *
00911  * CGTARG_Is_OP_Speculative_Load
00912  *
00913  * See interface description
00914  *
00915  * ====================================================================
00916  */
00917 BOOL
00918 CGTARG_Is_OP_Speculative_Load( OP *memop )
00919 {
00920   return FALSE;
00921 }
00922 
00923 /* ====================================================================
00924  *
00925  * CGTARG_Is_OP_Advanced_Load
00926  *
00927  * See interface description
00928  *
00929  * ====================================================================
00930  */
00931 BOOL
00932 CGTARG_Is_OP_Advanced_Load( OP *memop )
00933 {
00934   return FALSE;
00935 }
00936 
00937 /* ====================================================================
00938  *
00939  * CGTARG_Is_OP_Check_Load
00940  *
00941  * See interface description
00942  *
00943  * ====================================================================
00944  */
00945 BOOL
00946 CGTARG_Is_OP_Check_Load( OP *memop )
00947 {
00948   return FALSE;
00949 }
00950 
00951 /* ====================================================================
00952  *
00953  * CGTARG_OP_Defs_TN
00954  * CGTARG_OP_Refs_TN
00955  *
00956  * See interface description
00957  *
00958  * ====================================================================
00959  */
00960 BOOL
00961 CGTARG_OP_Defs_TN( OP *op, TN *tn )
00962 {
00963   return FALSE;
00964 }
00965 
00966 BOOL
00967 CGTARG_OP_Refs_TN( OP *op, TN *tn )
00968 {
00969   return FALSE;
00970 }
00971 
00972 
00973 /* ====================================================================
00974  *
00975  * CGTARG_Interference implementation starts here
00976  *
00977  * ====================================================================
00978  */
00979 
00980 static MEM_POOL interference_pool;
00981 static VOID_LIST** writing;     /* writing[i] is a list of live ranges being
00982                                    written into registers in cycle i */
00983 static BOOL is_loop;            /* Are we working on a loop? */
00984 static INT32 assumed_longest_latency = 40;
00985                                 /* We need to allocate <writing> to be somewhat
00986                                    longer than the number of cycles in the
00987                                    schedule in order to accommodate writes
00988                                    initiated near the end of the schedule.
00989                                    We'll check and grow this number as
00990                                    necessary. */
00991 static INT32 cycle_count;       /* Number of cycles in the schedule under
00992                                    consideration. */
00993 static void (*make_interference)(void*,void*);
00994                                 /* Client's interference call back. */
00995 
00996 /* ====================================================================
00997  *
00998  * Increase_Assumed_Longest_Latency
00999  *
01000  * We need to increase our assumptions about the longest latency operation
01001  * in our target.  Also reallocate <writing>.
01002  *
01003  * ====================================================================
01004  */
01005 static void
01006 Increase_Assumed_Longest_Latency(INT32 new_longest_latency )
01007 {
01008   DevWarn("Assumed longest latency should be at least %d",
01009           new_longest_latency);
01010   writing = TYPE_MEM_POOL_REALLOC_N(VOID_LIST*,&interference_pool,writing,
01011                                     cycle_count + assumed_longest_latency,
01012                                     cycle_count + new_longest_latency);
01013   assumed_longest_latency = new_longest_latency;
01014 }
01015 
01016 /* ====================================================================
01017  *
01018  * CGTARG_Interference_Required
01019  *
01020  * See interface description
01021  *
01022  * ====================================================================
01023  */
01024 BOOL
01025 CGTARG_Interference_Required(void)
01026 {
01027   return FALSE;
01028 }
01029 
01030 /* ====================================================================
01031  *
01032  * CGTARG_Interference_Initialize
01033  *
01034  * See interface description
01035  *
01036  * ====================================================================
01037  */
01038 void
01039 CGTARG_Interference_Initialize( INT32 cycle_count_local, BOOL is_loop_local,
01040                                 void (*make_interference_local)(void*,void*) )
01041 {
01042   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
01043 }
01044 
01045 /* ====================================================================
01046  *
01047  * CGTARG_Result_Live_Range
01048  *
01049  * See interface description
01050  *
01051  * ====================================================================
01052  */
01053 void
01054 CGTARG_Result_Live_Range( void* lrange, OP* op, INT32 offset )
01055 {
01056   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
01057 }
01058 
01059 /* ====================================================================
01060  *
01061  * CGTARG_Operand_Live_Range
01062  *
01063  * See interface description
01064  *
01065  * ====================================================================
01066  */
01067 void
01068 CGTARG_Operand_Live_Range( void* lrange, INT   opnd, OP*   op, INT32 offset )
01069 {
01070   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
01071 }
01072 
01073 /* ====================================================================
01074  *
01075  * CGTARG_Interference_Finalize
01076  *
01077  * See interface description
01078  *
01079  * ====================================================================
01080  */
01081 void
01082 CGTARG_Interference_Finalize(void)
01083 {
01084   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
01085 }
01086 
01087 
01088 /* ====================================================================
01089  *
01090  * CGTARG_Preg_Register_And_Class
01091  *
01092  * See interface description
01093  *
01094  * ====================================================================
01095  */
01096 BOOL
01097 CGTARG_Preg_Register_And_Class(
01098   WN_OFFSET preg,
01099   ISA_REGISTER_CLASS *p_rclass,
01100   REGISTER *p_reg
01101 )
01102 {
01103   ISA_REGISTER_CLASS rclass;
01104   INT regnum;
01105   /* Get the target register number and class associated with the
01106    * preg, if there is one that is.
01107    */
01108   if (!Preg_Is_Dedicated(preg))
01109     return FALSE;
01110 
01111   if (!Preg_Offset_Is_Int(preg) &&
01112       !Preg_Offset_Is_Float(preg) &&
01113       !Preg_Offset_Is_Fcc(preg))
01114     return FALSE;
01115 
01116   /* Get the target register number and class associated with the
01117    *    * preg, if there is one that is.
01118    */
01119   if (Preg_Offset_Is_Int(preg)) {
01120     regnum = preg - (Int_Preg_Min_Offset - 1);
01121     rclass = ISA_REGISTER_CLASS_integer;
01122   }
01123   else if (Preg_Offset_Is_Float(preg)) {
01124     regnum = preg - Float_Preg_Min_Offset;
01125     rclass = ISA_REGISTER_CLASS_float;
01126   }
01127   else if (Preg_Offset_Is_Fcc(preg)) {
01128     regnum = preg - Fcc_Preg_Min_Offset;
01129     rclass = ISA_REGISTER_CLASS_fcc;
01130   }
01131   else if (preg == 0) {
01132     regnum = 0;
01133     rclass = ISA_REGISTER_CLASS_integer;
01134   } 
01135   else {
01136     return FALSE;
01137   }
01138 
01139   /* Find the CG register for the target register and class. */
01140   for ( REGISTER reg = REGISTER_MIN;
01141   reg <= REGISTER_CLASS_last_register(rclass);
01142   reg++ )
01143   {
01144     if ( REGISTER_machine_id(rclass,reg) == regnum )
01145     {
01146       *p_reg = reg;
01147       *p_rclass = rclass;
01148       return TRUE;
01149     }
01150   }
01151 
01152   FmtAssert(FALSE, ("failed to map preg %d", preg));
01153   /*NOTREACHED*/
01154 }
01155 
01156 
01157 /* ====================================================================
01158  *
01159  * CGTARG_Compute_Branch_Parameters
01160  *
01161  * See interface description
01162  *
01163  * ====================================================================
01164  */
01165 void CGTARG_Compute_Branch_Parameters(INT32 *mispredict, INT32 *fixed, INT32 *brtaken, double *factor)
01166 {
01167   *mispredict = 0;
01168   *fixed = 0;
01169   *brtaken = 0;
01170   *factor = 0.0;
01171 
01172 #ifdef TARG_SL
01173   if (Is_Target_Sl1_pcore()  || Is_Target_Sl1_dsp()) {
01174     *mispredict= 7; *fixed= 1; *brtaken= 1; *factor = 1.0;
01175   }
01176   else if ( Is_Target_Sl2_pcore() || Is_Target_Sl2_mcore()) {
01177     *mispredict= 3; *fixed= 1; *brtaken= 1; *factor = 1.0;
01178   }
01179 #endif
01180 
01181  /*
01182   * override for command line options
01183   * -CG:mispredicted_branch=N
01184   * -CG:mispredicted_factor=N
01185   */
01186   if (CG_branch_mispredict_penalty >= 0)
01187     *mispredict= CG_branch_mispredict_penalty ;
01188 
01189   if (CG_branch_mispredict_factor >= 0)
01190     *factor= CG_branch_mispredict_factor * (.01);
01191 }
01192 
01193 
01194 /* ====================================================================
01195  *
01196  * CGTARG_Can_Change_To_Brlikely
01197  *
01198  * See interface description
01199  *
01200  * ====================================================================
01201  */
01202 BOOL CGTARG_Can_Change_To_Brlikely(OP *xfer_op, TOP *new_opcode)
01203 {
01204   return FALSE;
01205 }
01206 
01207 
01208 /* ====================================================================
01209  *
01210  * CGTARG_Is_Long_Latency
01211  *
01212  * See interface description
01213  *
01214  * ====================================================================
01215  */
01216 BOOL CGTARG_Is_Long_Latency(TOP op)
01217 {
01218   return (TI_LATENCY_Result_Available_Cycle(op, 0) -
01219     TI_LATENCY_Operand_Access_Cycle(op, 0)) > 2;
01220 }
01221 
01222 /* ====================================================================
01223  *
01224  * CGTARG_Analyze_Branch
01225  *
01226  * See interface description
01227  *
01228  * ====================================================================
01229  */
01230 VARIANT CGTARG_Analyze_Branch(
01231   OP *br,
01232   TN **tn1,
01233   TN **tn2)
01234 {
01235   INT variant;
01236 
01237   /* Branch operands are usually number 0 and 1. Where something
01238      different is used, we override below. */
01239 
01240   *tn1 = OP_opnd(br, 0);
01241   *tn2 = OP_opnd(br, 1);
01242 
01243   switch (OP_code(br))
01244   {
01245   case TOP_beq:
01246     variant = V_BR_I4EQ;
01247     break;
01248 
01249   case TOP_bne:
01250     variant = V_BR_I4NE;
01251     break;
01252 
01253   case TOP_bgez:
01254     variant = V_BR_I4GE;
01255     *tn2 = Gen_Literal_TN(0,4);
01256     break;
01257     
01258   case TOP_bltz:
01259     variant = V_BR_I4LT;
01260     *tn2 = Gen_Literal_TN(0,4);
01261     break;
01262 
01263   case TOP_bgtz:
01264     variant = V_BR_I4GT;
01265     *tn2 = Gen_Literal_TN(0,4);
01266     break;
01267     
01268   case TOP_blez:
01269     variant = V_BR_I4LE;
01270     *tn2 = Gen_Literal_TN(0,4);
01271     break;
01272 
01273   case TOP_bc1t:
01274     variant = V_BR_F_TRUE;
01275     *tn2 = NULL;
01276     break;
01277 
01278   case TOP_bc1f:
01279     variant = V_BR_F_FALSE;
01280     *tn2 = NULL;
01281     break;
01282 
01283   default:
01284     variant = V_BR_NONE;
01285     *tn1 = NULL;
01286     *tn2 = NULL;
01287 
01288     Is_True( !OP_cond( br ), ("unexpected conditional branch %d\n", OP_code(br) ) );
01289 
01290     break;
01291   }
01292 
01293   return variant;
01294 }
01295 
01296 
01297 /* ====================================================================
01298  *
01299  * CGTARG_Analyze_Compare
01300  *
01301  * See interface description
01302  *
01303  * ====================================================================
01304  */
01305 VARIANT CGTARG_Analyze_Compare(
01306   OP *br,
01307   TN **tn1,
01308   TN **tn2,
01309   OP **compare_op)
01310 {
01311   TN *cond_tn1;
01312   TN *cond_tn2;
01313 
01314   /* Classify the condition based on the branch instruction.  */
01315 
01316   INT variant = CGTARG_Analyze_Branch(br, &cond_tn1, &cond_tn2);
01317 
01318   /* Once we have varients for 'bf' and 'bt' (and possibly some
01319      others), we can attempt to find the comparison. For now, none of
01320      the branches have associated comparisons. */
01321 
01322   *compare_op = NULL;
01323   *tn1 = cond_tn1;
01324   *tn2 = cond_tn2;
01325 
01326   return variant;
01327 }
01328 
01329 
01330 /* ====================================================================
01331  *
01332  * CGTARG_Equivalent_Nonindex_Memory_Op
01333  *
01334  * See interface description
01335  *
01336  * ====================================================================
01337  */
01338 TOP
01339 CGTARG_Equiv_Nonindex_Memory_Op ( OP *op )
01340 {
01341   return TOP_UNDEFINED;
01342 }
01343 
01344 /* ====================================================================
01345  *
01346  * CGTARG_Which_OP_Select
01347  *
01348  * See interface description
01349  *
01350  * ====================================================================
01351  */
01352 TOP
01353 CGTARG_Which_OP_Select ( UINT16 bit_size, BOOL is_float, BOOL is_fcc )
01354 {
01355   FmtAssert( FALSE, ( "CGTARG_Which_OP_Select: Unsupported Target") );
01356   return TOP_UNDEFINED;
01357 }
01358 
01359 /* ====================================================================
01360  *
01361  * Is_OP_fp_op1
01362  *
01363  * FP_OP1 = {sfmac, sfmisc, xma, xmpy, fmac, cvt.fx, fmisc}
01364  *
01365  * ====================================================================
01366  */
01367 static BOOL
01368 Is_OP_fp_op1(OP *op)
01369 {
01370   return FALSE;
01371 }
01372 
01373 /* ====================================================================
01374  *
01375  * Insert_Stop_Bits
01376  *
01377  * ====================================================================
01378  */
01379 void
01380 Insert_Stop_Bits(BB *bb)
01381 {
01382 }
01383 
01384 /* ====================================================================
01385  *
01386  * CGTARG_Special_Min_II
01387  *
01388  * See interface description
01389  *
01390  * ====================================================================
01391  */
01392 INT32 CGTARG_Special_Min_II(BB* loop_body, BOOL trace)
01393 {
01394   return 0;
01395 }
01396 
01397 /* ====================================================================
01398  *
01399  * Hardware_Workarounds
01400  *
01401  * Placeholder for all Hardware workarounds. 
01402  *
01403  * ====================================================================
01404  */
01405 void
01406 Hardware_Workarounds(void)
01407 {
01408 }
01409 
01410 /* ====================================================================
01411  *
01412  * CGTARG_Initialize
01413  *
01414  * See interface description
01415  *
01416  * ====================================================================
01417  */
01418 void CGTARG_Initialize(void)
01419 {
01420   INT32 i;
01421 
01422   /* Init all table entries to TOP_UNDEFINED.
01423    */
01424   for(i = 0; i <= TOP_count; ++i) {
01425     CGTARG_Invert_Table[i] = TOP_UNDEFINED;
01426     CGTARG_Immed_To_Reg_Table[i] = TOP_UNDEFINED;
01427   }
01428 
01429   for (i = 0; i <= ISA_REGISTER_CLASS_MAX; ++i) {
01430     INT j;
01431     for (j = 0; j <= ISA_REGISTER_CLASS_MAX; ++j) {
01432       CGTARG_Inter_RegClass_Copy_Table[i][j][FALSE] = TOP_UNDEFINED;
01433       CGTARG_Inter_RegClass_Copy_Table[i][j][TRUE] = TOP_UNDEFINED;
01434     }
01435   }
01436 
01437   /* Init table for CGTARG_Invert:
01438    */
01439   CGTARG_Invert_Table[TOP_add_s]   = TOP_sub_s;
01440   CGTARG_Invert_Table[TOP_add_d]   = TOP_sub_d;
01441   CGTARG_Invert_Table[TOP_madd_s]   = TOP_nmadd_s;
01442   CGTARG_Invert_Table[TOP_madd_d]   = TOP_nmadd_d;
01443   CGTARG_Invert_Table[TOP_add]     = TOP_sub;
01444   CGTARG_Invert_Table[TOP_addu]    = TOP_subu;
01445   CGTARG_Invert_Table[TOP_dadd]     = TOP_dsub;
01446   CGTARG_Invert_Table[TOP_daddu]    = TOP_dsubu;
01447 
01448   CGTARG_Invert_Table[TOP_sub_s]   = TOP_add_s;
01449   CGTARG_Invert_Table[TOP_sub_d]   = TOP_add_d;
01450   CGTARG_Invert_Table[TOP_nmadd_s]   = TOP_madd_s;
01451   CGTARG_Invert_Table[TOP_nmadd_d]   = TOP_madd_d;
01452   CGTARG_Invert_Table[TOP_sub]     = TOP_add;
01453   CGTARG_Invert_Table[TOP_subu]    = TOP_addu;
01454   CGTARG_Invert_Table[TOP_dsub]     = TOP_dadd;
01455   CGTARG_Invert_Table[TOP_dsubu]    = TOP_daddu;
01456 
01457   CGTARG_Invert_Table[TOP_or]    = TOP_nor;
01458   CGTARG_Invert_Table[TOP_nor]    = TOP_or;
01459 
01460   CGTARG_Invert_Table[TOP_movf] = TOP_movt;
01461   CGTARG_Invert_Table[TOP_movt] = TOP_movf;
01462   CGTARG_Invert_Table[TOP_movz] = TOP_movn;
01463   CGTARG_Invert_Table[TOP_movn] = TOP_movz;
01464   CGTARG_Invert_Table[TOP_movf_s] = TOP_movt_s;
01465   CGTARG_Invert_Table[TOP_movt_s] = TOP_movf_s;
01466   CGTARG_Invert_Table[TOP_movz_s] = TOP_movn_s;
01467   CGTARG_Invert_Table[TOP_movn_s] = TOP_movz_s;
01468   CGTARG_Invert_Table[TOP_movf_d] = TOP_movt_d;
01469   CGTARG_Invert_Table[TOP_movt_d] = TOP_movf_d;
01470   CGTARG_Invert_Table[TOP_movz_d] = TOP_movn_d;
01471   CGTARG_Invert_Table[TOP_movn_d] = TOP_movz_d;
01472 
01473   CGTARG_Invert_Table[TOP_beq] = TOP_bne;
01474   CGTARG_Invert_Table[TOP_bne] = TOP_beq;
01475 
01476   CGTARG_Invert_Table[TOP_bgez] = TOP_bltz;
01477   CGTARG_Invert_Table[TOP_bgtz] = TOP_blez;
01478   CGTARG_Invert_Table[TOP_bltz] = TOP_bgez;
01479   CGTARG_Invert_Table[TOP_blez] = TOP_bgtz;
01480   CGTARG_Invert_Table[TOP_bgezal] = TOP_bltzal;
01481   CGTARG_Invert_Table[TOP_bltzal] = TOP_bgezal;
01482 
01483   CGTARG_Invert_Table[TOP_bc1f] = TOP_bc1t;
01484   CGTARG_Invert_Table[TOP_bc1t] = TOP_bc1f;
01485 
01486   CGTARG_Invert_Table[TOP_c_f_s] = TOP_c_t_s;
01487   CGTARG_Invert_Table[TOP_c_f_d] = TOP_c_t_d;
01488   CGTARG_Invert_Table[TOP_c_t_s] = TOP_c_f_s;
01489   CGTARG_Invert_Table[TOP_c_t_d] = TOP_c_f_d;
01490   CGTARG_Invert_Table[TOP_c_un_s] = TOP_c_or_s;
01491   CGTARG_Invert_Table[TOP_c_un_d] = TOP_c_or_d;
01492   CGTARG_Invert_Table[TOP_c_or_s] = TOP_c_un_s;
01493   CGTARG_Invert_Table[TOP_c_or_d] = TOP_c_un_d;
01494   CGTARG_Invert_Table[TOP_c_eq_s] = TOP_c_neq_s;
01495   CGTARG_Invert_Table[TOP_c_eq_d] = TOP_c_neq_d;
01496   CGTARG_Invert_Table[TOP_c_neq_s] = TOP_c_eq_s;
01497   CGTARG_Invert_Table[TOP_c_neq_d] = TOP_c_eq_d;
01498   CGTARG_Invert_Table[TOP_c_ueq_s] = TOP_c_olg_s;
01499   CGTARG_Invert_Table[TOP_c_ueq_d] = TOP_c_olg_d;
01500   CGTARG_Invert_Table[TOP_c_olg_s] = TOP_c_ueq_s;
01501   CGTARG_Invert_Table[TOP_c_olg_d] = TOP_c_ueq_d;
01502   CGTARG_Invert_Table[TOP_c_olt_s] = TOP_c_uge_s;
01503   CGTARG_Invert_Table[TOP_c_olt_d] = TOP_c_uge_d;
01504   CGTARG_Invert_Table[TOP_c_uge_s] = TOP_c_olt_s;
01505   CGTARG_Invert_Table[TOP_c_uge_d] = TOP_c_olt_d;
01506   CGTARG_Invert_Table[TOP_c_ult_s] = TOP_c_oge_s;
01507   CGTARG_Invert_Table[TOP_c_ult_d] = TOP_c_oge_d;
01508   CGTARG_Invert_Table[TOP_c_oge_s] = TOP_c_ult_s;
01509   CGTARG_Invert_Table[TOP_c_oge_d] = TOP_c_ult_d;
01510   CGTARG_Invert_Table[TOP_c_ole_s] = TOP_c_ugt_s;
01511   CGTARG_Invert_Table[TOP_c_ole_d] = TOP_c_ugt_d;
01512   CGTARG_Invert_Table[TOP_c_ugt_s] = TOP_c_ole_s;
01513   CGTARG_Invert_Table[TOP_c_ugt_d] = TOP_c_ole_d;
01514   CGTARG_Invert_Table[TOP_c_ule_s] = TOP_c_ogt_s;
01515   CGTARG_Invert_Table[TOP_c_ule_d] = TOP_c_ogt_d;
01516   CGTARG_Invert_Table[TOP_c_ogt_s] = TOP_c_ule_s;
01517   CGTARG_Invert_Table[TOP_c_ogt_d] = TOP_c_ule_d;
01518   CGTARG_Invert_Table[TOP_c_sf_s] = TOP_c_st_s;
01519   CGTARG_Invert_Table[TOP_c_sf_d] = TOP_c_st_d;
01520   CGTARG_Invert_Table[TOP_c_st_s] = TOP_c_sf_s;
01521   CGTARG_Invert_Table[TOP_c_st_d] = TOP_c_sf_d;
01522   CGTARG_Invert_Table[TOP_c_ngle_s] = TOP_c_gle_s;
01523   CGTARG_Invert_Table[TOP_c_ngle_d] = TOP_c_gle_d;
01524   CGTARG_Invert_Table[TOP_c_gle_s] = TOP_c_ngle_s;
01525   CGTARG_Invert_Table[TOP_c_gle_d] = TOP_c_ngle_d;
01526   CGTARG_Invert_Table[TOP_c_seq_s] = TOP_c_sne_s;
01527   CGTARG_Invert_Table[TOP_c_seq_d] = TOP_c_sne_d;
01528   CGTARG_Invert_Table[TOP_c_sne_s] = TOP_c_seq_s;
01529   CGTARG_Invert_Table[TOP_c_sne_d] = TOP_c_seq_d;
01530   CGTARG_Invert_Table[TOP_c_ngl_s] = TOP_c_gl_s;
01531   CGTARG_Invert_Table[TOP_c_ngl_d] = TOP_c_gl_d;
01532   CGTARG_Invert_Table[TOP_c_gl_s] = TOP_c_ngl_s;
01533   CGTARG_Invert_Table[TOP_c_gl_d] = TOP_c_ngl_d;
01534   CGTARG_Invert_Table[TOP_c_nlt_s] = TOP_c_lt_s;
01535   CGTARG_Invert_Table[TOP_c_nlt_d] = TOP_c_lt_d;
01536   CGTARG_Invert_Table[TOP_c_lt_s] = TOP_c_nlt_s;
01537   CGTARG_Invert_Table[TOP_c_lt_d] = TOP_c_nlt_d;
01538   CGTARG_Invert_Table[TOP_c_nge_s] = TOP_c_ge_s;
01539   CGTARG_Invert_Table[TOP_c_nge_d] = TOP_c_ge_d;
01540   CGTARG_Invert_Table[TOP_c_ge_s] = TOP_c_nge_s;
01541   CGTARG_Invert_Table[TOP_c_ge_d] = TOP_c_nge_d;
01542   CGTARG_Invert_Table[TOP_c_le_s] = TOP_c_nle_s;
01543   CGTARG_Invert_Table[TOP_c_le_d] = TOP_c_nle_d;
01544   CGTARG_Invert_Table[TOP_c_nle_s] = TOP_c_le_s;
01545   CGTARG_Invert_Table[TOP_c_nle_d] = TOP_c_le_d;
01546   CGTARG_Invert_Table[TOP_c_ngt_s] = TOP_c_gt_s;
01547   CGTARG_Invert_Table[TOP_c_ngt_d] = TOP_c_gt_d;
01548   CGTARG_Invert_Table[TOP_c_gt_s] = TOP_c_ngt_s;
01549   CGTARG_Invert_Table[TOP_c_gt_d] = TOP_c_ngt_d;
01550 
01551   CGTARG_Invert_Table[TOP_teq] = TOP_tne;
01552   CGTARG_Invert_Table[TOP_tne] = TOP_teq;
01553   CGTARG_Invert_Table[TOP_tge] = TOP_tlt;
01554   CGTARG_Invert_Table[TOP_tlt] = TOP_tge;
01555   CGTARG_Invert_Table[TOP_tgeu] = TOP_tltu;
01556   CGTARG_Invert_Table[TOP_tltu] = TOP_tgeu;
01557 
01558   CGTARG_Invert_Table[TOP_teqi] = TOP_tnei;
01559   CGTARG_Invert_Table[TOP_tnei] = TOP_teqi;
01560   CGTARG_Invert_Table[TOP_tgei] = TOP_tlti;
01561   CGTARG_Invert_Table[TOP_tlti] = TOP_tgei;
01562   CGTARG_Invert_Table[TOP_tgeiu] = TOP_tltiu;
01563   CGTARG_Invert_Table[TOP_tltiu] = TOP_tgeiu;
01564 
01565   /* Init table for CGTARG_Immed_To_Reg:
01566    */
01567   CGTARG_Immed_To_Reg_Table[TOP_addi]  = TOP_add;
01568   CGTARG_Immed_To_Reg_Table[TOP_daddi]  = TOP_dadd;
01569   CGTARG_Immed_To_Reg_Table[TOP_addiu]  = TOP_addu;
01570   CGTARG_Immed_To_Reg_Table[TOP_daddiu]  = TOP_daddu;
01571   CGTARG_Immed_To_Reg_Table[TOP_slti]  = TOP_slt;
01572   CGTARG_Immed_To_Reg_Table[TOP_sltiu]  = TOP_sltu;
01573   CGTARG_Immed_To_Reg_Table[TOP_andi]  = TOP_and;
01574   CGTARG_Immed_To_Reg_Table[TOP_ori]  = TOP_or;
01575   CGTARG_Immed_To_Reg_Table[TOP_xori]  = TOP_xor;
01576   CGTARG_Immed_To_Reg_Table[TOP_teqi]  = TOP_teq;
01577   CGTARG_Immed_To_Reg_Table[TOP_tgei]  = TOP_tge;
01578   CGTARG_Immed_To_Reg_Table[TOP_tgeiu]  = TOP_tgeu;
01579   CGTARG_Immed_To_Reg_Table[TOP_tlti]  = TOP_tlt;
01580   CGTARG_Immed_To_Reg_Table[TOP_tltiu]  = TOP_tltu;
01581   CGTARG_Immed_To_Reg_Table[TOP_tnei]  = TOP_tne;
01582 
01583   /* Init table for CGTARG_Inter_RegClass_Copy_Table:
01584    */
01585   CGTARG_Inter_RegClass_Copy_Table[ISA_REGISTER_CLASS_float]
01586           [ISA_REGISTER_CLASS_integer]
01587           [FALSE] = TOP_mfc1;
01588   CGTARG_Inter_RegClass_Copy_Table[ISA_REGISTER_CLASS_float]
01589           [ISA_REGISTER_CLASS_integer]
01590           [TRUE]  = TOP_dmfc1;
01591 
01592   CGTARG_Inter_RegClass_Copy_Table[ISA_REGISTER_CLASS_integer]
01593           [ISA_REGISTER_CLASS_float]
01594           [FALSE] = TOP_mtc1;
01595   CGTARG_Inter_RegClass_Copy_Table[ISA_REGISTER_CLASS_integer]
01596           [ISA_REGISTER_CLASS_float]
01597           [TRUE]  = TOP_dmtc1;
01598 }
01599 
01600 
01601 /* ====================================================================
01602  *
01603  * CGTARG_Load_From_Memory
01604  *
01605  * See interface description
01606  *
01607  * ====================================================================
01608  */
01609 void CGTARG_Load_From_Memory(TN *tn, ST *mem_loc, OPS *ops)
01610 {
01611   TYPE_ID mtype = TY_mtype(ST_type(mem_loc));
01612   Exp_Load(mtype, mtype, tn, mem_loc, 0, ops, 0);
01613 }
01614 
01615 
01616 /* ====================================================================
01617  *
01618  * CGTARG_Store_To_Memory
01619  *
01620  * See interface description
01621  *
01622  * ====================================================================
01623  */
01624 void CGTARG_Store_To_Memory(TN *tn, ST *mem_loc, OPS *ops)
01625 {
01626   TYPE_ID mtype = TY_mtype(ST_type(mem_loc));
01627   Exp_Store(mtype, tn, mem_loc, 0, ops, 0);
01628 }
01629 
01630 
01631 /* ====================================================================
01632  *
01633  * CGTARG_Init_Assoc_Base
01634  *
01635  * See interface description
01636  *
01637  * ====================================================================
01638  */
01639 void CGTARG_Init_Assoc_Base(void)
01640 {
01641   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
01642 }
01643 
01644 
01645 /* ====================================================================
01646  *
01647  * CGTARG_Copy_Operand
01648  *
01649  * See interface description
01650  *
01651  * ====================================================================
01652  */
01653 INT CGTARG_Copy_Operand(OP *op)
01654 {
01655   TOP opr = OP_code(op);
01656   switch (opr)
01657   {
01658   case TOP_addi:
01659   case TOP_addiu:
01660   case TOP_daddi:
01661   case TOP_daddiu:
01662   case TOP_sll:
01663   case TOP_srl:
01664   case TOP_sra:
01665   case TOP_dsll:
01666   case TOP_dsrl:
01667   case TOP_dsra:
01668     if (TN_has_value(OP_opnd(op,1)) && TN_value(OP_opnd(op,1)) == 0)
01669       return 0;
01670     break;
01671 
01672   case TOP_andi:
01673     {
01674       TN *src1 = OP_opnd( op, 1 );
01675       if (TN_is_constant(src1)) {
01676   INT64 val;
01677   if (TN_has_value(src1))
01678     val = TN_value(src1);
01679   else FmtAssert(FALSE,("unexpected constant in CGTARG_Copy_Operand"));
01680   if (val == -1)
01681     return 0;
01682       }
01683       break;
01684     }
01685 
01686   case TOP_ori:
01687   case TOP_xori:
01688     {
01689       TN *src1 = OP_opnd( op, 1 );
01690       if (TN_is_constant(src1)) {
01691   INT64 val;
01692   if (TN_has_value(src1))
01693     val = TN_value(src1);
01694   else FmtAssert(FALSE,("unexpected constant in CGTARG_Copy_Operand"));
01695   if (val == 0)
01696     return 0;
01697       }
01698       break;
01699     }
01700 
01701   case TOP_or:
01702   case TOP_xor:
01703   case TOP_addu:
01704   case TOP_daddu:
01705     if (OP_opnd( op, 1) == Zero_TN)
01706       return 0;
01707     else if (OP_opnd( op, 0) == Zero_TN)
01708       return 1;
01709     break;
01710 
01711   }
01712 
01713   if (OP_copy(op)) {
01714     if (opr == TOP_add || opr == TOP_dadd ||
01715         opr == TOP_addu || opr == TOP_daddu ||
01716         opr == TOP_or || 
01717         opr == TOP_mov_s || opr== TOP_mov_d)
01718       return 0;
01719   }
01720 
01721   return -1;
01722 }
01723 
01724 
01725 /* ====================================================================
01726  *
01727  * CGTARG_Can_Fit_Immediate_In_Add_Instruction
01728  *
01729  * See interface description
01730  *
01731  * ====================================================================
01732  */
01733 BOOL
01734 CGTARG_Can_Fit_Immediate_In_Add_Instruction (INT64 immed)
01735 {
01736   return ISA_LC_Value_In_Class (immed, LC_simm16);
01737 }
01738 
01739 
01740 /* ====================================================================
01741  *
01742  * CGTARG_Can_Load_Immediate_In_Single_Instruction
01743  *
01744  * See interface description
01745  *
01746  * ====================================================================
01747  */
01748 BOOL
01749 CGTARG_Can_Load_Immediate_In_Single_Instruction (INT64 immed)
01750 {
01751   return ISA_LC_Value_In_Class (immed, LC_simm16);
01752 }
01753 
01754 
01755 #ifdef TARG_MIPS
01756 //bug, it doesn't work now.
01757 BOOL 
01758 CGTARG_Can_Fit_Displacement_In_Branch_Instruction (INT64 disp){
01759  return true;
01760 }
01761 #endif
01762 
01763 
01764 /* ====================================================================
01765  *
01766  * CGTARG_Predicate_OP
01767  *
01768  * See interface description
01769  *
01770  * ====================================================================
01771  */
01772 /*ARGSUSED*/
01773 void
01774 CGTARG_Predicate_OP(BB* bb, OP* op, TN* pred_tn)
01775 {
01776   if (OP_has_predicate(op)) {
01777     FmtAssert( FALSE, ( "CGTARG_Which_OP_Select: Unsupported Target") );
01778   }
01779 }
01780 
01781 /* ====================================================================
01782  *
01783  * CGTARG_Branches_On_True
01784  *
01785  * See interface description
01786  *
01787  * ====================================================================
01788  */
01789 BOOL
01790 CGTARG_Branches_On_True(OP* br_op, OP* cmp_op)
01791 {
01792   return FALSE;
01793 }
01794 
01795 
01796 
01797 /* ====================================================================
01798  *
01799  * CGTARG_Parallel_Compare
01800  *
01801  * See interface description
01802  *
01803  * ====================================================================
01804  */
01805 TOP
01806 CGTARG_Parallel_Compare(OP* cmp_op, COMPARE_TYPE ctype)
01807 {
01808   return TOP_UNDEFINED;
01809 }
01810 
01811 /* ====================================================================
01812  *
01813  * CGTARG_Dependence_Required
01814  *
01815  * See interface description
01816  *
01817  * ====================================================================
01818  */
01819 BOOL
01820 CGTARG_Dependence_Required(OP *pred_op, OP *succ_op)
01821 {
01822   /* TODO for MIPS */
01823 #if defined(TARG_SL2)
01824   switch(OP_code(pred_op))
01825   {
01826     case TOP_c2_thctrl_lock:
01827     case TOP_c2_thctrl_unlock:
01828     case TOP_c2_thctrl_deact:
01829     case TOP_c2_thctrl_act:
01830     case TOP_c2_thctrl_mode4:
01831     case TOP_c2_thctrl_mode5:
01832     case TOP_c2_thctrl_mode6:
01833     case TOP_c2_thctrl_mode7:
01834     case TOP_c2_fork_m:
01835     case TOP_c2_fork_n:
01836     case TOP_peripheral_rw_begin:        
01837     case TOP_peripheral_rw_end:        
01838     return TRUE;
01839   }
01840   switch(OP_code(succ_op))
01841   {
01842     case TOP_c2_thctrl_lock:
01843     case TOP_c2_thctrl_unlock:
01844     case TOP_c2_thctrl_deact:
01845     case TOP_c2_thctrl_act:
01846     case TOP_c2_thctrl_mode4:
01847     case TOP_c2_thctrl_mode5:
01848     case TOP_c2_thctrl_mode6:
01849     case TOP_c2_thctrl_mode7:
01850     case TOP_c2_fork_m:
01851     case TOP_c2_fork_n:
01852     case TOP_c2_joint:
01853     case TOP_loop:
01854     case TOP_peripheral_rw_begin:
01855     case TOP_peripheral_rw_end:        
01856     return TRUE;
01857   }
01858 #endif   
01859   return FALSE;
01860 }
01861 
01862 /* ====================================================================
01863  *
01864  * CGTARG_Adjust_Latency
01865  *
01866  * See interface description
01867  *
01868  * ====================================================================
01869  */
01870 void
01871 CGTARG_Adjust_Latency(OP *pred_op, OP *succ_op, CG_DEP_KIND kind, UINT8 opnd, INT *latency)
01872 {
01873 #if !defined(TARG_SL2)
01874 // this function is used to check if bypass can be used between pred and succ
01875 // if bypass can be used the latency is 1, producer-to-consumer latency is 3
01876 // Following cases which can use bypass
01877 //    1. gpr to gpr
01878 //    2. instruction which use vmult, vadd 
01879 // following cases which can not use bypass
01880 //    1. vmov
01881 //    2. vspel 
01882 //    3. vspmacs
01883 //    4. other simd register and control register 
01884 //     
01885   TN* operand = NULL; 
01886   if(OP_opnds(succ_op) > opnd)
01887       operand = OP_opnd(succ_op, opnd);  
01888    
01889 #ifdef TARG_SL
01890   if(OP_has_bypass(pred_op))
01891     *latency = 0;
01892   else 
01893 
01894   if(operand && TN_is_register(operand) && TN_register_class(operand) == ISA_REGISTER_CLASS_cop_vreg)
01895   {
01896     *latency = 2;
01897   } 
01898 #endif
01899 #endif
01900 }
01901 
01902 /* ====================================================================
01903  *
01904  * CGTARG_Generate_Remainder_Branch
01905  *
01906  * See interface description
01907  *
01908  * ====================================================================
01909  */
01910 void
01911 CGTARG_Generate_Remainder_Branch(TN *trip_count, TN *label_tn,
01912          OPS *prolog_ops, OPS *body_ops)
01913 {
01914   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
01915 }
01916 
01917 
01918 /* ====================================================================
01919  *
01920  * CGTARG_OP_is_counted_loop
01921  *
01922  * See interface description
01923  *
01924  * ====================================================================
01925  */
01926 BOOL CGTARG_OP_is_counted_loop(OP *op) 
01927 {
01928   return FALSE;
01929 }
01930 
01931 
01932 /* ====================================================================
01933  *
01934  * CGTARG_Generate_Branch_Cloop
01935  *
01936  * See interface description
01937  *
01938  * ====================================================================
01939  */
01940 void
01941 CGTARG_Generate_Branch_Cloop(OP *br_op,
01942            TN *unrolled_trip_count,
01943            TN *trip_count_tn,
01944            INT32 ntimes,
01945            TN *label_tn,
01946            OPS *prolog_ops,
01947            OPS *body_ops)
01948 { 
01949   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
01950 }
01951 
01952 static TN* asm_constraint_tn[10];
01953 static ISA_REGISTER_SUBCLASS asm_constraint_sc[10];
01954 static char asm_constraint_name[10][8];
01955 static INT asm_constraint_index;
01956 
01957 // must be called once per asm
01958 void
01959 CGTARG_Init_Asm_Constraints (void)
01960 {
01961   // can use any type; it will be ignored
01962   Setup_Output_Parameter_Locations (MTYPE_To_TY(MTYPE_I8));
01963   for (INT i = 0; i < 10; ++i) {
01964     asm_constraint_tn[i] = NULL;
01965     asm_constraint_sc[i] = ISA_REGISTER_SUBCLASS_UNDEFINED;
01966     asm_constraint_name[i][0] = '\0';
01967   }
01968   asm_constraint_index = 0;
01969 }
01970 
01971 
01972 // -----------------------------------------------------------------------
01973 // Given a constraint for an ASM parameter, and the load of the matching
01974 // argument passed to ASM (possibly NULL), choose an appropriate TN for it
01975 // -----------------------------------------------------------------------
01976 extern TN* 
01977 CGTARG_TN_For_Asm_Operand (const char* constraint, 
01978                            const WN* load,
01979                            TN* pref_tn,
01980                            ISA_REGISTER_SUBCLASS* subclass, TYPE_ID id)
01981 {
01982   // skip constraint modifiers:
01983   // = input and output parameters are separated in the WHIRL for ASM
01984   // & early_clobber flag is set in Handle_ASM
01985   // % commutativity of operands is ignored for now
01986   static const char* modifiers = "=&%";
01987   while (strchr(modifiers, *constraint))
01988   {
01989     constraint++;
01990   }
01991   
01992   // TODO: we should really look at multiple specified constraints
01993   // and the load in order to select the best TN, but for now we
01994   // assume that when we get here we can safely pick a TN
01995 
01996   // if 'm' is one of the choices, always prefer that one
01997   // TODO: we decide this in the front end, but it's not optimal
01998   if (*constraint != 'm')
01999   {
02000     const char* m = constraint;
02001     while (*++m)
02002     {
02003       if (*m == 'm')
02004       {
02005         constraint = m;
02006         break;
02007       }
02008     }
02009   }
02010   
02011   // prefer register/memory over immediates; this isn't optimal, 
02012   // but we may not always be able to generate an immediate
02013   static const char* immediates = "in";
02014   while (strchr(immediates, *constraint) && *(constraint+1))
02015   {
02016     constraint++;
02017   }
02018 
02019   TN* ret_tn;
02020   
02021   // TODO: check that the operand satisifies immediate range constraint
02022   if (strchr(immediates, *constraint))
02023   {
02024     if (load && WN_operator(load)==OPR_LDID && WN_class(load)==CLASS_PREG)
02025     {
02026       // immediate could have been put in preg by wopt
02027       load = Preg_Is_Rematerializable(WN_load_offset(load), NULL);
02028     }
02029     FmtAssert(load && WN_operator(load) == OPR_INTCONST, 
02030               ("Cannot find immediate operand for ASM"));
02031     ret_tn = Gen_Literal_TN(WN_const_val(load), 
02032                             MTYPE_bit_size(WN_rtype(load))/8);
02033   }
02034   // digit constraint means that we should reuse a previous operand
02035   else if (isdigit(*constraint))
02036   {
02037     INT prev_index = *constraint - '0';
02038     FmtAssert(asm_constraint_tn[prev_index], 
02039               ("numeric matching constraint refers to NULL value"));
02040     ret_tn = asm_constraint_tn[prev_index];
02041   }
02042   else if (strchr("m", *constraint))
02043   {
02044     TYPE_ID rtype = (load != NULL ? WN_rtype(load) : MTYPE_I4);
02045     FmtAssert(MTYPE_is_integral(rtype),
02046               ("ASM operand does not satisfy its constraint"));
02047     ret_tn = (pref_tn ? pref_tn : Build_TN_Of_Mtype(rtype));
02048   }
02049   else if ((*constraint == 'r') || (*constraint == 'a') ||
02050      (*constraint == 'b') || (*constraint == 'v') ||
02051      (*constraint == 'h') || (*constraint == 'l') ||
02052      (*constraint == 'd'))
02053   {
02054     TYPE_ID rtype;
02055     if (load != NULL) {
02056       rtype = WN_rtype(load);
02057     } else {
02058       /* We can't figure out what type the operand is, probably because the
02059    optimizer deleted the references to it, so return some default
02060    type based on the constraint. */
02061       rtype = ((*constraint == 'b') ? MTYPE_B : MTYPE_I4);
02062     }
02063     ret_tn = (pref_tn ? pref_tn : Build_TN_Of_Mtype(rtype));
02064   }
02065   else if (*constraint == 't')
02066   {
02067     FmtAssert(pref_tn && TN_is_dedicated(pref_tn) &&
02068         TN_register_class(pref_tn)==ISA_REGISTER_CLASS_UNDEFINED,
02069     ("ASM constraint 't' requires a state register"));
02070     ret_tn = pref_tn;
02071   }
02072   else if (*constraint == 'f')
02073   {
02074     if (load && (WN_desc(load) != MTYPE_F4 || WN_rtype(load) != MTYPE_F4)) {
02075       FmtAssert(FALSE, ("ASM operand does not satisfy its constraint"));
02076     }
02077     ret_tn = (pref_tn ? pref_tn : Build_TN_Of_Mtype(MTYPE_F4));
02078   }
02079   else
02080   {
02081     FmtAssert(FALSE, ("ASM constraint <%s> not supported", constraint));
02082   }
02083 
02084   asm_constraint_tn[asm_constraint_index] = ret_tn;
02085   asm_constraint_index++;
02086   
02087   return ret_tn;
02088 }
02089 
02090 
02091 static char *
02092 Get_TN_Assembly_Name (TN *tn)
02093 {
02094   return "moo";
02095 }
02096 
02097 void
02098 CGTARG_TN_And_Name_For_Asm_Constraint (char *constraint, TYPE_ID mtype,
02099   TYPE_ID desc, TN **tn, char **name)
02100 {
02101   INT i;
02102   if (*constraint == '=') {
02103     // ignore
02104     CGTARG_TN_And_Name_For_Asm_Constraint (constraint+1, 
02105       mtype, desc, tn, name);
02106     return;
02107   }
02108   if (mtype == MTYPE_V) {
02109     // unknown parameter, so pick mtype from constraint
02110     if (*constraint == 'f') mtype = MTYPE_F8;
02111     else mtype = MTYPE_I8;
02112   }
02113   switch (*constraint) {
02114   case 'r':
02115     FmtAssert(MTYPE_is_integral(mtype), 
02116       ("ASM constraint is integer but parameter is not"));
02117     break;
02118   case 'f':
02119     FmtAssert(MTYPE_is_float(mtype), 
02120       ("ASM constraint is float but parameter is not"));
02121     break;
02122   case 'm':
02123     break;
02124   case '0':
02125   case '1':
02126   case '2':
02127   case '3':
02128   case '4':
02129   case '5':
02130   case '6':
02131   case '7':
02132   case '8':
02133   case '9':
02134     i = *constraint - '0';
02135     FmtAssert(asm_constraint_tn[i], 
02136         ("numeric matching constraint refers to NULL value"));
02137     ++asm_constraint_index;
02138     *tn = asm_constraint_tn[i];
02139     *name = asm_constraint_name[i];
02140     return;
02141   case 'i':
02142     // let caller figure out the name
02143     *tn = NULL;
02144     *name = NULL;
02145     return;
02146   default:
02147     FmtAssert(FALSE, ("ASM constraint <%s> not supported", constraint));
02148   }
02149   PLOC ploc = Get_Output_Parameter_Location (MTYPE_To_TY(mtype));
02150   *tn = PREG_To_TN (MTYPE_To_PREG(mtype), PLOC_reg(ploc));
02151   asm_constraint_tn[asm_constraint_index] = *tn;
02152   *name = Get_TN_Assembly_Name(*tn);
02153   if (*constraint == 'm') {
02154         sprintf(asm_constraint_name[asm_constraint_index], "[%s]", 
02155       *name);
02156   } else {
02157         sprintf(asm_constraint_name[asm_constraint_index], "%s", 
02158       *name);
02159   }
02160   *name = asm_constraint_name[asm_constraint_index];
02161   ++asm_constraint_index;
02162 }
02163 
02164 
02165 /* ====================================================================
02166  * target specific modifiers for printing different versions
02167  * of register names when they appear as AM operands 
02168  * ====================================================================
02169  */
02170 char CGTARG_Asm_Opnd_Modifiers[] = { 'r' };
02171 INT  CGTARG_Num_Asm_Opnd_Modifiers = 1;
02172 
02173 const char* 
02174 CGTARG_Modified_Asm_Opnd_Name(char modifier, TN* tn, char *tn_name)
02175 {
02176   if (modifier == 'r') {
02177     return tn_name;
02178   }
02179   else {
02180     FmtAssert(FALSE, ("Unknown ASM operand modifier '%c'", modifier));
02181   }
02182   /*NOTREACHED*/
02183 }
02184 
02185 
02186 /* ====================================================================
02187  *
02188  * CGTARG_Postprocess_Asm_String: currently no-op for IA-64
02189  *
02190  * ====================================================================
02191  */
02192 void 
02193 CGTARG_Postprocess_Asm_String (char*)
02194 {
02195 }
02196 
02197 /* ====================================================================
02198  *
02199  * CGTARG_Unconditional_Compare
02200  *
02201  * See interface description
02202  *
02203  * ====================================================================
02204  */
02205 BOOL CGTARG_Unconditional_Compare(OP *op, TOP* uncond_ver)
02206 {
02207   return FALSE;
02208 }
02209 
02210 /* ====================================================================
02211  *
02212  * CGTARG_Invert_Branch
02213  *
02214  * See interface description
02215  *
02216  * ====================================================================
02217  */
02218 TOP CGTARG_Invert_Branch(BB* bb)
02219 {
02220   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
02221 }
02222 
02223 
02224 /* ====================================================================
02225  *
02226  * CGTARG_Init_OP_cond_def_kind
02227  *
02228  *  See interface description
02229  *
02230  * ====================================================================
02231  */
02232 void CGTARG_Init_OP_cond_def_kind(OP *op)
02233 {
02234   if( OP_has_predicate(op) ) {
02235     FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
02236   } else {
02237       {
02238   Set_OP_cond_def_kind(op, OP_ALWAYS_UNC_DEF);
02239       }
02240   }
02241 }
02242 
02243 
02244 /* ====================================================================
02245  *
02246  * CGTARG_Get_unc_Variant
02247  *
02248  *  Given a compare opcode, return the unconditional variant form. 
02249  *  Return the opcode if there is no such form.
02250  *
02251  * ====================================================================
02252  */
02253 TOP CGTARG_Get_unc_Variant(TOP top)
02254 {
02255   /* This doesn't seem to be used. */
02256   FmtAssert(FALSE,("NOT YET IMPLEMENTED"));
02257   return TOP_UNDEFINED;
02258 }
02259 
02261 // If a BB ends in an unconditional branch, turn it into a conditional branch 
02262 // With TRUE predicate, so we can predicate with something else later.
02263 // If we can't find an unconditional branch, just give up and do nothing
02264 //
02265 void
02266 Make_Branch_Conditional(BB *bb)
02267 {
02268   return;
02269 }
02270 
02271 /* ====================================================================
02272  *
02273  * CGTARG_Check_OP_For_HB_Suitability
02274  *
02275  * Returns TRUE if OP is a suitable candidate for HBF. Otherwise, return
02276  * FALSE.
02277  *
02278  * ====================================================================
02279  */
02280 BOOL 
02281 CGTARG_Check_OP_For_HB_Suitability(OP *op)
02282 {
02283   switch(Eager_Level) {
02284   case EAGER_NONE:
02285     return FALSE;
02286   case EAGER_SAFE:
02287     if (OP_fadd(op) || 
02288   OP_fdiv(op) || 
02289   OP_fsub(op) || 
02290   OP_fmul(op) || 
02291   OP_load(op) ||
02292   OP_store(op) ||
02293   OP_prefetch(op) || 
02294   // idiv, imul use hilo registers
02295   OP_idiv(op) ||
02296   OP_imul(op) || 
02297   (OP_code(op) == TOP_mflo) || 
02298   (OP_code(op) == TOP_mfhi))
02299       return FALSE;
02300     else
02301       return TRUE;      
02302   case EAGER_ARITH:
02303     if (OP_load(op) ||
02304   OP_store(op) ||
02305   OP_prefetch(op) ||
02306   // Divide by zero
02307   OP_fdiv(op) || 
02308   OP_idiv(op) ||
02309   OP_imul(op) ||
02310   (OP_code(op) == TOP_mflo) || 
02311   (OP_code(op) == TOP_mfhi))
02312       return FALSE;
02313     else
02314       return TRUE;
02315   case EAGER_DIVIDE:
02316     if (OP_load(op) ||
02317   OP_store(op) ||
02318   OP_prefetch(op) ||
02319   OP_idiv(op) ||
02320   OP_imul(op) ||
02321   (OP_code(op) == TOP_mflo) || 
02322   (OP_code(op) == TOP_mfhi))
02323       return FALSE;
02324     else
02325       return TRUE;
02326   case EAGER_MEMORY:
02327   case EAGER_OTHER:
02328     if (OP_idiv(op) ||
02329   OP_imul(op) ||
02330   (OP_code(op) == TOP_mflo) || 
02331   (OP_code(op) == TOP_mfhi))      
02332       return FALSE;
02333     else
02334       return TRUE;
02335   default:
02336     FmtAssert(FALSE, ("Handle this case"));
02337     return FALSE;
02338   }
02339 }
02340