Open64: osprey/cygnus/opcodes/openrisc-desc.c Source File

00001 /*
00002  * Copyright 2003, 2004, 2005, 2006 PathScale, Inc.  All Rights Reserved.
00003  */
00004 
00005 /* CPU data for openrisc.
00006 
00007 THIS FILE IS MACHINE GENERATED WITH CGEN.
00008 
00009 Copyright 1996-2005 Free Software Foundation, Inc.
00010 
00011 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00012 
00013 This program is free software; you can redistribute it and/or modify
00014 it under the terms of the GNU General Public License as published by
00015 the Free Software Foundation; either version 2, or (at your option)
00016 any later version.
00017 
00018 This program is distributed in the hope that it will be useful,
00019 but WITHOUT ANY WARRANTY; without even the implied warranty of
00020 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00021 GNU General Public License for more details.
00022 
00023 You should have received a copy of the GNU General Public License along
00024 with this program; if not, write to the Free Software Foundation, Inc.,
00025 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00026 
00027 */
00028 
00029 #include "sysdep.h"
00030 #include <stdio.h>
00031 #include <stdarg.h>
00032 #include "ansidecl.h"
00033 #include "bfd.h"
00034 #include "symcat.h"
00035 #include "openrisc-desc.h"
00036 #include "openrisc-opc.h"
00037 #include "opintl.h"
00038 #include "libiberty.h"
00039 #include "xregex.h"
00040 
00041 /* Attributes.  */
00042 
00043 static const CGEN_ATTR_ENTRY bool_attr[] =
00044 {
00045   { "#f", 0 },
00046   { "#t", 1 },
00047   { 0, 0 }
00048 };
00049 
00050 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00051 {
00052   { "base", MACH_BASE },
00053   { "openrisc", MACH_OPENRISC },
00054   { "or1300", MACH_OR1300 },
00055   { "max", MACH_MAX },
00056   { 0, 0 }
00057 };
00058 
00059 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00060 {
00061   { "or32", ISA_OR32 },
00062   { "max", ISA_MAX },
00063   { 0, 0 }
00064 };
00065 
00066 static const CGEN_ATTR_ENTRY HAS_CACHE_attr[] ATTRIBUTE_UNUSED =
00067 {
00068   { "DATA_CACHE", HAS_CACHE_DATA_CACHE },
00069   { "INSN_CACHE", HAS_CACHE_INSN_CACHE },
00070   { 0, 0 }
00071 };
00072 
00073 const CGEN_ATTR_TABLE openrisc_cgen_ifield_attr_table[] =
00074 {
00075   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00076   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00077   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00078   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00079   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00080   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00081   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00082   { 0, 0, 0 }
00083 };
00084 
00085 const CGEN_ATTR_TABLE openrisc_cgen_hardware_attr_table[] =
00086 {
00087   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00088   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00089   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00090   { "PC", &bool_attr[0], &bool_attr[0] },
00091   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00092   { 0, 0, 0 }
00093 };
00094 
00095 const CGEN_ATTR_TABLE openrisc_cgen_operand_attr_table[] =
00096 {
00097   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00098   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00099   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00100   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00101   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00102   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00103   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00104   { "RELAX", &bool_attr[0], &bool_attr[0] },
00105   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00106   { 0, 0, 0 }
00107 };
00108 
00109 const CGEN_ATTR_TABLE openrisc_cgen_insn_attr_table[] =
00110 {
00111   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00112   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00113   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00114   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00115   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00116   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00117   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00118   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00119   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00120   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00121   { "PBB", &bool_attr[0], &bool_attr[0] },
00122   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00123   { 0, 0, 0 }
00124 };
00125 
00126 /* Instruction set variants.  */
00127 
00128 static const CGEN_ISA openrisc_cgen_isa_table[] = {
00129   { "or32", 32, 32, 32, 32 },
00130   { 0, 0, 0, 0, 0 }
00131 };
00132 
00133 /* Machine variants.  */
00134 
00135 static const CGEN_MACH openrisc_cgen_mach_table[] = {
00136   { "openrisc", "openrisc", MACH_OPENRISC, 0 },
00137   { "or1300", "openrisc:1300", MACH_OR1300, 0 },
00138   { 0, 0, 0, 0 }
00139 };
00140 
00141 static CGEN_KEYWORD_ENTRY openrisc_cgen_opval_h_gr_entries[] =
00142 {
00143   { "r0", 0, {0, {0}}, 0, 0 },
00144   { "r1", 1, {0, {0}}, 0, 0 },
00145   { "r2", 2, {0, {0}}, 0, 0 },
00146   { "r3", 3, {0, {0}}, 0, 0 },
00147   { "r4", 4, {0, {0}}, 0, 0 },
00148   { "r5", 5, {0, {0}}, 0, 0 },
00149   { "r6", 6, {0, {0}}, 0, 0 },
00150   { "r7", 7, {0, {0}}, 0, 0 },
00151   { "r8", 8, {0, {0}}, 0, 0 },
00152   { "r9", 9, {0, {0}}, 0, 0 },
00153   { "r10", 10, {0, {0}}, 0, 0 },
00154   { "r11", 11, {0, {0}}, 0, 0 },
00155   { "r12", 12, {0, {0}}, 0, 0 },
00156   { "r13", 13, {0, {0}}, 0, 0 },
00157   { "r14", 14, {0, {0}}, 0, 0 },
00158   { "r15", 15, {0, {0}}, 0, 0 },
00159   { "r16", 16, {0, {0}}, 0, 0 },
00160   { "r17", 17, {0, {0}}, 0, 0 },
00161   { "r18", 18, {0, {0}}, 0, 0 },
00162   { "r19", 19, {0, {0}}, 0, 0 },
00163   { "r20", 20, {0, {0}}, 0, 0 },
00164   { "r21", 21, {0, {0}}, 0, 0 },
00165   { "r22", 22, {0, {0}}, 0, 0 },
00166   { "r23", 23, {0, {0}}, 0, 0 },
00167   { "r24", 24, {0, {0}}, 0, 0 },
00168   { "r25", 25, {0, {0}}, 0, 0 },
00169   { "r26", 26, {0, {0}}, 0, 0 },
00170   { "r27", 27, {0, {0}}, 0, 0 },
00171   { "r28", 28, {0, {0}}, 0, 0 },
00172   { "r29", 29, {0, {0}}, 0, 0 },
00173   { "r30", 30, {0, {0}}, 0, 0 },
00174   { "r31", 31, {0, {0}}, 0, 0 },
00175   { "lr", 11, {0, {0}}, 0, 0 },
00176   { "sp", 1, {0, {0}}, 0, 0 },
00177   { "fp", 2, {0, {0}}, 0, 0 }
00178 };
00179 
00180 CGEN_KEYWORD openrisc_cgen_opval_h_gr =
00181 {
00182   & openrisc_cgen_opval_h_gr_entries[0],
00183   35,
00184   0, 0, 0, 0, ""
00185 };
00186 
00187 
00188 /* The hardware table.  */
00189 
00190 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00191 #define A(a) (1 << CGEN_HW_##a)
00192 #else
00193 #define A(a) (1 << CGEN_HW_a)
00194 #endif
00195 
00196 const CGEN_HW_ENTRY openrisc_cgen_hw_table[] =
00197 {
00198   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00199   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00200   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00201   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00202   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00203   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
00204   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & openrisc_cgen_opval_h_gr, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
00205   { "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00206   { "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00207   { "h-lo16", HW_H_LO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00208   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00209   { "h-delay-insn", HW_H_DELAY_INSN, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
00210   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
00211 };
00212 
00213 #undef A
00214 
00215 
00216 /* The instruction field table.  */
00217 
00218 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00219 #define A(a) (1 << CGEN_IFLD_##a)
00220 #else
00221 #define A(a) (1 << CGEN_IFLD_a)
00222 #endif
00223 
00224 const CGEN_IFLD openrisc_cgen_ifld_table[] =
00225 {
00226   { OPENRISC_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
00227   { OPENRISC_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
00228   { OPENRISC_F_CLASS, "f-class", 0, 32, 31, 2, { 0, { (1<<MACH_BASE) } }  },
00229   { OPENRISC_F_SUB, "f-sub", 0, 32, 29, 4, { 0, { (1<<MACH_BASE) } }  },
00230   { OPENRISC_F_R1, "f-r1", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
00231   { OPENRISC_F_R2, "f-r2", 0, 32, 20, 5, { 0, { (1<<MACH_BASE) } }  },
00232   { OPENRISC_F_R3, "f-r3", 0, 32, 15, 5, { 0, { (1<<MACH_BASE) } }  },
00233   { OPENRISC_F_SIMM16, "f-simm16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
00234   { OPENRISC_F_UIMM16, "f-uimm16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
00235   { OPENRISC_F_UIMM5, "f-uimm5", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } }  },
00236   { OPENRISC_F_HI16, "f-hi16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
00237   { OPENRISC_F_LO16, "f-lo16", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } }  },
00238   { OPENRISC_F_OP1, "f-op1", 0, 32, 31, 2, { 0, { (1<<MACH_BASE) } }  },
00239   { OPENRISC_F_OP2, "f-op2", 0, 32, 29, 4, { 0, { (1<<MACH_BASE) } }  },
00240   { OPENRISC_F_OP3, "f-op3", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
00241   { OPENRISC_F_OP4, "f-op4", 0, 32, 23, 3, { 0, { (1<<MACH_BASE) } }  },
00242   { OPENRISC_F_OP5, "f-op5", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
00243   { OPENRISC_F_OP6, "f-op6", 0, 32, 7, 3, { 0, { (1<<MACH_BASE) } }  },
00244   { OPENRISC_F_OP7, "f-op7", 0, 32, 3, 4, { 0, { (1<<MACH_BASE) } }  },
00245   { OPENRISC_F_I16_1, "f-i16-1", 0, 32, 10, 11, { 0, { (1<<MACH_BASE) } }  },
00246   { OPENRISC_F_I16_2, "f-i16-2", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } }  },
00247   { OPENRISC_F_DISP26, "f-disp26", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00248   { OPENRISC_F_ABS26, "f-abs26", 0, 32, 25, 26, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
00249   { OPENRISC_F_I16NC, "f-i16nc", 0, 0, 0, 0,{ 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
00250   { OPENRISC_F_F_15_8, "f-f-15-8", 0, 32, 15, 8, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
00251   { OPENRISC_F_F_10_3, "f-f-10-3", 0, 32, 10, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
00252   { OPENRISC_F_F_4_1, "f-f-4-1", 0, 32, 4, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
00253   { OPENRISC_F_F_7_3, "f-f-7-3", 0, 32, 7, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
00254   { OPENRISC_F_F_10_7, "f-f-10-7", 0, 32, 10, 7, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
00255   { OPENRISC_F_F_10_11, "f-f-10-11", 0, 32, 10, 11, { 0|A(RESERVED), { (1<<MACH_BASE) } }  },
00256   { 0, 0, 0, 0, 0, 0, {0, {0}} }
00257 };
00258 
00259 #undef A
00260 
00261 
00262 
00263 /* multi ifield declarations */
00264 
00265 const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [];
00266 
00267 
00268 /* multi ifield definitions */
00269 
00270 const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] =
00271 {
00272     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_1] } },
00273     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_I16_2] } },
00274     { 0, { (const PTR) 0 } }
00275 };
00276 
00277 /* The operand table.  */
00278 
00279 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00280 #define A(a) (1 << CGEN_OPERAND_##a)
00281 #else
00282 #define A(a) (1 << CGEN_OPERAND_a)
00283 #endif
00284 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00285 #define OPERAND(op) OPENRISC_OPERAND_##op
00286 #else
00287 #define OPERAND(op) OPENRISC_OPERAND_op
00288 #endif
00289 
00290 const CGEN_OPERAND openrisc_cgen_operand_table[] =
00291 {
00292 /* pc: program counter */
00293   { "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0,
00294     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_NIL] } }, 
00295     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00296 /* sr: special register */
00297   { "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0,
00298     { 0, { (const PTR) 0 } }, 
00299     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00300 /* cbit: condition bit */
00301   { "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
00302     { 0, { (const PTR) 0 } }, 
00303     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
00304 /* simm-16: 16 bit signed immediate */
00305   { "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16,
00306     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, 
00307     { 0, { (1<<MACH_BASE) } }  },
00308 /* uimm-16: 16 bit unsigned immediate */
00309   { "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
00310     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM16] } }, 
00311     { 0, { (1<<MACH_BASE) } }  },
00312 /* disp-26: pc-rel 26 bit */
00313   { "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26,
00314     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_DISP26] } }, 
00315     { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
00316 /* abs-26: abs 26 bit */
00317   { "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26,
00318     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_ABS26] } }, 
00319     { 0|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
00320 /* uimm-5: imm5 */
00321   { "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
00322     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_UIMM5] } }, 
00323     { 0, { (1<<MACH_BASE) } }  },
00324 /* rD: destination register */
00325   { "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5,
00326     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R1] } }, 
00327     { 0, { (1<<MACH_BASE) } }  },
00328 /* rA: source register A */
00329   { "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5,
00330     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R2] } }, 
00331     { 0, { (1<<MACH_BASE) } }  },
00332 /* rB: source register B */
00333   { "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5,
00334     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_R3] } }, 
00335     { 0, { (1<<MACH_BASE) } }  },
00336 /* op-f-23: f-op23 */
00337   { "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
00338     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP4] } }, 
00339     { 0, { (1<<MACH_BASE) } }  },
00340 /* op-f-3: f-op3 */
00341   { "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
00342     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_OP5] } }, 
00343     { 0, { (1<<MACH_BASE) } }  },
00344 /* hi16: high 16 bit immediate, sign optional */
00345   { "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16,
00346     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_SIMM16] } }, 
00347     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
00348 /* lo16: low 16 bit immediate, sign optional */
00349   { "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16,
00350     { 0, { (const PTR) &openrisc_cgen_ifld_table[OPENRISC_F_LO16] } }, 
00351     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
00352 /* ui16nc: 16 bit immediate, sign optional */
00353   { "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16,
00354     { 2, { (const PTR) &OPENRISC_F_I16NC_MULTI_IFIELD[0] } }, 
00355     { 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } }  },
00356 /* sentinel */
00357   { 0, 0, 0, 0, 0,
00358     { 0, { (const PTR) 0 } },
00359     { 0, { 0 } } }
00360 };
00361 
00362 #undef A
00363 
00364 
00365 /* The instruction table.  */
00366 
00367 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00368 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00369 #define A(a) (1 << CGEN_INSN_##a)
00370 #else
00371 #define A(a) (1 << CGEN_INSN_a)
00372 #endif
00373 
00374 static const CGEN_IBASE openrisc_cgen_insn_table[MAX_INSNS] =
00375 {
00376   /* Special null first entry.
00377      A `num' value of zero is thus invalid.
00378      Also, the special `invalid' insn resides here.  */
00379   { 0, 0, 0, 0, {0, {0}} },
00380 /* l.j ${abs-26} */
00381   {
00382     OPENRISC_INSN_L_J, "l-j", "l.j", 32,
00383     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00384   },
00385 /* l.jal ${abs-26} */
00386   {
00387     OPENRISC_INSN_L_JAL, "l-jal", "l.jal", 32,
00388     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00389   },
00390 /* l.jr $rA */
00391   {
00392     OPENRISC_INSN_L_JR, "l-jr", "l.jr", 32,
00393     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00394   },
00395 /* l.jalr $rA */
00396   {
00397     OPENRISC_INSN_L_JALR, "l-jalr", "l.jalr", 32,
00398     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00399   },
00400 /* l.bal ${disp-26} */
00401   {
00402     OPENRISC_INSN_L_BAL, "l-bal", "l.bal", 32,
00403     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00404   },
00405 /* l.bnf ${disp-26} */
00406   {
00407     OPENRISC_INSN_L_BNF, "l-bnf", "l.bnf", 32,
00408     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00409   },
00410 /* l.bf ${disp-26} */
00411   {
00412     OPENRISC_INSN_L_BF, "l-bf", "l.bf", 32,
00413     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00414   },
00415 /* l.brk ${uimm-16} */
00416   {
00417     OPENRISC_INSN_L_BRK, "l-brk", "l.brk", 32,
00418     { 0|A(NOT_IN_DELAY_SLOT), { (1<<MACH_BASE) } }
00419   },
00420 /* l.rfe $rA */
00421   {
00422     OPENRISC_INSN_L_RFE, "l-rfe", "l.rfe", 32,
00423     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00424   },
00425 /* l.sys ${uimm-16} */
00426   {
00427     OPENRISC_INSN_L_SYS, "l-sys", "l.sys", 32,
00428     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00429   },
00430 /* l.nop */
00431   {
00432     OPENRISC_INSN_L_NOP, "l-nop", "l.nop", 32,
00433     { 0, { (1<<MACH_BASE) } }
00434   },
00435 /* l.movhi $rD,$hi16 */
00436   {
00437     OPENRISC_INSN_L_MOVHI, "l-movhi", "l.movhi", 32,
00438     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00439   },
00440 /* l.mfsr $rD,$rA */
00441   {
00442     OPENRISC_INSN_L_MFSR, "l-mfsr", "l.mfsr", 32,
00443     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00444   },
00445 /* l.mtsr $rA,$rB */
00446   {
00447     OPENRISC_INSN_L_MTSR, "l-mtsr", "l.mtsr", 32,
00448     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00449   },
00450 /* l.lw $rD,${simm-16}($rA) */
00451   {
00452     OPENRISC_INSN_L_LW, "l-lw", "l.lw", 32,
00453     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00454   },
00455 /* l.lbz $rD,${simm-16}($rA) */
00456   {
00457     OPENRISC_INSN_L_LBZ, "l-lbz", "l.lbz", 32,
00458     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00459   },
00460 /* l.lbs $rD,${simm-16}($rA) */
00461   {
00462     OPENRISC_INSN_L_LBS, "l-lbs", "l.lbs", 32,
00463     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00464   },
00465 /* l.lhz $rD,${simm-16}($rA) */
00466   {
00467     OPENRISC_INSN_L_LHZ, "l-lhz", "l.lhz", 32,
00468     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00469   },
00470 /* l.lhs $rD,${simm-16}($rA) */
00471   {
00472     OPENRISC_INSN_L_LHS, "l-lhs", "l.lhs", 32,
00473     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00474   },
00475 /* l.sw ${ui16nc}($rA),$rB */
00476   {
00477     OPENRISC_INSN_L_SW, "l-sw", "l.sw", 32,
00478     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00479   },
00480 /* l.sb ${ui16nc}($rA),$rB */
00481   {
00482     OPENRISC_INSN_L_SB, "l-sb", "l.sb", 32,
00483     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00484   },
00485 /* l.sh ${ui16nc}($rA),$rB */
00486   {
00487     OPENRISC_INSN_L_SH, "l-sh", "l.sh", 32,
00488     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00489   },
00490 /* l.sll $rD,$rA,$rB */
00491   {
00492     OPENRISC_INSN_L_SLL, "l-sll", "l.sll", 32,
00493     { 0, { (1<<MACH_BASE) } }
00494   },
00495 /* l.slli $rD,$rA,${uimm-5} */
00496   {
00497     OPENRISC_INSN_L_SLLI, "l-slli", "l.slli", 32,
00498     { 0, { (1<<MACH_BASE) } }
00499   },
00500 /* l.srl $rD,$rA,$rB */
00501   {
00502     OPENRISC_INSN_L_SRL, "l-srl", "l.srl", 32,
00503     { 0, { (1<<MACH_BASE) } }
00504   },
00505 /* l.srli $rD,$rA,${uimm-5} */
00506   {
00507     OPENRISC_INSN_L_SRLI, "l-srli", "l.srli", 32,
00508     { 0, { (1<<MACH_BASE) } }
00509   },
00510 /* l.sra $rD,$rA,$rB */
00511   {
00512     OPENRISC_INSN_L_SRA, "l-sra", "l.sra", 32,
00513     { 0, { (1<<MACH_BASE) } }
00514   },
00515 /* l.srai $rD,$rA,${uimm-5} */
00516   {
00517     OPENRISC_INSN_L_SRAI, "l-srai", "l.srai", 32,
00518     { 0, { (1<<MACH_BASE) } }
00519   },
00520 /* l.ror $rD,$rA,$rB */
00521   {
00522     OPENRISC_INSN_L_ROR, "l-ror", "l.ror", 32,
00523     { 0, { (1<<MACH_BASE) } }
00524   },
00525 /* l.rori $rD,$rA,${uimm-5} */
00526   {
00527     OPENRISC_INSN_L_RORI, "l-rori", "l.rori", 32,
00528     { 0, { (1<<MACH_BASE) } }
00529   },
00530 /* l.add $rD,$rA,$rB */
00531   {
00532     OPENRISC_INSN_L_ADD, "l-add", "l.add", 32,
00533     { 0, { (1<<MACH_BASE) } }
00534   },
00535 /* l.addi $rD,$rA,$lo16 */
00536   {
00537     OPENRISC_INSN_L_ADDI, "l-addi", "l.addi", 32,
00538     { 0, { (1<<MACH_BASE) } }
00539   },
00540 /* l.sub $rD,$rA,$rB */
00541   {
00542     OPENRISC_INSN_L_SUB, "l-sub", "l.sub", 32,
00543     { 0, { (1<<MACH_BASE) } }
00544   },
00545 /* l.subi $rD,$rA,$lo16 */
00546   {
00547     OPENRISC_INSN_L_SUBI, "l-subi", "l.subi", 32,
00548     { 0, { (1<<MACH_BASE) } }
00549   },
00550 /* l.and $rD,$rA,$rB */
00551   {
00552     OPENRISC_INSN_L_AND, "l-and", "l.and", 32,
00553     { 0, { (1<<MACH_BASE) } }
00554   },
00555 /* l.andi $rD,$rA,$lo16 */
00556   {
00557     OPENRISC_INSN_L_ANDI, "l-andi", "l.andi", 32,
00558     { 0, { (1<<MACH_BASE) } }
00559   },
00560 /* l.or $rD,$rA,$rB */
00561   {
00562     OPENRISC_INSN_L_OR, "l-or", "l.or", 32,
00563     { 0, { (1<<MACH_BASE) } }
00564   },
00565 /* l.ori $rD,$rA,$lo16 */
00566   {
00567     OPENRISC_INSN_L_ORI, "l-ori", "l.ori", 32,
00568     { 0, { (1<<MACH_BASE) } }
00569   },
00570 /* l.xor $rD,$rA,$rB */
00571   {
00572     OPENRISC_INSN_L_XOR, "l-xor", "l.xor", 32,
00573     { 0, { (1<<MACH_BASE) } }
00574   },
00575 /* l.xori $rD,$rA,$lo16 */
00576   {
00577     OPENRISC_INSN_L_XORI, "l-xori", "l.xori", 32,
00578     { 0, { (1<<MACH_BASE) } }
00579   },
00580 /* l.mul $rD,$rA,$rB */
00581   {
00582     OPENRISC_INSN_L_MUL, "l-mul", "l.mul", 32,
00583     { 0, { (1<<MACH_BASE) } }
00584   },
00585 /* l.muli $rD,$rA,$lo16 */
00586   {
00587     OPENRISC_INSN_L_MULI, "l-muli", "l.muli", 32,
00588     { 0, { (1<<MACH_BASE) } }
00589   },
00590 /* l.div $rD,$rA,$rB */
00591   {
00592     OPENRISC_INSN_L_DIV, "l-div", "l.div", 32,
00593     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00594   },
00595 /* l.divu $rD,$rA,$rB */
00596   {
00597     OPENRISC_INSN_L_DIVU, "l-divu", "l.divu", 32,
00598     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00599   },
00600 /* l.sfgts $rA,$rB */
00601   {
00602     OPENRISC_INSN_L_SFGTS, "l-sfgts", "l.sfgts", 32,
00603     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00604   },
00605 /* l.sfgtu $rA,$rB */
00606   {
00607     OPENRISC_INSN_L_SFGTU, "l-sfgtu", "l.sfgtu", 32,
00608     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00609   },
00610 /* l.sfges $rA,$rB */
00611   {
00612     OPENRISC_INSN_L_SFGES, "l-sfges", "l.sfges", 32,
00613     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00614   },
00615 /* l.sfgeu $rA,$rB */
00616   {
00617     OPENRISC_INSN_L_SFGEU, "l-sfgeu", "l.sfgeu", 32,
00618     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00619   },
00620 /* l.sflts $rA,$rB */
00621   {
00622     OPENRISC_INSN_L_SFLTS, "l-sflts", "l.sflts", 32,
00623     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00624   },
00625 /* l.sfltu $rA,$rB */
00626   {
00627     OPENRISC_INSN_L_SFLTU, "l-sfltu", "l.sfltu", 32,
00628     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00629   },
00630 /* l.sfles $rA,$rB */
00631   {
00632     OPENRISC_INSN_L_SFLES, "l-sfles", "l.sfles", 32,
00633     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00634   },
00635 /* l.sfleu $rA,$rB */
00636   {
00637     OPENRISC_INSN_L_SFLEU, "l-sfleu", "l.sfleu", 32,
00638     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00639   },
00640 /* l.sfgtsi $rA,${simm-16} */
00641   {
00642     OPENRISC_INSN_L_SFGTSI, "l-sfgtsi", "l.sfgtsi", 32,
00643     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00644   },
00645 /* l.sfgtui $rA,${uimm-16} */
00646   {
00647     OPENRISC_INSN_L_SFGTUI, "l-sfgtui", "l.sfgtui", 32,
00648     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00649   },
00650 /* l.sfgesi $rA,${simm-16} */
00651   {
00652     OPENRISC_INSN_L_SFGESI, "l-sfgesi", "l.sfgesi", 32,
00653     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00654   },
00655 /* l.sfgeui $rA,${uimm-16} */
00656   {
00657     OPENRISC_INSN_L_SFGEUI, "l-sfgeui", "l.sfgeui", 32,
00658     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00659   },
00660 /* l.sfltsi $rA,${simm-16} */
00661   {
00662     OPENRISC_INSN_L_SFLTSI, "l-sfltsi", "l.sfltsi", 32,
00663     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00664   },
00665 /* l.sfltui $rA,${uimm-16} */
00666   {
00667     OPENRISC_INSN_L_SFLTUI, "l-sfltui", "l.sfltui", 32,
00668     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00669   },
00670 /* l.sflesi $rA,${simm-16} */
00671   {
00672     OPENRISC_INSN_L_SFLESI, "l-sflesi", "l.sflesi", 32,
00673     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00674   },
00675 /* l.sfleui $rA,${uimm-16} */
00676   {
00677     OPENRISC_INSN_L_SFLEUI, "l-sfleui", "l.sfleui", 32,
00678     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00679   },
00680 /* l.sfeq $rA,$rB */
00681   {
00682     OPENRISC_INSN_L_SFEQ, "l-sfeq", "l.sfeq", 32,
00683     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00684   },
00685 /* l.sfeqi $rA,${simm-16} */
00686   {
00687     OPENRISC_INSN_L_SFEQI, "l-sfeqi", "l.sfeqi", 32,
00688     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00689   },
00690 /* l.sfne $rA,$rB */
00691   {
00692     OPENRISC_INSN_L_SFNE, "l-sfne", "l.sfne", 32,
00693     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00694   },
00695 /* l.sfnei $rA,${simm-16} */
00696   {
00697     OPENRISC_INSN_L_SFNEI, "l-sfnei", "l.sfnei", 32,
00698     { 0|A(DELAY_SLOT), { (1<<MACH_BASE) } }
00699   },
00700 };
00701 
00702 #undef OP
00703 #undef A
00704 
00705 /* Initialize anything needed to be done once, before any cpu_open call.  */
00706 static void init_tables PARAMS ((void));
00707 
00708 static void
00709 init_tables ()
00710 {
00711 }
00712 
00713 static const CGEN_MACH * lookup_mach_via_bfd_name
00714   PARAMS ((const CGEN_MACH *, const char *));
00715 static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
00716 static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
00717 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
00718 static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
00719 static void openrisc_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
00720 
00721 /* Subroutine of openrisc_cgen_cpu_open to look up a mach via its bfd name.  */
00722 
00723 static const CGEN_MACH *
00724 lookup_mach_via_bfd_name (table, name)
00725      const CGEN_MACH *table;
00726      const char *name;
00727 {
00728   while (table->name)
00729     {
00730       if (strcmp (name, table->bfd_name) == 0)
00731   return table;
00732       ++table;
00733     }
00734   abort ();
00735 }
00736 
00737 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
00738 
00739 static void
00740 build_hw_table (cd)
00741      CGEN_CPU_TABLE *cd;
00742 {
00743   int i;
00744   int machs = cd->machs;
00745   const CGEN_HW_ENTRY *init = & openrisc_cgen_hw_table[0];
00746   /* MAX_HW is only an upper bound on the number of selected entries.
00747      However each entry is indexed by it's enum so there can be holes in
00748      the table.  */
00749   const CGEN_HW_ENTRY **selected =
00750     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
00751 
00752   cd->hw_table.init_entries = init;
00753   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
00754   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
00755   /* ??? For now we just use machs to determine which ones we want.  */
00756   for (i = 0; init[i].name != NULL; ++i)
00757     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
00758   & machs)
00759       selected[init[i].type] = &init[i];
00760   cd->hw_table.entries = selected;
00761   cd->hw_table.num_entries = MAX_HW;
00762 }
00763 
00764 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
00765 
00766 static void
00767 build_ifield_table (cd)
00768      CGEN_CPU_TABLE *cd;
00769 {
00770   cd->ifld_table = & openrisc_cgen_ifld_table[0];
00771 }
00772 
00773 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.  */
00774 
00775 static void
00776 build_operand_table (cd)
00777      CGEN_CPU_TABLE *cd;
00778 {
00779   int i;
00780   int machs = cd->machs;
00781   const CGEN_OPERAND *init = & openrisc_cgen_operand_table[0];
00782   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
00783      However each entry is indexed by it's enum so there can be holes in
00784      the table.  */
00785   const CGEN_OPERAND **selected =
00786     (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
00787 
00788   cd->operand_table.init_entries = init;
00789   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
00790   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
00791   /* ??? For now we just use mach to determine which ones we want.  */
00792   for (i = 0; init[i].name != NULL; ++i)
00793     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
00794   & machs)
00795       selected[init[i].type] = &init[i];
00796   cd->operand_table.entries = selected;
00797   cd->operand_table.num_entries = MAX_OPERANDS;
00798 }
00799 
00800 /* Subroutine of openrisc_cgen_cpu_open to build the hardware table.
00801    ??? This could leave out insns not supported by the specified mach/isa,
00802    but that would cause errors like "foo only supported by bar" to become
00803    "unknown insn", so for now we include all insns and require the app to
00804    do the checking later.
00805    ??? On the other hand, parsing of such insns may require their hardware or
00806    operand elements to be in the table [which they mightn't be].  */
00807 
00808 static void
00809 build_insn_table (cd)
00810      CGEN_CPU_TABLE *cd;
00811 {
00812   int i;
00813   const CGEN_IBASE *ib = & openrisc_cgen_insn_table[0];
00814   CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
00815 
00816   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
00817   for (i = 0; i < MAX_INSNS; ++i)
00818     insns[i].base = &ib[i];
00819   cd->insn_table.init_entries = insns;
00820   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
00821   cd->insn_table.num_init_entries = MAX_INSNS;
00822 }
00823 
00824 /* Subroutine of openrisc_cgen_cpu_open to rebuild the tables.  */
00825 
00826 static void
00827 openrisc_cgen_rebuild_tables (cd)
00828      CGEN_CPU_TABLE *cd;
00829 {
00830   int i;
00831   unsigned int isas = cd->isas;
00832   unsigned int machs = cd->machs;
00833 
00834   cd->int_insn_p = CGEN_INT_INSN_P;
00835 
00836   /* Data derived from the isa spec.  */
00837 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
00838   cd->default_insn_bitsize = UNSET;
00839   cd->base_insn_bitsize = UNSET;
00840   cd->min_insn_bitsize = 65535; /* some ridiculously big number */
00841   cd->max_insn_bitsize = 0;
00842   for (i = 0; i < MAX_ISAS; ++i)
00843     if (((1 << i) & isas) != 0)
00844       {
00845   const CGEN_ISA *isa = & openrisc_cgen_isa_table[i];
00846 
00847   /* Default insn sizes of all selected isas must be
00848      equal or we set the result to 0, meaning "unknown".  */
00849   if (cd->default_insn_bitsize == UNSET)
00850     cd->default_insn_bitsize = isa->default_insn_bitsize;
00851   else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
00852     ; /* this is ok */
00853   else
00854     cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
00855 
00856   /* Base insn sizes of all selected isas must be equal
00857      or we set the result to 0, meaning "unknown".  */
00858   if (cd->base_insn_bitsize == UNSET)
00859     cd->base_insn_bitsize = isa->base_insn_bitsize;
00860   else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
00861     ; /* this is ok */
00862   else
00863     cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
00864 
00865   /* Set min,max insn sizes.  */
00866   if (isa->min_insn_bitsize < cd->min_insn_bitsize)
00867     cd->min_insn_bitsize = isa->min_insn_bitsize;
00868   if (isa->max_insn_bitsize > cd->max_insn_bitsize)
00869     cd->max_insn_bitsize = isa->max_insn_bitsize;
00870       }
00871 
00872   /* Data derived from the mach spec.  */
00873   for (i = 0; i < MAX_MACHS; ++i)
00874     if (((1 << i) & machs) != 0)
00875       {
00876   const CGEN_MACH *mach = & openrisc_cgen_mach_table[i];
00877 
00878   if (mach->insn_chunk_bitsize != 0)
00879   {
00880     if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
00881       {
00882         fprintf (stderr, "openrisc_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
00883            cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
00884         abort ();
00885       }
00886 
00887     cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
00888   }
00889       }
00890 
00891   /* Determine which hw elements are used by MACH.  */
00892   build_hw_table (cd);
00893 
00894   /* Build the ifield table.  */
00895   build_ifield_table (cd);
00896 
00897   /* Determine which operands are used by MACH/ISA.  */
00898   build_operand_table (cd);
00899 
00900   /* Build the instruction table.  */
00901   build_insn_table (cd);
00902 }
00903 
00904 /* Initialize a cpu table and return a descriptor.
00905    It's much like opening a file, and must be the first function called.
00906    The arguments are a set of (type/value) pairs, terminated with
00907    CGEN_CPU_OPEN_END.
00908 
00909    Currently supported values:
00910    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
00911    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
00912    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
00913    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
00914    CGEN_CPU_OPEN_END:     terminates arguments
00915 
00916    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
00917    precluded.
00918 
00919    ??? We only support ISO C stdargs here, not K&R.
00920    Laziness, plus experiment to see if anything requires K&R - eventually
00921    K&R will no longer be supported - e.g. GDB is currently trying this.  */
00922 
00923 CGEN_CPU_DESC
00924 openrisc_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
00925 {
00926   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
00927   static int init_p;
00928   unsigned int isas = 0;  /* 0 = "unspecified" */
00929   unsigned int machs = 0; /* 0 = "unspecified" */
00930   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
00931   va_list ap;
00932 
00933   if (! init_p)
00934     {
00935       init_tables ();
00936       init_p = 1;
00937     }
00938 
00939   memset (cd, 0, sizeof (*cd));
00940 
00941   va_start (ap, arg_type);
00942   while (arg_type != CGEN_CPU_OPEN_END)
00943     {
00944       switch (arg_type)
00945   {
00946   case CGEN_CPU_OPEN_ISAS :
00947     isas = va_arg (ap, unsigned int);
00948     break;
00949   case CGEN_CPU_OPEN_MACHS :
00950     machs = va_arg (ap, unsigned int);
00951     break;
00952   case CGEN_CPU_OPEN_BFDMACH :
00953     {
00954       const char *name = va_arg (ap, const char *);
00955       const CGEN_MACH *mach =
00956         lookup_mach_via_bfd_name (openrisc_cgen_mach_table, name);
00957 
00958       machs |= 1 << mach->num;
00959       break;
00960     }
00961   case CGEN_CPU_OPEN_ENDIAN :
00962     endian = va_arg (ap, enum cgen_endian);
00963     break;
00964   default :
00965     fprintf (stderr, "openrisc_cgen_cpu_open: unsupported argument `%d'\n",
00966        arg_type);
00967     abort (); /* ??? return NULL? */
00968   }
00969       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
00970     }
00971   va_end (ap);
00972 
00973   /* mach unspecified means "all" */
00974   if (machs == 0)
00975     machs = (1 << MAX_MACHS) - 1;
00976   /* base mach is always selected */
00977   machs |= 1;
00978   /* isa unspecified means "all" */
00979   if (isas == 0)
00980     isas = (1 << MAX_ISAS) - 1;
00981   if (endian == CGEN_ENDIAN_UNKNOWN)
00982     {
00983       /* ??? If target has only one, could have a default.  */
00984       fprintf (stderr, "openrisc_cgen_cpu_open: no endianness specified\n");
00985       abort ();
00986     }
00987 
00988   cd->isas = isas;
00989   cd->machs = machs;
00990   cd->endian = endian;
00991   /* FIXME: for the sparc case we can determine insn-endianness statically.
00992      The worry here is where both data and insn endian can be independently
00993      chosen, in which case this function will need another argument.
00994      Actually, will want to allow for more arguments in the future anyway.  */
00995   cd->insn_endian = endian;
00996 
00997   /* Table (re)builder.  */
00998   cd->rebuild_tables = openrisc_cgen_rebuild_tables;
00999   openrisc_cgen_rebuild_tables (cd);
01000 
01001   /* Default to not allowing signed overflow.  */
01002   cd->signed_overflow_ok_p = 0;
01003   
01004   return (CGEN_CPU_DESC) cd;
01005 }
01006 
01007 /* Cover fn to openrisc_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
01008    MACH_NAME is the bfd name of the mach.  */
01009 
01010 CGEN_CPU_DESC
01011 openrisc_cgen_cpu_open_1 (mach_name, endian)
01012      const char *mach_name;
01013      enum cgen_endian endian;
01014 {
01015   return openrisc_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
01016              CGEN_CPU_OPEN_ENDIAN, endian,
01017              CGEN_CPU_OPEN_END);
01018 }
01019 
01020 /* Close a cpu table.
01021    ??? This can live in a machine independent file, but there's currently
01022    no place to put this file (there's no libcgen).  libopcodes is the wrong
01023    place as some simulator ports use this but they don't use libopcodes.  */
01024 
01025 void
01026 openrisc_cgen_cpu_close (cd)
01027      CGEN_CPU_DESC cd;
01028 {
01029   unsigned int i;
01030   const CGEN_INSN *insns;
01031 
01032   if (cd->macro_insn_table.init_entries)
01033     {
01034       insns = cd->macro_insn_table.init_entries;
01035       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
01036   {
01037     if (CGEN_INSN_RX ((insns)))
01038       regfree (CGEN_INSN_RX (insns));
01039   }
01040     }
01041 
01042   if (cd->insn_table.init_entries)
01043     {
01044       insns = cd->insn_table.init_entries;
01045       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
01046   {
01047     if (CGEN_INSN_RX (insns))
01048       regfree (CGEN_INSN_RX (insns));
01049   }
01050     }
01051 
01052   
01053 
01054   if (cd->macro_insn_table.init_entries)
01055     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
01056 
01057   if (cd->insn_table.init_entries)
01058     free ((CGEN_INSN *) cd->insn_table.init_entries);
01059 
01060   if (cd->hw_table.entries)
01061     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
01062 
01063   if (cd->operand_table.entries)
01064     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
01065 
01066   free (cd);
01067 }
01068