00001
00002
00003
00004 #include "config.h"
00005 #include "system.h"
00006 #include "rtl.h"
00007 #include "tm_p.h"
00008 #include "function.h"
00009 #include "expr.h"
00010 #include "optabs.h"
00011 #include "real.h"
00012 #include "flags.h"
00013 #include "output.h"
00014 #include "insn-config.h"
00015 #include "hard-reg-set.h"
00016 #include "recog.h"
00017 #include "resource.h"
00018 #include "reload.h"
00019 #include "toplev.h"
00020 #include "ggc.h"
00021
00022 #define FAIL return (end_sequence (), _val)
00023 #define DONE return (_val = get_insns (), end_sequence (), _val)
00024
00025
00026 rtx
00027 gen_trap ()
00028 {
00029 return gen_rtx_TRAP_IF (VOIDmode,
00030 const1_rtx,
00031 const0_rtx);
00032 }
00033
00034
00035 rtx
00036 gen_adddf3 (operand0, operand1, operand2)
00037 rtx operand0;
00038 rtx operand1;
00039 rtx operand2;
00040 {
00041 return gen_rtx_SET (VOIDmode,
00042 operand0,
00043 gen_rtx_PLUS (DFmode,
00044 operand1,
00045 operand2));
00046 }
00047
00048
00049 rtx
00050 gen_addsf3 (operand0, operand1, operand2)
00051 rtx operand0;
00052 rtx operand1;
00053 rtx operand2;
00054 {
00055 return gen_rtx_SET (VOIDmode,
00056 operand0,
00057 gen_rtx_PLUS (SFmode,
00058 operand1,
00059 operand2));
00060 }
00061
00062
00063 rtx
00064 gen_addsi3_internal (operand0, operand1, operand2)
00065 rtx operand0;
00066 rtx operand1;
00067 rtx operand2;
00068 {
00069 return gen_rtx_SET (VOIDmode,
00070 operand0,
00071 gen_rtx_PLUS (SImode,
00072 operand1,
00073 operand2));
00074 }
00075
00076
00077 rtx
00078 gen_adddi3_internal_1 (operand0, operand1, operand2, operand3)
00079 rtx operand0;
00080 rtx operand1;
00081 rtx operand2;
00082 rtx operand3;
00083 {
00084 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00085 gen_rtx_SET (VOIDmode,
00086 operand0,
00087 gen_rtx_PLUS (DImode,
00088 operand1,
00089 operand2)),
00090 gen_rtx_CLOBBER (VOIDmode,
00091 operand3)));
00092 }
00093
00094
00095 rtx
00096 gen_adddi3_internal_2 (operand0, operand1, operand2, operand3)
00097 rtx operand0;
00098 rtx operand1;
00099 rtx operand2;
00100 rtx operand3;
00101 {
00102 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00103 gen_rtx_SET (VOIDmode,
00104 operand0,
00105 gen_rtx_PLUS (DImode,
00106 operand1,
00107 operand2)),
00108 gen_rtx_CLOBBER (VOIDmode,
00109 operand3)));
00110 }
00111
00112
00113 rtx
00114 gen_adddi3_internal_3 (operand0, operand1, operand2)
00115 rtx operand0;
00116 rtx operand1;
00117 rtx operand2;
00118 {
00119 return gen_rtx_SET (VOIDmode,
00120 operand0,
00121 gen_rtx_PLUS (DImode,
00122 operand1,
00123 operand2));
00124 }
00125
00126
00127 rtx
00128 gen_addsi3_internal_2 (operand0, operand1, operand2)
00129 rtx operand0;
00130 rtx operand1;
00131 rtx operand2;
00132 {
00133 return gen_rtx_SET (VOIDmode,
00134 operand0,
00135 gen_rtx_SIGN_EXTEND (DImode,
00136 gen_rtx_PLUS (SImode,
00137 operand1,
00138 operand2)));
00139 }
00140
00141
00142 rtx
00143 gen_subdf3 (operand0, operand1, operand2)
00144 rtx operand0;
00145 rtx operand1;
00146 rtx operand2;
00147 {
00148 return gen_rtx_SET (VOIDmode,
00149 operand0,
00150 gen_rtx_MINUS (DFmode,
00151 operand1,
00152 operand2));
00153 }
00154
00155
00156 rtx
00157 gen_subsf3 (operand0, operand1, operand2)
00158 rtx operand0;
00159 rtx operand1;
00160 rtx operand2;
00161 {
00162 return gen_rtx_SET (VOIDmode,
00163 operand0,
00164 gen_rtx_MINUS (SFmode,
00165 operand1,
00166 operand2));
00167 }
00168
00169
00170 rtx
00171 gen_subsi3_internal (operand0, operand1, operand2)
00172 rtx operand0;
00173 rtx operand1;
00174 rtx operand2;
00175 {
00176 return gen_rtx_SET (VOIDmode,
00177 operand0,
00178 gen_rtx_MINUS (SImode,
00179 operand1,
00180 operand2));
00181 }
00182
00183
00184 rtx
00185 gen_subdi3_internal (operand0, operand1, operand2, operand3)
00186 rtx operand0;
00187 rtx operand1;
00188 rtx operand2;
00189 rtx operand3;
00190 {
00191 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00192 gen_rtx_SET (VOIDmode,
00193 operand0,
00194 gen_rtx_MINUS (DImode,
00195 operand1,
00196 operand2)),
00197 gen_rtx_CLOBBER (VOIDmode,
00198 operand3)));
00199 }
00200
00201
00202 rtx
00203 gen_subdi3_internal_2 (operand0, operand1, operand2, operand3)
00204 rtx operand0;
00205 rtx operand1;
00206 rtx operand2;
00207 rtx operand3;
00208 {
00209 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00210 gen_rtx_SET (VOIDmode,
00211 operand0,
00212 gen_rtx_MINUS (DImode,
00213 operand1,
00214 operand2)),
00215 gen_rtx_CLOBBER (VOIDmode,
00216 operand3)));
00217 }
00218
00219
00220 rtx
00221 gen_subdi3_internal_3 (operand0, operand1, operand2)
00222 rtx operand0;
00223 rtx operand1;
00224 rtx operand2;
00225 {
00226 return gen_rtx_SET (VOIDmode,
00227 operand0,
00228 gen_rtx_MINUS (DImode,
00229 operand1,
00230 operand2));
00231 }
00232
00233
00234 rtx
00235 gen_subsi3_internal_2 (operand0, operand1, operand2)
00236 rtx operand0;
00237 rtx operand1;
00238 rtx operand2;
00239 {
00240 return gen_rtx_SET (VOIDmode,
00241 operand0,
00242 gen_rtx_SIGN_EXTEND (DImode,
00243 gen_rtx_MINUS (SImode,
00244 operand1,
00245 operand2)));
00246 }
00247
00248
00249 rtx
00250 gen_muldf3_internal (operand0, operand1, operand2)
00251 rtx operand0;
00252 rtx operand1;
00253 rtx operand2;
00254 {
00255 return gen_rtx_SET (VOIDmode,
00256 operand0,
00257 gen_rtx_MULT (DFmode,
00258 operand1,
00259 operand2));
00260 }
00261
00262
00263 rtx
00264 gen_muldf3_r4300 (operand0, operand1, operand2)
00265 rtx operand0;
00266 rtx operand1;
00267 rtx operand2;
00268 {
00269 return gen_rtx_SET (VOIDmode,
00270 operand0,
00271 gen_rtx_MULT (DFmode,
00272 operand1,
00273 operand2));
00274 }
00275
00276
00277 rtx
00278 gen_mulsf3_internal (operand0, operand1, operand2)
00279 rtx operand0;
00280 rtx operand1;
00281 rtx operand2;
00282 {
00283 return gen_rtx_SET (VOIDmode,
00284 operand0,
00285 gen_rtx_MULT (SFmode,
00286 operand1,
00287 operand2));
00288 }
00289
00290
00291 rtx
00292 gen_mulsf3_r4300 (operand0, operand1, operand2)
00293 rtx operand0;
00294 rtx operand1;
00295 rtx operand2;
00296 {
00297 return gen_rtx_SET (VOIDmode,
00298 operand0,
00299 gen_rtx_MULT (SFmode,
00300 operand1,
00301 operand2));
00302 }
00303
00304
00305 rtx
00306 gen_mulsi3_mult3 (operand0, operand1, operand2)
00307 rtx operand0;
00308 rtx operand1;
00309 rtx operand2;
00310 {
00311 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
00312 gen_rtx_SET (VOIDmode,
00313 operand0,
00314 gen_rtx_MULT (SImode,
00315 operand1,
00316 operand2)),
00317 gen_rtx_CLOBBER (VOIDmode,
00318 gen_rtx_SCRATCH (SImode)),
00319 gen_rtx_CLOBBER (VOIDmode,
00320 gen_rtx_SCRATCH (SImode)),
00321 gen_rtx_CLOBBER (VOIDmode,
00322 gen_rtx_SCRATCH (SImode))));
00323 }
00324
00325
00326 rtx
00327 gen_mulsi3_internal (operand0, operand1, operand2)
00328 rtx operand0;
00329 rtx operand1;
00330 rtx operand2;
00331 {
00332 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00333 gen_rtx_SET (VOIDmode,
00334 operand0,
00335 gen_rtx_MULT (SImode,
00336 operand1,
00337 operand2)),
00338 gen_rtx_CLOBBER (VOIDmode,
00339 gen_rtx_SCRATCH (SImode)),
00340 gen_rtx_CLOBBER (VOIDmode,
00341 gen_rtx_SCRATCH (SImode))));
00342 }
00343
00344
00345 rtx
00346 gen_mulsi3_r4000 (operand0, operand1, operand2)
00347 rtx operand0;
00348 rtx operand1;
00349 rtx operand2;
00350 {
00351 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
00352 gen_rtx_SET (VOIDmode,
00353 operand0,
00354 gen_rtx_MULT (SImode,
00355 operand1,
00356 operand2)),
00357 gen_rtx_CLOBBER (VOIDmode,
00358 gen_rtx_SCRATCH (SImode)),
00359 gen_rtx_CLOBBER (VOIDmode,
00360 gen_rtx_SCRATCH (SImode)),
00361 gen_rtx_CLOBBER (VOIDmode,
00362 gen_rtx_SCRATCH (SImode))));
00363 }
00364
00365
00366 rtx
00367 gen_muldi3_internal (operand0, operand1, operand2)
00368 rtx operand0;
00369 rtx operand1;
00370 rtx operand2;
00371 {
00372 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00373 gen_rtx_SET (VOIDmode,
00374 operand0,
00375 gen_rtx_MULT (DImode,
00376 operand1,
00377 operand2)),
00378 gen_rtx_CLOBBER (VOIDmode,
00379 gen_rtx_SCRATCH (DImode)),
00380 gen_rtx_CLOBBER (VOIDmode,
00381 gen_rtx_SCRATCH (DImode))));
00382 }
00383
00384
00385 rtx
00386 gen_muldi3_internal2 (operand0, operand1, operand2)
00387 rtx operand0;
00388 rtx operand1;
00389 rtx operand2;
00390 {
00391 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
00392 gen_rtx_SET (VOIDmode,
00393 operand0,
00394 gen_rtx_MULT (DImode,
00395 operand1,
00396 operand2)),
00397 gen_rtx_CLOBBER (VOIDmode,
00398 gen_rtx_SCRATCH (DImode)),
00399 gen_rtx_CLOBBER (VOIDmode,
00400 gen_rtx_SCRATCH (DImode)),
00401 gen_rtx_CLOBBER (VOIDmode,
00402 gen_rtx_SCRATCH (DImode))));
00403 }
00404
00405
00406 rtx
00407 gen_mulsidi3_internal (operand0, operand1, operand2, operand3, operand4)
00408 rtx operand0;
00409 rtx operand1;
00410 rtx operand2;
00411 rtx operand3;
00412 rtx operand4;
00413 {
00414 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00415 gen_rtx_SET (VOIDmode,
00416 operand0,
00417 gen_rtx_MULT (DImode,
00418 gen_rtx (GET_CODE (operand3), DImode,
00419 operand1),
00420 gen_rtx (GET_CODE (operand4), DImode,
00421 operand2))),
00422 gen_rtx_CLOBBER (VOIDmode,
00423 gen_rtx_SCRATCH (SImode))));
00424 }
00425
00426
00427 rtx
00428 gen_mulsidi3_64bit (operand0, operand1, operand2, operand3, operand4)
00429 rtx operand0;
00430 rtx operand1;
00431 rtx operand2;
00432 rtx operand3;
00433 rtx operand4;
00434 {
00435 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00436 gen_rtx_SET (VOIDmode,
00437 operand0,
00438 gen_rtx_MULT (DImode,
00439 gen_rtx (GET_CODE (operand3), DImode,
00440 operand1),
00441 gen_rtx (GET_CODE (operand4), DImode,
00442 operand2))),
00443 gen_rtx_CLOBBER (VOIDmode,
00444 gen_rtx_SCRATCH (DImode)),
00445 gen_rtx_CLOBBER (VOIDmode,
00446 gen_rtx_SCRATCH (DImode))));
00447 }
00448
00449
00450 rtx
00451 gen_xmulsi3_highpart_internal (operand0, operand1, operand2, operand3, operand4, operand5)
00452 rtx operand0;
00453 rtx operand1;
00454 rtx operand2;
00455 rtx operand3;
00456 rtx operand4;
00457 rtx operand5;
00458 {
00459 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00460 gen_rtx_SET (VOIDmode,
00461 operand0,
00462 gen_rtx_TRUNCATE (SImode,
00463 gen_rtx (GET_CODE (operand5), DImode,
00464 gen_rtx_MULT (DImode,
00465 gen_rtx (GET_CODE (operand3), DImode,
00466 operand1),
00467 gen_rtx (GET_CODE (operand4), DImode,
00468 operand2)),
00469 GEN_INT (32LL)))),
00470 gen_rtx_CLOBBER (VOIDmode,
00471 gen_rtx_SCRATCH (SImode)),
00472 gen_rtx_CLOBBER (VOIDmode,
00473 gen_rtx_SCRATCH (SImode))));
00474 }
00475
00476
00477 rtx
00478 gen_xmulsi3_highpart_mulhi (operand0, operand1, operand2, operand3, operand4, operand5)
00479 rtx operand0;
00480 rtx operand1;
00481 rtx operand2;
00482 rtx operand3;
00483 rtx operand4;
00484 rtx operand5;
00485 {
00486 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (4,
00487 gen_rtx_SET (VOIDmode,
00488 operand0,
00489 gen_rtx_TRUNCATE (SImode,
00490 gen_rtx (GET_CODE (operand5), DImode,
00491 gen_rtx_MULT (DImode,
00492 gen_rtx (GET_CODE (operand3), DImode,
00493 operand1),
00494 gen_rtx (GET_CODE (operand4), DImode,
00495 operand2)),
00496 GEN_INT (32LL)))),
00497 gen_rtx_CLOBBER (VOIDmode,
00498 gen_rtx_SCRATCH (SImode)),
00499 gen_rtx_CLOBBER (VOIDmode,
00500 gen_rtx_SCRATCH (SImode)),
00501 gen_rtx_CLOBBER (VOIDmode,
00502 gen_rtx_SCRATCH (SImode))));
00503 }
00504
00505
00506 rtx
00507 gen_smuldi3_highpart (operand0, operand1, operand2)
00508 rtx operand0;
00509 rtx operand1;
00510 rtx operand2;
00511 {
00512 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00513 gen_rtx_SET (VOIDmode,
00514 operand0,
00515 gen_rtx_TRUNCATE (DImode,
00516 gen_rtx_LSHIFTRT (TImode,
00517 gen_rtx_MULT (TImode,
00518 gen_rtx_SIGN_EXTEND (TImode,
00519 operand1),
00520 gen_rtx_SIGN_EXTEND (TImode,
00521 operand2)),
00522 GEN_INT (64LL)))),
00523 gen_rtx_CLOBBER (VOIDmode,
00524 gen_rtx_SCRATCH (DImode)),
00525 gen_rtx_CLOBBER (VOIDmode,
00526 gen_rtx_SCRATCH (DImode))));
00527 }
00528
00529
00530 rtx
00531 gen_umuldi3_highpart (operand0, operand1, operand2)
00532 rtx operand0;
00533 rtx operand1;
00534 rtx operand2;
00535 {
00536 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00537 gen_rtx_SET (VOIDmode,
00538 operand0,
00539 gen_rtx_TRUNCATE (DImode,
00540 gen_rtx_LSHIFTRT (TImode,
00541 gen_rtx_MULT (TImode,
00542 gen_rtx_ZERO_EXTEND (TImode,
00543 operand1),
00544 gen_rtx_ZERO_EXTEND (TImode,
00545 operand2)),
00546 GEN_INT (64LL)))),
00547 gen_rtx_CLOBBER (VOIDmode,
00548 gen_rtx_SCRATCH (DImode)),
00549 gen_rtx_CLOBBER (VOIDmode,
00550 gen_rtx_SCRATCH (DImode))));
00551 }
00552
00553
00554 rtx
00555 gen_madsi (operand0, operand1, operand2)
00556 rtx operand0;
00557 rtx operand1;
00558 rtx operand2;
00559 {
00560 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00561 gen_rtx_SET (VOIDmode,
00562 operand0,
00563 gen_rtx_PLUS (SImode,
00564 gen_rtx_MULT (SImode,
00565 operand1,
00566 operand2),
00567 operand0)),
00568 gen_rtx_CLOBBER (VOIDmode,
00569 gen_rtx_SCRATCH (SImode)),
00570 gen_rtx_CLOBBER (VOIDmode,
00571 gen_rtx_SCRATCH (SImode))));
00572 }
00573
00574
00575 rtx
00576 gen_divdf3 (operand0, operand1, operand2)
00577 rtx operand0;
00578 rtx operand1;
00579 rtx operand2;
00580 {
00581 return gen_rtx_SET (VOIDmode,
00582 operand0,
00583 gen_rtx_DIV (DFmode,
00584 operand1,
00585 operand2));
00586 }
00587
00588
00589 rtx
00590 gen_divsf3 (operand0, operand1, operand2)
00591 rtx operand0;
00592 rtx operand1;
00593 rtx operand2;
00594 {
00595 return gen_rtx_SET (VOIDmode,
00596 operand0,
00597 gen_rtx_DIV (SFmode,
00598 operand1,
00599 operand2));
00600 }
00601
00602
00603 rtx
00604 gen_divmodsi4_internal (operand0, operand1, operand2, operand3)
00605 rtx operand0;
00606 rtx operand1;
00607 rtx operand2;
00608 rtx operand3;
00609 {
00610 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00611 gen_rtx_SET (VOIDmode,
00612 operand0,
00613 gen_rtx_DIV (SImode,
00614 operand1,
00615 operand2)),
00616 gen_rtx_SET (VOIDmode,
00617 operand3,
00618 gen_rtx_MOD (SImode,
00619 operand1,
00620 operand2)),
00621 gen_rtx_CLOBBER (VOIDmode,
00622 gen_rtx_SCRATCH (SImode))));
00623 }
00624
00625
00626 rtx
00627 gen_divmoddi4_internal (operand0, operand1, operand2, operand3)
00628 rtx operand0;
00629 rtx operand1;
00630 rtx operand2;
00631 rtx operand3;
00632 {
00633 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00634 gen_rtx_SET (VOIDmode,
00635 operand0,
00636 gen_rtx_DIV (DImode,
00637 operand1,
00638 operand2)),
00639 gen_rtx_SET (VOIDmode,
00640 operand3,
00641 gen_rtx_MOD (DImode,
00642 operand1,
00643 operand2)),
00644 gen_rtx_CLOBBER (VOIDmode,
00645 gen_rtx_SCRATCH (DImode))));
00646 }
00647
00648
00649 rtx
00650 gen_udivmodsi4_internal (operand0, operand1, operand2, operand3)
00651 rtx operand0;
00652 rtx operand1;
00653 rtx operand2;
00654 rtx operand3;
00655 {
00656 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00657 gen_rtx_SET (VOIDmode,
00658 operand0,
00659 gen_rtx_UDIV (SImode,
00660 operand1,
00661 operand2)),
00662 gen_rtx_SET (VOIDmode,
00663 operand3,
00664 gen_rtx_UMOD (SImode,
00665 operand1,
00666 operand2)),
00667 gen_rtx_CLOBBER (VOIDmode,
00668 gen_rtx_SCRATCH (SImode))));
00669 }
00670
00671
00672 rtx
00673 gen_udivmoddi4_internal (operand0, operand1, operand2, operand3)
00674 rtx operand0;
00675 rtx operand1;
00676 rtx operand2;
00677 rtx operand3;
00678 {
00679 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00680 gen_rtx_SET (VOIDmode,
00681 operand0,
00682 gen_rtx_UDIV (DImode,
00683 operand1,
00684 operand2)),
00685 gen_rtx_SET (VOIDmode,
00686 operand3,
00687 gen_rtx_UMOD (DImode,
00688 operand1,
00689 operand2)),
00690 gen_rtx_CLOBBER (VOIDmode,
00691 gen_rtx_SCRATCH (DImode))));
00692 }
00693
00694
00695 rtx
00696 gen_div_trap_normal (operand0, operand1, operand2)
00697 rtx operand0;
00698 rtx operand1;
00699 rtx operand2;
00700 {
00701 return gen_rtx_TRAP_IF (VOIDmode,
00702 gen_rtx_EQ (VOIDmode,
00703 operand0,
00704 operand1),
00705 operand2);
00706 }
00707
00708
00709 rtx
00710 gen_div_trap_mips16 (operand0, operand1, operand2)
00711 rtx operand0;
00712 rtx operand1;
00713 rtx operand2;
00714 {
00715 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
00716 gen_rtx_TRAP_IF (VOIDmode,
00717 gen_rtx_EQ (VOIDmode,
00718 operand0,
00719 operand1),
00720 operand2),
00721 gen_rtx_CLOBBER (VOIDmode,
00722 gen_rtx_REG (SImode,
00723 24))));
00724 }
00725
00726
00727 rtx
00728 gen_divsi3_internal (operand0, operand1, operand2)
00729 rtx operand0;
00730 rtx operand1;
00731 rtx operand2;
00732 {
00733 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00734 gen_rtx_SET (VOIDmode,
00735 operand0,
00736 gen_rtx_DIV (SImode,
00737 operand1,
00738 operand2)),
00739 gen_rtx_CLOBBER (VOIDmode,
00740 gen_rtx_SCRATCH (SImode)),
00741 gen_rtx_CLOBBER (VOIDmode,
00742 gen_rtx_SCRATCH (SImode))));
00743 }
00744
00745
00746 rtx
00747 gen_divdi3_internal (operand0, operand1, operand2)
00748 rtx operand0;
00749 rtx operand1;
00750 rtx operand2;
00751 {
00752 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00753 gen_rtx_SET (VOIDmode,
00754 operand0,
00755 gen_rtx_DIV (DImode,
00756 operand1,
00757 operand2)),
00758 gen_rtx_CLOBBER (VOIDmode,
00759 gen_rtx_SCRATCH (SImode)),
00760 gen_rtx_CLOBBER (VOIDmode,
00761 gen_rtx_SCRATCH (SImode))));
00762 }
00763
00764
00765 rtx
00766 gen_modsi3_internal (operand0, operand1, operand2)
00767 rtx operand0;
00768 rtx operand1;
00769 rtx operand2;
00770 {
00771 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00772 gen_rtx_SET (VOIDmode,
00773 operand0,
00774 gen_rtx_MOD (SImode,
00775 operand1,
00776 operand2)),
00777 gen_rtx_CLOBBER (VOIDmode,
00778 gen_rtx_SCRATCH (SImode)),
00779 gen_rtx_CLOBBER (VOIDmode,
00780 gen_rtx_SCRATCH (SImode))));
00781 }
00782
00783
00784 rtx
00785 gen_moddi3_internal (operand0, operand1, operand2)
00786 rtx operand0;
00787 rtx operand1;
00788 rtx operand2;
00789 {
00790 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00791 gen_rtx_SET (VOIDmode,
00792 operand0,
00793 gen_rtx_MOD (DImode,
00794 operand1,
00795 operand2)),
00796 gen_rtx_CLOBBER (VOIDmode,
00797 gen_rtx_SCRATCH (SImode)),
00798 gen_rtx_CLOBBER (VOIDmode,
00799 gen_rtx_SCRATCH (SImode))));
00800 }
00801
00802
00803 rtx
00804 gen_udivsi3_internal (operand0, operand1, operand2)
00805 rtx operand0;
00806 rtx operand1;
00807 rtx operand2;
00808 {
00809 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00810 gen_rtx_SET (VOIDmode,
00811 operand0,
00812 gen_rtx_UDIV (SImode,
00813 operand1,
00814 operand2)),
00815 gen_rtx_CLOBBER (VOIDmode,
00816 gen_rtx_SCRATCH (SImode)),
00817 gen_rtx_CLOBBER (VOIDmode,
00818 gen_rtx_SCRATCH (SImode))));
00819 }
00820
00821
00822 rtx
00823 gen_udivdi3_internal (operand0, operand1, operand2)
00824 rtx operand0;
00825 rtx operand1;
00826 rtx operand2;
00827 {
00828 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00829 gen_rtx_SET (VOIDmode,
00830 operand0,
00831 gen_rtx_UDIV (DImode,
00832 operand1,
00833 operand2)),
00834 gen_rtx_CLOBBER (VOIDmode,
00835 gen_rtx_SCRATCH (SImode)),
00836 gen_rtx_CLOBBER (VOIDmode,
00837 gen_rtx_SCRATCH (SImode))));
00838 }
00839
00840
00841 rtx
00842 gen_umodsi3_internal (operand0, operand1, operand2)
00843 rtx operand0;
00844 rtx operand1;
00845 rtx operand2;
00846 {
00847 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00848 gen_rtx_SET (VOIDmode,
00849 operand0,
00850 gen_rtx_UMOD (SImode,
00851 operand1,
00852 operand2)),
00853 gen_rtx_CLOBBER (VOIDmode,
00854 gen_rtx_SCRATCH (SImode)),
00855 gen_rtx_CLOBBER (VOIDmode,
00856 gen_rtx_SCRATCH (SImode))));
00857 }
00858
00859
00860 rtx
00861 gen_umoddi3_internal (operand0, operand1, operand2)
00862 rtx operand0;
00863 rtx operand1;
00864 rtx operand2;
00865 {
00866 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00867 gen_rtx_SET (VOIDmode,
00868 operand0,
00869 gen_rtx_UMOD (DImode,
00870 operand1,
00871 operand2)),
00872 gen_rtx_CLOBBER (VOIDmode,
00873 gen_rtx_SCRATCH (SImode)),
00874 gen_rtx_CLOBBER (VOIDmode,
00875 gen_rtx_SCRATCH (SImode))));
00876 }
00877
00878
00879 rtx
00880 gen_sqrtdf2 (operand0, operand1)
00881 rtx operand0;
00882 rtx operand1;
00883 {
00884 return gen_rtx_SET (VOIDmode,
00885 operand0,
00886 gen_rtx_SQRT (DFmode,
00887 operand1));
00888 }
00889
00890
00891 rtx
00892 gen_sqrtsf2 (operand0, operand1)
00893 rtx operand0;
00894 rtx operand1;
00895 {
00896 return gen_rtx_SET (VOIDmode,
00897 operand0,
00898 gen_rtx_SQRT (SFmode,
00899 operand1));
00900 }
00901
00902
00903 rtx
00904 gen_abssi2 (operand0, operand1)
00905 rtx operand0;
00906 rtx operand1;
00907 {
00908 return gen_rtx_SET (VOIDmode,
00909 operand0,
00910 gen_rtx_ABS (SImode,
00911 operand1));
00912 }
00913
00914
00915 rtx
00916 gen_absdi2 (operand0, operand1)
00917 rtx operand0;
00918 rtx operand1;
00919 {
00920 return gen_rtx_SET (VOIDmode,
00921 operand0,
00922 gen_rtx_ABS (DImode,
00923 operand1));
00924 }
00925
00926
00927 rtx
00928 gen_absdf2 (operand0, operand1)
00929 rtx operand0;
00930 rtx operand1;
00931 {
00932 return gen_rtx_SET (VOIDmode,
00933 operand0,
00934 gen_rtx_ABS (DFmode,
00935 operand1));
00936 }
00937
00938
00939 rtx
00940 gen_abssf2 (operand0, operand1)
00941 rtx operand0;
00942 rtx operand1;
00943 {
00944 return gen_rtx_SET (VOIDmode,
00945 operand0,
00946 gen_rtx_ABS (SFmode,
00947 operand1));
00948 }
00949
00950
00951 rtx
00952 gen_ffssi2 (operand0, operand1)
00953 rtx operand0;
00954 rtx operand1;
00955 {
00956 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00957 gen_rtx_SET (VOIDmode,
00958 operand0,
00959 gen_rtx_FFS (SImode,
00960 operand1)),
00961 gen_rtx_CLOBBER (VOIDmode,
00962 gen_rtx_SCRATCH (SImode)),
00963 gen_rtx_CLOBBER (VOIDmode,
00964 gen_rtx_SCRATCH (SImode))));
00965 }
00966
00967
00968 rtx
00969 gen_ffsdi2 (operand0, operand1)
00970 rtx operand0;
00971 rtx operand1;
00972 {
00973 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
00974 gen_rtx_SET (VOIDmode,
00975 operand0,
00976 gen_rtx_FFS (DImode,
00977 operand1)),
00978 gen_rtx_CLOBBER (VOIDmode,
00979 gen_rtx_SCRATCH (DImode)),
00980 gen_rtx_CLOBBER (VOIDmode,
00981 gen_rtx_SCRATCH (DImode))));
00982 }
00983
00984
00985 rtx
00986 gen_negsi2 (operand0, operand1)
00987 rtx operand0;
00988 rtx operand1;
00989 {
00990 return gen_rtx_SET (VOIDmode,
00991 operand0,
00992 gen_rtx_NEG (SImode,
00993 operand1));
00994 }
00995
00996
00997 rtx
00998 gen_negdi2_internal (operand0, operand1, operand2)
00999 rtx operand0;
01000 rtx operand1;
01001 rtx operand2;
01002 {
01003 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01004 gen_rtx_SET (VOIDmode,
01005 operand0,
01006 gen_rtx_NEG (DImode,
01007 operand1)),
01008 gen_rtx_CLOBBER (VOIDmode,
01009 operand2)));
01010 }
01011
01012
01013 rtx
01014 gen_negdi2_internal_2 (operand0, operand1)
01015 rtx operand0;
01016 rtx operand1;
01017 {
01018 return gen_rtx_SET (VOIDmode,
01019 operand0,
01020 gen_rtx_NEG (DImode,
01021 operand1));
01022 }
01023
01024
01025 rtx
01026 gen_negdf2 (operand0, operand1)
01027 rtx operand0;
01028 rtx operand1;
01029 {
01030 return gen_rtx_SET (VOIDmode,
01031 operand0,
01032 gen_rtx_NEG (DFmode,
01033 operand1));
01034 }
01035
01036
01037 rtx
01038 gen_negsf2 (operand0, operand1)
01039 rtx operand0;
01040 rtx operand1;
01041 {
01042 return gen_rtx_SET (VOIDmode,
01043 operand0,
01044 gen_rtx_NEG (SFmode,
01045 operand1));
01046 }
01047
01048
01049 rtx
01050 gen_one_cmplsi2 (operand0, operand1)
01051 rtx operand0;
01052 rtx operand1;
01053 {
01054 return gen_rtx_SET (VOIDmode,
01055 operand0,
01056 gen_rtx_NOT (SImode,
01057 operand1));
01058 }
01059
01060
01061 rtx
01062 gen_one_cmpldi2 (operand0, operand1)
01063 rtx operand0;
01064 rtx operand1;
01065 {
01066 return gen_rtx_SET (VOIDmode,
01067 operand0,
01068 gen_rtx_NOT (DImode,
01069 operand1));
01070 }
01071
01072
01073 rtx
01074 gen_anddi3_internal1 (operand0, operand1, operand2)
01075 rtx operand0;
01076 rtx operand1;
01077 rtx operand2;
01078 {
01079 return gen_rtx_SET (VOIDmode,
01080 operand0,
01081 gen_rtx_AND (DImode,
01082 operand1,
01083 operand2));
01084 }
01085
01086
01087 rtx
01088 gen_xordi3_immed (operand0, operand1, operand2)
01089 rtx operand0;
01090 rtx operand1;
01091 rtx operand2;
01092 {
01093 return gen_rtx_SET (VOIDmode,
01094 operand0,
01095 gen_rtx_XOR (DImode,
01096 operand1,
01097 operand2));
01098 }
01099
01100
01101 rtx
01102 gen_truncdfsf2 (operand0, operand1)
01103 rtx operand0;
01104 rtx operand1;
01105 {
01106 return gen_rtx_SET (VOIDmode,
01107 operand0,
01108 gen_rtx_FLOAT_TRUNCATE (SFmode,
01109 operand1));
01110 }
01111
01112
01113 rtx
01114 gen_truncdisi2 (operand0, operand1)
01115 rtx operand0;
01116 rtx operand1;
01117 {
01118 return gen_rtx_SET (VOIDmode,
01119 operand0,
01120 gen_rtx_TRUNCATE (SImode,
01121 operand1));
01122 }
01123
01124
01125 rtx
01126 gen_truncdihi2 (operand0, operand1)
01127 rtx operand0;
01128 rtx operand1;
01129 {
01130 return gen_rtx_SET (VOIDmode,
01131 operand0,
01132 gen_rtx_TRUNCATE (HImode,
01133 operand1));
01134 }
01135
01136
01137 rtx
01138 gen_truncdiqi2 (operand0, operand1)
01139 rtx operand0;
01140 rtx operand1;
01141 {
01142 return gen_rtx_SET (VOIDmode,
01143 operand0,
01144 gen_rtx_TRUNCATE (QImode,
01145 operand1));
01146 }
01147
01148
01149 rtx
01150 gen_zero_extendsidi2_internal (operand0, operand1)
01151 rtx operand0;
01152 rtx operand1;
01153 {
01154 return gen_rtx_SET (VOIDmode,
01155 operand0,
01156 gen_rtx_ZERO_EXTEND (DImode,
01157 operand1));
01158 }
01159
01160
01161 rtx
01162 gen_extendhidi2_internal (operand0, operand1)
01163 rtx operand0;
01164 rtx operand1;
01165 {
01166 return gen_rtx_SET (VOIDmode,
01167 operand0,
01168 gen_rtx_SIGN_EXTEND (DImode,
01169 operand1));
01170 }
01171
01172
01173 rtx
01174 gen_extendhisi2_internal (operand0, operand1)
01175 rtx operand0;
01176 rtx operand1;
01177 {
01178 return gen_rtx_SET (VOIDmode,
01179 operand0,
01180 gen_rtx_SIGN_EXTEND (SImode,
01181 operand1));
01182 }
01183
01184
01185 rtx
01186 gen_extendqihi2_internal (operand0, operand1)
01187 rtx operand0;
01188 rtx operand1;
01189 {
01190 return gen_rtx_SET (VOIDmode,
01191 operand0,
01192 gen_rtx_SIGN_EXTEND (HImode,
01193 operand1));
01194 }
01195
01196
01197 rtx
01198 gen_extendqisi2_insn (operand0, operand1)
01199 rtx operand0;
01200 rtx operand1;
01201 {
01202 return gen_rtx_SET (VOIDmode,
01203 operand0,
01204 gen_rtx_SIGN_EXTEND (SImode,
01205 operand1));
01206 }
01207
01208
01209 rtx
01210 gen_extendqidi2_insn (operand0, operand1)
01211 rtx operand0;
01212 rtx operand1;
01213 {
01214 return gen_rtx_SET (VOIDmode,
01215 operand0,
01216 gen_rtx_SIGN_EXTEND (DImode,
01217 operand1));
01218 }
01219
01220
01221 rtx
01222 gen_extendsfdf2 (operand0, operand1)
01223 rtx operand0;
01224 rtx operand1;
01225 {
01226 return gen_rtx_SET (VOIDmode,
01227 operand0,
01228 gen_rtx_FLOAT_EXTEND (DFmode,
01229 operand1));
01230 }
01231
01232
01233 rtx
01234 gen_fix_truncdfsi2_insn (operand0, operand1)
01235 rtx operand0;
01236 rtx operand1;
01237 {
01238 return gen_rtx_SET (VOIDmode,
01239 operand0,
01240 gen_rtx_FIX (SImode,
01241 operand1));
01242 }
01243
01244
01245 rtx
01246 gen_fix_truncdfsi2_macro (operand0, operand1)
01247 rtx operand0;
01248 rtx operand1;
01249 {
01250 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01251 gen_rtx_SET (VOIDmode,
01252 operand0,
01253 gen_rtx_FIX (SImode,
01254 operand1)),
01255 gen_rtx_CLOBBER (VOIDmode,
01256 gen_rtx_SCRATCH (DFmode))));
01257 }
01258
01259
01260 rtx
01261 gen_fix_truncsfsi2_insn (operand0, operand1)
01262 rtx operand0;
01263 rtx operand1;
01264 {
01265 return gen_rtx_SET (VOIDmode,
01266 operand0,
01267 gen_rtx_FIX (SImode,
01268 operand1));
01269 }
01270
01271
01272 rtx
01273 gen_fix_truncsfsi2_macro (operand0, operand1)
01274 rtx operand0;
01275 rtx operand1;
01276 {
01277 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01278 gen_rtx_SET (VOIDmode,
01279 operand0,
01280 gen_rtx_FIX (SImode,
01281 operand1)),
01282 gen_rtx_CLOBBER (VOIDmode,
01283 gen_rtx_SCRATCH (SFmode))));
01284 }
01285
01286
01287 rtx
01288 gen_fix_truncdfdi2 (operand0, operand1)
01289 rtx operand0;
01290 rtx operand1;
01291 {
01292 return gen_rtx_SET (VOIDmode,
01293 operand0,
01294 gen_rtx_FIX (DImode,
01295 operand1));
01296 }
01297
01298
01299 rtx
01300 gen_fix_truncsfdi2 (operand0, operand1)
01301 rtx operand0;
01302 rtx operand1;
01303 {
01304 return gen_rtx_SET (VOIDmode,
01305 operand0,
01306 gen_rtx_FIX (DImode,
01307 operand1));
01308 }
01309
01310
01311 rtx
01312 gen_floatsidf2 (operand0, operand1)
01313 rtx operand0;
01314 rtx operand1;
01315 {
01316 return gen_rtx_SET (VOIDmode,
01317 operand0,
01318 gen_rtx_FLOAT (DFmode,
01319 operand1));
01320 }
01321
01322
01323 rtx
01324 gen_floatdidf2 (operand0, operand1)
01325 rtx operand0;
01326 rtx operand1;
01327 {
01328 return gen_rtx_SET (VOIDmode,
01329 operand0,
01330 gen_rtx_FLOAT (DFmode,
01331 operand1));
01332 }
01333
01334
01335 rtx
01336 gen_floatsisf2 (operand0, operand1)
01337 rtx operand0;
01338 rtx operand1;
01339 {
01340 return gen_rtx_SET (VOIDmode,
01341 operand0,
01342 gen_rtx_FLOAT (SFmode,
01343 operand1));
01344 }
01345
01346
01347 rtx
01348 gen_floatdisf2 (operand0, operand1)
01349 rtx operand0;
01350 rtx operand1;
01351 {
01352 return gen_rtx_SET (VOIDmode,
01353 operand0,
01354 gen_rtx_FLOAT (SFmode,
01355 operand1));
01356 }
01357
01358
01359 rtx
01360 gen_movsi_ulw (operand0, operand1)
01361 rtx operand0;
01362 rtx operand1;
01363 {
01364 return gen_rtx_SET (VOIDmode,
01365 operand0,
01366 gen_rtx_UNSPEC (SImode,
01367 gen_rtvec (1,
01368 operand1),
01369 0));
01370 }
01371
01372
01373 rtx
01374 gen_movsi_usw (operand0, operand1)
01375 rtx operand0;
01376 rtx operand1;
01377 {
01378 return gen_rtx_SET (VOIDmode,
01379 operand0,
01380 gen_rtx_UNSPEC (BLKmode,
01381 gen_rtvec (1,
01382 operand1),
01383 1));
01384 }
01385
01386
01387 rtx
01388 gen_movdi_uld (operand0, operand1)
01389 rtx operand0;
01390 rtx operand1;
01391 {
01392 return gen_rtx_SET (VOIDmode,
01393 operand0,
01394 gen_rtx_UNSPEC (DImode,
01395 gen_rtvec (1,
01396 operand1),
01397 2));
01398 }
01399
01400
01401 rtx
01402 gen_movdi_usd (operand0, operand1)
01403 rtx operand0;
01404 rtx operand1;
01405 {
01406 return gen_rtx_SET (VOIDmode,
01407 operand0,
01408 gen_rtx_UNSPEC (BLKmode,
01409 gen_rtvec (1,
01410 operand1),
01411 3));
01412 }
01413
01414
01415 rtx
01416 gen_high (operand0, operand1)
01417 rtx operand0;
01418 rtx operand1;
01419 {
01420 return gen_rtx_SET (VOIDmode,
01421 operand0,
01422 gen_rtx_HIGH (SImode,
01423 operand1));
01424 }
01425
01426
01427 rtx
01428 gen_low (operand0, operand1, operand2)
01429 rtx operand0;
01430 rtx operand1;
01431 rtx operand2;
01432 {
01433 return gen_rtx_SET (VOIDmode,
01434 operand0,
01435 gen_rtx_LO_SUM (SImode,
01436 operand1,
01437 operand2));
01438 }
01439
01440
01441 rtx
01442 gen_movdi_internal (operand0, operand1)
01443 rtx operand0;
01444 rtx operand1;
01445 {
01446 return gen_rtx_SET (VOIDmode,
01447 operand0,
01448 operand1);
01449 }
01450
01451
01452 rtx
01453 gen_movdi_internal2 (operand0, operand1)
01454 rtx operand0;
01455 rtx operand1;
01456 {
01457 return gen_rtx_SET (VOIDmode,
01458 operand0,
01459 operand1);
01460 }
01461
01462
01463 rtx
01464 gen_movsi_internal (operand0, operand1)
01465 rtx operand0;
01466 rtx operand1;
01467 {
01468 return gen_rtx_SET (VOIDmode,
01469 operand0,
01470 operand1);
01471 }
01472
01473
01474 rtx
01475 gen_hilo_delay (operand0)
01476 rtx operand0;
01477 {
01478 return gen_rtx_UNSPEC (VOIDmode,
01479 gen_rtvec (1,
01480 operand0),
01481 5);
01482 }
01483
01484
01485 rtx
01486 gen_movcc (operand0, operand1)
01487 rtx operand0;
01488 rtx operand1;
01489 {
01490 return gen_rtx_SET (VOIDmode,
01491 operand0,
01492 operand1);
01493 }
01494
01495
01496 rtx
01497 gen_movhi_internal (operand0, operand1)
01498 rtx operand0;
01499 rtx operand1;
01500 {
01501 return gen_rtx_SET (VOIDmode,
01502 operand0,
01503 operand1);
01504 }
01505
01506
01507 rtx
01508 gen_movqi_internal (operand0, operand1)
01509 rtx operand0;
01510 rtx operand1;
01511 {
01512 return gen_rtx_SET (VOIDmode,
01513 operand0,
01514 operand1);
01515 }
01516
01517
01518 rtx
01519 gen_movsf_internal1 (operand0, operand1)
01520 rtx operand0;
01521 rtx operand1;
01522 {
01523 return gen_rtx_SET (VOIDmode,
01524 operand0,
01525 operand1);
01526 }
01527
01528
01529 rtx
01530 gen_movsf_internal2 (operand0, operand1)
01531 rtx operand0;
01532 rtx operand1;
01533 {
01534 return gen_rtx_SET (VOIDmode,
01535 operand0,
01536 operand1);
01537 }
01538
01539
01540 rtx
01541 gen_movdf_internal1 (operand0, operand1)
01542 rtx operand0;
01543 rtx operand1;
01544 {
01545 return gen_rtx_SET (VOIDmode,
01546 operand0,
01547 operand1);
01548 }
01549
01550
01551 rtx
01552 gen_movdf_internal1a (operand0, operand1)
01553 rtx operand0;
01554 rtx operand1;
01555 {
01556 return gen_rtx_SET (VOIDmode,
01557 operand0,
01558 operand1);
01559 }
01560
01561
01562 rtx
01563 gen_movdf_internal2 (operand0, operand1)
01564 rtx operand0;
01565 rtx operand1;
01566 {
01567 return gen_rtx_SET (VOIDmode,
01568 operand0,
01569 operand1);
01570 }
01571
01572
01573 rtx
01574 gen_loadgp (operand0, operand1)
01575 rtx operand0;
01576 rtx operand1;
01577 {
01578 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01579 gen_rtx_SET (VOIDmode,
01580 gen_rtx_REG (DImode,
01581 28),
01582 gen_rtx_UNSPEC_VOLATILE (DImode,
01583 gen_rtvec (2,
01584 operand0,
01585 operand1),
01586 7)),
01587 gen_rtx_CLOBBER (VOIDmode,
01588 gen_rtx_REG (DImode,
01589 1))));
01590 }
01591
01592
01593 rtx
01594 gen_movstrsi_internal (operand0, operand1, operand2, operand3)
01595 rtx operand0;
01596 rtx operand1;
01597 rtx operand2;
01598 rtx operand3;
01599 {
01600 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (8,
01601 gen_rtx_SET (VOIDmode,
01602 operand0,
01603 operand1),
01604 gen_rtx_CLOBBER (VOIDmode,
01605 gen_rtx_SCRATCH (SImode)),
01606 gen_rtx_CLOBBER (VOIDmode,
01607 gen_rtx_SCRATCH (SImode)),
01608 gen_rtx_CLOBBER (VOIDmode,
01609 gen_rtx_SCRATCH (SImode)),
01610 gen_rtx_CLOBBER (VOIDmode,
01611 gen_rtx_SCRATCH (SImode)),
01612 gen_rtx_USE (VOIDmode,
01613 operand2),
01614 gen_rtx_USE (VOIDmode,
01615 operand3),
01616 gen_rtx_USE (VOIDmode,
01617 const0_rtx)));
01618 }
01619
01620
01621 rtx
01622 gen_movstrsi_internal2 (operand0, operand1, operand2, operand3)
01623 rtx operand0;
01624 rtx operand1;
01625 rtx operand2;
01626 rtx operand3;
01627 {
01628 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (8,
01629 gen_rtx_SET (VOIDmode,
01630 operand0,
01631 operand1),
01632 gen_rtx_CLOBBER (VOIDmode,
01633 gen_rtx_SCRATCH (SImode)),
01634 gen_rtx_CLOBBER (VOIDmode,
01635 gen_rtx_SCRATCH (SImode)),
01636 gen_rtx_CLOBBER (VOIDmode,
01637 gen_rtx_SCRATCH (SImode)),
01638 gen_rtx_CLOBBER (VOIDmode,
01639 gen_rtx_SCRATCH (SImode)),
01640 gen_rtx_USE (VOIDmode,
01641 operand2),
01642 gen_rtx_USE (VOIDmode,
01643 operand3),
01644 gen_rtx_USE (VOIDmode,
01645 const1_rtx)));
01646 }
01647
01648
01649 rtx
01650 gen_movstrsi_internal3 (operand0, operand1, operand2, operand3)
01651 rtx operand0;
01652 rtx operand1;
01653 rtx operand2;
01654 rtx operand3;
01655 {
01656 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (8,
01657 gen_rtx_SET (VOIDmode,
01658 operand0,
01659 operand1),
01660 gen_rtx_CLOBBER (VOIDmode,
01661 gen_rtx_SCRATCH (SImode)),
01662 gen_rtx_CLOBBER (VOIDmode,
01663 gen_rtx_SCRATCH (SImode)),
01664 gen_rtx_CLOBBER (VOIDmode,
01665 gen_rtx_SCRATCH (SImode)),
01666 gen_rtx_CLOBBER (VOIDmode,
01667 gen_rtx_SCRATCH (SImode)),
01668 gen_rtx_USE (VOIDmode,
01669 operand2),
01670 gen_rtx_USE (VOIDmode,
01671 operand3),
01672 gen_rtx_USE (VOIDmode,
01673 GEN_INT (2LL))));
01674 }
01675
01676
01677 rtx
01678 gen_ashlsi3_internal1 (operand0, operand1, operand2)
01679 rtx operand0;
01680 rtx operand1;
01681 rtx operand2;
01682 {
01683 return gen_rtx_SET (VOIDmode,
01684 operand0,
01685 gen_rtx_ASHIFT (SImode,
01686 operand1,
01687 operand2));
01688 }
01689
01690
01691 rtx
01692 gen_ashlsi3_internal2 (operand0, operand1, operand2)
01693 rtx operand0;
01694 rtx operand1;
01695 rtx operand2;
01696 {
01697 return gen_rtx_SET (VOIDmode,
01698 operand0,
01699 gen_rtx_ASHIFT (SImode,
01700 operand1,
01701 operand2));
01702 }
01703
01704
01705 rtx
01706 gen_ashldi3_internal (operand0, operand1, operand2, operand3)
01707 rtx operand0;
01708 rtx operand1;
01709 rtx operand2;
01710 rtx operand3;
01711 {
01712 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01713 gen_rtx_SET (VOIDmode,
01714 operand0,
01715 gen_rtx_ASHIFT (DImode,
01716 operand1,
01717 operand2)),
01718 gen_rtx_CLOBBER (VOIDmode,
01719 operand3)));
01720 }
01721
01722
01723 rtx
01724 gen_ashldi3_internal2 (operand0, operand1, operand2, operand3)
01725 rtx operand0;
01726 rtx operand1;
01727 rtx operand2;
01728 rtx operand3;
01729 {
01730 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01731 gen_rtx_SET (VOIDmode,
01732 operand0,
01733 gen_rtx_ASHIFT (DImode,
01734 operand1,
01735 operand2)),
01736 gen_rtx_CLOBBER (VOIDmode,
01737 operand3)));
01738 }
01739
01740
01741 rtx
01742 gen_ashldi3_internal3 (operand0, operand1, operand2, operand3)
01743 rtx operand0;
01744 rtx operand1;
01745 rtx operand2;
01746 rtx operand3;
01747 {
01748 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01749 gen_rtx_SET (VOIDmode,
01750 operand0,
01751 gen_rtx_ASHIFT (DImode,
01752 operand1,
01753 operand2)),
01754 gen_rtx_CLOBBER (VOIDmode,
01755 operand3)));
01756 }
01757
01758
01759 rtx
01760 gen_ashldi3_internal4 (operand0, operand1, operand2)
01761 rtx operand0;
01762 rtx operand1;
01763 rtx operand2;
01764 {
01765 return gen_rtx_SET (VOIDmode,
01766 operand0,
01767 gen_rtx_ASHIFT (DImode,
01768 operand1,
01769 operand2));
01770 }
01771
01772
01773 rtx
01774 gen_ashrsi3_internal1 (operand0, operand1, operand2)
01775 rtx operand0;
01776 rtx operand1;
01777 rtx operand2;
01778 {
01779 return gen_rtx_SET (VOIDmode,
01780 operand0,
01781 gen_rtx_ASHIFTRT (SImode,
01782 operand1,
01783 operand2));
01784 }
01785
01786
01787 rtx
01788 gen_ashrsi3_internal2 (operand0, operand1, operand2)
01789 rtx operand0;
01790 rtx operand1;
01791 rtx operand2;
01792 {
01793 return gen_rtx_SET (VOIDmode,
01794 operand0,
01795 gen_rtx_ASHIFTRT (SImode,
01796 operand1,
01797 operand2));
01798 }
01799
01800
01801 rtx
01802 gen_ashrdi3_internal (operand0, operand1, operand2, operand3)
01803 rtx operand0;
01804 rtx operand1;
01805 rtx operand2;
01806 rtx operand3;
01807 {
01808 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01809 gen_rtx_SET (VOIDmode,
01810 operand0,
01811 gen_rtx_ASHIFTRT (DImode,
01812 operand1,
01813 operand2)),
01814 gen_rtx_CLOBBER (VOIDmode,
01815 operand3)));
01816 }
01817
01818
01819 rtx
01820 gen_ashrdi3_internal2 (operand0, operand1, operand2, operand3)
01821 rtx operand0;
01822 rtx operand1;
01823 rtx operand2;
01824 rtx operand3;
01825 {
01826 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01827 gen_rtx_SET (VOIDmode,
01828 operand0,
01829 gen_rtx_ASHIFTRT (DImode,
01830 operand1,
01831 operand2)),
01832 gen_rtx_CLOBBER (VOIDmode,
01833 operand3)));
01834 }
01835
01836
01837 rtx
01838 gen_ashrdi3_internal3 (operand0, operand1, operand2, operand3)
01839 rtx operand0;
01840 rtx operand1;
01841 rtx operand2;
01842 rtx operand3;
01843 {
01844 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01845 gen_rtx_SET (VOIDmode,
01846 operand0,
01847 gen_rtx_ASHIFTRT (DImode,
01848 operand1,
01849 operand2)),
01850 gen_rtx_CLOBBER (VOIDmode,
01851 operand3)));
01852 }
01853
01854
01855 rtx
01856 gen_ashrdi3_internal4 (operand0, operand1, operand2)
01857 rtx operand0;
01858 rtx operand1;
01859 rtx operand2;
01860 {
01861 return gen_rtx_SET (VOIDmode,
01862 operand0,
01863 gen_rtx_ASHIFTRT (DImode,
01864 operand1,
01865 operand2));
01866 }
01867
01868
01869 rtx
01870 gen_lshrsi3_internal1 (operand0, operand1, operand2)
01871 rtx operand0;
01872 rtx operand1;
01873 rtx operand2;
01874 {
01875 return gen_rtx_SET (VOIDmode,
01876 operand0,
01877 gen_rtx_LSHIFTRT (SImode,
01878 operand1,
01879 operand2));
01880 }
01881
01882
01883 rtx
01884 gen_lshrsi3_internal2 (operand0, operand1, operand2)
01885 rtx operand0;
01886 rtx operand1;
01887 rtx operand2;
01888 {
01889 return gen_rtx_SET (VOIDmode,
01890 operand0,
01891 gen_rtx_LSHIFTRT (SImode,
01892 operand1,
01893 operand2));
01894 }
01895
01896
01897 rtx
01898 gen_lshrdi3_internal (operand0, operand1, operand2, operand3)
01899 rtx operand0;
01900 rtx operand1;
01901 rtx operand2;
01902 rtx operand3;
01903 {
01904 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01905 gen_rtx_SET (VOIDmode,
01906 operand0,
01907 gen_rtx_LSHIFTRT (DImode,
01908 operand1,
01909 operand2)),
01910 gen_rtx_CLOBBER (VOIDmode,
01911 operand3)));
01912 }
01913
01914
01915 rtx
01916 gen_lshrdi3_internal2 (operand0, operand1, operand2, operand3)
01917 rtx operand0;
01918 rtx operand1;
01919 rtx operand2;
01920 rtx operand3;
01921 {
01922 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01923 gen_rtx_SET (VOIDmode,
01924 operand0,
01925 gen_rtx_LSHIFTRT (DImode,
01926 operand1,
01927 operand2)),
01928 gen_rtx_CLOBBER (VOIDmode,
01929 operand3)));
01930 }
01931
01932
01933 rtx
01934 gen_lshrdi3_internal3 (operand0, operand1, operand2, operand3)
01935 rtx operand0;
01936 rtx operand1;
01937 rtx operand2;
01938 rtx operand3;
01939 {
01940 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
01941 gen_rtx_SET (VOIDmode,
01942 operand0,
01943 gen_rtx_LSHIFTRT (DImode,
01944 operand1,
01945 operand2)),
01946 gen_rtx_CLOBBER (VOIDmode,
01947 operand3)));
01948 }
01949
01950
01951 rtx
01952 gen_lshrdi3_internal4 (operand0, operand1, operand2)
01953 rtx operand0;
01954 rtx operand1;
01955 rtx operand2;
01956 {
01957 return gen_rtx_SET (VOIDmode,
01958 operand0,
01959 gen_rtx_LSHIFTRT (DImode,
01960 operand1,
01961 operand2));
01962 }
01963
01964
01965 rtx
01966 gen_rotrsi3 (operand0, operand1, operand2)
01967 rtx operand0;
01968 rtx operand1;
01969 rtx operand2;
01970 {
01971 return gen_rtx_SET (VOIDmode,
01972 operand0,
01973 gen_rtx_ROTATERT (SImode,
01974 operand1,
01975 operand2));
01976 }
01977
01978
01979 rtx
01980 gen_rotrdi3 (operand0, operand1, operand2)
01981 rtx operand0;
01982 rtx operand1;
01983 rtx operand2;
01984 {
01985 return gen_rtx_SET (VOIDmode,
01986 operand0,
01987 gen_rtx_ROTATERT (DImode,
01988 operand1,
01989 operand2));
01990 }
01991
01992
01993 rtx
01994 gen_branch_fp (operand0, operand1, operand2)
01995 rtx operand0;
01996 rtx operand1;
01997 rtx operand2;
01998 {
01999 return gen_rtx_SET (VOIDmode,
02000 pc_rtx,
02001 gen_rtx_IF_THEN_ELSE (VOIDmode,
02002 gen_rtx (GET_CODE (operand0), CCmode,
02003 operand2,
02004 const0_rtx),
02005 gen_rtx_LABEL_REF (VOIDmode,
02006 operand1),
02007 pc_rtx));
02008 }
02009
02010
02011 rtx
02012 gen_branch_fp_inverted (operand0, operand1, operand2)
02013 rtx operand0;
02014 rtx operand1;
02015 rtx operand2;
02016 {
02017 return gen_rtx_SET (VOIDmode,
02018 pc_rtx,
02019 gen_rtx_IF_THEN_ELSE (VOIDmode,
02020 gen_rtx (GET_CODE (operand0), CCmode,
02021 operand2,
02022 const0_rtx),
02023 pc_rtx,
02024 gen_rtx_LABEL_REF (VOIDmode,
02025 operand1)));
02026 }
02027
02028
02029 rtx
02030 gen_branch_zero (operand0, operand1, operand2)
02031 rtx operand0;
02032 rtx operand1;
02033 rtx operand2;
02034 {
02035 return gen_rtx_SET (VOIDmode,
02036 pc_rtx,
02037 gen_rtx_IF_THEN_ELSE (VOIDmode,
02038 gen_rtx (GET_CODE (operand0), SImode,
02039 operand2,
02040 const0_rtx),
02041 gen_rtx_LABEL_REF (VOIDmode,
02042 operand1),
02043 pc_rtx));
02044 }
02045
02046
02047 rtx
02048 gen_branch_zero_inverted (operand0, operand1, operand2)
02049 rtx operand0;
02050 rtx operand1;
02051 rtx operand2;
02052 {
02053 return gen_rtx_SET (VOIDmode,
02054 pc_rtx,
02055 gen_rtx_IF_THEN_ELSE (VOIDmode,
02056 gen_rtx (GET_CODE (operand0), SImode,
02057 operand2,
02058 const0_rtx),
02059 pc_rtx,
02060 gen_rtx_LABEL_REF (VOIDmode,
02061 operand1)));
02062 }
02063
02064
02065 rtx
02066 gen_branch_zero_di (operand0, operand1, operand2)
02067 rtx operand0;
02068 rtx operand1;
02069 rtx operand2;
02070 {
02071 return gen_rtx_SET (VOIDmode,
02072 pc_rtx,
02073 gen_rtx_IF_THEN_ELSE (VOIDmode,
02074 gen_rtx (GET_CODE (operand0), DImode,
02075 operand2,
02076 const0_rtx),
02077 gen_rtx_LABEL_REF (VOIDmode,
02078 operand1),
02079 pc_rtx));
02080 }
02081
02082
02083 rtx
02084 gen_branch_zero_di_inverted (operand0, operand1, operand2)
02085 rtx operand0;
02086 rtx operand1;
02087 rtx operand2;
02088 {
02089 return gen_rtx_SET (VOIDmode,
02090 pc_rtx,
02091 gen_rtx_IF_THEN_ELSE (VOIDmode,
02092 gen_rtx (GET_CODE (operand0), DImode,
02093 operand2,
02094 const0_rtx),
02095 pc_rtx,
02096 gen_rtx_LABEL_REF (VOIDmode,
02097 operand1)));
02098 }
02099
02100
02101 rtx
02102 gen_branch_equality (operand0, operand1, operand2, operand3)
02103 rtx operand0;
02104 rtx operand1;
02105 rtx operand2;
02106 rtx operand3;
02107 {
02108 return gen_rtx_SET (VOIDmode,
02109 pc_rtx,
02110 gen_rtx_IF_THEN_ELSE (VOIDmode,
02111 gen_rtx (GET_CODE (operand0), SImode,
02112 operand2,
02113 operand3),
02114 gen_rtx_LABEL_REF (VOIDmode,
02115 operand1),
02116 pc_rtx));
02117 }
02118
02119
02120 rtx
02121 gen_branch_equality_di (operand0, operand1, operand2, operand3)
02122 rtx operand0;
02123 rtx operand1;
02124 rtx operand2;
02125 rtx operand3;
02126 {
02127 return gen_rtx_SET (VOIDmode,
02128 pc_rtx,
02129 gen_rtx_IF_THEN_ELSE (VOIDmode,
02130 gen_rtx (GET_CODE (operand0), DImode,
02131 operand2,
02132 operand3),
02133 gen_rtx_LABEL_REF (VOIDmode,
02134 operand1),
02135 pc_rtx));
02136 }
02137
02138
02139 rtx
02140 gen_branch_equality_inverted (operand0, operand1, operand2, operand3)
02141 rtx operand0;
02142 rtx operand1;
02143 rtx operand2;
02144 rtx operand3;
02145 {
02146 return gen_rtx_SET (VOIDmode,
02147 pc_rtx,
02148 gen_rtx_IF_THEN_ELSE (VOIDmode,
02149 gen_rtx (GET_CODE (operand0), SImode,
02150 operand2,
02151 operand3),
02152 pc_rtx,
02153 gen_rtx_LABEL_REF (VOIDmode,
02154 operand1)));
02155 }
02156
02157
02158 rtx
02159 gen_branch_equality_di_inverted (operand0, operand1, operand2, operand3)
02160 rtx operand0;
02161 rtx operand1;
02162 rtx operand2;
02163 rtx operand3;
02164 {
02165 return gen_rtx_SET (VOIDmode,
02166 pc_rtx,
02167 gen_rtx_IF_THEN_ELSE (VOIDmode,
02168 gen_rtx (GET_CODE (operand0), DImode,
02169 operand2,
02170 operand3),
02171 pc_rtx,
02172 gen_rtx_LABEL_REF (VOIDmode,
02173 operand1)));
02174 }
02175
02176
02177 rtx
02178 gen_seq_si_zero (operand0, operand1)
02179 rtx operand0;
02180 rtx operand1;
02181 {
02182 return gen_rtx_SET (VOIDmode,
02183 operand0,
02184 gen_rtx_EQ (SImode,
02185 operand1,
02186 const0_rtx));
02187 }
02188
02189
02190 rtx
02191 gen_seq_di_zero (operand0, operand1)
02192 rtx operand0;
02193 rtx operand1;
02194 {
02195 return gen_rtx_SET (VOIDmode,
02196 operand0,
02197 gen_rtx_EQ (DImode,
02198 operand1,
02199 const0_rtx));
02200 }
02201
02202
02203 rtx
02204 gen_sne_si_zero (operand0, operand1)
02205 rtx operand0;
02206 rtx operand1;
02207 {
02208 return gen_rtx_SET (VOIDmode,
02209 operand0,
02210 gen_rtx_NE (SImode,
02211 operand1,
02212 const0_rtx));
02213 }
02214
02215
02216 rtx
02217 gen_sne_di_zero (operand0, operand1)
02218 rtx operand0;
02219 rtx operand1;
02220 {
02221 return gen_rtx_SET (VOIDmode,
02222 operand0,
02223 gen_rtx_NE (DImode,
02224 operand1,
02225 const0_rtx));
02226 }
02227
02228
02229 rtx
02230 gen_sgt_si (operand0, operand1, operand2)
02231 rtx operand0;
02232 rtx operand1;
02233 rtx operand2;
02234 {
02235 return gen_rtx_SET (VOIDmode,
02236 operand0,
02237 gen_rtx_GT (SImode,
02238 operand1,
02239 operand2));
02240 }
02241
02242
02243 rtx
02244 gen_sgt_di (operand0, operand1, operand2)
02245 rtx operand0;
02246 rtx operand1;
02247 rtx operand2;
02248 {
02249 return gen_rtx_SET (VOIDmode,
02250 operand0,
02251 gen_rtx_GT (DImode,
02252 operand1,
02253 operand2));
02254 }
02255
02256
02257 rtx
02258 gen_slt_si (operand0, operand1, operand2)
02259 rtx operand0;
02260 rtx operand1;
02261 rtx operand2;
02262 {
02263 return gen_rtx_SET (VOIDmode,
02264 operand0,
02265 gen_rtx_LT (SImode,
02266 operand1,
02267 operand2));
02268 }
02269
02270
02271 rtx
02272 gen_slt_di (operand0, operand1, operand2)
02273 rtx operand0;
02274 rtx operand1;
02275 rtx operand2;
02276 {
02277 return gen_rtx_SET (VOIDmode,
02278 operand0,
02279 gen_rtx_LT (DImode,
02280 operand1,
02281 operand2));
02282 }
02283
02284
02285 rtx
02286 gen_sle_si_const (operand0, operand1, operand2)
02287 rtx operand0;
02288 rtx operand1;
02289 rtx operand2;
02290 {
02291 return gen_rtx_SET (VOIDmode,
02292 operand0,
02293 gen_rtx_LE (SImode,
02294 operand1,
02295 operand2));
02296 }
02297
02298
02299 rtx
02300 gen_sle_di_const (operand0, operand1, operand2)
02301 rtx operand0;
02302 rtx operand1;
02303 rtx operand2;
02304 {
02305 return gen_rtx_SET (VOIDmode,
02306 operand0,
02307 gen_rtx_LE (DImode,
02308 operand1,
02309 operand2));
02310 }
02311
02312
02313 rtx
02314 gen_sgtu_si (operand0, operand1, operand2)
02315 rtx operand0;
02316 rtx operand1;
02317 rtx operand2;
02318 {
02319 return gen_rtx_SET (VOIDmode,
02320 operand0,
02321 gen_rtx_GTU (SImode,
02322 operand1,
02323 operand2));
02324 }
02325
02326
02327 rtx
02328 gen_sgtu_di (operand0, operand1, operand2)
02329 rtx operand0;
02330 rtx operand1;
02331 rtx operand2;
02332 {
02333 return gen_rtx_SET (VOIDmode,
02334 operand0,
02335 gen_rtx_GTU (DImode,
02336 operand1,
02337 operand2));
02338 }
02339
02340
02341 rtx
02342 gen_sltu_si (operand0, operand1, operand2)
02343 rtx operand0;
02344 rtx operand1;
02345 rtx operand2;
02346 {
02347 return gen_rtx_SET (VOIDmode,
02348 operand0,
02349 gen_rtx_LTU (SImode,
02350 operand1,
02351 operand2));
02352 }
02353
02354
02355 rtx
02356 gen_sltu_di (operand0, operand1, operand2)
02357 rtx operand0;
02358 rtx operand1;
02359 rtx operand2;
02360 {
02361 return gen_rtx_SET (VOIDmode,
02362 operand0,
02363 gen_rtx_LTU (DImode,
02364 operand1,
02365 operand2));
02366 }
02367
02368
02369 rtx
02370 gen_sleu_si_const (operand0, operand1, operand2)
02371 rtx operand0;
02372 rtx operand1;
02373 rtx operand2;
02374 {
02375 return gen_rtx_SET (VOIDmode,
02376 operand0,
02377 gen_rtx_LEU (SImode,
02378 operand1,
02379 operand2));
02380 }
02381
02382
02383 rtx
02384 gen_sleu_di_const (operand0, operand1, operand2)
02385 rtx operand0;
02386 rtx operand1;
02387 rtx operand2;
02388 {
02389 return gen_rtx_SET (VOIDmode,
02390 operand0,
02391 gen_rtx_LEU (DImode,
02392 operand1,
02393 operand2));
02394 }
02395
02396
02397 rtx
02398 gen_sunordered_df (operand0, operand1, operand2)
02399 rtx operand0;
02400 rtx operand1;
02401 rtx operand2;
02402 {
02403 return gen_rtx_SET (VOIDmode,
02404 operand0,
02405 gen_rtx_UNORDERED (CCmode,
02406 operand1,
02407 operand2));
02408 }
02409
02410
02411 rtx
02412 gen_sunlt_df (operand0, operand1, operand2)
02413 rtx operand0;
02414 rtx operand1;
02415 rtx operand2;
02416 {
02417 return gen_rtx_SET (VOIDmode,
02418 operand0,
02419 gen_rtx_UNLT (CCmode,
02420 operand1,
02421 operand2));
02422 }
02423
02424
02425 rtx
02426 gen_suneq_df (operand0, operand1, operand2)
02427 rtx operand0;
02428 rtx operand1;
02429 rtx operand2;
02430 {
02431 return gen_rtx_SET (VOIDmode,
02432 operand0,
02433 gen_rtx_UNEQ (CCmode,
02434 operand1,
02435 operand2));
02436 }
02437
02438
02439 rtx
02440 gen_sunle_df (operand0, operand1, operand2)
02441 rtx operand0;
02442 rtx operand1;
02443 rtx operand2;
02444 {
02445 return gen_rtx_SET (VOIDmode,
02446 operand0,
02447 gen_rtx_UNLE (CCmode,
02448 operand1,
02449 operand2));
02450 }
02451
02452
02453 rtx
02454 gen_seq_df (operand0, operand1, operand2)
02455 rtx operand0;
02456 rtx operand1;
02457 rtx operand2;
02458 {
02459 return gen_rtx_SET (VOIDmode,
02460 operand0,
02461 gen_rtx_EQ (CCmode,
02462 operand1,
02463 operand2));
02464 }
02465
02466
02467 rtx
02468 gen_slt_df (operand0, operand1, operand2)
02469 rtx operand0;
02470 rtx operand1;
02471 rtx operand2;
02472 {
02473 return gen_rtx_SET (VOIDmode,
02474 operand0,
02475 gen_rtx_LT (CCmode,
02476 operand1,
02477 operand2));
02478 }
02479
02480
02481 rtx
02482 gen_sle_df (operand0, operand1, operand2)
02483 rtx operand0;
02484 rtx operand1;
02485 rtx operand2;
02486 {
02487 return gen_rtx_SET (VOIDmode,
02488 operand0,
02489 gen_rtx_LE (CCmode,
02490 operand1,
02491 operand2));
02492 }
02493
02494
02495 rtx
02496 gen_sgt_df (operand0, operand1, operand2)
02497 rtx operand0;
02498 rtx operand1;
02499 rtx operand2;
02500 {
02501 return gen_rtx_SET (VOIDmode,
02502 operand0,
02503 gen_rtx_GT (CCmode,
02504 operand1,
02505 operand2));
02506 }
02507
02508
02509 rtx
02510 gen_sge_df (operand0, operand1, operand2)
02511 rtx operand0;
02512 rtx operand1;
02513 rtx operand2;
02514 {
02515 return gen_rtx_SET (VOIDmode,
02516 operand0,
02517 gen_rtx_GE (CCmode,
02518 operand1,
02519 operand2));
02520 }
02521
02522
02523 rtx
02524 gen_sunordered_sf (operand0, operand1, operand2)
02525 rtx operand0;
02526 rtx operand1;
02527 rtx operand2;
02528 {
02529 return gen_rtx_SET (VOIDmode,
02530 operand0,
02531 gen_rtx_UNORDERED (CCmode,
02532 operand1,
02533 operand2));
02534 }
02535
02536
02537 rtx
02538 gen_sunlt_sf (operand0, operand1, operand2)
02539 rtx operand0;
02540 rtx operand1;
02541 rtx operand2;
02542 {
02543 return gen_rtx_SET (VOIDmode,
02544 operand0,
02545 gen_rtx_UNLT (CCmode,
02546 operand1,
02547 operand2));
02548 }
02549
02550
02551 rtx
02552 gen_suneq_sf (operand0, operand1, operand2)
02553 rtx operand0;
02554 rtx operand1;
02555 rtx operand2;
02556 {
02557 return gen_rtx_SET (VOIDmode,
02558 operand0,
02559 gen_rtx_UNEQ (CCmode,
02560 operand1,
02561 operand2));
02562 }
02563
02564
02565 rtx
02566 gen_sunle_sf (operand0, operand1, operand2)
02567 rtx operand0;
02568 rtx operand1;
02569 rtx operand2;
02570 {
02571 return gen_rtx_SET (VOIDmode,
02572 operand0,
02573 gen_rtx_UNLE (CCmode,
02574 operand1,
02575 operand2));
02576 }
02577
02578
02579 rtx
02580 gen_seq_sf (operand0, operand1, operand2)
02581 rtx operand0;
02582 rtx operand1;
02583 rtx operand2;
02584 {
02585 return gen_rtx_SET (VOIDmode,
02586 operand0,
02587 gen_rtx_EQ (CCmode,
02588 operand1,
02589 operand2));
02590 }
02591
02592
02593 rtx
02594 gen_slt_sf (operand0, operand1, operand2)
02595 rtx operand0;
02596 rtx operand1;
02597 rtx operand2;
02598 {
02599 return gen_rtx_SET (VOIDmode,
02600 operand0,
02601 gen_rtx_LT (CCmode,
02602 operand1,
02603 operand2));
02604 }
02605
02606
02607 rtx
02608 gen_sle_sf (operand0, operand1, operand2)
02609 rtx operand0;
02610 rtx operand1;
02611 rtx operand2;
02612 {
02613 return gen_rtx_SET (VOIDmode,
02614 operand0,
02615 gen_rtx_LE (CCmode,
02616 operand1,
02617 operand2));
02618 }
02619
02620
02621 rtx
02622 gen_sgt_sf (operand0, operand1, operand2)
02623 rtx operand0;
02624 rtx operand1;
02625 rtx operand2;
02626 {
02627 return gen_rtx_SET (VOIDmode,
02628 operand0,
02629 gen_rtx_GT (CCmode,
02630 operand1,
02631 operand2));
02632 }
02633
02634
02635 rtx
02636 gen_sge_sf (operand0, operand1, operand2)
02637 rtx operand0;
02638 rtx operand1;
02639 rtx operand2;
02640 {
02641 return gen_rtx_SET (VOIDmode,
02642 operand0,
02643 gen_rtx_GE (CCmode,
02644 operand1,
02645 operand2));
02646 }
02647
02648
02649 rtx
02650 gen_jump (operand0)
02651 rtx operand0;
02652 {
02653 return gen_rtx_SET (VOIDmode,
02654 pc_rtx,
02655 gen_rtx_LABEL_REF (VOIDmode,
02656 operand0));
02657 }
02658
02659
02660 rtx
02661 gen_indirect_jump_internal1 (operand0)
02662 rtx operand0;
02663 {
02664 return gen_rtx_SET (VOIDmode,
02665 pc_rtx,
02666 operand0);
02667 }
02668
02669
02670 rtx
02671 gen_indirect_jump_internal2 (operand0)
02672 rtx operand0;
02673 {
02674 return gen_rtx_SET (VOIDmode,
02675 pc_rtx,
02676 operand0);
02677 }
02678
02679
02680 rtx
02681 gen_tablejump_internal1 (operand0, operand1)
02682 rtx operand0;
02683 rtx operand1;
02684 {
02685 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02686 gen_rtx_SET (VOIDmode,
02687 pc_rtx,
02688 operand0),
02689 gen_rtx_USE (VOIDmode,
02690 gen_rtx_LABEL_REF (VOIDmode,
02691 operand1))));
02692 }
02693
02694
02695 rtx
02696 gen_tablejump_internal2 (operand0, operand1)
02697 rtx operand0;
02698 rtx operand1;
02699 {
02700 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02701 gen_rtx_SET (VOIDmode,
02702 pc_rtx,
02703 operand0),
02704 gen_rtx_USE (VOIDmode,
02705 gen_rtx_LABEL_REF (VOIDmode,
02706 operand1))));
02707 }
02708
02709
02710 rtx
02711 gen_casesi_internal (operand0, operand1, operand2)
02712 rtx operand0;
02713 rtx operand1;
02714 rtx operand2;
02715 {
02716 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02717 gen_rtx_SET (VOIDmode,
02718 pc_rtx,
02719 gen_rtx_MEM (SImode,
02720 gen_rtx_PLUS (SImode,
02721 gen_rtx_MULT (SImode,
02722 operand0,
02723 GEN_INT (4LL)),
02724 gen_rtx_LABEL_REF (VOIDmode,
02725 operand1)))),
02726 gen_rtx_CLOBBER (VOIDmode,
02727 operand2),
02728 gen_rtx_CLOBBER (VOIDmode,
02729 gen_rtx_REG (SImode,
02730 31))));
02731 }
02732
02733
02734 rtx
02735 gen_casesi_internal_di (operand0, operand1, operand2)
02736 rtx operand0;
02737 rtx operand1;
02738 rtx operand2;
02739 {
02740 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
02741 gen_rtx_SET (VOIDmode,
02742 pc_rtx,
02743 gen_rtx_MEM (DImode,
02744 gen_rtx_PLUS (DImode,
02745 gen_rtx_SIGN_EXTEND (DImode,
02746 gen_rtx_MULT (SImode,
02747 operand0,
02748 GEN_INT (8LL))),
02749 gen_rtx_LABEL_REF (VOIDmode,
02750 operand1)))),
02751 gen_rtx_CLOBBER (VOIDmode,
02752 operand2),
02753 gen_rtx_CLOBBER (VOIDmode,
02754 gen_rtx_REG (DImode,
02755 31))));
02756 }
02757
02758
02759 rtx
02760 gen_blockage ()
02761 {
02762 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
02763 gen_rtvec (1,
02764 const0_rtx),
02765 6);
02766 }
02767
02768
02769 rtx
02770 gen_return ()
02771 {
02772 return gen_rtx_RETURN (VOIDmode);
02773 }
02774
02775
02776 rtx
02777 gen_return_internal (operand0)
02778 rtx operand0;
02779 {
02780 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02781 gen_rtx_USE (VOIDmode,
02782 operand0),
02783 gen_rtx_RETURN (VOIDmode)));
02784 }
02785
02786
02787 rtx
02788 gen_get_fnaddr (operand0, operand1)
02789 rtx operand0;
02790 rtx operand1;
02791 {
02792 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02793 gen_rtx_SET (VOIDmode,
02794 operand0,
02795 gen_rtx_UNSPEC (VOIDmode,
02796 gen_rtvec (1,
02797 operand1),
02798 4)),
02799 gen_rtx_CLOBBER (VOIDmode,
02800 gen_rtx_REG (SImode,
02801 31))));
02802 }
02803
02804
02805 rtx
02806 gen_eh_set_lr_si (operand0)
02807 rtx operand0;
02808 {
02809 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02810 gen_rtx_UNSPEC (VOIDmode,
02811 gen_rtvec (1,
02812 operand0),
02813 11),
02814 gen_rtx_CLOBBER (VOIDmode,
02815 gen_rtx_SCRATCH (SImode))));
02816 }
02817
02818
02819 rtx
02820 gen_eh_set_lr_di (operand0)
02821 rtx operand0;
02822 {
02823 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02824 gen_rtx_UNSPEC (VOIDmode,
02825 gen_rtvec (1,
02826 operand0),
02827 11),
02828 gen_rtx_CLOBBER (VOIDmode,
02829 gen_rtx_SCRATCH (DImode))));
02830 }
02831
02832
02833 rtx
02834 gen_exception_receiver ()
02835 {
02836 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
02837 gen_rtvec (1,
02838 const0_rtx),
02839 10);
02840 }
02841
02842
02843 rtx
02844 gen_call_internal1 (operand0, operand1, operand2)
02845 rtx operand0;
02846 rtx operand1;
02847 rtx operand2;
02848 {
02849 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02850 gen_rtx_CALL (VOIDmode,
02851 gen_rtx_MEM (VOIDmode,
02852 operand0),
02853 operand1),
02854 gen_rtx_CLOBBER (VOIDmode,
02855 operand2)));
02856 }
02857
02858
02859 rtx
02860 gen_call_internal2 (operand0, operand1, operand2)
02861 rtx operand0;
02862 rtx operand1;
02863 rtx operand2;
02864 {
02865 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02866 gen_rtx_CALL (VOIDmode,
02867 gen_rtx_MEM (VOIDmode,
02868 operand0),
02869 operand1),
02870 gen_rtx_CLOBBER (VOIDmode,
02871 operand2)));
02872 }
02873
02874
02875 rtx
02876 gen_call_internal3a (operand0, operand1, operand2)
02877 rtx operand0;
02878 rtx operand1;
02879 rtx operand2;
02880 {
02881 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02882 gen_rtx_CALL (VOIDmode,
02883 gen_rtx_MEM (SImode,
02884 operand0),
02885 operand1),
02886 gen_rtx_CLOBBER (VOIDmode,
02887 operand2)));
02888 }
02889
02890
02891 rtx
02892 gen_call_internal3b (operand0, operand1, operand2)
02893 rtx operand0;
02894 rtx operand1;
02895 rtx operand2;
02896 {
02897 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02898 gen_rtx_CALL (VOIDmode,
02899 gen_rtx_MEM (DImode,
02900 operand0),
02901 operand1),
02902 gen_rtx_CLOBBER (VOIDmode,
02903 operand2)));
02904 }
02905
02906
02907 rtx
02908 gen_call_internal3c (operand0, operand1, operand2)
02909 rtx operand0;
02910 rtx operand1;
02911 rtx operand2;
02912 {
02913 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02914 gen_rtx_CALL (VOIDmode,
02915 gen_rtx_MEM (SImode,
02916 operand0),
02917 operand1),
02918 gen_rtx_CLOBBER (VOIDmode,
02919 operand2)));
02920 }
02921
02922
02923 rtx
02924 gen_call_internal4a (operand0, operand1, operand2)
02925 rtx operand0;
02926 rtx operand1;
02927 rtx operand2;
02928 {
02929 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02930 gen_rtx_CALL (VOIDmode,
02931 gen_rtx_MEM (SImode,
02932 operand0),
02933 operand1),
02934 gen_rtx_CLOBBER (VOIDmode,
02935 operand2)));
02936 }
02937
02938
02939 rtx
02940 gen_call_internal4b (operand0, operand1, operand2)
02941 rtx operand0;
02942 rtx operand1;
02943 rtx operand2;
02944 {
02945 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02946 gen_rtx_CALL (VOIDmode,
02947 gen_rtx_MEM (DImode,
02948 operand0),
02949 operand1),
02950 gen_rtx_CLOBBER (VOIDmode,
02951 operand2)));
02952 }
02953
02954
02955 rtx
02956 gen_call_value_internal1 (operand0, operand1, operand2, operand3)
02957 rtx operand0;
02958 rtx operand1;
02959 rtx operand2;
02960 rtx operand3;
02961 {
02962 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02963 gen_rtx_SET (VOIDmode,
02964 operand0,
02965 gen_rtx_CALL (VOIDmode,
02966 gen_rtx_MEM (VOIDmode,
02967 operand1),
02968 operand2)),
02969 gen_rtx_CLOBBER (VOIDmode,
02970 operand3)));
02971 }
02972
02973
02974 rtx
02975 gen_call_value_internal2 (operand0, operand1, operand2, operand3)
02976 rtx operand0;
02977 rtx operand1;
02978 rtx operand2;
02979 rtx operand3;
02980 {
02981 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
02982 gen_rtx_SET (VOIDmode,
02983 operand0,
02984 gen_rtx_CALL (VOIDmode,
02985 gen_rtx_MEM (VOIDmode,
02986 operand1),
02987 operand2)),
02988 gen_rtx_CLOBBER (VOIDmode,
02989 operand3)));
02990 }
02991
02992
02993 rtx
02994 gen_call_value_internal3a (operand0, operand1, operand2, operand3)
02995 rtx operand0;
02996 rtx operand1;
02997 rtx operand2;
02998 rtx operand3;
02999 {
03000 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
03001 gen_rtx_SET (VOIDmode,
03002 operand0,
03003 gen_rtx_CALL (VOIDmode,
03004 gen_rtx_MEM (SImode,
03005 operand1),
03006 operand2)),
03007 gen_rtx_CLOBBER (VOIDmode,
03008 operand3)));
03009 }
03010
03011
03012 rtx
03013 gen_call_value_internal3b (operand0, operand1, operand2, operand3)
03014 rtx operand0;
03015 rtx operand1;
03016 rtx operand2;
03017 rtx operand3;
03018 {
03019 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
03020 gen_rtx_SET (VOIDmode,
03021 operand0,
03022 gen_rtx_CALL (VOIDmode,
03023 gen_rtx_MEM (DImode,
03024 operand1),
03025 operand2)),
03026 gen_rtx_CLOBBER (VOIDmode,
03027 operand3)));
03028 }
03029
03030
03031 rtx
03032 gen_call_value_internal3c (operand0, operand1, operand2, operand3)
03033 rtx operand0;
03034 rtx operand1;
03035 rtx operand2;
03036 rtx operand3;
03037 {
03038 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
03039 gen_rtx_SET (VOIDmode,
03040 operand0,
03041 gen_rtx_CALL (VOIDmode,
03042 gen_rtx_MEM (SImode,
03043 operand1),
03044 operand2)),
03045 gen_rtx_CLOBBER (VOIDmode,
03046 operand3)));
03047 }
03048
03049
03050 rtx
03051 gen_call_value_internal4a (operand0, operand1, operand2, operand3)
03052 rtx operand0;
03053 rtx operand1;
03054 rtx operand2;
03055 rtx operand3;
03056 {
03057 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
03058 gen_rtx_SET (VOIDmode,
03059 operand0,
03060 gen_rtx_CALL (VOIDmode,
03061 gen_rtx_MEM (SImode,
03062 operand1),
03063 operand2)),
03064 gen_rtx_CLOBBER (VOIDmode,
03065 operand3)));
03066 }
03067
03068
03069 rtx
03070 gen_call_value_internal4b (operand0, operand1, operand2, operand3)
03071 rtx operand0;
03072 rtx operand1;
03073 rtx operand2;
03074 rtx operand3;
03075 {
03076 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2,
03077 gen_rtx_SET (VOIDmode,
03078 operand0,
03079 gen_rtx_CALL (VOIDmode,
03080 gen_rtx_MEM (DImode,
03081 operand1),
03082 operand2)),
03083 gen_rtx_CLOBBER (VOIDmode,
03084 operand3)));
03085 }
03086
03087
03088 rtx
03089 gen_call_value_multiple_internal1 (operand0, operand1, operand2, operand3, operand4)
03090 rtx operand0;
03091 rtx operand1;
03092 rtx operand2;
03093 rtx operand3;
03094 rtx operand4;
03095 {
03096 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
03097 gen_rtx_SET (VOIDmode,
03098 operand0,
03099 gen_rtx_CALL (VOIDmode,
03100 gen_rtx_MEM (VOIDmode,
03101 operand1),
03102 operand2)),
03103 gen_rtx_SET (VOIDmode,
03104 operand3,
03105 gen_rtx_CALL (VOIDmode,
03106 gen_rtx_MEM (VOIDmode,
03107 operand1),
03108 operand2)),
03109 gen_rtx_CLOBBER (VOIDmode,
03110 operand4)));
03111 }
03112
03113
03114 rtx
03115 gen_call_value_multiple_internal2 (operand0, operand1, operand2, operand3, operand4)
03116 rtx operand0;
03117 rtx operand1;
03118 rtx operand2;
03119 rtx operand3;
03120 rtx operand4;
03121 {
03122 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3,
03123 gen_rtx_SET (VOIDmode,
03124 operand0,
03125 gen_rtx_CALL (VOIDmode,
03126 gen_rtx_MEM (VOIDmode,
03127 operand1),
03128 operand2)),
03129 gen_rtx_SET (VOIDmode,
03130 operand3,
03131 gen_rtx_CALL (VOIDmode,
03132 gen_rtx_MEM (VOIDmode,
03133 operand1),
03134 operand2)),
03135 gen_rtx_CLOBBER (VOIDmode,
03136 operand4)));
03137 }
03138
03139
03140 rtx
03141 gen_prefetch_si_address (operand0, operand1, operand2, operand3)
03142 rtx operand0;
03143 rtx operand1;
03144 rtx operand2;
03145 rtx operand3;
03146 {
03147 return gen_rtx_PREFETCH (VOIDmode,
03148 gen_rtx_PLUS (SImode,
03149 operand0,
03150 operand3),
03151 operand1,
03152 operand2);
03153 }
03154
03155
03156 rtx
03157 gen_prefetch_si (operand0, operand1, operand2)
03158 rtx operand0;
03159 rtx operand1;
03160 rtx operand2;
03161 {
03162 return gen_rtx_PREFETCH (VOIDmode,
03163 operand0,
03164 operand1,
03165 operand2);
03166 }
03167
03168
03169 rtx
03170 gen_prefetch_di_address (operand0, operand1, operand2, operand3)
03171 rtx operand0;
03172 rtx operand1;
03173 rtx operand2;
03174 rtx operand3;
03175 {
03176 return gen_rtx_PREFETCH (VOIDmode,
03177 gen_rtx_PLUS (DImode,
03178 operand0,
03179 operand3),
03180 operand1,
03181 operand2);
03182 }
03183
03184
03185 rtx
03186 gen_prefetch_di (operand0, operand1, operand2)
03187 rtx operand0;
03188 rtx operand1;
03189 rtx operand2;
03190 {
03191 return gen_rtx_PREFETCH (VOIDmode,
03192 operand0,
03193 operand1,
03194 operand2);
03195 }
03196
03197
03198 rtx
03199 gen_nop ()
03200 {
03201 return const0_rtx;
03202 }
03203
03204
03205 rtx
03206 gen_consttable_qi (operand0)
03207 rtx operand0;
03208 {
03209 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03210 gen_rtvec (1,
03211 operand0),
03212 12);
03213 }
03214
03215
03216 rtx
03217 gen_consttable_hi (operand0)
03218 rtx operand0;
03219 {
03220 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03221 gen_rtvec (1,
03222 operand0),
03223 13);
03224 }
03225
03226
03227 rtx
03228 gen_consttable_si (operand0)
03229 rtx operand0;
03230 {
03231 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03232 gen_rtvec (1,
03233 operand0),
03234 14);
03235 }
03236
03237
03238 rtx
03239 gen_consttable_di (operand0)
03240 rtx operand0;
03241 {
03242 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03243 gen_rtvec (1,
03244 operand0),
03245 15);
03246 }
03247
03248
03249 rtx
03250 gen_consttable_sf (operand0)
03251 rtx operand0;
03252 {
03253 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03254 gen_rtvec (1,
03255 operand0),
03256 16);
03257 }
03258
03259
03260 rtx
03261 gen_consttable_df (operand0)
03262 rtx operand0;
03263 {
03264 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03265 gen_rtvec (1,
03266 operand0),
03267 17);
03268 }
03269
03270
03271 rtx
03272 gen_align_2 ()
03273 {
03274 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03275 gen_rtvec (1,
03276 const0_rtx),
03277 18);
03278 }
03279
03280
03281 rtx
03282 gen_align_4 ()
03283 {
03284 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03285 gen_rtvec (1,
03286 const0_rtx),
03287 19);
03288 }
03289
03290
03291 rtx
03292 gen_align_8 ()
03293 {
03294 return gen_rtx_UNSPEC_VOLATILE (VOIDmode,
03295 gen_rtvec (1,
03296 const0_rtx),
03297 20);
03298 }
03299
03300
03301 rtx
03302 gen_leasi (operand0, operand1)
03303 rtx operand0;
03304 rtx operand1;
03305 {
03306 return gen_rtx_SET (VOIDmode,
03307 operand0,
03308 operand1);
03309 }
03310
03311
03312 rtx
03313 gen_leadi (operand0, operand1)
03314 rtx operand0;
03315 rtx operand1;
03316 {
03317 return gen_rtx_SET (VOIDmode,
03318 operand0,
03319 operand1);
03320 }
03321
03322
03323 rtx
03324 gen_conditional_trap (operand0, operand1)
03325 rtx operand0;
03326 rtx operand1;
03327 {
03328 rtx operand2;
03329 rtx operand3;
03330 rtx _val = 0;
03331 start_sequence ();
03332 {
03333 rtx operands[4];
03334 operands[0] = operand0;
03335 operands[1] = operand1;
03336
03337 {
03338 mips_gen_conditional_trap (operands);
03339 DONE;
03340 }
03341 operand0 = operands[0];
03342 operand1 = operands[1];
03343 operand2 = operands[2];
03344 operand3 = operands[3];
03345 }
03346 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
03347 gen_rtx (GET_CODE (operand0), VOIDmode,
03348 operand2,
03349 operand3),
03350 operand1));
03351 _val = get_insns ();
03352 end_sequence ();
03353 return _val;
03354 }
03355
03356
03357 rtx
03358 gen_addsi3 (operand0, operand1, operand2)
03359 rtx operand0;
03360 rtx operand1;
03361 rtx operand2;
03362 {
03363 rtx _val = 0;
03364 start_sequence ();
03365 {
03366 rtx operands[3];
03367 operands[0] = operand0;
03368 operands[1] = operand1;
03369 operands[2] = operand2;
03370
03371 {
03372
03373
03374
03375 if (! TARGET_MIPS16
03376 && ! TARGET_GAS
03377 && GET_CODE (operands[2]) == CONST_INT
03378 && INTVAL (operands[2]) == -32768)
03379 operands[2] = force_reg (SImode, operands[2]);
03380
03381
03382
03383
03384
03385
03386
03387
03388 if (TARGET_MIPS16
03389 && REGNO (operands[0]) == STACK_POINTER_REGNUM
03390 && ((GET_CODE (operands[1]) == REG
03391 && REGNO (operands[1]) != STACK_POINTER_REGNUM)
03392 || GET_CODE (operands[2]) != CONST_INT))
03393 {
03394 rtx tmp = gen_reg_rtx (SImode);
03395
03396 emit_move_insn (tmp, operands[1]);
03397 emit_insn (gen_addsi3 (tmp, tmp, operands[2]));
03398 emit_move_insn (operands[0], tmp);
03399 DONE;
03400 }
03401 }
03402 operand0 = operands[0];
03403 operand1 = operands[1];
03404 operand2 = operands[2];
03405 }
03406 emit_insn (gen_rtx_SET (VOIDmode,
03407 operand0,
03408 gen_rtx_PLUS (SImode,
03409 operand1,
03410 operand2)));
03411 _val = get_insns ();
03412 end_sequence ();
03413 return _val;
03414 }
03415
03416
03417 extern rtx gen_split_344 PARAMS ((rtx *));
03418 rtx
03419 gen_split_344 (operands)
03420 rtx *operands;
03421 {
03422 rtx operand0;
03423 rtx operand1;
03424 rtx operand2;
03425 rtx _val = 0;
03426 start_sequence ();
03427
03428 {
03429 HOST_WIDE_INT val = INTVAL (operands[1]);
03430
03431 if (val >= 0)
03432 {
03433 operands[1] = GEN_INT (0x7f);
03434 operands[2] = GEN_INT (val - 0x7f);
03435 }
03436 else
03437 {
03438 operands[1] = GEN_INT (- 0x80);
03439 operands[2] = GEN_INT (val + 0x80);
03440 }
03441 }
03442 operand0 = operands[0];
03443 operand1 = operands[1];
03444 operand2 = operands[2];
03445 emit_insn (gen_rtx_SET (VOIDmode,
03446 operand0,
03447 gen_rtx_PLUS (SImode,
03448 copy_rtx (operand0),
03449 operand1)));
03450 emit_insn (gen_rtx_SET (VOIDmode,
03451 copy_rtx (operand0),
03452 gen_rtx_PLUS (SImode,
03453 copy_rtx (operand0),
03454 operand2)));
03455 _val = get_insns ();
03456 end_sequence ();
03457 return _val;
03458 }
03459
03460
03461 extern rtx gen_split_345 PARAMS ((rtx *));
03462 rtx
03463 gen_split_345 (operands)
03464 rtx *operands;
03465 {
03466 rtx operand0;
03467 rtx operand1;
03468 rtx operand2;
03469 rtx operand3;
03470 rtx _val = 0;
03471 start_sequence ();
03472
03473 {
03474 HOST_WIDE_INT val = INTVAL (operands[2]);
03475
03476 if (val >= 0)
03477 {
03478 operands[2] = GEN_INT (0x7);
03479 operands[3] = GEN_INT (val - 0x7);
03480 }
03481 else
03482 {
03483 operands[2] = GEN_INT (- 0x8);
03484 operands[3] = GEN_INT (val + 0x8);
03485 }
03486 }
03487 operand0 = operands[0];
03488 operand1 = operands[1];
03489 operand2 = operands[2];
03490 operand3 = operands[3];
03491 emit_insn (gen_rtx_SET (VOIDmode,
03492 operand0,
03493 gen_rtx_PLUS (SImode,
03494 operand1,
03495 operand2)));
03496 emit_insn (gen_rtx_SET (VOIDmode,
03497 copy_rtx (operand0),
03498 gen_rtx_PLUS (SImode,
03499 copy_rtx (operand0),
03500 operand3)));
03501 _val = get_insns ();
03502 end_sequence ();
03503 return _val;
03504 }
03505
03506
03507 rtx
03508 gen_adddi3 (operand0, operand1, operand2)
03509 rtx operand0;
03510 rtx operand1;
03511 rtx operand2;
03512 {
03513 rtx operand3;
03514 rtx _val = 0;
03515 start_sequence ();
03516 {
03517 rtx operands[4];
03518 operands[0] = operand0;
03519 operands[1] = operand1;
03520 operands[2] = operand2;
03521
03522 {
03523
03524
03525
03526 if (! TARGET_MIPS16
03527 && ! TARGET_GAS
03528 && GET_CODE (operands[2]) == CONST_INT
03529 && INTVAL (operands[2]) == -32768)
03530 operands[2] = force_reg (DImode, operands[2]);
03531
03532
03533
03534
03535
03536
03537
03538
03539 if (TARGET_MIPS16
03540 && REGNO (operands[0]) == STACK_POINTER_REGNUM
03541 && ((GET_CODE (operands[1]) == REG
03542 && REGNO (operands[1]) != STACK_POINTER_REGNUM)
03543 || GET_CODE (operands[2]) != CONST_INT))
03544 {
03545 rtx tmp = gen_reg_rtx (DImode);
03546
03547 emit_move_insn (tmp, operands[1]);
03548 emit_insn (gen_addsi3 (tmp, tmp, operands[2]));
03549 emit_move_insn (operands[0], tmp);
03550 DONE;
03551 }
03552
03553 if (TARGET_64BIT)
03554 {
03555 emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
03556 operands[2]));
03557 DONE;
03558 }
03559
03560 operands[3] = gen_reg_rtx (SImode);
03561 }
03562 operand0 = operands[0];
03563 operand1 = operands[1];
03564 operand2 = operands[2];
03565 operand3 = operands[3];
03566 }
03567 emit (gen_rtx_PARALLEL (VOIDmode,
03568 gen_rtvec (2,
03569 gen_rtx_SET (VOIDmode,
03570 operand0,
03571 gen_rtx_PLUS (DImode,
03572 operand1,
03573 operand2)),
03574 gen_rtx_CLOBBER (VOIDmode,
03575 operand3))));
03576 _val = get_insns ();
03577 end_sequence ();
03578 return _val;
03579 }
03580
03581
03582 extern rtx gen_split_347 PARAMS ((rtx *));
03583 rtx
03584 gen_split_347 (operands)
03585 rtx *operands;
03586 {
03587 rtx operand0;
03588 rtx operand1;
03589 rtx operand2;
03590 rtx operand3;
03591 rtx _val = 0;
03592 start_sequence ();
03593
03594 operand0 = operands[0];
03595 operand1 = operands[1];
03596 operand2 = operands[2];
03597 operand3 = operands[3];
03598 emit_insn (gen_rtx_SET (VOIDmode,
03599 gen_rtx_SUBREG (SImode,
03600 operand0,
03601 0),
03602 gen_rtx_PLUS (SImode,
03603 gen_rtx_SUBREG (SImode,
03604 operand1,
03605 0),
03606 gen_rtx_SUBREG (SImode,
03607 operand2,
03608 0))));
03609 emit_insn (gen_rtx_SET (VOIDmode,
03610 operand3,
03611 gen_rtx_LTU (SImode,
03612 gen_rtx_SUBREG (SImode,
03613 copy_rtx (operand0),
03614 0),
03615 gen_rtx_SUBREG (SImode,
03616 copy_rtx (operand2),
03617 0))));
03618 emit_insn (gen_rtx_SET (VOIDmode,
03619 gen_rtx_SUBREG (SImode,
03620 copy_rtx (operand0),
03621 4),
03622 gen_rtx_PLUS (SImode,
03623 gen_rtx_SUBREG (SImode,
03624 copy_rtx (operand1),
03625 4),
03626 gen_rtx_SUBREG (SImode,
03627 copy_rtx (operand2),
03628 4))));
03629 emit_insn (gen_rtx_SET (VOIDmode,
03630 gen_rtx_SUBREG (SImode,
03631 copy_rtx (operand0),
03632 4),
03633 gen_rtx_PLUS (SImode,
03634 gen_rtx_SUBREG (SImode,
03635 copy_rtx (operand0),
03636 4),
03637 copy_rtx (operand3))));
03638 _val = get_insns ();
03639 end_sequence ();
03640 return _val;
03641 }
03642
03643
03644 extern rtx gen_split_348 PARAMS ((rtx *));
03645 rtx
03646 gen_split_348 (operands)
03647 rtx *operands;
03648 {
03649 rtx operand0;
03650 rtx operand1;
03651 rtx operand2;
03652 rtx operand3;
03653 rtx _val = 0;
03654 start_sequence ();
03655
03656 operand0 = operands[0];
03657 operand1 = operands[1];
03658 operand2 = operands[2];
03659 operand3 = operands[3];
03660 emit_insn (gen_rtx_SET (VOIDmode,
03661 gen_rtx_SUBREG (SImode,
03662 operand0,
03663 4),
03664 gen_rtx_PLUS (SImode,
03665 gen_rtx_SUBREG (SImode,
03666 operand1,
03667 4),
03668 gen_rtx_SUBREG (SImode,
03669 operand2,
03670 4))));
03671 emit_insn (gen_rtx_SET (VOIDmode,
03672 operand3,
03673 gen_rtx_LTU (SImode,
03674 gen_rtx_SUBREG (SImode,
03675 copy_rtx (operand0),
03676 4),
03677 gen_rtx_SUBREG (SImode,
03678 copy_rtx (operand2),
03679 4))));
03680 emit_insn (gen_rtx_SET (VOIDmode,
03681 gen_rtx_SUBREG (SImode,
03682 copy_rtx (operand0),
03683 0),
03684 gen_rtx_PLUS (SImode,
03685 gen_rtx_SUBREG (SImode,
03686 copy_rtx (operand1),
03687 0),
03688 gen_rtx_SUBREG (SImode,
03689 copy_rtx (operand2),
03690 0))));
03691 emit_insn (gen_rtx_SET (VOIDmode,
03692 gen_rtx_SUBREG (SImode,
03693 copy_rtx (operand0),
03694 0),
03695 gen_rtx_PLUS (SImode,
03696 gen_rtx_SUBREG (SImode,
03697 copy_rtx (operand0),
03698 0),
03699 copy_rtx (operand3))));
03700 _val = get_insns ();
03701 end_sequence ();
03702 return _val;
03703 }
03704
03705
03706 extern rtx gen_split_349 PARAMS ((rtx *));
03707 rtx
03708 gen_split_349 (operands)
03709 rtx *operands;
03710 {
03711 rtx operand0;
03712 rtx operand1;
03713 rtx operand2;
03714 rtx operand3;
03715 rtx _val = 0;
03716 start_sequence ();
03717
03718 operand0 = operands[0];
03719 operand1 = operands[1];
03720 operand2 = operands[2];
03721 operand3 = operands[3];
03722 emit_insn (gen_rtx_SET (VOIDmode,
03723 gen_rtx_SUBREG (SImode,
03724 operand0,
03725 0),
03726 gen_rtx_PLUS (SImode,
03727 gen_rtx_SUBREG (SImode,
03728 operand1,
03729 0),
03730 operand2)));
03731 emit_insn (gen_rtx_SET (VOIDmode,
03732 operand3,
03733 gen_rtx_LTU (SImode,
03734 gen_rtx_SUBREG (SImode,
03735 copy_rtx (operand0),
03736 0),
03737 copy_rtx (operand2))));
03738 emit_insn (gen_rtx_SET (VOIDmode,
03739 gen_rtx_SUBREG (SImode,
03740 copy_rtx (operand0),
03741 4),
03742 gen_rtx_PLUS (SImode,
03743 gen_rtx_SUBREG (SImode,
03744 copy_rtx (operand1),
03745 4),
03746 copy_rtx (operand3))));
03747 _val = get_insns ();
03748 end_sequence ();
03749 return _val;
03750 }
03751
03752
03753 extern rtx gen_split_350 PARAMS ((rtx *));
03754 rtx
03755 gen_split_350 (operands)
03756 rtx *operands;
03757 {
03758 rtx operand0;
03759 rtx operand1;
03760 rtx operand2;
03761 rtx operand3;
03762 rtx _val = 0;
03763 start_sequence ();
03764
03765 operand0 = operands[0];
03766 operand1 = operands[1];
03767 operand2 = operands[2];
03768 operand3 = operands[3];
03769 emit_insn (gen_rtx_SET (VOIDmode,
03770 gen_rtx_SUBREG (SImode,
03771 operand0,
03772 4),
03773 gen_rtx_PLUS (SImode,
03774 gen_rtx_SUBREG (SImode,
03775 operand1,
03776 4),
03777 operand2)));
03778 emit_insn (gen_rtx_SET (VOIDmode,
03779 operand3,
03780 gen_rtx_LTU (SImode,
03781 gen_rtx_SUBREG (SImode,
03782 copy_rtx (operand0),
03783 4),
03784 copy_rtx (operand2))));
03785 emit_insn (gen_rtx_SET (VOIDmode,
03786 gen_rtx_SUBREG (SImode,
03787 copy_rtx (operand0),
03788 0),
03789 gen_rtx_PLUS (SImode,
03790 gen_rtx_SUBREG (SImode,
03791 copy_rtx (operand1),
03792 0),
03793 copy_rtx (operand3))));
03794 _val = get_insns ();
03795 end_sequence ();
03796 return _val;
03797 }
03798
03799
03800 extern rtx gen_split_351 PARAMS ((rtx *));
03801 rtx
03802 gen_split_351 (operands)
03803 rtx *operands;
03804 {
03805 rtx operand0;
03806 rtx operand1;
03807 rtx operand2;
03808 rtx _val = 0;
03809 start_sequence ();
03810
03811 {
03812 HOST_WIDE_INT val = INTVAL (operands[1]);
03813
03814 if (val >= 0)
03815 {
03816 operands[1] = GEN_INT (0xf);
03817 operands[2] = GEN_INT (val - 0xf);
03818 }
03819 else
03820 {
03821 operands[1] = GEN_INT (- 0x10);
03822 operands[2] = GEN_INT (val + 0x10);
03823 }
03824 }
03825 operand0 = operands[0];
03826 operand1 = operands[1];
03827 operand2 = operands[2];
03828 emit_insn (gen_rtx_SET (VOIDmode,
03829 operand0,
03830 gen_rtx_PLUS (DImode,
03831 copy_rtx (operand0),
03832 operand1)));
03833 emit_insn (gen_rtx_SET (VOIDmode,
03834 copy_rtx (operand0),
03835 gen_rtx_PLUS (DImode,
03836 copy_rtx (operand0),
03837 operand2)));
03838 _val = get_insns ();
03839 end_sequence ();
03840 return _val;
03841 }
03842
03843
03844 extern rtx gen_split_352 PARAMS ((rtx *));
03845 rtx
03846 gen_split_352 (operands)
03847 rtx *operands;
03848 {
03849 rtx operand0;
03850 rtx operand1;
03851 rtx operand2;
03852 rtx operand3;
03853 rtx _val = 0;
03854 start_sequence ();
03855
03856 {
03857 HOST_WIDE_INT val = INTVAL (operands[2]);
03858
03859 if (val >= 0)
03860 {
03861 operands[2] = GEN_INT (0x7);
03862 operands[3] = GEN_INT (val - 0x7);
03863 }
03864 else
03865 {
03866 operands[2] = GEN_INT (- 0x8);
03867 operands[3] = GEN_INT (val + 0x8);
03868 }
03869 }
03870 operand0 = operands[0];
03871 operand1 = operands[1];
03872 operand2 = operands[2];
03873 operand3 = operands[3];
03874 emit_insn (gen_rtx_SET (VOIDmode,
03875 operand0,
03876 gen_rtx_PLUS (DImode,
03877 operand1,
03878 operand2)));
03879 emit_insn (gen_rtx_SET (VOIDmode,
03880 copy_rtx (operand0),
03881 gen_rtx_PLUS (DImode,
03882 copy_rtx (operand0),
03883 operand3)));
03884 _val = get_insns ();
03885 end_sequence ();
03886 return _val;
03887 }
03888
03889
03890 rtx
03891 gen_subsi3 (operand0, operand1, operand2)
03892 rtx operand0;
03893 rtx operand1;
03894 rtx operand2;
03895 {
03896 rtx _val = 0;
03897 start_sequence ();
03898 {
03899 rtx operands[3];
03900 operands[0] = operand0;
03901 operands[1] = operand1;
03902 operands[2] = operand2;
03903
03904 {
03905 if (GET_CODE (operands[2]) == CONST_INT
03906 && (INTVAL (operands[2]) == -32768
03907 || (TARGET_MIPS16
03908 && INTVAL (operands[2]) == -0x4000)))
03909 operands[2] = force_reg (SImode, operands[2]);
03910 }
03911 operand0 = operands[0];
03912 operand1 = operands[1];
03913 operand2 = operands[2];
03914 }
03915 emit_insn (gen_rtx_SET (VOIDmode,
03916 operand0,
03917 gen_rtx_MINUS (SImode,
03918 operand1,
03919 operand2)));
03920 _val = get_insns ();
03921 end_sequence ();
03922 return _val;
03923 }
03924
03925
03926 extern rtx gen_split_354 PARAMS ((rtx *));
03927 rtx
03928 gen_split_354 (operands)
03929 rtx *operands;
03930 {
03931 rtx operand0;
03932 rtx operand1;
03933 rtx operand2;
03934 rtx _val = 0;
03935 start_sequence ();
03936
03937 {
03938 HOST_WIDE_INT val = INTVAL (operands[1]);
03939
03940 if (val >= 0)
03941 {
03942 operands[1] = GEN_INT (0x80);
03943 operands[2] = GEN_INT (val - 0x80);
03944 }
03945 else
03946 {
03947 operands[1] = GEN_INT (- 0x7f);
03948 operands[2] = GEN_INT (val + 0x7f);
03949 }
03950 }
03951 operand0 = operands[0];
03952 operand1 = operands[1];
03953 operand2 = operands[2];
03954 emit_insn (gen_rtx_SET (VOIDmode,
03955 operand0,
03956 gen_rtx_MINUS (SImode,
03957 copy_rtx (operand0),
03958 operand1)));
03959 emit_insn (gen_rtx_SET (VOIDmode,
03960 copy_rtx (operand0),
03961 gen_rtx_MINUS (SImode,
03962 copy_rtx (operand0),
03963 operand2)));
03964 _val = get_insns ();
03965 end_sequence ();
03966 return _val;
03967 }
03968
03969
03970 extern rtx gen_split_355 PARAMS ((rtx *));
03971 rtx
03972 gen_split_355 (operands)
03973 rtx *operands;
03974 {
03975 rtx operand0;
03976 rtx operand1;
03977 rtx operand2;
03978 rtx operand3;
03979 rtx _val = 0;
03980 start_sequence ();
03981
03982 {
03983 HOST_WIDE_INT val = INTVAL (operands[2]);
03984
03985 if (val >= 0)
03986 {
03987 operands[2] = GEN_INT (0x8);
03988 operands[3] = GEN_INT (val - 0x8);
03989 }
03990 else
03991 {
03992 operands[2] = GEN_INT (- 0x7);
03993 operands[3] = GEN_INT (val + 0x7);
03994 }
03995 }
03996 operand0 = operands[0];
03997 operand1 = operands[1];
03998 operand2 = operands[2];
03999 operand3 = operands[3];
04000 emit_insn (gen_rtx_SET (VOIDmode,
04001 operand0,
04002 gen_rtx_MINUS (SImode,
04003 operand1,
04004 operand2)));
04005 emit_insn (gen_rtx_SET (VOIDmode,
04006 copy_rtx (operand0),
04007 gen_rtx_MINUS (SImode,
04008 copy_rtx (operand0),
04009 operand3)));
04010 _val = get_insns ();
04011 end_sequence ();
04012 return _val;
04013 }
04014
04015
04016 rtx
04017 gen_subdi3 (operand0, operand1, operand2)
04018 rtx operand0;
04019 rtx operand1;
04020 rtx operand2;
04021 {
04022 rtx operand3;
04023 rtx _val = 0;
04024 start_sequence ();
04025 {
04026 rtx operands[4];
04027 operands[0] = operand0;
04028 operands[1] = operand1;
04029 operands[2] = operand2;
04030
04031 {
04032 if (TARGET_64BIT)
04033 {
04034 emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
04035 operands[2]));
04036 DONE;
04037 }
04038
04039 operands[3] = gen_reg_rtx (SImode);
04040 }
04041 operand0 = operands[0];
04042 operand1 = operands[1];
04043 operand2 = operands[2];
04044 operand3 = operands[3];
04045 }
04046 emit (gen_rtx_PARALLEL (VOIDmode,
04047 gen_rtvec (2,
04048 gen_rtx_SET (VOIDmode,
04049 operand0,
04050 gen_rtx_MINUS (DImode,
04051 operand1,
04052 operand2)),
04053 gen_rtx_CLOBBER (VOIDmode,
04054 operand3))));
04055 _val = get_insns ();
04056 end_sequence ();
04057 return _val;
04058 }
04059
04060
04061 extern rtx gen_split_357 PARAMS ((rtx *));
04062 rtx
04063 gen_split_357 (operands)
04064 rtx *operands;
04065 {
04066 rtx operand0;
04067 rtx operand1;
04068 rtx operand2;
04069 rtx operand3;
04070 rtx _val = 0;
04071 start_sequence ();
04072
04073 operand0 = operands[0];
04074 operand1 = operands[1];
04075 operand2 = operands[2];
04076 operand3 = operands[3];
04077 emit_insn (gen_rtx_SET (VOIDmode,
04078 operand3,
04079 gen_rtx_LTU (SImode,
04080 gen_rtx_SUBREG (SImode,
04081 operand1,
04082 0),
04083 gen_rtx_SUBREG (SImode,
04084 operand2,
04085 0))));
04086 emit_insn (gen_rtx_SET (VOIDmode,
04087 gen_rtx_SUBREG (SImode,
04088 operand0,
04089 0),
04090 gen_rtx_MINUS (SImode,
04091 gen_rtx_SUBREG (SImode,
04092 copy_rtx (operand1),
04093 0),
04094 gen_rtx_SUBREG (SImode,
04095 copy_rtx (operand2),
04096 0))));
04097 emit_insn (gen_rtx_SET (VOIDmode,
04098 gen_rtx_SUBREG (SImode,
04099 copy_rtx (operand0),
04100 4),
04101 gen_rtx_MINUS (SImode,
04102 gen_rtx_SUBREG (SImode,
04103 copy_rtx (operand1),
04104 4),
04105 gen_rtx_SUBREG (SImode,
04106 copy_rtx (operand2),
04107 4))));
04108 emit_insn (gen_rtx_SET (VOIDmode,
04109 gen_rtx_SUBREG (SImode,
04110 copy_rtx (operand0),
04111 4),
04112 gen_rtx_MINUS (SImode,
04113 gen_rtx_SUBREG (SImode,
04114 copy_rtx (operand0),
04115 4),
04116 copy_rtx (operand3))));
04117 _val = get_insns ();
04118 end_sequence ();
04119 return _val;
04120 }
04121
04122
04123 extern rtx gen_split_358 PARAMS ((rtx *));
04124 rtx
04125 gen_split_358 (operands)
04126 rtx *operands;
04127 {
04128 rtx operand0;
04129 rtx operand1;
04130 rtx operand2;
04131 rtx operand3;
04132 rtx _val = 0;
04133 start_sequence ();
04134
04135 operand0 = operands[0];
04136 operand1 = operands[1];
04137 operand2 = operands[2];
04138 operand3 = operands[3];
04139 emit_insn (gen_rtx_SET (VOIDmode,
04140 operand3,
04141 gen_rtx_LTU (SImode,
04142 gen_rtx_SUBREG (SImode,
04143 operand1,
04144 4),
04145 gen_rtx_SUBREG (SImode,
04146 operand2,
04147 4))));
04148 emit_insn (gen_rtx_SET (VOIDmode,
04149 gen_rtx_SUBREG (SImode,
04150 operand0,
04151 4),
04152 gen_rtx_MINUS (SImode,
04153 gen_rtx_SUBREG (SImode,
04154 copy_rtx (operand1),
04155 4),
04156 gen_rtx_SUBREG (SImode,
04157 copy_rtx (operand2),
04158 4))));
04159 emit_insn (gen_rtx_SET (VOIDmode,
04160 gen_rtx_SUBREG (SImode,
04161 copy_rtx (operand0),
04162 0),
04163 gen_rtx_MINUS (SImode,
04164 gen_rtx_SUBREG (SImode,
04165 copy_rtx (operand1),
04166 0),
04167 gen_rtx_SUBREG (SImode,
04168 copy_rtx (operand2),
04169 0))));
04170 emit_insn (gen_rtx_SET (VOIDmode,
04171 gen_rtx_SUBREG (SImode,
04172 copy_rtx (operand0),
04173 0),
04174 gen_rtx_MINUS (SImode,
04175 gen_rtx_SUBREG (SImode,
04176 copy_rtx (operand0),
04177 0),
04178 copy_rtx (operand3))));
04179 _val = get_insns ();
04180 end_sequence ();
04181 return _val;
04182 }
04183
04184
04185 extern rtx gen_split_359 PARAMS ((rtx *));
04186 rtx
04187 gen_split_359 (operands)
04188 rtx *operands;
04189 {
04190 rtx operand0;
04191 rtx operand1;
04192 rtx operand2;
04193 rtx operand3;
04194 rtx _val = 0;
04195 start_sequence ();
04196
04197 operand0 = operands[0];
04198 operand1 = operands[1];
04199 operand2 = operands[2];
04200 operand3 = operands[3];
04201 emit_insn (gen_rtx_SET (VOIDmode,
04202 operand3,
04203 gen_rtx_LTU (SImode,
04204 gen_rtx_SUBREG (SImode,
04205 operand1,
04206 0),
04207 operand2)));
04208 emit_insn (gen_rtx_SET (VOIDmode,
04209 gen_rtx_SUBREG (SImode,
04210 operand0,
04211 0),
04212 gen_rtx_MINUS (SImode,
04213 gen_rtx_SUBREG (SImode,
04214 copy_rtx (operand1),
04215 0),
04216 copy_rtx (operand2))));
04217 emit_insn (gen_rtx_SET (VOIDmode,
04218 gen_rtx_SUBREG (SImode,
04219 copy_rtx (operand0),
04220 4),
04221 gen_rtx_MINUS (SImode,
04222 gen_rtx_SUBREG (SImode,
04223 copy_rtx (operand1),
04224 4),
04225 copy_rtx (operand3))));
04226 _val = get_insns ();
04227 end_sequence ();
04228 return _val;
04229 }
04230
04231
04232 extern rtx gen_split_360 PARAMS ((rtx *));
04233 rtx
04234 gen_split_360 (operands)
04235 rtx *operands;
04236 {
04237 rtx operand0;
04238 rtx operand1;
04239 rtx operand2;
04240 rtx operand3;
04241 rtx _val = 0;
04242 start_sequence ();
04243
04244 operand0 = operands[0];
04245 operand1 = operands[1];
04246 operand2 = operands[2];
04247 operand3 = operands[3];
04248 emit_insn (gen_rtx_SET (VOIDmode,
04249 operand3,
04250 gen_rtx_LTU (SImode,
04251 gen_rtx_SUBREG (SImode,
04252 operand1,
04253 4),
04254 operand2)));
04255 emit_insn (gen_rtx_SET (VOIDmode,
04256 gen_rtx_SUBREG (SImode,
04257 operand0,
04258 4),
04259 gen_rtx_MINUS (SImode,
04260 gen_rtx_SUBREG (SImode,
04261 copy_rtx (operand1),
04262 4),
04263 copy_rtx (operand2))));
04264 emit_insn (gen_rtx_SET (VOIDmode,
04265 gen_rtx_SUBREG (SImode,
04266 copy_rtx (operand0),
04267 0),
04268 gen_rtx_MINUS (SImode,
04269 gen_rtx_SUBREG (SImode,
04270 copy_rtx (operand1),
04271 0),
04272 copy_rtx (operand3))));
04273 _val = get_insns ();
04274 end_sequence ();
04275 return _val;
04276 }
04277
04278
04279 extern rtx gen_split_361 PARAMS ((rtx *));
04280 rtx
04281 gen_split_361 (operands)
04282 rtx *operands;
04283 {
04284 rtx operand0;
04285 rtx operand1;
04286 rtx operand2;
04287 rtx _val = 0;
04288 start_sequence ();
04289
04290 {
04291 HOST_WIDE_INT val = INTVAL (operands[1]);
04292
04293 if (val >= 0)
04294 {
04295 operands[1] = GEN_INT (0xf);
04296 operands[2] = GEN_INT (val - 0xf);
04297 }
04298 else
04299 {
04300 operands[1] = GEN_INT (- 0x10);
04301 operands[2] = GEN_INT (val + 0x10);
04302 }
04303 }
04304 operand0 = operands[0];
04305 operand1 = operands[1];
04306 operand2 = operands[2];
04307 emit_insn (gen_rtx_SET (VOIDmode,
04308 operand0,
04309 gen_rtx_MINUS (DImode,
04310 copy_rtx (operand0),
04311 operand1)));
04312 emit_insn (gen_rtx_SET (VOIDmode,
04313 copy_rtx (operand0),
04314 gen_rtx_MINUS (DImode,
04315 copy_rtx (operand0),
04316 operand2)));
04317 _val = get_insns ();
04318 end_sequence ();
04319 return _val;
04320 }
04321
04322
04323 extern rtx gen_split_362 PARAMS ((rtx *));
04324 rtx
04325 gen_split_362 (operands)
04326 rtx *operands;
04327 {
04328 rtx operand0;
04329 rtx operand1;
04330 rtx operand2;
04331 rtx operand3;
04332 rtx _val = 0;
04333 start_sequence ();
04334
04335 {
04336 HOST_WIDE_INT val = INTVAL (operands[2]);
04337
04338 if (val >= 0)
04339 {
04340 operands[2] = GEN_INT (0x8);
04341 operands[3] = GEN_INT (val - 0x8);
04342 }
04343 else
04344 {
04345 operands[2] = GEN_INT (- 0x7);
04346 operands[3] = GEN_INT (val + 0x7);
04347 }
04348 }
04349 operand0 = operands[0];
04350 operand1 = operands[1];
04351 operand2 = operands[2];
04352 operand3 = operands[3];
04353 emit_insn (gen_rtx_SET (VOIDmode,
04354 operand0,
04355 gen_rtx_MINUS (DImode,
04356 operand1,
04357 operand2)));
04358 emit_insn (gen_rtx_SET (VOIDmode,
04359 copy_rtx (operand0),
04360 gen_rtx_MINUS (DImode,
04361 copy_rtx (operand0),
04362 operand3)));
04363 _val = get_insns ();
04364 end_sequence ();
04365 return _val;
04366 }
04367
04368
04369 rtx
04370 gen_muldf3 (operand0, operand1, operand2)
04371 rtx operand0;
04372 rtx operand1;
04373 rtx operand2;
04374 {
04375 rtx _val = 0;
04376 start_sequence ();
04377 {
04378 rtx operands[3];
04379 operands[0] = operand0;
04380 operands[1] = operand1;
04381 operands[2] = operand2;
04382
04383 {
04384 if (!TARGET_MIPS4300)
04385 emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
04386 else
04387 emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
04388 DONE;
04389 }
04390 operand0 = operands[0];
04391 operand1 = operands[1];
04392 operand2 = operands[2];
04393 }
04394 emit_insn (gen_rtx_SET (VOIDmode,
04395 operand0,
04396 gen_rtx_MULT (DFmode,
04397 operand1,
04398 operand2)));
04399 _val = get_insns ();
04400 end_sequence ();
04401 return _val;
04402 }
04403
04404
04405 rtx
04406 gen_mulsf3 (operand0, operand1, operand2)
04407 rtx operand0;
04408 rtx operand1;
04409 rtx operand2;
04410 {
04411 rtx _val = 0;
04412 start_sequence ();
04413 {
04414 rtx operands[3];
04415 operands[0] = operand0;
04416 operands[1] = operand1;
04417 operands[2] = operand2;
04418
04419 {
04420 if (!TARGET_MIPS4300)
04421 emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
04422 else
04423 emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
04424 DONE;
04425 }
04426 operand0 = operands[0];
04427 operand1 = operands[1];
04428 operand2 = operands[2];
04429 }
04430 emit_insn (gen_rtx_SET (VOIDmode,
04431 operand0,
04432 gen_rtx_MULT (SFmode,
04433 operand1,
04434 operand2)));
04435 _val = get_insns ();
04436 end_sequence ();
04437 return _val;
04438 }
04439
04440
04441 rtx
04442 gen_mulsi3 (operand0, operand1, operand2)
04443 rtx operand0;
04444 rtx operand1;
04445 rtx operand2;
04446 {
04447 rtx operand3 ATTRIBUTE_UNUSED;
04448 rtx operand4 ATTRIBUTE_UNUSED;
04449 rtx _val = 0;
04450 start_sequence ();
04451 {
04452 rtx operands[5];
04453 operands[0] = operand0;
04454 operands[1] = operand1;
04455 operands[2] = operand2;
04456
04457 {
04458 if (GENERATE_MULT3_SI || TARGET_MAD)
04459 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
04460 else if (!TARGET_MIPS4000 || TARGET_MIPS16)
04461 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
04462 else
04463 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
04464 DONE;
04465 }
04466 operand0 = operands[0];
04467 operand1 = operands[1];
04468 operand2 = operands[2];
04469 operand3 = operands[3];
04470 operand4 = operands[4];
04471 }
04472 emit_insn (gen_rtx_SET (VOIDmode,
04473 operand0,
04474 gen_rtx_MULT (SImode,
04475 operand1,
04476 operand2)));
04477 emit_insn (gen_rtx_CLOBBER (VOIDmode,
04478 gen_rtx_SCRATCH (SImode)));
04479 emit_insn (gen_rtx_CLOBBER (VOIDmode,
04480 gen_rtx_SCRATCH (SImode)));
04481 _val = get_insns ();
04482 end_sequence ();
04483 return _val;
04484 }
04485
04486
04487 extern rtx gen_split_366 PARAMS ((rtx *));
04488 rtx
04489 gen_split_366 (operands)
04490 rtx *operands;
04491 {
04492 rtx operand0;
04493 rtx operand1;
04494 rtx operand2;
04495 rtx operand3;
04496 rtx operand4;
04497 rtx operand5;
04498 rtx operand6;
04499 rtx operand7;
04500 rtx _val = 0;
04501 start_sequence ();
04502
04503 operand0 = operands[0];
04504 operand1 = operands[1];
04505 operand2 = operands[2];
04506 operand3 = operands[3];
04507 operand4 = operands[4];
04508 operand5 = operands[5];
04509 operand6 = operands[6];
04510 operand7 = operands[7];
04511 emit (gen_rtx_PARALLEL (VOIDmode,
04512 gen_rtvec (4,
04513 gen_rtx_SET (VOIDmode,
04514 operand7,
04515 gen_rtx_MULT (SImode,
04516 operand1,
04517 operand2)),
04518 gen_rtx_CLOBBER (VOIDmode,
04519 operand4),
04520 gen_rtx_CLOBBER (VOIDmode,
04521 operand5),
04522 gen_rtx_CLOBBER (VOIDmode,
04523 operand6))));
04524 emit_insn (gen_rtx_SET (VOIDmode,
04525 operand0,
04526 gen_rtx_PLUS (SImode,
04527 copy_rtx (operand7),
04528 operand3)));
04529 _val = get_insns ();
04530 end_sequence ();
04531 return _val;
04532 }
04533
04534
04535 extern rtx gen_split_367 PARAMS ((rtx *));
04536 rtx
04537 gen_split_367 (operands)
04538 rtx *operands;
04539 {
04540 rtx operand0;
04541 rtx operand1;
04542 rtx operand2;
04543 rtx operand3;
04544 rtx operand4;
04545 rtx operand5;
04546 rtx operand6;
04547 rtx operand7;
04548 rtx _val = 0;
04549 start_sequence ();
04550
04551 operand0 = operands[0];
04552 operand1 = operands[1];
04553 operand2 = operands[2];
04554 operand3 = operands[3];
04555 operand4 = operands[4];
04556 operand5 = operands[5];
04557 operand6 = operands[6];
04558 operand7 = operands[7];
04559 emit (gen_rtx_PARALLEL (VOIDmode,
04560 gen_rtvec (5,
04561 gen_rtx_SET (VOIDmode,
04562 operand3,
04563 gen_rtx_PLUS (SImode,
04564 gen_rtx_MULT (SImode,
04565 operand1,
04566 operand2),
04567 copy_rtx (operand3))),
04568 gen_rtx_CLOBBER (VOIDmode,
04569 operand4),
04570 gen_rtx_CLOBBER (VOIDmode,
04571 operand5),
04572 gen_rtx_CLOBBER (VOIDmode,
04573 operand6),
04574 gen_rtx_CLOBBER (VOIDmode,
04575 operand7))));
04576 emit_insn (gen_rtx_SET (VOIDmode,
04577 operand0,
04578 copy_rtx (operand3)));
04579 _val = get_insns ();
04580 end_sequence ();
04581 return _val;
04582 }
04583
04584
04585 extern rtx gen_split_368 PARAMS ((rtx *));
04586 rtx
04587 gen_split_368 (operands)
04588 rtx *operands;
04589 {
04590 rtx operand0;
04591 rtx operand1;
04592 rtx operand2;
04593 rtx operand3;
04594 rtx operand4;
04595 rtx operand5;
04596 rtx operand6;
04597 rtx operand7;
04598 rtx _val = 0;
04599 start_sequence ();
04600
04601 operand0 = operands[0];
04602 operand1 = operands[1];
04603 operand2 = operands[2];
04604 operand3 = operands[3];
04605 operand4 = operands[4];
04606 operand5 = operands[5];
04607 operand6 = operands[6];
04608 operand7 = operands[7];
04609 emit (gen_rtx_PARALLEL (VOIDmode,
04610 gen_rtvec (4,
04611 gen_rtx_SET (VOIDmode,
04612 operand7,
04613 gen_rtx_MULT (SImode,
04614 operand2,
04615 operand3)),
04616 gen_rtx_CLOBBER (VOIDmode,
04617 operand4),
04618 gen_rtx_CLOBBER (VOIDmode,
04619 operand5),
04620 gen_rtx_CLOBBER (VOIDmode,
04621 operand6))));
04622 emit_insn (gen_rtx_SET (VOIDmode,
04623 operand0,
04624 gen_rtx_MINUS (SImode,
04625 operand1,
04626 copy_rtx (operand7))));
04627 _val = get_insns ();
04628 end_sequence ();
04629 return _val;
04630 }
04631
04632
04633 extern rtx gen_split_369 PARAMS ((rtx *));
04634 rtx
04635 gen_split_369 (operands)
04636 rtx *operands;
04637 {
04638 rtx operand0;
04639 rtx operand1;
04640 rtx operand2;
04641 rtx operand3;
04642 rtx operand4;
04643 rtx operand5;
04644 rtx operand6;
04645 rtx operand7;
04646 rtx _val = 0;
04647 start_sequence ();
04648
04649 operand0 = operands[0];
04650 operand1 = operands[1];
04651 operand2 = operands[2];
04652 operand3 = operands[3];
04653 operand4 = operands[4];
04654 operand5 = operands[5];
04655 operand6 = operands[6];
04656 operand7 = operands[7];
04657 emit (gen_rtx_PARALLEL (VOIDmode,
04658 gen_rtvec (5,
04659 gen_rtx_SET (VOIDmode,
04660 operand1,
04661 gen_rtx_MINUS (SImode,
04662 copy_rtx (operand1),
04663 gen_rtx_MULT (SImode,
04664 operand2,
04665 operand3))),
04666 gen_rtx_CLOBBER (VOIDmode,
04667 operand4),
04668 gen_rtx_CLOBBER (VOIDmode,
04669 operand5),
04670 gen_rtx_CLOBBER (VOIDmode,
04671 operand6),
04672 gen_rtx_CLOBBER (VOIDmode,
04673 operand7))));
04674 emit_insn (gen_rtx_SET (VOIDmode,
04675 operand0,
04676 copy_rtx (operand1)));
04677 _val = get_insns ();
04678 end_sequence ();
04679 return _val;
04680 }
04681
04682
04683 extern rtx gen_split_370 PARAMS ((rtx *));
04684 rtx
04685 gen_split_370 (operands)
04686 rtx *operands;
04687 {
04688 rtx operand0;
04689 rtx operand1;
04690 rtx operand2;
04691 rtx operand3;
04692 rtx operand4;
04693 rtx operand5;
04694 rtx operand6;
04695 rtx operand7;
04696 rtx _val = 0;
04697 start_sequence ();
04698
04699 operand0 = operands[0];
04700 operand1 = operands[1];
04701 operand2 = operands[2];
04702 operand3 = operands[3];
04703 operand4 = operands[4];
04704 operand5 = operands[5];
04705 operand6 = operands[6];
04706 operand7 = operands[7];
04707 emit (gen_rtx_PARALLEL (VOIDmode,
04708 gen_rtvec (4,
04709 gen_rtx_SET (VOIDmode,
04710 operand7,
04711 gen_rtx_MULT (SImode,
04712 operand2,
04713 operand3)),
04714 gen_rtx_CLOBBER (VOIDmode,
04715 operand4),
04716 gen_rtx_CLOBBER (VOIDmode,
04717 operand5),
04718 gen_rtx_CLOBBER (VOIDmode,
04719 operand6))));
04720 emit_insn (gen_rtx_SET (VOIDmode,
04721 operand0,
04722 gen_rtx_MINUS (SImode,
04723 operand1,
04724 copy_rtx (operand7))));
04725 _val = get_insns ();
04726 end_sequence ();
04727 return _val;
04728 }
04729
04730
04731 rtx
04732 gen_muldi3 (operand0, operand1, operand2)
04733 rtx operand0;
04734 rtx operand1;
04735 rtx operand2;
04736 {
04737 rtx operand3 ATTRIBUTE_UNUSED;
04738 rtx operand4 ATTRIBUTE_UNUSED;
04739 rtx _val = 0;
04740 start_sequence ();
04741 {
04742 rtx operands[5];
04743 operands[0] = operand0;
04744 operands[1] = operand1;
04745 operands[2] = operand2;
04746
04747 {
04748 if (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)
04749 emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
04750 else
04751 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
04752 DONE;
04753 }
04754 operand0 = operands[0];
04755 operand1 = operands[1];
04756 operand2 = operands[2];
04757 operand3 = operands[3];
04758 operand4 = operands[4];
04759 }
04760 emit_insn (gen_rtx_SET (VOIDmode,
04761 operand0,
04762 gen_rtx_MULT (DImode,
04763 operand1,
04764 operand2)));
04765 emit_insn (gen_rtx_CLOBBER (VOIDmode,
04766 gen_rtx_SCRATCH (DImode)));
04767 emit_insn (gen_rtx_CLOBBER (VOIDmode,
04768 gen_rtx_SCRATCH (DImode)));
04769 _val = get_insns ();
04770 end_sequence ();
04771 return _val;
04772 }
04773
04774
04775 rtx
04776 gen_mulsidi3 (operand0, operand1, operand2)
04777 rtx operand0;
04778 rtx operand1;
04779 rtx operand2;
04780 {
04781 rtx _val = 0;
04782 start_sequence ();
04783 {
04784 rtx operands[3];
04785 operands[0] = operand0;
04786 operands[1] = operand1;
04787 operands[2] = operand2;
04788
04789 {
04790 rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
04791 if (TARGET_64BIT)
04792 emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
04793 dummy, dummy));
04794 else
04795 emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
04796 dummy, dummy));
04797 DONE;
04798 }
04799 operand0 = operands[0];
04800 operand1 = operands[1];
04801 operand2 = operands[2];
04802 }
04803 emit_insn (gen_rtx_SET (VOIDmode,
04804 operand0,
04805 gen_rtx_MULT (DImode,
04806 gen_rtx_SIGN_EXTEND (DImode,
04807 operand1),
04808 gen_rtx_SIGN_EXTEND (DImode,
04809 operand2))));
04810 _val = get_insns ();
04811 end_sequence ();
04812 return _val;
04813 }
04814
04815
04816 rtx
04817 gen_umulsidi3 (operand0, operand1, operand2)
04818 rtx operand0;
04819 rtx operand1;
04820 rtx operand2;
04821 {
04822 rtx _val = 0;
04823 start_sequence ();
04824 {
04825 rtx operands[3];
04826 operands[0] = operand0;
04827 operands[1] = operand1;
04828 operands[2] = operand2;
04829
04830 {
04831 rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
04832 if (TARGET_64BIT)
04833 emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
04834 dummy, dummy));
04835 else
04836 emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
04837 dummy, dummy));
04838 DONE;
04839 }
04840 operand0 = operands[0];
04841 operand1 = operands[1];
04842 operand2 = operands[2];
04843 }
04844 emit_insn (gen_rtx_SET (VOIDmode,
04845 operand0,
04846 gen_rtx_MULT (DImode,
04847 gen_rtx_ZERO_EXTEND (DImode,
04848 operand1),
04849 gen_rtx_ZERO_EXTEND (DImode,
04850 operand2))));
04851 _val = get_insns ();
04852 end_sequence ();
04853 return _val;
04854 }
04855
04856
04857 rtx
04858 gen_smulsi3_highpart (operand0, operand1, operand2)
04859 rtx operand0;
04860 rtx operand1;
04861 rtx operand2;
04862 {
04863 rtx _val = 0;
04864 start_sequence ();
04865 {
04866 rtx operands[3];
04867 operands[0] = operand0;
04868 operands[1] = operand1;
04869 operands[2] = operand2;
04870
04871 {
04872 rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
04873 rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
04874 #ifndef NO_MD_PROTOTYPES
04875 rtx (*genfn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
04876 #else
04877 rtx (*genfn) ();
04878 #endif
04879 if (ISA_HAS_MULHI && TARGET_64BIT)
04880 genfn = gen_xmulsi3_highpart_mulhi;
04881 else
04882 genfn = gen_xmulsi3_highpart_internal;
04883 emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
04884 dummy, dummy2));
04885 DONE;
04886 }
04887 operand0 = operands[0];
04888 operand1 = operands[1];
04889 operand2 = operands[2];
04890 }
04891 emit_insn (gen_rtx_SET (VOIDmode,
04892 operand0,
04893 gen_rtx_TRUNCATE (SImode,
04894 gen_rtx_LSHIFTRT (DImode,
04895 gen_rtx_MULT (DImode,
04896 gen_rtx_SIGN_EXTEND (DImode,
04897 operand1),
04898 gen_rtx_SIGN_EXTEND (DImode,
04899 operand2)),
04900 GEN_INT (32LL)))));
04901 _val = get_insns ();
04902 end_sequence ();
04903 return _val;
04904 }
04905
04906
04907 rtx
04908 gen_umulsi3_highpart (operand0, operand1, operand2)
04909 rtx operand0;
04910 rtx operand1;
04911 rtx operand2;
04912 {
04913 rtx _val = 0;
04914 start_sequence ();
04915 {
04916 rtx operands[3];
04917 operands[0] = operand0;
04918 operands[1] = operand1;
04919 operands[2] = operand2;
04920
04921 {
04922 rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
04923 rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
04924 #ifndef NO_MD_PROTOTYPES
04925 rtx (*genfn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
04926 #else
04927 rtx (*genfn) ();
04928 #endif
04929 if (ISA_HAS_MULHI && TARGET_64BIT)
04930 genfn = gen_xmulsi3_highpart_mulhi;
04931 else
04932 genfn = gen_xmulsi3_highpart_internal;
04933 emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
04934 dummy, dummy2));
04935 DONE;
04936 }
04937 operand0 = operands[0];
04938 operand1 = operands[1];
04939 operand2 = operands[2];
04940 }
04941 emit_insn (gen_rtx_SET (VOIDmode,
04942 operand0,
04943 gen_rtx_TRUNCATE (SImode,
04944 gen_rtx_LSHIFTRT (DImode,
04945 gen_rtx_MULT (DImode,
04946 gen_rtx_ZERO_EXTEND (DImode,
04947 operand1),
04948 gen_rtx_ZERO_EXTEND (DImode,
04949 operand2)),
04950 GEN_INT (32LL)))));
04951 _val = get_insns ();
04952 end_sequence ();
04953 return _val;
04954 }
04955
04956
04957 rtx
04958 gen_divmodsi4 (operand0, operand1, operand2, operand3)
04959 rtx operand0;
04960 rtx operand1;
04961 rtx operand2;
04962 rtx operand3;
04963 {
04964 rtx operand4 ATTRIBUTE_UNUSED;
04965 rtx operand5 ATTRIBUTE_UNUSED;
04966 rtx operand6 ATTRIBUTE_UNUSED;
04967 rtx _val = 0;
04968 start_sequence ();
04969 {
04970 rtx operands[7];
04971 operands[0] = operand0;
04972 operands[1] = operand1;
04973 operands[2] = operand2;
04974 operands[3] = operand3;
04975
04976 {
04977 emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2],
04978 operands[3]));
04979 if (!TARGET_NO_CHECK_ZERO_DIV)
04980 {
04981 emit_insn (gen_div_trap (operands[2],
04982 GEN_INT (0),
04983 GEN_INT (0x7)));
04984 }
04985 if (TARGET_CHECK_RANGE_DIV)
04986 {
04987 emit_insn (gen_div_trap (operands[2],
04988 copy_to_mode_reg (SImode, GEN_INT (-1)),
04989 GEN_INT (0x6)));
04990 emit_insn (gen_div_trap (operands[2],
04991 copy_to_mode_reg (SImode,
04992 GEN_INT
04993 (trunc_int_for_mode
04994 (BITMASK_HIGH, SImode))),
04995 GEN_INT (0x6)));
04996 }
04997
04998 DONE;
04999 }
05000 operand0 = operands[0];
05001 operand1 = operands[1];
05002 operand2 = operands[2];
05003 operand3 = operands[3];
05004 operand4 = operands[4];
05005 operand5 = operands[5];
05006 operand6 = operands[6];
05007 }
05008 emit_insn (gen_rtx_SET (VOIDmode,
05009 operand0,
05010 gen_rtx_DIV (SImode,
05011 operand1,
05012 operand2)));
05013 emit_insn (gen_rtx_SET (VOIDmode,
05014 operand3,
05015 gen_rtx_MOD (SImode,
05016 operand1,
05017 operand2)));
05018 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05019 gen_rtx_SCRATCH (SImode)));
05020 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05021 gen_rtx_SCRATCH (SImode)));
05022 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05023 gen_rtx_SCRATCH (SImode)));
05024 _val = get_insns ();
05025 end_sequence ();
05026 return _val;
05027 }
05028
05029
05030 rtx
05031 gen_divmoddi4 (operand0, operand1, operand2, operand3)
05032 rtx operand0;
05033 rtx operand1;
05034 rtx operand2;
05035 rtx operand3;
05036 {
05037 rtx operand4 ATTRIBUTE_UNUSED;
05038 rtx operand5 ATTRIBUTE_UNUSED;
05039 rtx operand6 ATTRIBUTE_UNUSED;
05040 rtx _val = 0;
05041 start_sequence ();
05042 {
05043 rtx operands[7];
05044 operands[0] = operand0;
05045 operands[1] = operand1;
05046 operands[2] = operand2;
05047 operands[3] = operand3;
05048
05049 {
05050 emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2],
05051 operands[3]));
05052 if (!TARGET_NO_CHECK_ZERO_DIV)
05053 {
05054 emit_insn (gen_div_trap (operands[2],
05055 GEN_INT (0),
05056 GEN_INT (0x7)));
05057 }
05058 if (TARGET_CHECK_RANGE_DIV)
05059 {
05060 emit_insn (gen_div_trap (operands[2],
05061 copy_to_mode_reg (DImode, GEN_INT (-1)),
05062 GEN_INT (0x6)));
05063 emit_insn (gen_div_trap (operands[2],
05064 copy_to_mode_reg (DImode,
05065 GEN_INT (BITMASK_HIGH)),
05066 GEN_INT (0x6)));
05067 }
05068
05069 DONE;
05070 }
05071 operand0 = operands[0];
05072 operand1 = operands[1];
05073 operand2 = operands[2];
05074 operand3 = operands[3];
05075 operand4 = operands[4];
05076 operand5 = operands[5];
05077 operand6 = operands[6];
05078 }
05079 emit_insn (gen_rtx_SET (VOIDmode,
05080 operand0,
05081 gen_rtx_DIV (DImode,
05082 operand1,
05083 operand2)));
05084 emit_insn (gen_rtx_SET (VOIDmode,
05085 operand3,
05086 gen_rtx_MOD (DImode,
05087 operand1,
05088 operand2)));
05089 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05090 gen_rtx_SCRATCH (DImode)));
05091 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05092 gen_rtx_SCRATCH (DImode)));
05093 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05094 gen_rtx_SCRATCH (DImode)));
05095 _val = get_insns ();
05096 end_sequence ();
05097 return _val;
05098 }
05099
05100
05101 rtx
05102 gen_udivmodsi4 (operand0, operand1, operand2, operand3)
05103 rtx operand0;
05104 rtx operand1;
05105 rtx operand2;
05106 rtx operand3;
05107 {
05108 rtx operand4 ATTRIBUTE_UNUSED;
05109 rtx operand5 ATTRIBUTE_UNUSED;
05110 rtx operand6 ATTRIBUTE_UNUSED;
05111 rtx _val = 0;
05112 start_sequence ();
05113 {
05114 rtx operands[7];
05115 operands[0] = operand0;
05116 operands[1] = operand1;
05117 operands[2] = operand2;
05118 operands[3] = operand3;
05119
05120 {
05121 emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2],
05122 operands[3]));
05123 if (!TARGET_NO_CHECK_ZERO_DIV)
05124 {
05125 emit_insn (gen_div_trap (operands[2],
05126 GEN_INT (0),
05127 GEN_INT (0x7)));
05128 }
05129
05130 DONE;
05131 }
05132 operand0 = operands[0];
05133 operand1 = operands[1];
05134 operand2 = operands[2];
05135 operand3 = operands[3];
05136 operand4 = operands[4];
05137 operand5 = operands[5];
05138 operand6 = operands[6];
05139 }
05140 emit_insn (gen_rtx_SET (VOIDmode,
05141 operand0,
05142 gen_rtx_UDIV (SImode,
05143 operand1,
05144 operand2)));
05145 emit_insn (gen_rtx_SET (VOIDmode,
05146 operand3,
05147 gen_rtx_UMOD (SImode,
05148 operand1,
05149 operand2)));
05150 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05151 gen_rtx_SCRATCH (SImode)));
05152 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05153 gen_rtx_SCRATCH (SImode)));
05154 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05155 gen_rtx_SCRATCH (SImode)));
05156 _val = get_insns ();
05157 end_sequence ();
05158 return _val;
05159 }
05160
05161
05162 rtx
05163 gen_udivmoddi4 (operand0, operand1, operand2, operand3)
05164 rtx operand0;
05165 rtx operand1;
05166 rtx operand2;
05167 rtx operand3;
05168 {
05169 rtx operand4 ATTRIBUTE_UNUSED;
05170 rtx operand5 ATTRIBUTE_UNUSED;
05171 rtx operand6 ATTRIBUTE_UNUSED;
05172 rtx _val = 0;
05173 start_sequence ();
05174 {
05175 rtx operands[7];
05176 operands[0] = operand0;
05177 operands[1] = operand1;
05178 operands[2] = operand2;
05179 operands[3] = operand3;
05180
05181 {
05182 emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2],
05183 operands[3]));
05184 if (!TARGET_NO_CHECK_ZERO_DIV)
05185 {
05186 emit_insn (gen_div_trap (operands[2],
05187 GEN_INT (0),
05188 GEN_INT (0x7)));
05189 }
05190
05191 DONE;
05192 }
05193 operand0 = operands[0];
05194 operand1 = operands[1];
05195 operand2 = operands[2];
05196 operand3 = operands[3];
05197 operand4 = operands[4];
05198 operand5 = operands[5];
05199 operand6 = operands[6];
05200 }
05201 emit_insn (gen_rtx_SET (VOIDmode,
05202 operand0,
05203 gen_rtx_UDIV (DImode,
05204 operand1,
05205 operand2)));
05206 emit_insn (gen_rtx_SET (VOIDmode,
05207 operand3,
05208 gen_rtx_UMOD (DImode,
05209 operand1,
05210 operand2)));
05211 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05212 gen_rtx_SCRATCH (DImode)));
05213 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05214 gen_rtx_SCRATCH (DImode)));
05215 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05216 gen_rtx_SCRATCH (DImode)));
05217 _val = get_insns ();
05218 end_sequence ();
05219 return _val;
05220 }
05221
05222
05223 rtx
05224 gen_div_trap (operand0, operand1, operand2)
05225 rtx operand0;
05226 rtx operand1;
05227 rtx operand2;
05228 {
05229 rtx _val = 0;
05230 start_sequence ();
05231 {
05232 rtx operands[3];
05233 operands[0] = operand0;
05234 operands[1] = operand1;
05235 operands[2] = operand2;
05236
05237 {
05238 if (TARGET_MIPS16)
05239 emit_insn (gen_div_trap_mips16 (operands[0],operands[1],operands[2]));
05240 else
05241 emit_insn (gen_div_trap_normal (operands[0],operands[1],operands[2]));
05242 DONE;
05243 }
05244 operand0 = operands[0];
05245 operand1 = operands[1];
05246 operand2 = operands[2];
05247 }
05248 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
05249 gen_rtx_EQ (VOIDmode,
05250 operand0,
05251 operand1),
05252 operand2));
05253 _val = get_insns ();
05254 end_sequence ();
05255 return _val;
05256 }
05257
05258
05259 rtx
05260 gen_divsi3 (operand0, operand1, operand2)
05261 rtx operand0;
05262 rtx operand1;
05263 rtx operand2;
05264 {
05265 rtx operand3 ATTRIBUTE_UNUSED;
05266 rtx operand4 ATTRIBUTE_UNUSED;
05267 rtx _val = 0;
05268 start_sequence ();
05269 {
05270 rtx operands[5];
05271 operands[0] = operand0;
05272 operands[1] = operand1;
05273 operands[2] = operand2;
05274
05275 {
05276 emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2]));
05277 if (!TARGET_NO_CHECK_ZERO_DIV)
05278 {
05279 emit_insn (gen_div_trap (operands[2],
05280 GEN_INT (0),
05281 GEN_INT (0x7)));
05282 }
05283 if (TARGET_CHECK_RANGE_DIV)
05284 {
05285 emit_insn (gen_div_trap (operands[2],
05286 copy_to_mode_reg (SImode, GEN_INT (-1)),
05287 GEN_INT (0x6)));
05288 emit_insn (gen_div_trap (operands[2],
05289 copy_to_mode_reg (SImode,
05290 GEN_INT
05291 (trunc_int_for_mode
05292 (BITMASK_HIGH, SImode))),
05293 GEN_INT (0x6)));
05294 }
05295
05296 DONE;
05297 }
05298 operand0 = operands[0];
05299 operand1 = operands[1];
05300 operand2 = operands[2];
05301 operand3 = operands[3];
05302 operand4 = operands[4];
05303 }
05304 emit_insn (gen_rtx_SET (VOIDmode,
05305 operand0,
05306 gen_rtx_DIV (SImode,
05307 operand1,
05308 operand2)));
05309 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05310 gen_rtx_SCRATCH (SImode)));
05311 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05312 gen_rtx_SCRATCH (SImode)));
05313 _val = get_insns ();
05314 end_sequence ();
05315 return _val;
05316 }
05317
05318
05319 rtx
05320 gen_divdi3 (operand0, operand1, operand2)
05321 rtx operand0;
05322 rtx operand1;
05323 rtx operand2;
05324 {
05325 rtx operand3 ATTRIBUTE_UNUSED;
05326 rtx operand4 ATTRIBUTE_UNUSED;
05327 rtx _val = 0;
05328 start_sequence ();
05329 {
05330 rtx operands[5];
05331 operands[0] = operand0;
05332 operands[1] = operand1;
05333 operands[2] = operand2;
05334
05335 {
05336 emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2]));
05337 if (!TARGET_NO_CHECK_ZERO_DIV)
05338 {
05339 emit_insn (gen_div_trap (operands[2],
05340 GEN_INT (0),
05341 GEN_INT (0x7)));
05342 }
05343 if (TARGET_CHECK_RANGE_DIV)
05344 {
05345 emit_insn (gen_div_trap (operands[2],
05346 copy_to_mode_reg (DImode, GEN_INT (-1)),
05347 GEN_INT (0x6)));
05348 emit_insn (gen_div_trap (operands[2],
05349 copy_to_mode_reg (DImode,
05350 GEN_INT (BITMASK_HIGH)),
05351 GEN_INT (0x6)));
05352 }
05353
05354 DONE;
05355 }
05356 operand0 = operands[0];
05357 operand1 = operands[1];
05358 operand2 = operands[2];
05359 operand3 = operands[3];
05360 operand4 = operands[4];
05361 }
05362 emit_insn (gen_rtx_SET (VOIDmode,
05363 operand0,
05364 gen_rtx_DIV (DImode,
05365 operand1,
05366 operand2)));
05367 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05368 gen_rtx_SCRATCH (DImode)));
05369 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05370 gen_rtx_SCRATCH (DImode)));
05371 _val = get_insns ();
05372 end_sequence ();
05373 return _val;
05374 }
05375
05376
05377 rtx
05378 gen_modsi3 (operand0, operand1, operand2)
05379 rtx operand0;
05380 rtx operand1;
05381 rtx operand2;
05382 {
05383 rtx operand3 ATTRIBUTE_UNUSED;
05384 rtx operand4 ATTRIBUTE_UNUSED;
05385 rtx _val = 0;
05386 start_sequence ();
05387 {
05388 rtx operands[5];
05389 operands[0] = operand0;
05390 operands[1] = operand1;
05391 operands[2] = operand2;
05392
05393 {
05394 emit_insn (gen_modsi3_internal (operands[0], operands[1], operands[2]));
05395 if (!TARGET_NO_CHECK_ZERO_DIV)
05396 {
05397 emit_insn (gen_div_trap (operands[2],
05398 GEN_INT (0),
05399 GEN_INT (0x7)));
05400 }
05401 if (TARGET_CHECK_RANGE_DIV)
05402 {
05403 emit_insn (gen_div_trap (operands[2],
05404 copy_to_mode_reg (SImode, GEN_INT (-1)),
05405 GEN_INT (0x6)));
05406 emit_insn (gen_div_trap (operands[2],
05407 copy_to_mode_reg (SImode,
05408 GEN_INT
05409 (trunc_int_for_mode
05410 (BITMASK_HIGH, SImode))),
05411 GEN_INT (0x6)));
05412 }
05413
05414 DONE;
05415 }
05416 operand0 = operands[0];
05417 operand1 = operands[1];
05418 operand2 = operands[2];
05419 operand3 = operands[3];
05420 operand4 = operands[4];
05421 }
05422 emit_insn (gen_rtx_SET (VOIDmode,
05423 operand0,
05424 gen_rtx_MOD (SImode,
05425 operand1,
05426 operand2)));
05427 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05428 gen_rtx_SCRATCH (SImode)));
05429 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05430 gen_rtx_SCRATCH (SImode)));
05431 _val = get_insns ();
05432 end_sequence ();
05433 return _val;
05434 }
05435
05436
05437 rtx
05438 gen_moddi3 (operand0, operand1, operand2)
05439 rtx operand0;
05440 rtx operand1;
05441 rtx operand2;
05442 {
05443 rtx operand3 ATTRIBUTE_UNUSED;
05444 rtx operand4 ATTRIBUTE_UNUSED;
05445 rtx _val = 0;
05446 start_sequence ();
05447 {
05448 rtx operands[5];
05449 operands[0] = operand0;
05450 operands[1] = operand1;
05451 operands[2] = operand2;
05452
05453 {
05454 emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2]));
05455 if (!TARGET_NO_CHECK_ZERO_DIV)
05456 {
05457 emit_insn (gen_div_trap (operands[2],
05458 GEN_INT (0),
05459 GEN_INT (0x7)));
05460 }
05461 if (TARGET_CHECK_RANGE_DIV)
05462 {
05463 emit_insn (gen_div_trap (operands[2],
05464 copy_to_mode_reg (DImode, GEN_INT (-1)),
05465 GEN_INT (0x6)));
05466 emit_insn (gen_div_trap (operands[2],
05467 copy_to_mode_reg (DImode,
05468 GEN_INT (BITMASK_HIGH)),
05469 GEN_INT (0x6)));
05470 }
05471
05472 DONE;
05473 }
05474 operand0 = operands[0];
05475 operand1 = operands[1];
05476 operand2 = operands[2];
05477 operand3 = operands[3];
05478 operand4 = operands[4];
05479 }
05480 emit_insn (gen_rtx_SET (VOIDmode,
05481 operand0,
05482 gen_rtx_MOD (DImode,
05483 operand1,
05484 operand2)));
05485 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05486 gen_rtx_SCRATCH (DImode)));
05487 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05488 gen_rtx_SCRATCH (DImode)));
05489 _val = get_insns ();
05490 end_sequence ();
05491 return _val;
05492 }
05493
05494
05495 rtx
05496 gen_udivsi3 (operand0, operand1, operand2)
05497 rtx operand0;
05498 rtx operand1;
05499 rtx operand2;
05500 {
05501 rtx operand3 ATTRIBUTE_UNUSED;
05502 rtx operand4 ATTRIBUTE_UNUSED;
05503 rtx _val = 0;
05504 start_sequence ();
05505 {
05506 rtx operands[5];
05507 operands[0] = operand0;
05508 operands[1] = operand1;
05509 operands[2] = operand2;
05510
05511 {
05512 emit_insn (gen_udivsi3_internal (operands[0], operands[1], operands[2]));
05513 if (!TARGET_NO_CHECK_ZERO_DIV)
05514 {
05515 emit_insn (gen_div_trap (operands[2],
05516 GEN_INT (0),
05517 GEN_INT (0x7)));
05518 }
05519
05520 DONE;
05521 }
05522 operand0 = operands[0];
05523 operand1 = operands[1];
05524 operand2 = operands[2];
05525 operand3 = operands[3];
05526 operand4 = operands[4];
05527 }
05528 emit_insn (gen_rtx_SET (VOIDmode,
05529 operand0,
05530 gen_rtx_UDIV (SImode,
05531 operand1,
05532 operand2)));
05533 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05534 gen_rtx_SCRATCH (SImode)));
05535 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05536 gen_rtx_SCRATCH (SImode)));
05537 _val = get_insns ();
05538 end_sequence ();
05539 return _val;
05540 }
05541
05542
05543 rtx
05544 gen_udivdi3 (operand0, operand1, operand2)
05545 rtx operand0;
05546 rtx operand1;
05547 rtx operand2;
05548 {
05549 rtx operand3 ATTRIBUTE_UNUSED;
05550 rtx operand4 ATTRIBUTE_UNUSED;
05551 rtx _val = 0;
05552 start_sequence ();
05553 {
05554 rtx operands[5];
05555 operands[0] = operand0;
05556 operands[1] = operand1;
05557 operands[2] = operand2;
05558
05559 {
05560 emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2]));
05561 if (!TARGET_NO_CHECK_ZERO_DIV)
05562 {
05563 emit_insn (gen_div_trap (operands[2],
05564 GEN_INT (0),
05565 GEN_INT (0x7)));
05566 }
05567
05568 DONE;
05569 }
05570 operand0 = operands[0];
05571 operand1 = operands[1];
05572 operand2 = operands[2];
05573 operand3 = operands[3];
05574 operand4 = operands[4];
05575 }
05576 emit_insn (gen_rtx_SET (VOIDmode,
05577 operand0,
05578 gen_rtx_UDIV (DImode,
05579 operand1,
05580 operand2)));
05581 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05582 gen_rtx_SCRATCH (DImode)));
05583 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05584 gen_rtx_SCRATCH (DImode)));
05585 _val = get_insns ();
05586 end_sequence ();
05587 return _val;
05588 }
05589
05590
05591 rtx
05592 gen_umodsi3 (operand0, operand1, operand2)
05593 rtx operand0;
05594 rtx operand1;
05595 rtx operand2;
05596 {
05597 rtx operand3 ATTRIBUTE_UNUSED;
05598 rtx operand4 ATTRIBUTE_UNUSED;
05599 rtx _val = 0;
05600 start_sequence ();
05601 {
05602 rtx operands[5];
05603 operands[0] = operand0;
05604 operands[1] = operand1;
05605 operands[2] = operand2;
05606
05607 {
05608 emit_insn (gen_umodsi3_internal (operands[0], operands[1], operands[2]));
05609 if (!TARGET_NO_CHECK_ZERO_DIV)
05610 {
05611 emit_insn (gen_div_trap (operands[2],
05612 GEN_INT (0),
05613 GEN_INT (0x7)));
05614 }
05615
05616 DONE;
05617 }
05618 operand0 = operands[0];
05619 operand1 = operands[1];
05620 operand2 = operands[2];
05621 operand3 = operands[3];
05622 operand4 = operands[4];
05623 }
05624 emit_insn (gen_rtx_SET (VOIDmode,
05625 operand0,
05626 gen_rtx_UMOD (SImode,
05627 operand1,
05628 operand2)));
05629 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05630 gen_rtx_SCRATCH (SImode)));
05631 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05632 gen_rtx_SCRATCH (SImode)));
05633 _val = get_insns ();
05634 end_sequence ();
05635 return _val;
05636 }
05637
05638
05639 rtx
05640 gen_umoddi3 (operand0, operand1, operand2)
05641 rtx operand0;
05642 rtx operand1;
05643 rtx operand2;
05644 {
05645 rtx operand3 ATTRIBUTE_UNUSED;
05646 rtx operand4 ATTRIBUTE_UNUSED;
05647 rtx _val = 0;
05648 start_sequence ();
05649 {
05650 rtx operands[5];
05651 operands[0] = operand0;
05652 operands[1] = operand1;
05653 operands[2] = operand2;
05654
05655 {
05656 emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2]));
05657 if (!TARGET_NO_CHECK_ZERO_DIV)
05658 {
05659 emit_insn (gen_div_trap (operands[2],
05660 GEN_INT (0),
05661 GEN_INT (0x7)));
05662 }
05663
05664 DONE;
05665 }
05666 operand0 = operands[0];
05667 operand1 = operands[1];
05668 operand2 = operands[2];
05669 operand3 = operands[3];
05670 operand4 = operands[4];
05671 }
05672 emit_insn (gen_rtx_SET (VOIDmode,
05673 operand0,
05674 gen_rtx_UMOD (DImode,
05675 operand1,
05676 operand2)));
05677 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05678 gen_rtx_SCRATCH (DImode)));
05679 emit_insn (gen_rtx_CLOBBER (VOIDmode,
05680 gen_rtx_SCRATCH (DImode)));
05681 _val = get_insns ();
05682 end_sequence ();
05683 return _val;
05684 }
05685
05686
05687 rtx
05688 gen_negdi2 (operand0, operand1)
05689 rtx operand0;
05690 rtx operand1;
05691 {
05692 rtx operand2;
05693 rtx _val = 0;
05694 start_sequence ();
05695 {
05696 rtx operands[3];
05697 operands[0] = operand0;
05698 operands[1] = operand1;
05699
05700 {
05701 if (TARGET_64BIT)
05702 {
05703 emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
05704 DONE;
05705 }
05706
05707 operands[2] = gen_reg_rtx (SImode);
05708 }
05709 operand0 = operands[0];
05710 operand1 = operands[1];
05711 operand2 = operands[2];
05712 }
05713 emit (gen_rtx_PARALLEL (VOIDmode,
05714 gen_rtvec (2,
05715 gen_rtx_SET (VOIDmode,
05716 operand0,
05717 gen_rtx_NEG (DImode,
05718 operand1)),
05719 gen_rtx_CLOBBER (VOIDmode,
05720 operand2))));
05721 _val = get_insns ();
05722 end_sequence ();
05723 return _val;
05724 }
05725
05726
05727 extern rtx gen_split_390 PARAMS ((rtx *));
05728 rtx
05729 gen_split_390 (operands)
05730 rtx *operands;
05731 {
05732 rtx operand0;
05733 rtx operand1;
05734 rtx _val = 0;
05735 start_sequence ();
05736
05737 operand0 = operands[0];
05738 operand1 = operands[1];
05739 emit_insn (gen_rtx_SET (VOIDmode,
05740 gen_rtx_SUBREG (SImode,
05741 operand0,
05742 0),
05743 gen_rtx_NOT (SImode,
05744 gen_rtx_SUBREG (SImode,
05745 operand1,
05746 0))));
05747 emit_insn (gen_rtx_SET (VOIDmode,
05748 gen_rtx_SUBREG (SImode,
05749 copy_rtx (operand0),
05750 4),
05751 gen_rtx_NOT (SImode,
05752 gen_rtx_SUBREG (SImode,
05753 copy_rtx (operand1),
05754 4))));
05755 _val = get_insns ();
05756 end_sequence ();
05757 return _val;
05758 }
05759
05760
05761 rtx
05762 gen_andsi3 (operand0, operand1, operand2)
05763 rtx operand0;
05764 rtx operand1;
05765 rtx operand2;
05766 {
05767 rtx _val = 0;
05768 start_sequence ();
05769 {
05770 rtx operands[3];
05771 operands[0] = operand0;
05772 operands[1] = operand1;
05773 operands[2] = operand2;
05774
05775 {
05776 if (TARGET_MIPS16)
05777 {
05778 operands[1] = force_reg (SImode, operands[1]);
05779 operands[2] = force_reg (SImode, operands[2]);
05780 }
05781 }
05782 operand0 = operands[0];
05783 operand1 = operands[1];
05784 operand2 = operands[2];
05785 }
05786 emit_insn (gen_rtx_SET (VOIDmode,
05787 operand0,
05788 gen_rtx_AND (SImode,
05789 operand1,
05790 operand2)));
05791 _val = get_insns ();
05792 end_sequence ();
05793 return _val;
05794 }
05795
05796
05797 rtx
05798 gen_anddi3 (operand0, operand1, operand2)
05799 rtx operand0;
05800 rtx operand1;
05801 rtx operand2;
05802 {
05803 rtx _val = 0;
05804 start_sequence ();
05805 {
05806 rtx operands[3];
05807 operands[0] = operand0;
05808 operands[1] = operand1;
05809 operands[2] = operand2;
05810
05811 {
05812 if (TARGET_MIPS16)
05813 {
05814 operands[1] = force_reg (DImode, operands[1]);
05815 operands[2] = force_reg (DImode, operands[2]);
05816 }
05817 }
05818 operand0 = operands[0];
05819 operand1 = operands[1];
05820 operand2 = operands[2];
05821 }
05822 emit_insn (gen_rtx_SET (VOIDmode,
05823 operand0,
05824 gen_rtx_AND (DImode,
05825 operand1,
05826 operand2)));
05827 _val = get_insns ();
05828 end_sequence ();
05829 return _val;
05830 }
05831
05832
05833 extern rtx gen_split_393 PARAMS ((rtx *));
05834 rtx
05835 gen_split_393 (operands)
05836 rtx *operands;
05837 {
05838 rtx operand0;
05839 rtx operand1;
05840 rtx operand2;
05841 rtx _val = 0;
05842 start_sequence ();
05843
05844 operand0 = operands[0];
05845 operand1 = operands[1];
05846 operand2 = operands[2];
05847 emit_insn (gen_rtx_SET (VOIDmode,
05848 gen_rtx_SUBREG (SImode,
05849 operand0,
05850 0),
05851 gen_rtx_AND (SImode,
05852 gen_rtx_SUBREG (SImode,
05853 operand1,
05854 0),
05855 gen_rtx_SUBREG (SImode,
05856 operand2,
05857 0))));
05858 emit_insn (gen_rtx_SET (VOIDmode,
05859 gen_rtx_SUBREG (SImode,
05860 copy_rtx (operand0),
05861 4),
05862 gen_rtx_AND (SImode,
05863 gen_rtx_SUBREG (SImode,
05864 copy_rtx (operand1),
05865 4),
05866 gen_rtx_SUBREG (SImode,
05867 copy_rtx (operand2),
05868 4))));
05869 _val = get_insns ();
05870 end_sequence ();
05871 return _val;
05872 }
05873
05874
05875 rtx
05876 gen_iorsi3 (operand0, operand1, operand2)
05877 rtx operand0;
05878 rtx operand1;
05879 rtx operand2;
05880 {
05881 rtx _val = 0;
05882 start_sequence ();
05883 {
05884 rtx operands[3];
05885 operands[0] = operand0;
05886 operands[1] = operand1;
05887 operands[2] = operand2;
05888
05889 {
05890 if (TARGET_MIPS16)
05891 {
05892 operands[1] = force_reg (SImode, operands[1]);
05893 operands[2] = force_reg (SImode, operands[2]);
05894 }
05895 }
05896 operand0 = operands[0];
05897 operand1 = operands[1];
05898 operand2 = operands[2];
05899 }
05900 emit_insn (gen_rtx_SET (VOIDmode,
05901 operand0,
05902 gen_rtx_IOR (SImode,
05903 operand1,
05904 operand2)));
05905 _val = get_insns ();
05906 end_sequence ();
05907 return _val;
05908 }
05909
05910
05911 rtx
05912 gen_iordi3 (operand0, operand1, operand2)
05913 rtx operand0;
05914 rtx operand1;
05915 rtx operand2;
05916 {
05917 return gen_rtx_SET (VOIDmode,
05918 operand0,
05919 gen_rtx_IOR (DImode,
05920 operand1,
05921 operand2));
05922 }
05923
05924
05925 extern rtx gen_split_396 PARAMS ((rtx *));
05926 rtx
05927 gen_split_396 (operands)
05928 rtx *operands;
05929 {
05930 rtx operand0;
05931 rtx operand1;
05932 rtx operand2;
05933 rtx _val = 0;
05934 start_sequence ();
05935
05936 operand0 = operands[0];
05937 operand1 = operands[1];
05938 operand2 = operands[2];
05939 emit_insn (gen_rtx_SET (VOIDmode,
05940 gen_rtx_SUBREG (SImode,
05941 operand0,
05942 0),
05943 gen_rtx_IOR (SImode,
05944 gen_rtx_SUBREG (SImode,
05945 operand1,
05946 0),
05947 gen_rtx_SUBREG (SImode,
05948 operand2,
05949 0))));
05950 emit_insn (gen_rtx_SET (VOIDmode,
05951 gen_rtx_SUBREG (SImode,
05952 copy_rtx (operand0),
05953 4),
05954 gen_rtx_IOR (SImode,
05955 gen_rtx_SUBREG (SImode,
05956 copy_rtx (operand1),
05957 4),
05958 gen_rtx_SUBREG (SImode,
05959 copy_rtx (operand2),
05960 4))));
05961 _val = get_insns ();
05962 end_sequence ();
05963 return _val;
05964 }
05965
05966
05967 rtx
05968 gen_xorsi3 (operand0, operand1, operand2)
05969 rtx operand0;
05970 rtx operand1;
05971 rtx operand2;
05972 {
05973 return gen_rtx_SET (VOIDmode,
05974 operand0,
05975 gen_rtx_XOR (SImode,
05976 operand1,
05977 operand2));
05978 }
05979
05980
05981 rtx
05982 gen_xordi3 (operand0, operand1, operand2)
05983 rtx operand0;
05984 rtx operand1;
05985 rtx operand2;
05986 {
05987 return gen_rtx_SET (VOIDmode,
05988 operand0,
05989 gen_rtx_XOR (DImode,
05990 operand1,
05991 operand2));
05992 }
05993
05994
05995 extern rtx gen_split_399 PARAMS ((rtx *));
05996 rtx
05997 gen_split_399 (operands)
05998 rtx *operands;
05999 {
06000 rtx operand0;
06001 rtx operand1;
06002 rtx operand2;
06003 rtx _val = 0;
06004 start_sequence ();
06005
06006 operand0 = operands[0];
06007 operand1 = operands[1];
06008 operand2 = operands[2];
06009 emit_insn (gen_rtx_SET (VOIDmode,
06010 gen_rtx_SUBREG (SImode,
06011 operand0,
06012 0),
06013 gen_rtx_XOR (SImode,
06014 gen_rtx_SUBREG (SImode,
06015 operand1,
06016 0),
06017 gen_rtx_SUBREG (SImode,
06018 operand2,
06019 0))));
06020 emit_insn (gen_rtx_SET (VOIDmode,
06021 gen_rtx_SUBREG (SImode,
06022 copy_rtx (operand0),
06023 4),
06024 gen_rtx_XOR (SImode,
06025 gen_rtx_SUBREG (SImode,
06026 copy_rtx (operand1),
06027 4),
06028 gen_rtx_SUBREG (SImode,
06029 copy_rtx (operand2),
06030 4))));
06031 _val = get_insns ();
06032 end_sequence ();
06033 return _val;
06034 }
06035
06036
06037 extern rtx gen_split_400 PARAMS ((rtx *));
06038 rtx
06039 gen_split_400 (operands)
06040 rtx *operands;
06041 {
06042 rtx operand0;
06043 rtx operand1;
06044 rtx operand2;
06045 rtx _val = 0;
06046 start_sequence ();
06047
06048 operand0 = operands[0];
06049 operand1 = operands[1];
06050 operand2 = operands[2];
06051 emit_insn (gen_rtx_SET (VOIDmode,
06052 gen_rtx_SUBREG (SImode,
06053 operand0,
06054 0),
06055 gen_rtx_AND (SImode,
06056 gen_rtx_NOT (SImode,
06057 gen_rtx_SUBREG (SImode,
06058 operand1,
06059 0)),
06060 gen_rtx_NOT (SImode,
06061 gen_rtx_SUBREG (SImode,
06062 operand2,
06063 0)))));
06064 emit_insn (gen_rtx_SET (VOIDmode,
06065 gen_rtx_SUBREG (SImode,
06066 copy_rtx (operand0),
06067 4),
06068 gen_rtx_AND (SImode,
06069 gen_rtx_NOT (SImode,
06070 gen_rtx_SUBREG (SImode,
06071 copy_rtx (operand1),
06072 4)),
06073 gen_rtx_NOT (SImode,
06074 gen_rtx_SUBREG (SImode,
06075 copy_rtx (operand2),
06076 4)))));
06077 _val = get_insns ();
06078 end_sequence ();
06079 return _val;
06080 }
06081
06082
06083 rtx
06084 gen_zero_extendsidi2 (operand0, operand1)
06085 rtx operand0;
06086 rtx operand1;
06087 {
06088 rtx _val = 0;
06089 start_sequence ();
06090 {
06091 rtx operands[2];
06092 operands[0] = operand0;
06093 operands[1] = operand1;
06094
06095 {
06096 if ((optimize || TARGET_MIPS16) && GET_CODE (operands[1]) == MEM)
06097 operands[1] = force_not_mem (operands[1]);
06098
06099 if (GET_CODE (operands[1]) != MEM)
06100 {
06101 rtx op1 = gen_lowpart (DImode, operands[1]);
06102 rtx temp = gen_reg_rtx (DImode);
06103 rtx shift = GEN_INT (32);
06104
06105 emit_insn (gen_ashldi3 (temp, op1, shift));
06106 emit_insn (gen_lshrdi3 (operands[0], temp, shift));
06107 DONE;
06108 }
06109 }
06110 operand0 = operands[0];
06111 operand1 = operands[1];
06112 }
06113 emit_insn (gen_rtx_SET (VOIDmode,
06114 operand0,
06115 gen_rtx_ZERO_EXTEND (DImode,
06116 operand1)));
06117 _val = get_insns ();
06118 end_sequence ();
06119 return _val;
06120 }
06121
06122
06123 rtx
06124 gen_zero_extendhisi2 (operand0, operand1)
06125 rtx operand0;
06126 rtx operand1;
06127 {
06128 rtx _val = 0;
06129 start_sequence ();
06130 {
06131 rtx operands[2];
06132 operands[0] = operand0;
06133 operands[1] = operand1;
06134
06135 {
06136 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
06137 {
06138 rtx op = gen_lowpart (SImode, operands[1]);
06139 rtx temp = force_reg (SImode, GEN_INT (0xffff));
06140
06141 emit_insn (gen_andsi3 (operands[0], op, temp));
06142 DONE;
06143 }
06144 }
06145 operand0 = operands[0];
06146 operand1 = operands[1];
06147 }
06148 emit_insn (gen_rtx_SET (VOIDmode,
06149 operand0,
06150 gen_rtx_ZERO_EXTEND (SImode,
06151 operand1)));
06152 _val = get_insns ();
06153 end_sequence ();
06154 return _val;
06155 }
06156
06157
06158 rtx
06159 gen_zero_extendhidi2 (operand0, operand1)
06160 rtx operand0;
06161 rtx operand1;
06162 {
06163 rtx _val = 0;
06164 start_sequence ();
06165 {
06166 rtx operands[2];
06167 operands[0] = operand0;
06168 operands[1] = operand1;
06169
06170 {
06171 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
06172 {
06173 rtx op = gen_lowpart (DImode, operands[1]);
06174 rtx temp = force_reg (DImode, GEN_INT (0xffff));
06175
06176 emit_insn (gen_anddi3 (operands[0], op, temp));
06177 DONE;
06178 }
06179 }
06180 operand0 = operands[0];
06181 operand1 = operands[1];
06182 }
06183 emit_insn (gen_rtx_SET (VOIDmode,
06184 operand0,
06185 gen_rtx_ZERO_EXTEND (DImode,
06186 operand1)));
06187 _val = get_insns ();
06188 end_sequence ();
06189 return _val;
06190 }
06191
06192
06193 rtx
06194 gen_zero_extendqihi2 (operand0, operand1)
06195 rtx operand0;
06196 rtx operand1;
06197 {
06198 rtx _val = 0;
06199 start_sequence ();
06200 {
06201 rtx operands[2];
06202 operands[0] = operand0;
06203 operands[1] = operand1;
06204
06205 {
06206 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
06207 {
06208 rtx op0 = gen_lowpart (SImode, operands[0]);
06209 rtx op1 = gen_lowpart (SImode, operands[1]);
06210 rtx temp = force_reg (SImode, GEN_INT (0xff));
06211
06212 emit_insn (gen_andsi3 (op0, op1, temp));
06213 DONE;
06214 }
06215 }
06216 operand0 = operands[0];
06217 operand1 = operands[1];
06218 }
06219 emit_insn (gen_rtx_SET (VOIDmode,
06220 operand0,
06221 gen_rtx_ZERO_EXTEND (HImode,
06222 operand1)));
06223 _val = get_insns ();
06224 end_sequence ();
06225 return _val;
06226 }
06227
06228
06229 rtx
06230 gen_zero_extendqisi2 (operand0, operand1)
06231 rtx operand0;
06232 rtx operand1;
06233 {
06234 rtx _val = 0;
06235 start_sequence ();
06236 {
06237 rtx operands[2];
06238 operands[0] = operand0;
06239 operands[1] = operand1;
06240
06241 {
06242 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
06243 {
06244 rtx op = gen_lowpart (SImode, operands[1]);
06245 rtx temp = force_reg (SImode, GEN_INT (0xff));
06246
06247 emit_insn (gen_andsi3 (operands[0], op, temp));
06248 DONE;
06249 }
06250 }
06251 operand0 = operands[0];
06252 operand1 = operands[1];
06253 }
06254 emit_insn (gen_rtx_SET (VOIDmode,
06255 operand0,
06256 gen_rtx_ZERO_EXTEND (SImode,
06257 operand1)));
06258 _val = get_insns ();
06259 end_sequence ();
06260 return _val;
06261 }
06262
06263
06264 rtx
06265 gen_zero_extendqidi2 (operand0, operand1)
06266 rtx operand0;
06267 rtx operand1;
06268 {
06269 rtx _val = 0;
06270 start_sequence ();
06271 {
06272 rtx operands[2];
06273 operands[0] = operand0;
06274 operands[1] = operand1;
06275
06276 {
06277 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
06278 {
06279 rtx op = gen_lowpart (DImode, operands[1]);
06280 rtx temp = force_reg (DImode, GEN_INT (0xff));
06281
06282 emit_insn (gen_anddi3 (operands[0], op, temp));
06283 DONE;
06284 }
06285 }
06286 operand0 = operands[0];
06287 operand1 = operands[1];
06288 }
06289 emit_insn (gen_rtx_SET (VOIDmode,
06290 operand0,
06291 gen_rtx_ZERO_EXTEND (DImode,
06292 operand1)));
06293 _val = get_insns ();
06294 end_sequence ();
06295 return _val;
06296 }
06297
06298
06299 rtx
06300 gen_extendsidi2 (operand0, operand1)
06301 rtx operand0;
06302 rtx operand1;
06303 {
06304 return gen_rtx_SET (VOIDmode,
06305 operand0,
06306 gen_rtx_SIGN_EXTEND (DImode,
06307 operand1));
06308 }
06309
06310
06311 rtx
06312 gen_extendhidi2 (operand0, operand1)
06313 rtx operand0;
06314 rtx operand1;
06315 {
06316 rtx _val = 0;
06317 start_sequence ();
06318 {
06319 rtx operands[2];
06320 operands[0] = operand0;
06321 operands[1] = operand1;
06322
06323 {
06324 if (optimize && GET_CODE (operands[1]) == MEM)
06325 operands[1] = force_not_mem (operands[1]);
06326
06327 if (GET_CODE (operands[1]) != MEM)
06328 {
06329 rtx op1 = gen_lowpart (DImode, operands[1]);
06330 rtx temp = gen_reg_rtx (DImode);
06331 rtx shift = GEN_INT (48);
06332
06333 emit_insn (gen_ashldi3 (temp, op1, shift));
06334 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
06335 DONE;
06336 }
06337 }
06338 operand0 = operands[0];
06339 operand1 = operands[1];
06340 }
06341 emit_insn (gen_rtx_SET (VOIDmode,
06342 operand0,
06343 gen_rtx_SIGN_EXTEND (DImode,
06344 operand1)));
06345 _val = get_insns ();
06346 end_sequence ();
06347 return _val;
06348 }
06349
06350
06351 rtx
06352 gen_extendhisi2 (operand0, operand1)
06353 rtx operand0;
06354 rtx operand1;
06355 {
06356 rtx _val = 0;
06357 start_sequence ();
06358 {
06359 rtx operands[2];
06360 operands[0] = operand0;
06361 operands[1] = operand1;
06362
06363 {
06364 if (optimize && GET_CODE (operands[1]) == MEM)
06365 operands[1] = force_not_mem (operands[1]);
06366
06367 if (GET_CODE (operands[1]) != MEM)
06368 {
06369 rtx op1 = gen_lowpart (SImode, operands[1]);
06370 rtx temp = gen_reg_rtx (SImode);
06371 rtx shift = GEN_INT (16);
06372
06373 emit_insn (gen_ashlsi3 (temp, op1, shift));
06374 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
06375 DONE;
06376 }
06377 }
06378 operand0 = operands[0];
06379 operand1 = operands[1];
06380 }
06381 emit_insn (gen_rtx_SET (VOIDmode,
06382 operand0,
06383 gen_rtx_SIGN_EXTEND (SImode,
06384 operand1)));
06385 _val = get_insns ();
06386 end_sequence ();
06387 return _val;
06388 }
06389
06390
06391 rtx
06392 gen_extendqihi2 (operand0, operand1)
06393 rtx operand0;
06394 rtx operand1;
06395 {
06396 rtx _val = 0;
06397 start_sequence ();
06398 {
06399 rtx operands[2];
06400 operands[0] = operand0;
06401 operands[1] = operand1;
06402
06403 {
06404 if (optimize && GET_CODE (operands[1]) == MEM)
06405 operands[1] = force_not_mem (operands[1]);
06406
06407 if (GET_CODE (operands[1]) != MEM)
06408 {
06409 rtx op0 = gen_lowpart (SImode, operands[0]);
06410 rtx op1 = gen_lowpart (SImode, operands[1]);
06411 rtx temp = gen_reg_rtx (SImode);
06412 rtx shift = GEN_INT (24);
06413
06414 emit_insn (gen_ashlsi3 (temp, op1, shift));
06415 emit_insn (gen_ashrsi3 (op0, temp, shift));
06416 DONE;
06417 }
06418 }
06419 operand0 = operands[0];
06420 operand1 = operands[1];
06421 }
06422 emit_insn (gen_rtx_SET (VOIDmode,
06423 operand0,
06424 gen_rtx_SIGN_EXTEND (HImode,
06425 operand1)));
06426 _val = get_insns ();
06427 end_sequence ();
06428 return _val;
06429 }
06430
06431
06432 rtx
06433 gen_extendqisi2 (operand0, operand1)
06434 rtx operand0;
06435 rtx operand1;
06436 {
06437 rtx _val = 0;
06438 start_sequence ();
06439 {
06440 rtx operands[2];
06441 operands[0] = operand0;
06442 operands[1] = operand1;
06443
06444 {
06445 if (optimize && GET_CODE (operands[1]) == MEM)
06446 operands[1] = force_not_mem (operands[1]);
06447
06448 if (GET_CODE (operands[1]) != MEM)
06449 {
06450 rtx op1 = gen_lowpart (SImode, operands[1]);
06451 rtx temp = gen_reg_rtx (SImode);
06452 rtx shift = GEN_INT (24);
06453
06454 emit_insn (gen_ashlsi3 (temp, op1, shift));
06455 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
06456 DONE;
06457 }
06458 }
06459 operand0 = operands[0];
06460 operand1 = operands[1];
06461 }
06462 emit_insn (gen_rtx_SET (VOIDmode,
06463 operand0,
06464 gen_rtx_SIGN_EXTEND (SImode,
06465 operand1)));
06466 _val = get_insns ();
06467 end_sequence ();
06468 return _val;
06469 }
06470
06471
06472 rtx
06473 gen_extendqidi2 (operand0, operand1)
06474 rtx operand0;
06475 rtx operand1;
06476 {
06477 rtx _val = 0;
06478 start_sequence ();
06479 {
06480 rtx operands[2];
06481 operands[0] = operand0;
06482 operands[1] = operand1;
06483
06484 {
06485 if (optimize && GET_CODE (operands[1]) == MEM)
06486 operands[1] = force_not_mem (operands[1]);
06487
06488 if (GET_CODE (operands[1]) != MEM)
06489 {
06490 rtx op1 = gen_lowpart (DImode, operands[1]);
06491 rtx temp = gen_reg_rtx (DImode);
06492 rtx shift = GEN_INT (56);
06493
06494 emit_insn (gen_ashldi3 (temp, op1, shift));
06495 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
06496 DONE;
06497 }
06498 }
06499 operand0 = operands[0];
06500 operand1 = operands[1];
06501 }
06502 emit_insn (gen_rtx_SET (VOIDmode,
06503 operand0,
06504 gen_rtx_SIGN_EXTEND (DImode,
06505 operand1)));
06506 _val = get_insns ();
06507 end_sequence ();
06508 return _val;
06509 }
06510
06511
06512 rtx
06513 gen_fix_truncdfsi2 (operand0, operand1)
06514 rtx operand0;
06515 rtx operand1;
06516 {
06517 rtx _val = 0;
06518 start_sequence ();
06519 {
06520 rtx operands[2];
06521 operands[0] = operand0;
06522 operands[1] = operand1;
06523 {
06524 if (!ISA_HAS_TRUNC_W)
06525 {
06526 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
06527 DONE;
06528 }
06529 }
06530 operand0 = operands[0];
06531 operand1 = operands[1];
06532 }
06533 emit_insn (gen_rtx_SET (VOIDmode,
06534 operand0,
06535 gen_rtx_FIX (SImode,
06536 operand1)));
06537 _val = get_insns ();
06538 end_sequence ();
06539 return _val;
06540 }
06541
06542
06543 rtx
06544 gen_fix_truncsfsi2 (operand0, operand1)
06545 rtx operand0;
06546 rtx operand1;
06547 {
06548 rtx _val = 0;
06549 start_sequence ();
06550 {
06551 rtx operands[2];
06552 operands[0] = operand0;
06553 operands[1] = operand1;
06554 {
06555 if (!ISA_HAS_TRUNC_W)
06556 {
06557 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
06558 DONE;
06559 }
06560 }
06561 operand0 = operands[0];
06562 operand1 = operands[1];
06563 }
06564 emit_insn (gen_rtx_SET (VOIDmode,
06565 operand0,
06566 gen_rtx_FIX (SImode,
06567 operand1)));
06568 _val = get_insns ();
06569 end_sequence ();
06570 return _val;
06571 }
06572
06573
06574 rtx
06575 gen_fixuns_truncdfsi2 (operand0, operand1)
06576 rtx operand0;
06577 rtx operand1;
06578 {
06579 rtx _val = 0;
06580 start_sequence ();
06581 {
06582 rtx operands[2];
06583 operands[0] = operand0;
06584 operands[1] = operand1;
06585
06586 {
06587 rtx reg1 = gen_reg_rtx (DFmode);
06588 rtx reg2 = gen_reg_rtx (DFmode);
06589 rtx reg3 = gen_reg_rtx (SImode);
06590 rtx label1 = gen_label_rtx ();
06591 rtx label2 = gen_label_rtx ();
06592 REAL_VALUE_TYPE offset;
06593
06594 real_2expN (&offset, 31);
06595
06596 if (reg1)
06597 {
06598 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
06599 do_pending_stack_adjust ();
06600
06601 emit_insn (gen_cmpdf (operands[1], reg1));
06602 emit_jump_insn (gen_bge (label1));
06603
06604 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
06605 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
06606 gen_rtx_LABEL_REF (VOIDmode, label2)));
06607 emit_barrier ();
06608
06609 emit_label (label1);
06610 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
06611 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
06612 (BITMASK_HIGH, SImode)));
06613
06614 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
06615 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
06616
06617 emit_label (label2);
06618
06619
06620
06621 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
06622 DONE;
06623 }
06624 }
06625 operand0 = operands[0];
06626 operand1 = operands[1];
06627 }
06628 emit_insn (gen_rtx_SET (VOIDmode,
06629 operand0,
06630 gen_rtx_UNSIGNED_FIX (SImode,
06631 operand1)));
06632 _val = get_insns ();
06633 end_sequence ();
06634 return _val;
06635 }
06636
06637
06638 rtx
06639 gen_fixuns_truncdfdi2 (operand0, operand1)
06640 rtx operand0;
06641 rtx operand1;
06642 {
06643 rtx _val = 0;
06644 start_sequence ();
06645 {
06646 rtx operands[2];
06647 operands[0] = operand0;
06648 operands[1] = operand1;
06649
06650 {
06651 rtx reg1 = gen_reg_rtx (DFmode);
06652 rtx reg2 = gen_reg_rtx (DFmode);
06653 rtx reg3 = gen_reg_rtx (DImode);
06654 rtx label1 = gen_label_rtx ();
06655 rtx label2 = gen_label_rtx ();
06656 REAL_VALUE_TYPE offset;
06657
06658 real_2expN (&offset, 63);
06659
06660 if (reg1)
06661 {
06662 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
06663 do_pending_stack_adjust ();
06664
06665 emit_insn (gen_cmpdf (operands[1], reg1));
06666 emit_jump_insn (gen_bge (label1));
06667
06668 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
06669 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
06670 gen_rtx_LABEL_REF (VOIDmode, label2)));
06671 emit_barrier ();
06672
06673 emit_label (label1);
06674 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
06675 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
06676 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
06677
06678 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
06679 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
06680
06681 emit_label (label2);
06682
06683
06684
06685 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
06686 DONE;
06687 }
06688 }
06689 operand0 = operands[0];
06690 operand1 = operands[1];
06691 }
06692 emit_insn (gen_rtx_SET (VOIDmode,
06693 operand0,
06694 gen_rtx_UNSIGNED_FIX (DImode,
06695 operand1)));
06696 _val = get_insns ();
06697 end_sequence ();
06698 return _val;
06699 }
06700
06701
06702 rtx
06703 gen_fixuns_truncsfsi2 (operand0, operand1)
06704 rtx operand0;
06705 rtx operand1;
06706 {
06707 rtx _val = 0;
06708 start_sequence ();
06709 {
06710 rtx operands[2];
06711 operands[0] = operand0;
06712 operands[1] = operand1;
06713
06714 {
06715 rtx reg1 = gen_reg_rtx (SFmode);
06716 rtx reg2 = gen_reg_rtx (SFmode);
06717 rtx reg3 = gen_reg_rtx (SImode);
06718 rtx label1 = gen_label_rtx ();
06719 rtx label2 = gen_label_rtx ();
06720 REAL_VALUE_TYPE offset;
06721
06722 real_2expN (&offset, 31);
06723
06724 if (reg1)
06725 {
06726 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
06727 do_pending_stack_adjust ();
06728
06729 emit_insn (gen_cmpsf (operands[1], reg1));
06730 emit_jump_insn (gen_bge (label1));
06731
06732 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
06733 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
06734 gen_rtx_LABEL_REF (VOIDmode, label2)));
06735 emit_barrier ();
06736
06737 emit_label (label1);
06738 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
06739 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
06740 (BITMASK_HIGH, SImode)));
06741
06742 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
06743 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
06744
06745 emit_label (label2);
06746
06747
06748
06749 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
06750 DONE;
06751 }
06752 }
06753 operand0 = operands[0];
06754 operand1 = operands[1];
06755 }
06756 emit_insn (gen_rtx_SET (VOIDmode,
06757 operand0,
06758 gen_rtx_UNSIGNED_FIX (SImode,
06759 operand1)));
06760 _val = get_insns ();
06761 end_sequence ();
06762 return _val;
06763 }
06764
06765
06766 rtx
06767 gen_fixuns_truncsfdi2 (operand0, operand1)
06768 rtx operand0;
06769 rtx operand1;
06770 {
06771 rtx _val = 0;
06772 start_sequence ();
06773 {
06774 rtx operands[2];
06775 operands[0] = operand0;
06776 operands[1] = operand1;
06777
06778 {
06779 rtx reg1 = gen_reg_rtx (SFmode);
06780 rtx reg2 = gen_reg_rtx (SFmode);
06781 rtx reg3 = gen_reg_rtx (DImode);
06782 rtx label1 = gen_label_rtx ();
06783 rtx label2 = gen_label_rtx ();
06784 REAL_VALUE_TYPE offset;
06785
06786 real_2expN (&offset, 63);
06787
06788 if (reg1)
06789 {
06790 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
06791 do_pending_stack_adjust ();
06792
06793 emit_insn (gen_cmpsf (operands[1], reg1));
06794 emit_jump_insn (gen_bge (label1));
06795
06796 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
06797 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
06798 gen_rtx_LABEL_REF (VOIDmode, label2)));
06799 emit_barrier ();
06800
06801 emit_label (label1);
06802 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
06803 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
06804 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
06805
06806 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
06807 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
06808
06809 emit_label (label2);
06810
06811
06812
06813 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
06814 DONE;
06815 }
06816 }
06817 operand0 = operands[0];
06818 operand1 = operands[1];
06819 }
06820 emit_insn (gen_rtx_SET (VOIDmode,
06821 operand0,
06822 gen_rtx_UNSIGNED_FIX (DImode,
06823 operand1)));
06824 _val = get_insns ();
06825 end_sequence ();
06826 return _val;
06827 }
06828
06829
06830 rtx
06831 gen_extv (operand0, operand1, operand2, operand3)
06832 rtx operand0;
06833 rtx operand1;
06834 rtx operand2;
06835 rtx operand3;
06836 {
06837 rtx _val = 0;
06838 start_sequence ();
06839 {
06840 rtx operands[4];
06841 operands[0] = operand0;
06842 operands[1] = operand1;
06843 operands[2] = operand2;
06844 operands[3] = operand3;
06845
06846 {
06847
06848 if (INTVAL (operands[3]) % 8 != 0)
06849 FAIL;
06850
06851
06852 if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
06853 FAIL;
06854
06855
06856 if (TARGET_64BIT
06857 && INTVAL (operands[2]) != 64
06858 && INTVAL (operands[2]) != 32)
06859 FAIL;
06860
06861
06862
06863
06864 if (GET_CODE (operands[1]) != MEM)
06865 FAIL;
06866
06867
06868 operands[1] = adjust_address (operands[1], BLKmode, 0);
06869 set_mem_size (operands[1], GEN_INT (INTVAL (operands[2]) / BITS_PER_UNIT));
06870
06871
06872 if (INTVAL (operands[2]) == 64)
06873 emit_insn (gen_movdi_uld (operands[0], operands[1]));
06874 else
06875 {
06876 if (TARGET_64BIT)
06877 {
06878 operands[0] = gen_lowpart (SImode, operands[0]);
06879 if (operands[0] == NULL_RTX)
06880 FAIL;
06881 }
06882 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
06883 }
06884 DONE;
06885 }
06886 operand0 = operands[0];
06887 operand1 = operands[1];
06888 operand2 = operands[2];
06889 operand3 = operands[3];
06890 }
06891 emit_insn (gen_rtx_SET (VOIDmode,
06892 operand0,
06893 gen_rtx_SIGN_EXTRACT (VOIDmode,
06894 operand1,
06895 operand2,
06896 operand3)));
06897 _val = get_insns ();
06898 end_sequence ();
06899 return _val;
06900 }
06901
06902
06903 rtx
06904 gen_extzv (operand0, operand1, operand2, operand3)
06905 rtx operand0;
06906 rtx operand1;
06907 rtx operand2;
06908 rtx operand3;
06909 {
06910 rtx _val = 0;
06911 start_sequence ();
06912 {
06913 rtx operands[4];
06914 operands[0] = operand0;
06915 operands[1] = operand1;
06916 operands[2] = operand2;
06917 operands[3] = operand3;
06918
06919 {
06920
06921 if (INTVAL (operands[3]) % 8 != 0)
06922 FAIL;
06923
06924
06925 if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
06926 FAIL;
06927
06928
06929 if (TARGET_64BIT
06930 && INTVAL (operands[2]) != 64
06931 && INTVAL (operands[2]) != 32)
06932 FAIL;
06933
06934
06935
06936
06937 if (GET_CODE (operands[1]) != MEM)
06938 FAIL;
06939
06940
06941 operands[1] = adjust_address (operands[1], BLKmode, 0);
06942 set_mem_size (operands[1], GEN_INT (INTVAL (operands[2]) / BITS_PER_UNIT));
06943
06944
06945 if (INTVAL (operands[2]) == 64)
06946 emit_insn (gen_movdi_uld (operands[0], operands[1]));
06947 else
06948 {
06949 if (TARGET_64BIT)
06950 {
06951 operands[0] = gen_lowpart (SImode, operands[0]);
06952 if (operands[0] == NULL_RTX)
06953 FAIL;
06954 }
06955 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
06956 }
06957 DONE;
06958 }
06959 operand0 = operands[0];
06960 operand1 = operands[1];
06961 operand2 = operands[2];
06962 operand3 = operands[3];
06963 }
06964 emit_insn (gen_rtx_SET (VOIDmode,
06965 operand0,
06966 gen_rtx_ZERO_EXTRACT (VOIDmode,
06967 operand1,
06968 operand2,
06969 operand3)));
06970 _val = get_insns ();
06971 end_sequence ();
06972 return _val;
06973 }
06974
06975
06976 rtx
06977 gen_insv (operand0, operand1, operand2, operand3)
06978 rtx operand0;
06979 rtx operand1;
06980 rtx operand2;
06981 rtx operand3;
06982 {
06983 rtx _val = 0;
06984 start_sequence ();
06985 {
06986 rtx operands[4];
06987 operands[0] = operand0;
06988 operands[1] = operand1;
06989 operands[2] = operand2;
06990 operands[3] = operand3;
06991
06992 {
06993
06994 if (INTVAL (operands[2]) % 8 != 0)
06995 FAIL;
06996
06997
06998 if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
06999 FAIL;
07000
07001
07002 if (TARGET_64BIT
07003 && INTVAL (operands[1]) != 64
07004 && INTVAL (operands[1]) != 32)
07005 FAIL;
07006
07007
07008
07009
07010 if (GET_CODE (operands[0]) != MEM)
07011 FAIL;
07012
07013
07014 operands[0] = adjust_address (operands[0], BLKmode, 0);
07015 set_mem_size (operands[0], GEN_INT (INTVAL (operands[1]) / BITS_PER_UNIT));
07016
07017
07018 if (INTVAL (operands[1]) == 64)
07019 emit_insn (gen_movdi_usd (operands[0], operands[3]));
07020 else
07021 {
07022 if (TARGET_64BIT)
07023 {
07024 operands[3] = gen_lowpart (SImode, operands[3]);
07025 if (operands[3] == NULL_RTX)
07026 FAIL;
07027 }
07028 emit_insn (gen_movsi_usw (operands[0], operands[3]));
07029 }
07030 DONE;
07031 }
07032 operand0 = operands[0];
07033 operand1 = operands[1];
07034 operand2 = operands[2];
07035 operand3 = operands[3];
07036 }
07037 emit_insn (gen_rtx_SET (VOIDmode,
07038 gen_rtx_ZERO_EXTRACT (VOIDmode,
07039 operand0,
07040 operand1,
07041 operand2),
07042 operand3));
07043 _val = get_insns ();
07044 end_sequence ();
07045 return _val;
07046 }
07047
07048
07049 rtx
07050 gen_movdi (operand0, operand1)
07051 rtx operand0;
07052 rtx operand1;
07053 {
07054 rtx _val = 0;
07055 start_sequence ();
07056 {
07057 rtx operands[2];
07058 operands[0] = operand0;
07059 operands[1] = operand1;
07060
07061 {
07062 if (mips_split_addresses && mips_check_split (operands[1], DImode))
07063 {
07064 enum machine_mode mode = GET_MODE (operands[0]);
07065 rtx tem = ((reload_in_progress | reload_completed)
07066 ? operands[0] : gen_reg_rtx (mode));
07067
07068 emit_insn (gen_rtx_SET (VOIDmode, tem,
07069 gen_rtx_HIGH (mode, operands[1])));
07070
07071 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
07072 }
07073
07074
07075
07076
07077 if (TARGET_EMBEDDED_PIC
07078 && (GET_CODE (operands[1]) == LABEL_REF
07079 || (GET_CODE (operands[1]) == SYMBOL_REF
07080 && ! SYMBOL_REF_FLAG (operands[1]))))
07081 {
07082 rtx temp;
07083
07084 temp = embedded_pic_offset (operands[1]);
07085 temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
07086 force_reg (DImode, temp));
07087 emit_move_insn (operands[0], force_reg (DImode, temp));
07088 DONE;
07089 }
07090
07091
07092
07093 if (flag_pic && pic_address_needs_scratch (operands[1]))
07094 {
07095 rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
07096 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
07097
07098 if (! SMALL_INT (temp2))
07099 temp2 = force_reg (DImode, temp2);
07100
07101 emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
07102 DONE;
07103 }
07104
07105
07106
07107
07108 if (TARGET_MIPS16
07109 && register_operand (operands[0], DImode)
07110 && GET_CODE (operands[1]) == SYMBOL_REF
07111 && SYMBOL_REF_FLAG (operands[1]))
07112 {
07113 const char *name = XSTR (operands[1], 0);
07114
07115 if (name[0] != '*'
07116 || strncmp (name + 1, LOCAL_LABEL_PREFIX,
07117 sizeof LOCAL_LABEL_PREFIX - 1) != 0)
07118 {
07119 rtx base_reg;
07120
07121 if (reload_in_progress || reload_completed)
07122 {
07123
07124
07125
07126
07127 base_reg = operands[0];
07128 emit_move_insn (base_reg,
07129 gen_rtx (CONST, DImode,
07130 gen_rtx (REG, DImode,
07131 GP_REG_FIRST + 28)));
07132 }
07133 else
07134 {
07135 base_reg = gen_reg_rtx (Pmode);
07136 emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
07137 }
07138
07139 emit_move_insn (operands[0],
07140 gen_rtx (PLUS, Pmode, base_reg,
07141 mips16_gp_offset (operands[1])));
07142 DONE;
07143 }
07144 }
07145
07146 if ((reload_in_progress | reload_completed) == 0
07147 && !register_operand (operands[0], DImode)
07148 && !register_operand (operands[1], DImode)
07149 && (TARGET_MIPS16
07150 || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
07151 && operands[1] != CONST0_RTX (DImode))))
07152 {
07153 rtx temp = force_reg (DImode, operands[1]);
07154 emit_move_insn (operands[0], temp);
07155 DONE;
07156 }
07157 }
07158 operand0 = operands[0];
07159 operand1 = operands[1];
07160 }
07161 emit_insn (gen_rtx_SET (VOIDmode,
07162 operand0,
07163 operand1));
07164 _val = get_insns ();
07165 end_sequence ();
07166 return _val;
07167 }
07168
07169
07170 extern rtx gen_split_423 PARAMS ((rtx *));
07171 rtx
07172 gen_split_423 (operands)
07173 rtx *operands;
07174 {
07175 rtx operand0;
07176 rtx operand1;
07177 rtx _val = 0;
07178 start_sequence ();
07179
07180 operand0 = operands[0];
07181 operand1 = operands[1];
07182 emit_insn (gen_rtx_SET (VOIDmode,
07183 gen_rtx_SUBREG (SImode,
07184 operand0,
07185 0),
07186 gen_rtx_SUBREG (SImode,
07187 operand1,
07188 0)));
07189 emit_insn (gen_rtx_SET (VOIDmode,
07190 gen_rtx_SUBREG (SImode,
07191 copy_rtx (operand0),
07192 4),
07193 gen_rtx_SUBREG (SImode,
07194 copy_rtx (operand1),
07195 4)));
07196 _val = get_insns ();
07197 end_sequence ();
07198 return _val;
07199 }
07200
07201
07202 extern rtx gen_split_424 PARAMS ((rtx *));
07203 rtx
07204 gen_split_424 (operands)
07205 rtx *operands;
07206 {
07207 rtx operand0;
07208 rtx operand1;
07209 rtx operand2;
07210 rtx _val = 0;
07211 start_sequence ();
07212
07213 {
07214 HOST_WIDE_INT val = INTVAL (operands[1]);
07215
07216 if (val < 0)
07217 operands[2] = GEN_INT (0);
07218 else if (val >= 32 * 8)
07219 {
07220 int off = val & 7;
07221
07222 operands[1] = GEN_INT (0x8 + off);
07223 operands[2] = GEN_INT (val - off - 0x8);
07224 }
07225 else
07226 {
07227 int off = val & 7;
07228
07229 operands[1] = GEN_INT (off);
07230 operands[2] = GEN_INT (val - off);
07231 }
07232 }
07233 operand0 = operands[0];
07234 operand1 = operands[1];
07235 operand2 = operands[2];
07236 emit_insn (gen_rtx_SET (VOIDmode,
07237 operand0,
07238 gen_rtx_PLUS (DImode,
07239 copy_rtx (operand0),
07240 operand1)));
07241 emit_insn (gen_rtx_SET (VOIDmode,
07242 copy_rtx (operand0),
07243 gen_rtx_MEM (DImode,
07244 gen_rtx_PLUS (DImode,
07245 copy_rtx (operand0),
07246 operand2))));
07247 _val = get_insns ();
07248 end_sequence ();
07249 return _val;
07250 }
07251
07252
07253 rtx
07254 gen_reload_indi (operand0, operand1, operand2)
07255 rtx operand0;
07256 rtx operand1;
07257 rtx operand2;
07258 {
07259 rtx _val = 0;
07260 start_sequence ();
07261 {
07262 rtx operands[3];
07263 operands[0] = operand0;
07264 operands[1] = operand1;
07265 operands[2] = operand2;
07266
07267 {
07268 rtx scratch = gen_rtx_REG (DImode,
07269 (REGNO (operands[0]) == REGNO (operands[2])
07270 ? REGNO (operands[2]) + 1
07271 : REGNO (operands[2])));
07272
07273 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
07274 {
07275 if (GET_CODE (operands[1]) == MEM)
07276 {
07277 rtx memword, offword, hi_word, lo_word;
07278 rtx addr = find_replacement (&XEXP (operands[1], 0));
07279 rtx op1 = replace_equiv_address (operands[1], addr);
07280
07281 scratch = gen_rtx_REG (SImode, REGNO (scratch));
07282 memword = adjust_address (op1, SImode, 0);
07283 offword = adjust_address (op1, SImode, 4);
07284
07285 if (BYTES_BIG_ENDIAN)
07286 {
07287 hi_word = memword;
07288 lo_word = offword;
07289 }
07290 else
07291 {
07292 hi_word = offword;
07293 lo_word = memword;
07294 }
07295 emit_move_insn (scratch, hi_word);
07296 emit_move_insn (gen_rtx_REG (SImode, 64), scratch);
07297 emit_move_insn (scratch, lo_word);
07298 emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
07299 emit_insn (gen_hilo_delay (operands[0]));
07300 }
07301 else
07302 {
07303 emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
07304 emit_insn (gen_movdi (gen_rtx_REG (DImode, 64), scratch));
07305 emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
07306 emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
07307 emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
07308 emit_insn (gen_hilo_delay (operands[0]));
07309 }
07310 DONE;
07311 }
07312 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
07313 {
07314 emit_insn (gen_movdi (scratch, gen_rtx_REG (DImode, 65)));
07315 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
07316 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
07317 emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64)));
07318 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
07319 emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
07320 emit_insn (gen_hilo_delay (operands[1]));
07321 DONE;
07322 }
07323
07324 emit_move_insn (scratch, operands[1]);
07325 emit_move_insn (operands[0], scratch);
07326 DONE;
07327 }
07328 operand0 = operands[0];
07329 operand1 = operands[1];
07330 operand2 = operands[2];
07331 }
07332 emit_insn (gen_rtx_SET (VOIDmode,
07333 operand0,
07334 operand1));
07335 emit_insn (gen_rtx_CLOBBER (VOIDmode,
07336 operand2));
07337 _val = get_insns ();
07338 end_sequence ();
07339 return _val;
07340 }
07341
07342
07343 rtx
07344 gen_reload_outdi (operand0, operand1, operand2)
07345 rtx operand0;
07346 rtx operand1;
07347 rtx operand2;
07348 {
07349 rtx _val = 0;
07350 start_sequence ();
07351 {
07352 rtx operands[3];
07353 operands[0] = operand0;
07354 operands[1] = operand1;
07355 operands[2] = operand2;
07356
07357 {
07358 rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
07359
07360 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
07361 {
07362 emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
07363 emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
07364 emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
07365 emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
07366 emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
07367 emit_insn (gen_hilo_delay (operands[0]));
07368 DONE;
07369 }
07370 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
07371 {
07372 if (GET_CODE (operands[0]) == MEM)
07373 {
07374 rtx scratch, memword, offword, hi_word, lo_word;
07375 rtx addr = find_replacement (&XEXP (operands[0], 0));
07376 rtx op0 = replace_equiv_address (operands[0], addr);
07377
07378 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
07379 memword = adjust_address (op0, SImode, 0);
07380 offword = adjust_address (op0, SImode, 4);
07381
07382 if (BYTES_BIG_ENDIAN)
07383 {
07384 hi_word = memword;
07385 lo_word = offword;
07386 }
07387 else
07388 {
07389 hi_word = offword;
07390 lo_word = memword;
07391 }
07392 emit_move_insn (scratch, gen_rtx_REG (SImode, 64));
07393 emit_move_insn (hi_word, scratch);
07394 emit_move_insn (scratch, gen_rtx_REG (SImode, 65));
07395 emit_move_insn (lo_word, scratch);
07396 emit_insn (gen_hilo_delay (operands[1]));
07397 }
07398 else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0])))
07399 {
07400
07401
07402
07403 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
07404 emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
07405 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
07406 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
07407 emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64)));
07408 emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
07409 emit_insn (gen_iordi3 (scratch, scratch, scratch2));
07410 emit_insn (gen_movdi (operands[0], scratch));
07411 emit_insn (gen_hilo_delay (operands[1]));
07412 }
07413 else
07414 {
07415 emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
07416 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
07417 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
07418 emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
07419 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
07420 emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
07421 emit_insn (gen_hilo_delay (operands[1]));
07422 }
07423 DONE;
07424 }
07425
07426 emit_move_insn (scratch, operands[1]);
07427 emit_move_insn (operands[0], scratch);
07428 DONE;
07429 }
07430 operand0 = operands[0];
07431 operand1 = operands[1];
07432 operand2 = operands[2];
07433 }
07434 emit_insn (gen_rtx_SET (VOIDmode,
07435 operand0,
07436 operand1));
07437 emit_insn (gen_rtx_CLOBBER (VOIDmode,
07438 operand2));
07439 _val = get_insns ();
07440 end_sequence ();
07441 return _val;
07442 }
07443
07444
07445 extern rtx gen_split_427 PARAMS ((rtx *));
07446 rtx
07447 gen_split_427 (operands)
07448 rtx *operands;
07449 {
07450 rtx operand0;
07451 rtx operand1;
07452 rtx operand2;
07453 rtx operand3;
07454 rtx _val = 0;
07455 start_sequence ();
07456
07457 {
07458 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
07459 & BITMASK_UPPER16,
07460 SImode));
07461 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
07462 }
07463 operand0 = operands[0];
07464 operand1 = operands[1];
07465 operand2 = operands[2];
07466 operand3 = operands[3];
07467 emit_insn (gen_rtx_SET (VOIDmode,
07468 operand0,
07469 operand2));
07470 emit_insn (gen_rtx_SET (VOIDmode,
07471 copy_rtx (operand0),
07472 gen_rtx_IOR (SImode,
07473 copy_rtx (operand0),
07474 operand3)));
07475 _val = get_insns ();
07476 end_sequence ();
07477 return _val;
07478 }
07479
07480
07481 rtx
07482 gen_movsi (operand0, operand1)
07483 rtx operand0;
07484 rtx operand1;
07485 {
07486 rtx _val = 0;
07487 start_sequence ();
07488 {
07489 rtx operands[2];
07490 operands[0] = operand0;
07491 operands[1] = operand1;
07492
07493 {
07494 if (mips_split_addresses && mips_check_split (operands[1], SImode))
07495 {
07496 enum machine_mode mode = GET_MODE (operands[0]);
07497 rtx tem = ((reload_in_progress | reload_completed)
07498 ? operands[0] : gen_reg_rtx (mode));
07499
07500 emit_insn (gen_rtx_SET (VOIDmode, tem,
07501 gen_rtx_HIGH (mode, operands[1])));
07502
07503 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
07504 }
07505
07506
07507
07508
07509 if (TARGET_EMBEDDED_PIC
07510 && (GET_CODE (operands[1]) == LABEL_REF
07511 || (GET_CODE (operands[1]) == SYMBOL_REF
07512 && ! SYMBOL_REF_FLAG (operands[1]))))
07513 {
07514 rtx temp;
07515
07516 temp = embedded_pic_offset (operands[1]);
07517 temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
07518 force_reg (SImode, temp));
07519 emit_move_insn (operands[0], force_reg (SImode, temp));
07520 DONE;
07521 }
07522
07523
07524
07525 if (flag_pic && pic_address_needs_scratch (operands[1]))
07526 {
07527 rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
07528 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
07529
07530 if (! SMALL_INT (temp2))
07531 temp2 = force_reg (SImode, temp2);
07532
07533 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, temp2));
07534 DONE;
07535 }
07536
07537
07538
07539
07540 if (TARGET_MIPS16
07541 && register_operand (operands[0], SImode)
07542 && GET_CODE (operands[1]) == SYMBOL_REF
07543 && SYMBOL_REF_FLAG (operands[1]))
07544 {
07545 const char *name = XSTR (operands[1], 0);
07546
07547 if (name[0] != '*'
07548 || strncmp (name + 1, LOCAL_LABEL_PREFIX,
07549 sizeof LOCAL_LABEL_PREFIX - 1) != 0)
07550 {
07551 rtx base_reg;
07552
07553 if (reload_in_progress || reload_completed)
07554 {
07555
07556
07557
07558
07559
07560
07561
07562
07563 emit_move_insn (operands[0],
07564 force_const_mem (SImode, operands[1]));
07565 DONE;
07566 }
07567
07568 base_reg = gen_reg_rtx (Pmode);
07569 emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
07570
07571 emit_move_insn (operands[0],
07572 gen_rtx (PLUS, Pmode, base_reg,
07573 mips16_gp_offset (operands[1])));
07574 DONE;
07575 }
07576 }
07577
07578 if ((reload_in_progress | reload_completed) == 0
07579 && !register_operand (operands[0], SImode)
07580 && !register_operand (operands[1], SImode)
07581 && (TARGET_MIPS16
07582 || GET_CODE (operands[1]) != CONST_INT
07583 || INTVAL (operands[1]) != 0))
07584 {
07585 rtx temp = force_reg (SImode, operands[1]);
07586 emit_move_insn (operands[0], temp);
07587 DONE;
07588 }
07589 }
07590 operand0 = operands[0];
07591 operand1 = operands[1];
07592 }
07593 emit_insn (gen_rtx_SET (VOIDmode,
07594 operand0,
07595 operand1));
07596 _val = get_insns ();
07597 end_sequence ();
07598 return _val;
07599 }
07600
07601
07602 extern rtx gen_split_429 PARAMS ((rtx *));
07603 rtx
07604 gen_split_429 (operands)
07605 rtx *operands;
07606 {
07607 rtx operand0;
07608 rtx operand1;
07609 rtx operand2;
07610 rtx _val = 0;
07611 start_sequence ();
07612
07613 {
07614 HOST_WIDE_INT val = INTVAL (operands[1]);
07615
07616 if (val < 0)
07617 operands[2] = GEN_INT (0);
07618 else if (val >= 32 * 4)
07619 {
07620 int off = val & 3;
07621
07622 operands[1] = GEN_INT (0x7c + off);
07623 operands[2] = GEN_INT (val - off - 0x7c);
07624 }
07625 else
07626 {
07627 int off = val & 3;
07628
07629 operands[1] = GEN_INT (off);
07630 operands[2] = GEN_INT (val - off);
07631 }
07632 }
07633 operand0 = operands[0];
07634 operand1 = operands[1];
07635 operand2 = operands[2];
07636 emit_insn (gen_rtx_SET (VOIDmode,
07637 operand0,
07638 gen_rtx_PLUS (SImode,
07639 copy_rtx (operand0),
07640 operand1)));
07641 emit_insn (gen_rtx_SET (VOIDmode,
07642 copy_rtx (operand0),
07643 gen_rtx_MEM (SImode,
07644 gen_rtx_PLUS (SImode,
07645 copy_rtx (operand0),
07646 operand2))));
07647 _val = get_insns ();
07648 end_sequence ();
07649 return _val;
07650 }
07651
07652
07653 extern rtx gen_split_430 PARAMS ((rtx *));
07654 rtx
07655 gen_split_430 (operands)
07656 rtx *operands;
07657 {
07658 rtx operand0;
07659 rtx operand1;
07660 rtx operand2;
07661 rtx _val = 0;
07662 start_sequence ();
07663
07664 {
07665 int val = INTVAL (operands[1]);
07666
07667 operands[1] = GEN_INT (0xff);
07668 operands[2] = GEN_INT (val - 0xff);
07669 }
07670 operand0 = operands[0];
07671 operand1 = operands[1];
07672 operand2 = operands[2];
07673 emit_insn (gen_rtx_SET (VOIDmode,
07674 operand0,
07675 operand1));
07676 emit_insn (gen_rtx_SET (VOIDmode,
07677 copy_rtx (operand0),
07678 gen_rtx_PLUS (SImode,
07679 copy_rtx (operand0),
07680 operand2)));
07681 _val = get_insns ();
07682 end_sequence ();
07683 return _val;
07684 }
07685
07686
07687 extern rtx gen_split_431 PARAMS ((rtx *));
07688 rtx
07689 gen_split_431 (operands)
07690 rtx *operands;
07691 {
07692 rtx operand0;
07693 rtx operand1;
07694 rtx _val = 0;
07695 start_sequence ();
07696
07697 {
07698 operands[1] = GEN_INT (- INTVAL (operands[1]));
07699 }
07700 operand0 = operands[0];
07701 operand1 = operands[1];
07702 emit_insn (gen_rtx_SET (VOIDmode,
07703 operand0,
07704 operand1));
07705 emit_insn (gen_rtx_SET (VOIDmode,
07706 copy_rtx (operand0),
07707 gen_rtx_NEG (SImode,
07708 copy_rtx (operand0))));
07709 _val = get_insns ();
07710 end_sequence ();
07711 return _val;
07712 }
07713
07714
07715 rtx
07716 gen_reload_outsi (operand0, operand1, operand2)
07717 rtx operand0;
07718 rtx operand1;
07719 rtx operand2;
07720 {
07721 rtx _val = 0;
07722 start_sequence ();
07723 {
07724 rtx operands[3];
07725 operands[0] = operand0;
07726 operands[1] = operand1;
07727 operands[2] = operand2;
07728
07729 {
07730 if (TARGET_64BIT
07731 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
07732 {
07733 emit_insn (gen_movsi (gen_rtx_REG (SImode, 65), operands[1]));
07734 emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
07735 emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
07736 emit_insn (gen_hilo_delay (operands[0]));
07737 DONE;
07738 }
07739
07740 if (TARGET_MIPS16
07741 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
07742 {
07743 emit_insn (gen_movsi (operands[2], GEN_INT (1)));
07744
07745
07746 emit_insn (gen_rtx (PARALLEL, VOIDmode,
07747 gen_rtvec (3,
07748 gen_rtx (SET, VOIDmode,
07749 operands[0],
07750 gen_rtx (MULT, SImode,
07751 operands[1],
07752 operands[2])),
07753 gen_rtx (CLOBBER, VOIDmode,
07754 gen_rtx (REG, SImode, 64)),
07755 gen_rtx (CLOBBER, VOIDmode,
07756 gen_rtx (REG, SImode, 66)))));
07757 DONE;
07758 }
07759
07760 if (GET_CODE (operands[0]) == REG
07761 && (TARGET_MIPS16 ? M16_REG_P (REGNO (operands[0]))
07762 : GP_REG_P (REGNO (operands[0]))))
07763 {
07764 emit_move_insn (operands[0], operands[1]);
07765 DONE;
07766 }
07767
07768 emit_move_insn (operands[2], operands[1]);
07769 emit_move_insn (operands[0], operands[2]);
07770 DONE;
07771 }
07772 operand0 = operands[0];
07773 operand1 = operands[1];
07774 operand2 = operands[2];
07775 }
07776 emit_insn (gen_rtx_SET (VOIDmode,
07777 operand0,
07778 operand1));
07779 emit_insn (gen_rtx_CLOBBER (VOIDmode,
07780 operand2));
07781 _val = get_insns ();
07782 end_sequence ();
07783 return _val;
07784 }
07785
07786
07787 rtx
07788 gen_reload_insi (operand0, operand1, operand2)
07789 rtx operand0;
07790 rtx operand1;
07791 rtx operand2;
07792 {
07793 rtx _val = 0;
07794 start_sequence ();
07795 {
07796 rtx operands[3];
07797 operands[0] = operand0;
07798 operands[1] = operand1;
07799 operands[2] = operand2;
07800
07801 {
07802 if (TARGET_MIPS16
07803 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
07804 {
07805 emit_insn (gen_movsi (operands[2], GEN_INT (1)));
07806
07807
07808 emit_insn (gen_rtx (PARALLEL, VOIDmode,
07809 gen_rtvec (3,
07810 gen_rtx (SET, VOIDmode,
07811 operands[0],
07812 gen_rtx (MULT, SImode,
07813 operands[1],
07814 operands[2])),
07815 gen_rtx (CLOBBER, VOIDmode,
07816 gen_rtx (REG, SImode, 64)),
07817 gen_rtx (CLOBBER, VOIDmode,
07818 gen_rtx (REG, SImode, 66)))));
07819 DONE;
07820 }
07821
07822
07823
07824 if (TARGET_MIPS16 && GET_CODE (operands[1]) == PLUS)
07825 {
07826 rtx plus_op;
07827
07828 if (XEXP (operands[1], 0) == stack_pointer_rtx)
07829 plus_op = XEXP (operands[1], 1);
07830 else if (XEXP (operands[1], 1) == stack_pointer_rtx)
07831 plus_op = XEXP (operands[1], 0);
07832 else
07833 abort ();
07834
07835
07836 if (GET_CODE (plus_op) != REG)
07837 abort ();
07838
07839 if (REGNO (plus_op) < FIRST_PSEUDO_REGISTER)
07840 {
07841
07842
07843 if (! rtx_equal_p (plus_op, operands[0]))
07844 {
07845 emit_move_insn (operands[0], stack_pointer_rtx);
07846 emit_insn (gen_addsi3 (operands[0], operands[0], plus_op));
07847 }
07848 else if (! rtx_equal_p (plus_op, operands[2]))
07849 {
07850 emit_move_insn (operands[2], stack_pointer_rtx);
07851 emit_insn (gen_addsi3 (operands[0], plus_op, operands[2]));
07852 }
07853 else
07854 abort ();
07855 }
07856 else
07857 {
07858
07859 if (! rtx_equal_p (operands[0], operands[2]))
07860 {
07861 emit_move_insn (operands[0], stack_pointer_rtx);
07862 emit_move_insn (operands[2], plus_op);
07863 emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
07864 }
07865 else
07866 abort ();
07867 }
07868 DONE;
07869 }
07870
07871
07872 emit_move_insn (operands[0], operands[1]);
07873 DONE;
07874 }
07875 operand0 = operands[0];
07876 operand1 = operands[1];
07877 operand2 = operands[2];
07878 }
07879 emit_insn (gen_rtx_SET (VOIDmode,
07880 operand0,
07881 operand1));
07882 emit_insn (gen_rtx_CLOBBER (VOIDmode,
07883 operand2));
07884 _val = get_insns ();
07885 end_sequence ();
07886 return _val;
07887 }
07888
07889
07890 rtx
07891 gen_reload_incc (operand0, operand1, operand2)
07892 rtx operand0;
07893 rtx operand1;
07894 rtx operand2;
07895 {
07896 rtx _val = 0;
07897 start_sequence ();
07898 {
07899 rtx operands[3];
07900 operands[0] = operand0;
07901 operands[1] = operand1;
07902 operands[2] = operand2;
07903
07904 {
07905 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
07906 DONE;
07907 }
07908 operand0 = operands[0];
07909 operand1 = operands[1];
07910 operand2 = operands[2];
07911 }
07912 emit_insn (gen_rtx_SET (VOIDmode,
07913 operand0,
07914 operand1));
07915 emit_insn (gen_rtx_CLOBBER (VOIDmode,
07916 operand2));
07917 _val = get_insns ();
07918 end_sequence ();
07919 return _val;
07920 }
07921
07922
07923 rtx
07924 gen_reload_outcc (operand0, operand1, operand2)
07925 rtx operand0;
07926 rtx operand1;
07927 rtx operand2;
07928 {
07929 rtx _val = 0;
07930 start_sequence ();
07931 {
07932 rtx operands[3];
07933 operands[0] = operand0;
07934 operands[1] = operand1;
07935 operands[2] = operand2;
07936
07937 {
07938 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
07939 DONE;
07940 }
07941 operand0 = operands[0];
07942 operand1 = operands[1];
07943 operand2 = operands[2];
07944 }
07945 emit_insn (gen_rtx_SET (VOIDmode,
07946 operand0,
07947 operand1));
07948 emit_insn (gen_rtx_CLOBBER (VOIDmode,
07949 operand2));
07950 _val = get_insns ();
07951 end_sequence ();
07952 return _val;
07953 }
07954
07955
07956 rtx
07957 gen_movhi (operand0, operand1)
07958 rtx operand0;
07959 rtx operand1;
07960 {
07961 rtx _val = 0;
07962 start_sequence ();
07963 {
07964 rtx operands[2];
07965 operands[0] = operand0;
07966 operands[1] = operand1;
07967
07968 {
07969 if ((reload_in_progress | reload_completed) == 0
07970 && !register_operand (operands[0], HImode)
07971 && !register_operand (operands[1], HImode)
07972 && (TARGET_MIPS16
07973 || (GET_CODE (operands[1]) != CONST_INT
07974 || INTVAL (operands[1]) != 0)))
07975 {
07976 rtx temp = force_reg (HImode, operands[1]);
07977 emit_move_insn (operands[0], temp);
07978 DONE;
07979 }
07980 }
07981 operand0 = operands[0];
07982 operand1 = operands[1];
07983 }
07984 emit_insn (gen_rtx_SET (VOIDmode,
07985 operand0,
07986 operand1));
07987 _val = get_insns ();
07988 end_sequence ();
07989 return _val;
07990 }
07991
07992
07993 extern rtx gen_split_437 PARAMS ((rtx *));
07994 rtx
07995 gen_split_437 (operands)
07996 rtx *operands;
07997 {
07998 rtx operand0;
07999 rtx operand1;
08000 rtx operand2;
08001 rtx _val = 0;
08002 start_sequence ();
08003
08004 {
08005 HOST_WIDE_INT val = INTVAL (operands[1]);
08006
08007 if (val < 0)
08008 operands[2] = GEN_INT (0);
08009 else if (val >= 32 * 2)
08010 {
08011 int off = val & 1;
08012
08013 operands[1] = GEN_INT (0x7e + off);
08014 operands[2] = GEN_INT (val - off - 0x7e);
08015 }
08016 else
08017 {
08018 int off = val & 1;
08019
08020 operands[1] = GEN_INT (off);
08021 operands[2] = GEN_INT (val - off);
08022 }
08023 }
08024 operand0 = operands[0];
08025 operand1 = operands[1];
08026 operand2 = operands[2];
08027 emit_insn (gen_rtx_SET (VOIDmode,
08028 operand0,
08029 gen_rtx_PLUS (SImode,
08030 copy_rtx (operand0),
08031 operand1)));
08032 emit_insn (gen_rtx_SET (VOIDmode,
08033 copy_rtx (operand0),
08034 gen_rtx_MEM (HImode,
08035 gen_rtx_PLUS (SImode,
08036 copy_rtx (operand0),
08037 operand2))));
08038 _val = get_insns ();
08039 end_sequence ();
08040 return _val;
08041 }
08042
08043
08044 rtx
08045 gen_movqi (operand0, operand1)
08046 rtx operand0;
08047 rtx operand1;
08048 {
08049 rtx _val = 0;
08050 start_sequence ();
08051 {
08052 rtx operands[2];
08053 operands[0] = operand0;
08054 operands[1] = operand1;
08055
08056 {
08057 if ((reload_in_progress | reload_completed) == 0
08058 && !register_operand (operands[0], QImode)
08059 && !register_operand (operands[1], QImode)
08060 && (TARGET_MIPS16
08061 || (GET_CODE (operands[1]) != CONST_INT
08062 || INTVAL (operands[1]) != 0)))
08063 {
08064 rtx temp = force_reg (QImode, operands[1]);
08065 emit_move_insn (operands[0], temp);
08066 DONE;
08067 }
08068 }
08069 operand0 = operands[0];
08070 operand1 = operands[1];
08071 }
08072 emit_insn (gen_rtx_SET (VOIDmode,
08073 operand0,
08074 operand1));
08075 _val = get_insns ();
08076 end_sequence ();
08077 return _val;
08078 }
08079
08080
08081 extern rtx gen_split_439 PARAMS ((rtx *));
08082 rtx
08083 gen_split_439 (operands)
08084 rtx *operands;
08085 {
08086 rtx operand0;
08087 rtx operand1;
08088 rtx operand2;
08089 rtx _val = 0;
08090 start_sequence ();
08091
08092 {
08093 HOST_WIDE_INT val = INTVAL (operands[1]);
08094
08095 if (val < 0)
08096 operands[2] = GEN_INT (0);
08097 else
08098 {
08099 operands[1] = GEN_INT (0x7f);
08100 operands[2] = GEN_INT (val - 0x7f);
08101 }
08102 }
08103 operand0 = operands[0];
08104 operand1 = operands[1];
08105 operand2 = operands[2];
08106 emit_insn (gen_rtx_SET (VOIDmode,
08107 operand0,
08108 gen_rtx_PLUS (SImode,
08109 copy_rtx (operand0),
08110 operand1)));
08111 emit_insn (gen_rtx_SET (VOIDmode,
08112 copy_rtx (operand0),
08113 gen_rtx_MEM (QImode,
08114 gen_rtx_PLUS (SImode,
08115 copy_rtx (operand0),
08116 operand2))));
08117 _val = get_insns ();
08118 end_sequence ();
08119 return _val;
08120 }
08121
08122
08123 rtx
08124 gen_movsf (operand0, operand1)
08125 rtx operand0;
08126 rtx operand1;
08127 {
08128 rtx _val = 0;
08129 start_sequence ();
08130 {
08131 rtx operands[2];
08132 operands[0] = operand0;
08133 operands[1] = operand1;
08134
08135 {
08136 if ((reload_in_progress | reload_completed) == 0
08137 && !register_operand (operands[0], SFmode)
08138 && !nonmemory_operand (operands[1], SFmode))
08139 operands[1] = force_reg (SFmode, operands[1]);
08140 }
08141 operand0 = operands[0];
08142 operand1 = operands[1];
08143 }
08144 emit_insn (gen_rtx_SET (VOIDmode,
08145 operand0,
08146 operand1));
08147 _val = get_insns ();
08148 end_sequence ();
08149 return _val;
08150 }
08151
08152
08153 rtx
08154 gen_movdf (operand0, operand1)
08155 rtx operand0;
08156 rtx operand1;
08157 {
08158 rtx _val = 0;
08159 start_sequence ();
08160 {
08161 rtx operands[2];
08162 operands[0] = operand0;
08163 operands[1] = operand1;
08164
08165 {
08166 if ((reload_in_progress | reload_completed) == 0
08167 && !register_operand (operands[0], DFmode)
08168 && !nonmemory_operand (operands[1], DFmode))
08169 operands[1] = force_reg (DFmode, operands[1]);
08170 }
08171 operand0 = operands[0];
08172 operand1 = operands[1];
08173 }
08174 emit_insn (gen_rtx_SET (VOIDmode,
08175 operand0,
08176 operand1));
08177 _val = get_insns ();
08178 end_sequence ();
08179 return _val;
08180 }
08181
08182
08183 extern rtx gen_split_442 PARAMS ((rtx *));
08184 rtx
08185 gen_split_442 (operands)
08186 rtx *operands;
08187 {
08188 rtx operand0;
08189 rtx operand1;
08190 rtx _val = 0;
08191 start_sequence ();
08192
08193 operand0 = operands[0];
08194 operand1 = operands[1];
08195 emit_insn (gen_rtx_SET (VOIDmode,
08196 gen_rtx_SUBREG (SImode,
08197 operand0,
08198 0),
08199 gen_rtx_SUBREG (SImode,
08200 operand1,
08201 0)));
08202 emit_insn (gen_rtx_SET (VOIDmode,
08203 gen_rtx_SUBREG (SImode,
08204 copy_rtx (operand0),
08205 4),
08206 gen_rtx_SUBREG (SImode,
08207 copy_rtx (operand1),
08208 4)));
08209 _val = get_insns ();
08210 end_sequence ();
08211 return _val;
08212 }
08213
08214
08215 rtx
08216 gen_movstrsi (operand0, operand1, operand2, operand3)
08217 rtx operand0;
08218 rtx operand1;
08219 rtx operand2;
08220 rtx operand3;
08221 {
08222 rtx _val = 0;
08223 start_sequence ();
08224 {
08225 rtx operands[4];
08226 operands[0] = operand0;
08227 operands[1] = operand1;
08228 operands[2] = operand2;
08229 operands[3] = operand3;
08230
08231 {
08232 if (operands[0])
08233 {
08234 expand_block_move (operands);
08235 DONE;
08236 }
08237 }
08238 operand0 = operands[0];
08239 operand1 = operands[1];
08240 operand2 = operands[2];
08241 operand3 = operands[3];
08242 }
08243 emit (gen_rtx_PARALLEL (VOIDmode,
08244 gen_rtvec (3,
08245 gen_rtx_SET (VOIDmode,
08246 operand0,
08247 operand1),
08248 gen_rtx_USE (VOIDmode,
08249 operand2),
08250 gen_rtx_USE (VOIDmode,
08251 operand3))));
08252 _val = get_insns ();
08253 end_sequence ();
08254 return _val;
08255 }
08256
08257
08258 rtx
08259 gen_ashlsi3 (operand0, operand1, operand2)
08260 rtx operand0;
08261 rtx operand1;
08262 rtx operand2;
08263 {
08264 rtx _val = 0;
08265 start_sequence ();
08266 {
08267 rtx operands[3];
08268 operands[0] = operand0;
08269 operands[1] = operand1;
08270 operands[2] = operand2;
08271
08272 {
08273
08274
08275
08276
08277
08278
08279
08280 if (TARGET_MIPS16
08281 && optimize
08282 && GET_CODE (operands[2]) == CONST_INT
08283 && INTVAL (operands[2]) > 8
08284 && INTVAL (operands[2]) <= 16
08285 && ! reload_in_progress
08286 && ! reload_completed)
08287 {
08288 rtx temp = gen_reg_rtx (SImode);
08289
08290 emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
08291 emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
08292 GEN_INT (INTVAL (operands[2]) - 8)));
08293 DONE;
08294 }
08295 }
08296 operand0 = operands[0];
08297 operand1 = operands[1];
08298 operand2 = operands[2];
08299 }
08300 emit_insn (gen_rtx_SET (VOIDmode,
08301 operand0,
08302 gen_rtx_ASHIFT (SImode,
08303 operand1,
08304 operand2)));
08305 _val = get_insns ();
08306 end_sequence ();
08307 return _val;
08308 }
08309
08310
08311 extern rtx gen_split_445 PARAMS ((rtx *));
08312 rtx
08313 gen_split_445 (operands)
08314 rtx *operands;
08315 {
08316 rtx operand0;
08317 rtx operand1;
08318 rtx operand2;
08319 rtx _val = 0;
08320 start_sequence ();
08321
08322 {
08323 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
08324 }
08325 operand0 = operands[0];
08326 operand1 = operands[1];
08327 operand2 = operands[2];
08328 emit_insn (gen_rtx_SET (VOIDmode,
08329 operand0,
08330 gen_rtx_ASHIFT (SImode,
08331 operand1,
08332 GEN_INT (8LL))));
08333 emit_insn (gen_rtx_SET (VOIDmode,
08334 copy_rtx (operand0),
08335 gen_rtx_ASHIFT (SImode,
08336 copy_rtx (operand0),
08337 operand2)));
08338 _val = get_insns ();
08339 end_sequence ();
08340 return _val;
08341 }
08342
08343
08344 rtx
08345 gen_ashldi3 (operand0, operand1, operand2)
08346 rtx operand0;
08347 rtx operand1;
08348 rtx operand2;
08349 {
08350 rtx operand3;
08351 rtx _val = 0;
08352 start_sequence ();
08353 {
08354 rtx operands[4];
08355 operands[0] = operand0;
08356 operands[1] = operand1;
08357 operands[2] = operand2;
08358
08359 {
08360 if (TARGET_64BIT)
08361 {
08362
08363
08364
08365
08366
08367
08368
08369 if (TARGET_MIPS16
08370 && optimize
08371 && GET_CODE (operands[2]) == CONST_INT
08372 && INTVAL (operands[2]) > 8
08373 && INTVAL (operands[2]) <= 16
08374 && ! reload_in_progress
08375 && ! reload_completed)
08376 {
08377 rtx temp = gen_reg_rtx (DImode);
08378
08379 emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
08380 emit_insn (gen_ashldi3_internal4 (operands[0], temp,
08381 GEN_INT (INTVAL (operands[2]) - 8)));
08382 DONE;
08383 }
08384
08385 emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
08386 operands[2]));
08387 DONE;
08388 }
08389
08390 operands[3] = gen_reg_rtx (SImode);
08391 }
08392 operand0 = operands[0];
08393 operand1 = operands[1];
08394 operand2 = operands[2];
08395 operand3 = operands[3];
08396 }
08397 emit (gen_rtx_PARALLEL (VOIDmode,
08398 gen_rtvec (2,
08399 gen_rtx_SET (VOIDmode,
08400 operand0,
08401 gen_rtx_ASHIFT (DImode,
08402 operand1,
08403 operand2)),
08404 gen_rtx_CLOBBER (VOIDmode,
08405 operand3))));
08406 _val = get_insns ();
08407 end_sequence ();
08408 return _val;
08409 }
08410
08411
08412 extern rtx gen_split_447 PARAMS ((rtx *));
08413 rtx
08414 gen_split_447 (operands)
08415 rtx *operands;
08416 {
08417 rtx operand0;
08418 rtx operand1;
08419 rtx operand2;
08420 rtx _val = 0;
08421 start_sequence ();
08422 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
08423 operand0 = operands[0];
08424 operand1 = operands[1];
08425 operand2 = operands[2];
08426 emit_insn (gen_rtx_SET (VOIDmode,
08427 gen_rtx_SUBREG (SImode,
08428 operand0,
08429 4),
08430 gen_rtx_ASHIFT (SImode,
08431 gen_rtx_SUBREG (SImode,
08432 operand1,
08433 0),
08434 operand2)));
08435 emit_insn (gen_rtx_SET (VOIDmode,
08436 gen_rtx_SUBREG (SImode,
08437 copy_rtx (operand0),
08438 0),
08439 const0_rtx));
08440 _val = get_insns ();
08441 end_sequence ();
08442 return _val;
08443 }
08444
08445
08446 extern rtx gen_split_448 PARAMS ((rtx *));
08447 rtx
08448 gen_split_448 (operands)
08449 rtx *operands;
08450 {
08451 rtx operand0;
08452 rtx operand1;
08453 rtx operand2;
08454 rtx _val = 0;
08455 start_sequence ();
08456 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
08457 operand0 = operands[0];
08458 operand1 = operands[1];
08459 operand2 = operands[2];
08460 emit_insn (gen_rtx_SET (VOIDmode,
08461 gen_rtx_SUBREG (SImode,
08462 operand0,
08463 0),
08464 gen_rtx_ASHIFT (SImode,
08465 gen_rtx_SUBREG (SImode,
08466 operand1,
08467 4),
08468 operand2)));
08469 emit_insn (gen_rtx_SET (VOIDmode,
08470 gen_rtx_SUBREG (SImode,
08471 copy_rtx (operand0),
08472 4),
08473 const0_rtx));
08474 _val = get_insns ();
08475 end_sequence ();
08476 return _val;
08477 }
08478
08479
08480 extern rtx gen_split_449 PARAMS ((rtx *));
08481 rtx
08482 gen_split_449 (operands)
08483 rtx *operands;
08484 {
08485 rtx operand0;
08486 rtx operand1;
08487 rtx operand2;
08488 rtx operand3;
08489 rtx operand4;
08490 rtx _val = 0;
08491 start_sequence ();
08492
08493 {
08494 int amount = INTVAL (operands[2]);
08495 operands[2] = GEN_INT (amount & 31);
08496 operands[4] = GEN_INT ((-amount) & 31);
08497 }
08498 operand0 = operands[0];
08499 operand1 = operands[1];
08500 operand2 = operands[2];
08501 operand3 = operands[3];
08502 operand4 = operands[4];
08503 emit_insn (gen_rtx_SET (VOIDmode,
08504 gen_rtx_SUBREG (SImode,
08505 operand0,
08506 4),
08507 gen_rtx_ASHIFT (SImode,
08508 gen_rtx_SUBREG (SImode,
08509 operand1,
08510 4),
08511 operand2)));
08512 emit_insn (gen_rtx_SET (VOIDmode,
08513 operand3,
08514 gen_rtx_LSHIFTRT (SImode,
08515 gen_rtx_SUBREG (SImode,
08516 copy_rtx (operand1),
08517 0),
08518 operand4)));
08519 emit_insn (gen_rtx_SET (VOIDmode,
08520 gen_rtx_SUBREG (SImode,
08521 copy_rtx (operand0),
08522 4),
08523 gen_rtx_IOR (SImode,
08524 gen_rtx_SUBREG (SImode,
08525 copy_rtx (operand0),
08526 4),
08527 copy_rtx (operand3))));
08528 emit_insn (gen_rtx_SET (VOIDmode,
08529 gen_rtx_SUBREG (SImode,
08530 copy_rtx (operand0),
08531 0),
08532 gen_rtx_ASHIFT (SImode,
08533 gen_rtx_SUBREG (SImode,
08534 copy_rtx (operand1),
08535 0),
08536 copy_rtx (operand2))));
08537 _val = get_insns ();
08538 end_sequence ();
08539 return _val;
08540 }
08541
08542
08543 extern rtx gen_split_450 PARAMS ((rtx *));
08544 rtx
08545 gen_split_450 (operands)
08546 rtx *operands;
08547 {
08548 rtx operand0;
08549 rtx operand1;
08550 rtx operand2;
08551 rtx operand3;
08552 rtx operand4;
08553 rtx _val = 0;
08554 start_sequence ();
08555
08556 {
08557 int amount = INTVAL (operands[2]);
08558 operands[2] = GEN_INT (amount & 31);
08559 operands[4] = GEN_INT ((-amount) & 31);
08560 }
08561 operand0 = operands[0];
08562 operand1 = operands[1];
08563 operand2 = operands[2];
08564 operand3 = operands[3];
08565 operand4 = operands[4];
08566 emit_insn (gen_rtx_SET (VOIDmode,
08567 gen_rtx_SUBREG (SImode,
08568 operand0,
08569 0),
08570 gen_rtx_ASHIFT (SImode,
08571 gen_rtx_SUBREG (SImode,
08572 operand1,
08573 0),
08574 operand2)));
08575 emit_insn (gen_rtx_SET (VOIDmode,
08576 operand3,
08577 gen_rtx_LSHIFTRT (SImode,
08578 gen_rtx_SUBREG (SImode,
08579 copy_rtx (operand1),
08580 4),
08581 operand4)));
08582 emit_insn (gen_rtx_SET (VOIDmode,
08583 gen_rtx_SUBREG (SImode,
08584 copy_rtx (operand0),
08585 0),
08586 gen_rtx_IOR (SImode,
08587 gen_rtx_SUBREG (SImode,
08588 copy_rtx (operand0),
08589 0),
08590 copy_rtx (operand3))));
08591 emit_insn (gen_rtx_SET (VOIDmode,
08592 gen_rtx_SUBREG (SImode,
08593 copy_rtx (operand0),
08594 4),
08595 gen_rtx_ASHIFT (SImode,
08596 gen_rtx_SUBREG (SImode,
08597 copy_rtx (operand1),
08598 4),
08599 copy_rtx (operand2))));
08600 _val = get_insns ();
08601 end_sequence ();
08602 return _val;
08603 }
08604
08605
08606 extern rtx gen_split_451 PARAMS ((rtx *));
08607 rtx
08608 gen_split_451 (operands)
08609 rtx *operands;
08610 {
08611 rtx operand0;
08612 rtx operand1;
08613 rtx operand2;
08614 rtx _val = 0;
08615 start_sequence ();
08616
08617 {
08618 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
08619 }
08620 operand0 = operands[0];
08621 operand1 = operands[1];
08622 operand2 = operands[2];
08623 emit_insn (gen_rtx_SET (VOIDmode,
08624 operand0,
08625 gen_rtx_ASHIFT (DImode,
08626 operand1,
08627 GEN_INT (8LL))));
08628 emit_insn (gen_rtx_SET (VOIDmode,
08629 copy_rtx (operand0),
08630 gen_rtx_ASHIFT (DImode,
08631 copy_rtx (operand0),
08632 operand2)));
08633 _val = get_insns ();
08634 end_sequence ();
08635 return _val;
08636 }
08637
08638
08639 rtx
08640 gen_ashrsi3 (operand0, operand1, operand2)
08641 rtx operand0;
08642 rtx operand1;
08643 rtx operand2;
08644 {
08645 rtx _val = 0;
08646 start_sequence ();
08647 {
08648 rtx operands[3];
08649 operands[0] = operand0;
08650 operands[1] = operand1;
08651 operands[2] = operand2;
08652
08653 {
08654
08655
08656
08657
08658
08659 if (TARGET_MIPS16
08660 && optimize
08661 && GET_CODE (operands[2]) == CONST_INT
08662 && INTVAL (operands[2]) > 8
08663 && INTVAL (operands[2]) <= 16)
08664 {
08665 rtx temp = gen_reg_rtx (SImode);
08666
08667 emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
08668 emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
08669 GEN_INT (INTVAL (operands[2]) - 8)));
08670 DONE;
08671 }
08672 }
08673 operand0 = operands[0];
08674 operand1 = operands[1];
08675 operand2 = operands[2];
08676 }
08677 emit_insn (gen_rtx_SET (VOIDmode,
08678 operand0,
08679 gen_rtx_ASHIFTRT (SImode,
08680 operand1,
08681 operand2)));
08682 _val = get_insns ();
08683 end_sequence ();
08684 return _val;
08685 }
08686
08687
08688 extern rtx gen_split_453 PARAMS ((rtx *));
08689 rtx
08690 gen_split_453 (operands)
08691 rtx *operands;
08692 {
08693 rtx operand0;
08694 rtx operand1;
08695 rtx operand2;
08696 rtx _val = 0;
08697 start_sequence ();
08698
08699 {
08700 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
08701 }
08702 operand0 = operands[0];
08703 operand1 = operands[1];
08704 operand2 = operands[2];
08705 emit_insn (gen_rtx_SET (VOIDmode,
08706 operand0,
08707 gen_rtx_ASHIFTRT (SImode,
08708 operand1,
08709 GEN_INT (8LL))));
08710 emit_insn (gen_rtx_SET (VOIDmode,
08711 copy_rtx (operand0),
08712 gen_rtx_ASHIFTRT (SImode,
08713 copy_rtx (operand0),
08714 operand2)));
08715 _val = get_insns ();
08716 end_sequence ();
08717 return _val;
08718 }
08719
08720
08721 rtx
08722 gen_ashrdi3 (operand0, operand1, operand2)
08723 rtx operand0;
08724 rtx operand1;
08725 rtx operand2;
08726 {
08727 rtx operand3;
08728 rtx _val = 0;
08729 start_sequence ();
08730 {
08731 rtx operands[4];
08732 operands[0] = operand0;
08733 operands[1] = operand1;
08734 operands[2] = operand2;
08735
08736 {
08737 if (TARGET_64BIT)
08738 {
08739
08740
08741
08742
08743
08744 if (TARGET_MIPS16
08745 && optimize
08746 && GET_CODE (operands[2]) == CONST_INT
08747 && INTVAL (operands[2]) > 8
08748 && INTVAL (operands[2]) <= 16)
08749 {
08750 rtx temp = gen_reg_rtx (DImode);
08751
08752 emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
08753 emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
08754 GEN_INT (INTVAL (operands[2]) - 8)));
08755 DONE;
08756 }
08757
08758 emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
08759 operands[2]));
08760 DONE;
08761 }
08762
08763 operands[3] = gen_reg_rtx (SImode);
08764 }
08765 operand0 = operands[0];
08766 operand1 = operands[1];
08767 operand2 = operands[2];
08768 operand3 = operands[3];
08769 }
08770 emit (gen_rtx_PARALLEL (VOIDmode,
08771 gen_rtvec (2,
08772 gen_rtx_SET (VOIDmode,
08773 operand0,
08774 gen_rtx_ASHIFTRT (DImode,
08775 operand1,
08776 operand2)),
08777 gen_rtx_CLOBBER (VOIDmode,
08778 operand3))));
08779 _val = get_insns ();
08780 end_sequence ();
08781 return _val;
08782 }
08783
08784
08785 extern rtx gen_split_455 PARAMS ((rtx *));
08786 rtx
08787 gen_split_455 (operands)
08788 rtx *operands;
08789 {
08790 rtx operand0;
08791 rtx operand1;
08792 rtx operand2;
08793 rtx _val = 0;
08794 start_sequence ();
08795 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
08796 operand0 = operands[0];
08797 operand1 = operands[1];
08798 operand2 = operands[2];
08799 emit_insn (gen_rtx_SET (VOIDmode,
08800 gen_rtx_SUBREG (SImode,
08801 operand0,
08802 0),
08803 gen_rtx_ASHIFTRT (SImode,
08804 gen_rtx_SUBREG (SImode,
08805 operand1,
08806 4),
08807 operand2)));
08808 emit_insn (gen_rtx_SET (VOIDmode,
08809 gen_rtx_SUBREG (SImode,
08810 copy_rtx (operand0),
08811 4),
08812 gen_rtx_ASHIFTRT (SImode,
08813 gen_rtx_SUBREG (SImode,
08814 copy_rtx (operand1),
08815 4),
08816 GEN_INT (31LL))));
08817 _val = get_insns ();
08818 end_sequence ();
08819 return _val;
08820 }
08821
08822
08823 extern rtx gen_split_456 PARAMS ((rtx *));
08824 rtx
08825 gen_split_456 (operands)
08826 rtx *operands;
08827 {
08828 rtx operand0;
08829 rtx operand1;
08830 rtx operand2;
08831 rtx _val = 0;
08832 start_sequence ();
08833 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
08834 operand0 = operands[0];
08835 operand1 = operands[1];
08836 operand2 = operands[2];
08837 emit_insn (gen_rtx_SET (VOIDmode,
08838 gen_rtx_SUBREG (SImode,
08839 operand0,
08840 4),
08841 gen_rtx_ASHIFTRT (SImode,
08842 gen_rtx_SUBREG (SImode,
08843 operand1,
08844 0),
08845 operand2)));
08846 emit_insn (gen_rtx_SET (VOIDmode,
08847 gen_rtx_SUBREG (SImode,
08848 copy_rtx (operand0),
08849 0),
08850 gen_rtx_ASHIFTRT (SImode,
08851 gen_rtx_SUBREG (SImode,
08852 copy_rtx (operand1),
08853 0),
08854 GEN_INT (31LL))));
08855 _val = get_insns ();
08856 end_sequence ();
08857 return _val;
08858 }
08859
08860
08861 extern rtx gen_split_457 PARAMS ((rtx *));
08862 rtx
08863 gen_split_457 (operands)
08864 rtx *operands;
08865 {
08866 rtx operand0;
08867 rtx operand1;
08868 rtx operand2;
08869 rtx operand3;
08870 rtx operand4;
08871 rtx _val = 0;
08872 start_sequence ();
08873
08874 {
08875 int amount = INTVAL (operands[2]);
08876 operands[2] = GEN_INT (amount & 31);
08877 operands[4] = GEN_INT ((-amount) & 31);
08878 }
08879 operand0 = operands[0];
08880 operand1 = operands[1];
08881 operand2 = operands[2];
08882 operand3 = operands[3];
08883 operand4 = operands[4];
08884 emit_insn (gen_rtx_SET (VOIDmode,
08885 gen_rtx_SUBREG (SImode,
08886 operand0,
08887 0),
08888 gen_rtx_LSHIFTRT (SImode,
08889 gen_rtx_SUBREG (SImode,
08890 operand1,
08891 0),
08892 operand2)));
08893 emit_insn (gen_rtx_SET (VOIDmode,
08894 operand3,
08895 gen_rtx_ASHIFT (SImode,
08896 gen_rtx_SUBREG (SImode,
08897 copy_rtx (operand1),
08898 4),
08899 operand4)));
08900 emit_insn (gen_rtx_SET (VOIDmode,
08901 gen_rtx_SUBREG (SImode,
08902 copy_rtx (operand0),
08903 0),
08904 gen_rtx_IOR (SImode,
08905 gen_rtx_SUBREG (SImode,
08906 copy_rtx (operand0),
08907 0),
08908 copy_rtx (operand3))));
08909 emit_insn (gen_rtx_SET (VOIDmode,
08910 gen_rtx_SUBREG (SImode,
08911 copy_rtx (operand0),
08912 4),
08913 gen_rtx_ASHIFTRT (SImode,
08914 gen_rtx_SUBREG (SImode,
08915 copy_rtx (operand1),
08916 4),
08917 copy_rtx (operand2))));
08918 _val = get_insns ();
08919 end_sequence ();
08920 return _val;
08921 }
08922
08923
08924 extern rtx gen_split_458 PARAMS ((rtx *));
08925 rtx
08926 gen_split_458 (operands)
08927 rtx *operands;
08928 {
08929 rtx operand0;
08930 rtx operand1;
08931 rtx operand2;
08932 rtx operand3;
08933 rtx operand4;
08934 rtx _val = 0;
08935 start_sequence ();
08936
08937 {
08938 int amount = INTVAL (operands[2]);
08939 operands[2] = GEN_INT (amount & 31);
08940 operands[4] = GEN_INT ((-amount) & 31);
08941 }
08942 operand0 = operands[0];
08943 operand1 = operands[1];
08944 operand2 = operands[2];
08945 operand3 = operands[3];
08946 operand4 = operands[4];
08947 emit_insn (gen_rtx_SET (VOIDmode,
08948 gen_rtx_SUBREG (SImode,
08949 operand0,
08950 4),
08951 gen_rtx_LSHIFTRT (SImode,
08952 gen_rtx_SUBREG (SImode,
08953 operand1,
08954 4),
08955 operand2)));
08956 emit_insn (gen_rtx_SET (VOIDmode,
08957 operand3,
08958 gen_rtx_ASHIFT (SImode,
08959 gen_rtx_SUBREG (SImode,
08960 copy_rtx (operand1),
08961 0),
08962 operand4)));
08963 emit_insn (gen_rtx_SET (VOIDmode,
08964 gen_rtx_SUBREG (SImode,
08965 copy_rtx (operand0),
08966 4),
08967 gen_rtx_IOR (SImode,
08968 gen_rtx_SUBREG (SImode,
08969 copy_rtx (operand0),
08970 4),
08971 copy_rtx (operand3))));
08972 emit_insn (gen_rtx_SET (VOIDmode,
08973 gen_rtx_SUBREG (SImode,
08974 copy_rtx (operand0),
08975 0),
08976 gen_rtx_ASHIFTRT (SImode,
08977 gen_rtx_SUBREG (SImode,
08978 copy_rtx (operand1),
08979 0),
08980 copy_rtx (operand2))));
08981 _val = get_insns ();
08982 end_sequence ();
08983 return _val;
08984 }
08985
08986
08987 extern rtx gen_split_459 PARAMS ((rtx *));
08988 rtx
08989 gen_split_459 (operands)
08990 rtx *operands;
08991 {
08992 rtx operand0;
08993 rtx operand1;
08994 rtx operand2;
08995 rtx _val = 0;
08996 start_sequence ();
08997
08998 {
08999 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
09000 }
09001 operand0 = operands[0];
09002 operand1 = operands[1];
09003 operand2 = operands[2];
09004 emit_insn (gen_rtx_SET (VOIDmode,
09005 operand0,
09006 gen_rtx_ASHIFTRT (DImode,
09007 operand1,
09008 GEN_INT (8LL))));
09009 emit_insn (gen_rtx_SET (VOIDmode,
09010 copy_rtx (operand0),
09011 gen_rtx_ASHIFTRT (DImode,
09012 copy_rtx (operand0),
09013 operand2)));
09014 _val = get_insns ();
09015 end_sequence ();
09016 return _val;
09017 }
09018
09019
09020 rtx
09021 gen_lshrsi3 (operand0, operand1, operand2)
09022 rtx operand0;
09023 rtx operand1;
09024 rtx operand2;
09025 {
09026 rtx _val = 0;
09027 start_sequence ();
09028 {
09029 rtx operands[3];
09030 operands[0] = operand0;
09031 operands[1] = operand1;
09032 operands[2] = operand2;
09033
09034 {
09035
09036
09037
09038
09039
09040 if (TARGET_MIPS16
09041 && optimize
09042 && GET_CODE (operands[2]) == CONST_INT
09043 && INTVAL (operands[2]) > 8
09044 && INTVAL (operands[2]) <= 16)
09045 {
09046 rtx temp = gen_reg_rtx (SImode);
09047
09048 emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
09049 emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
09050 GEN_INT (INTVAL (operands[2]) - 8)));
09051 DONE;
09052 }
09053 }
09054 operand0 = operands[0];
09055 operand1 = operands[1];
09056 operand2 = operands[2];
09057 }
09058 emit_insn (gen_rtx_SET (VOIDmode,
09059 operand0,
09060 gen_rtx_LSHIFTRT (SImode,
09061 operand1,
09062 operand2)));
09063 _val = get_insns ();
09064 end_sequence ();
09065 return _val;
09066 }
09067
09068
09069 extern rtx gen_split_461 PARAMS ((rtx *));
09070 rtx
09071 gen_split_461 (operands)
09072 rtx *operands;
09073 {
09074 rtx operand0;
09075 rtx operand1;
09076 rtx operand2;
09077 rtx _val = 0;
09078 start_sequence ();
09079
09080 {
09081 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
09082 }
09083 operand0 = operands[0];
09084 operand1 = operands[1];
09085 operand2 = operands[2];
09086 emit_insn (gen_rtx_SET (VOIDmode,
09087 operand0,
09088 gen_rtx_LSHIFTRT (SImode,
09089 operand1,
09090 GEN_INT (8LL))));
09091 emit_insn (gen_rtx_SET (VOIDmode,
09092 copy_rtx (operand0),
09093 gen_rtx_LSHIFTRT (SImode,
09094 copy_rtx (operand0),
09095 operand2)));
09096 _val = get_insns ();
09097 end_sequence ();
09098 return _val;
09099 }
09100
09101
09102 extern rtx gen_split_462 PARAMS ((rtx *));
09103 rtx
09104 gen_split_462 (operands)
09105 rtx *operands;
09106 {
09107 rtx operand0;
09108 rtx operand1;
09109 rtx operand2;
09110 rtx _val = 0;
09111 start_sequence ();
09112
09113 operand0 = operands[0];
09114 operand1 = operands[1];
09115 operand2 = operands[2];
09116 emit_insn (gen_rtx_SET (VOIDmode,
09117 operand0,
09118 operand1));
09119 emit_insn (gen_rtx_SET (VOIDmode,
09120 copy_rtx (operand0),
09121 gen_rtx_LSHIFTRT (SImode,
09122 copy_rtx (operand0),
09123 operand2)));
09124 _val = get_insns ();
09125 end_sequence ();
09126 return _val;
09127 }
09128
09129
09130 rtx
09131 gen_lshrdi3 (operand0, operand1, operand2)
09132 rtx operand0;
09133 rtx operand1;
09134 rtx operand2;
09135 {
09136 rtx operand3;
09137 rtx _val = 0;
09138 start_sequence ();
09139 {
09140 rtx operands[4];
09141 operands[0] = operand0;
09142 operands[1] = operand1;
09143 operands[2] = operand2;
09144
09145 {
09146 if (TARGET_64BIT)
09147 {
09148
09149
09150
09151
09152
09153 if (TARGET_MIPS16
09154 && optimize
09155 && GET_CODE (operands[2]) == CONST_INT
09156 && INTVAL (operands[2]) > 8
09157 && INTVAL (operands[2]) <= 16)
09158 {
09159 rtx temp = gen_reg_rtx (DImode);
09160
09161 emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
09162 emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
09163 GEN_INT (INTVAL (operands[2]) - 8)));
09164 DONE;
09165 }
09166
09167 emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
09168 operands[2]));
09169 DONE;
09170 }
09171
09172 operands[3] = gen_reg_rtx (SImode);
09173 }
09174 operand0 = operands[0];
09175 operand1 = operands[1];
09176 operand2 = operands[2];
09177 operand3 = operands[3];
09178 }
09179 emit (gen_rtx_PARALLEL (VOIDmode,
09180 gen_rtvec (2,
09181 gen_rtx_SET (VOIDmode,
09182 operand0,
09183 gen_rtx_LSHIFTRT (DImode,
09184 operand1,
09185 operand2)),
09186 gen_rtx_CLOBBER (VOIDmode,
09187 operand3))));
09188 _val = get_insns ();
09189 end_sequence ();
09190 return _val;
09191 }
09192
09193
09194 extern rtx gen_split_464 PARAMS ((rtx *));
09195 rtx
09196 gen_split_464 (operands)
09197 rtx *operands;
09198 {
09199 rtx operand0;
09200 rtx operand1;
09201 rtx operand2;
09202 rtx _val = 0;
09203 start_sequence ();
09204 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
09205 operand0 = operands[0];
09206 operand1 = operands[1];
09207 operand2 = operands[2];
09208 emit_insn (gen_rtx_SET (VOIDmode,
09209 gen_rtx_SUBREG (SImode,
09210 operand0,
09211 0),
09212 gen_rtx_LSHIFTRT (SImode,
09213 gen_rtx_SUBREG (SImode,
09214 operand1,
09215 4),
09216 operand2)));
09217 emit_insn (gen_rtx_SET (VOIDmode,
09218 gen_rtx_SUBREG (SImode,
09219 copy_rtx (operand0),
09220 4),
09221 const0_rtx));
09222 _val = get_insns ();
09223 end_sequence ();
09224 return _val;
09225 }
09226
09227
09228 extern rtx gen_split_465 PARAMS ((rtx *));
09229 rtx
09230 gen_split_465 (operands)
09231 rtx *operands;
09232 {
09233 rtx operand0;
09234 rtx operand1;
09235 rtx operand2;
09236 rtx _val = 0;
09237 start_sequence ();
09238 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
09239 operand0 = operands[0];
09240 operand1 = operands[1];
09241 operand2 = operands[2];
09242 emit_insn (gen_rtx_SET (VOIDmode,
09243 gen_rtx_SUBREG (SImode,
09244 operand0,
09245 4),
09246 gen_rtx_LSHIFTRT (SImode,
09247 gen_rtx_SUBREG (SImode,
09248 operand1,
09249 0),
09250 operand2)));
09251 emit_insn (gen_rtx_SET (VOIDmode,
09252 gen_rtx_SUBREG (SImode,
09253 copy_rtx (operand0),
09254 0),
09255 const0_rtx));
09256 _val = get_insns ();
09257 end_sequence ();
09258 return _val;
09259 }
09260
09261
09262 extern rtx gen_split_466 PARAMS ((rtx *));
09263 rtx
09264 gen_split_466 (operands)
09265 rtx *operands;
09266 {
09267 rtx operand0;
09268 rtx operand1;
09269 rtx operand2;
09270 rtx operand3;
09271 rtx operand4;
09272 rtx _val = 0;
09273 start_sequence ();
09274
09275 {
09276 int amount = INTVAL (operands[2]);
09277 operands[2] = GEN_INT (amount & 31);
09278 operands[4] = GEN_INT ((-amount) & 31);
09279 }
09280 operand0 = operands[0];
09281 operand1 = operands[1];
09282 operand2 = operands[2];
09283 operand3 = operands[3];
09284 operand4 = operands[4];
09285 emit_insn (gen_rtx_SET (VOIDmode,
09286 gen_rtx_SUBREG (SImode,
09287 operand0,
09288 0),
09289 gen_rtx_LSHIFTRT (SImode,
09290 gen_rtx_SUBREG (SImode,
09291 operand1,
09292 0),
09293 operand2)));
09294 emit_insn (gen_rtx_SET (VOIDmode,
09295 operand3,
09296 gen_rtx_ASHIFT (SImode,
09297 gen_rtx_SUBREG (SImode,
09298 copy_rtx (operand1),
09299 4),
09300 operand4)));
09301 emit_insn (gen_rtx_SET (VOIDmode,
09302 gen_rtx_SUBREG (SImode,
09303 copy_rtx (operand0),
09304 0),
09305 gen_rtx_IOR (SImode,
09306 gen_rtx_SUBREG (SImode,
09307 copy_rtx (operand0),
09308 0),
09309 copy_rtx (operand3))));
09310 emit_insn (gen_rtx_SET (VOIDmode,
09311 gen_rtx_SUBREG (SImode,
09312 copy_rtx (operand0),
09313 4),
09314 gen_rtx_LSHIFTRT (SImode,
09315 gen_rtx_SUBREG (SImode,
09316 copy_rtx (operand1),
09317 4),
09318 copy_rtx (operand2))));
09319 _val = get_insns ();
09320 end_sequence ();
09321 return _val;
09322 }
09323
09324
09325 extern rtx gen_split_467 PARAMS ((rtx *));
09326 rtx
09327 gen_split_467 (operands)
09328 rtx *operands;
09329 {
09330 rtx operand0;
09331 rtx operand1;
09332 rtx operand2;
09333 rtx operand3;
09334 rtx operand4;
09335 rtx _val = 0;
09336 start_sequence ();
09337
09338 {
09339 int amount = INTVAL (operands[2]);
09340 operands[2] = GEN_INT (amount & 31);
09341 operands[4] = GEN_INT ((-amount) & 31);
09342 }
09343 operand0 = operands[0];
09344 operand1 = operands[1];
09345 operand2 = operands[2];
09346 operand3 = operands[3];
09347 operand4 = operands[4];
09348 emit_insn (gen_rtx_SET (VOIDmode,
09349 gen_rtx_SUBREG (SImode,
09350 operand0,
09351 4),
09352 gen_rtx_LSHIFTRT (SImode,
09353 gen_rtx_SUBREG (SImode,
09354 operand1,
09355 4),
09356 operand2)));
09357 emit_insn (gen_rtx_SET (VOIDmode,
09358 operand3,
09359 gen_rtx_ASHIFT (SImode,
09360 gen_rtx_SUBREG (SImode,
09361 copy_rtx (operand1),
09362 0),
09363 operand4)));
09364 emit_insn (gen_rtx_SET (VOIDmode,
09365 gen_rtx_SUBREG (SImode,
09366 copy_rtx (operand0),
09367 4),
09368 gen_rtx_IOR (SImode,
09369 gen_rtx_SUBREG (SImode,
09370 copy_rtx (operand0),
09371 4),
09372 copy_rtx (operand3))));
09373 emit_insn (gen_rtx_SET (VOIDmode,
09374 gen_rtx_SUBREG (SImode,
09375 copy_rtx (operand0),
09376 0),
09377 gen_rtx_LSHIFTRT (SImode,
09378 gen_rtx_SUBREG (SImode,
09379 copy_rtx (operand1),
09380 0),
09381 copy_rtx (operand2))));
09382 _val = get_insns ();
09383 end_sequence ();
09384 return _val;
09385 }
09386
09387
09388 extern rtx gen_split_468 PARAMS ((rtx *));
09389 rtx
09390 gen_split_468 (operands)
09391 rtx *operands;
09392 {
09393 rtx operand0;
09394 rtx operand1;
09395 rtx operand2;
09396 rtx _val = 0;
09397 start_sequence ();
09398
09399 {
09400 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
09401 }
09402 operand0 = operands[0];
09403 operand1 = operands[1];
09404 operand2 = operands[2];
09405 emit_insn (gen_rtx_SET (VOIDmode,
09406 operand0,
09407 gen_rtx_LSHIFTRT (DImode,
09408 operand1,
09409 GEN_INT (8LL))));
09410 emit_insn (gen_rtx_SET (VOIDmode,
09411 copy_rtx (operand0),
09412 gen_rtx_LSHIFTRT (DImode,
09413 copy_rtx (operand0),
09414 operand2)));
09415 _val = get_insns ();
09416 end_sequence ();
09417 return _val;
09418 }
09419
09420
09421 rtx
09422 gen_cmpsi (operand0, operand1)
09423 rtx operand0;
09424 rtx operand1;
09425 {
09426 rtx _val = 0;
09427 start_sequence ();
09428 {
09429 rtx operands[2];
09430 operands[0] = operand0;
09431 operands[1] = operand1;
09432
09433 {
09434 if (operands[0])
09435 {
09436 branch_cmp[0] = operands[0];
09437 branch_cmp[1] = operands[1];
09438 branch_type = CMP_SI;
09439 DONE;
09440 }
09441 }
09442 operand0 = operands[0];
09443 operand1 = operands[1];
09444 }
09445 emit_insn (gen_rtx_SET (VOIDmode,
09446 cc0_rtx,
09447 gen_rtx_COMPARE (CCmode,
09448 operand0,
09449 operand1)));
09450 _val = get_insns ();
09451 end_sequence ();
09452 return _val;
09453 }
09454
09455
09456 rtx
09457 gen_tstsi (operand0)
09458 rtx operand0;
09459 {
09460 rtx _val = 0;
09461 start_sequence ();
09462 {
09463 rtx operands[1];
09464 operands[0] = operand0;
09465
09466 {
09467 if (operands[0])
09468 {
09469 branch_cmp[0] = operands[0];
09470 branch_cmp[1] = const0_rtx;
09471 branch_type = CMP_SI;
09472 DONE;
09473 }
09474 }
09475 operand0 = operands[0];
09476 }
09477 emit_insn (gen_rtx_SET (VOIDmode,
09478 cc0_rtx,
09479 operand0));
09480 _val = get_insns ();
09481 end_sequence ();
09482 return _val;
09483 }
09484
09485
09486 rtx
09487 gen_cmpdi (operand0, operand1)
09488 rtx operand0;
09489 rtx operand1;
09490 {
09491 rtx _val = 0;
09492 start_sequence ();
09493 {
09494 rtx operands[2];
09495 operands[0] = operand0;
09496 operands[1] = operand1;
09497
09498 {
09499 if (operands[0])
09500 {
09501 branch_cmp[0] = operands[0];
09502 branch_cmp[1] = operands[1];
09503 branch_type = CMP_DI;
09504 DONE;
09505 }
09506 }
09507 operand0 = operands[0];
09508 operand1 = operands[1];
09509 }
09510 emit_insn (gen_rtx_SET (VOIDmode,
09511 cc0_rtx,
09512 gen_rtx_COMPARE (CCmode,
09513 operand0,
09514 operand1)));
09515 _val = get_insns ();
09516 end_sequence ();
09517 return _val;
09518 }
09519
09520
09521 rtx
09522 gen_tstdi (operand0)
09523 rtx operand0;
09524 {
09525 rtx _val = 0;
09526 start_sequence ();
09527 {
09528 rtx operands[1];
09529 operands[0] = operand0;
09530
09531 {
09532 if (operands[0])
09533 {
09534 branch_cmp[0] = operands[0];
09535 branch_cmp[1] = const0_rtx;
09536 branch_type = CMP_DI;
09537 DONE;
09538 }
09539 }
09540 operand0 = operands[0];
09541 }
09542 emit_insn (gen_rtx_SET (VOIDmode,
09543 cc0_rtx,
09544 operand0));
09545 _val = get_insns ();
09546 end_sequence ();
09547 return _val;
09548 }
09549
09550
09551 rtx
09552 gen_cmpdf (operand0, operand1)
09553 rtx operand0;
09554 rtx operand1;
09555 {
09556 rtx _val = 0;
09557 start_sequence ();
09558 {
09559 rtx operands[2];
09560 operands[0] = operand0;
09561 operands[1] = operand1;
09562
09563 {
09564 if (operands[0])
09565 {
09566 branch_cmp[0] = operands[0];
09567 branch_cmp[1] = operands[1];
09568 branch_type = CMP_DF;
09569 DONE;
09570 }
09571 }
09572 operand0 = operands[0];
09573 operand1 = operands[1];
09574 }
09575 emit_insn (gen_rtx_SET (VOIDmode,
09576 cc0_rtx,
09577 gen_rtx_COMPARE (CCmode,
09578 operand0,
09579 operand1)));
09580 _val = get_insns ();
09581 end_sequence ();
09582 return _val;
09583 }
09584
09585
09586 rtx
09587 gen_cmpsf (operand0, operand1)
09588 rtx operand0;
09589 rtx operand1;
09590 {
09591 rtx _val = 0;
09592 start_sequence ();
09593 {
09594 rtx operands[2];
09595 operands[0] = operand0;
09596 operands[1] = operand1;
09597
09598 {
09599 if (operands[0])
09600 {
09601 branch_cmp[0] = operands[0];
09602 branch_cmp[1] = operands[1];
09603 branch_type = CMP_SF;
09604 DONE;
09605 }
09606 }
09607 operand0 = operands[0];
09608 operand1 = operands[1];
09609 }
09610 emit_insn (gen_rtx_SET (VOIDmode,
09611 cc0_rtx,
09612 gen_rtx_COMPARE (CCmode,
09613 operand0,
09614 operand1)));
09615 _val = get_insns ();
09616 end_sequence ();
09617 return _val;
09618 }
09619
09620
09621 rtx
09622 gen_bunordered (operand0)
09623 rtx operand0;
09624 {
09625 rtx _val = 0;
09626 start_sequence ();
09627 {
09628 rtx operands[1];
09629 operands[0] = operand0;
09630
09631 {
09632 if (operands[0])
09633 {
09634 gen_conditional_branch (operands, UNORDERED);
09635 DONE;
09636 }
09637 }
09638 operand0 = operands[0];
09639 }
09640 emit_jump_insn (gen_rtx_SET (VOIDmode,
09641 pc_rtx,
09642 gen_rtx_IF_THEN_ELSE (VOIDmode,
09643 gen_rtx_UNORDERED (CCmode,
09644 cc0_rtx,
09645 const0_rtx),
09646 gen_rtx_LABEL_REF (VOIDmode,
09647 operand0),
09648 pc_rtx)));
09649 _val = get_insns ();
09650 end_sequence ();
09651 return _val;
09652 }
09653
09654
09655 rtx
09656 gen_bordered (operand0)
09657 rtx operand0;
09658 {
09659 rtx _val = 0;
09660 start_sequence ();
09661 {
09662 rtx operands[1];
09663 operands[0] = operand0;
09664
09665 {
09666 if (operands[0])
09667 {
09668 gen_conditional_branch (operands, ORDERED);
09669 DONE;
09670 }
09671 }
09672 operand0 = operands[0];
09673 }
09674 emit_jump_insn (gen_rtx_SET (VOIDmode,
09675 pc_rtx,
09676 gen_rtx_IF_THEN_ELSE (VOIDmode,
09677 gen_rtx_ORDERED (CCmode,
09678 cc0_rtx,
09679 const0_rtx),
09680 gen_rtx_LABEL_REF (VOIDmode,
09681 operand0),
09682 pc_rtx)));
09683 _val = get_insns ();
09684 end_sequence ();
09685 return _val;
09686 }
09687
09688
09689 rtx
09690 gen_bunlt (operand0)
09691 rtx operand0;
09692 {
09693 rtx _val = 0;
09694 start_sequence ();
09695 {
09696 rtx operands[1];
09697 operands[0] = operand0;
09698
09699 {
09700 if (operands[0])
09701 {
09702 gen_conditional_branch (operands, UNLT);
09703 DONE;
09704 }
09705 }
09706 operand0 = operands[0];
09707 }
09708 emit_jump_insn (gen_rtx_SET (VOIDmode,
09709 pc_rtx,
09710 gen_rtx_IF_THEN_ELSE (VOIDmode,
09711 gen_rtx_UNLT (CCmode,
09712 cc0_rtx,
09713 const0_rtx),
09714 gen_rtx_LABEL_REF (VOIDmode,
09715 operand0),
09716 pc_rtx)));
09717 _val = get_insns ();
09718 end_sequence ();
09719 return _val;
09720 }
09721
09722
09723 rtx
09724 gen_bunge (operand0)
09725 rtx operand0;
09726 {
09727 rtx _val = 0;
09728 start_sequence ();
09729 {
09730 rtx operands[1];
09731 operands[0] = operand0;
09732
09733 {
09734 gen_conditional_branch (operands, UNGE);
09735 DONE;
09736 }
09737 operand0 = operands[0];
09738 }
09739 emit_jump_insn (gen_rtx_SET (VOIDmode,
09740 pc_rtx,
09741 gen_rtx_IF_THEN_ELSE (VOIDmode,
09742 gen_rtx_UNGE (CCmode,
09743 cc0_rtx,
09744 const0_rtx),
09745 gen_rtx_LABEL_REF (VOIDmode,
09746 operand0),
09747 pc_rtx)));
09748 _val = get_insns ();
09749 end_sequence ();
09750 return _val;
09751 }
09752
09753
09754 rtx
09755 gen_buneq (operand0)
09756 rtx operand0;
09757 {
09758 rtx _val = 0;
09759 start_sequence ();
09760 {
09761 rtx operands[1];
09762 operands[0] = operand0;
09763
09764 {
09765 if (operands[0])
09766 {
09767 gen_conditional_branch (operands, UNEQ);
09768 DONE;
09769 }
09770 }
09771 operand0 = operands[0];
09772 }
09773 emit_jump_insn (gen_rtx_SET (VOIDmode,
09774 pc_rtx,
09775 gen_rtx_IF_THEN_ELSE (VOIDmode,
09776 gen_rtx_UNEQ (CCmode,
09777 cc0_rtx,
09778 const0_rtx),
09779 gen_rtx_LABEL_REF (VOIDmode,
09780 operand0),
09781 pc_rtx)));
09782 _val = get_insns ();
09783 end_sequence ();
09784 return _val;
09785 }
09786
09787
09788 rtx
09789 gen_bltgt (operand0)
09790 rtx operand0;
09791 {
09792 rtx _val = 0;
09793 start_sequence ();
09794 {
09795 rtx operands[1];
09796 operands[0] = operand0;
09797
09798 {
09799 gen_conditional_branch (operands, LTGT);
09800 DONE;
09801 }
09802 operand0 = operands[0];
09803 }
09804 emit_jump_insn (gen_rtx_SET (VOIDmode,
09805 pc_rtx,
09806 gen_rtx_IF_THEN_ELSE (VOIDmode,
09807 gen_rtx_LTGT (CCmode,
09808 cc0_rtx,
09809 const0_rtx),
09810 gen_rtx_LABEL_REF (VOIDmode,
09811 operand0),
09812 pc_rtx)));
09813 _val = get_insns ();
09814 end_sequence ();
09815 return _val;
09816 }
09817
09818
09819 rtx
09820 gen_bunle (operand0)
09821 rtx operand0;
09822 {
09823 rtx _val = 0;
09824 start_sequence ();
09825 {
09826 rtx operands[1];
09827 operands[0] = operand0;
09828
09829 {
09830 if (operands[0])
09831 {
09832 gen_conditional_branch (operands, UNLE);
09833 DONE;
09834 }
09835 }
09836 operand0 = operands[0];
09837 }
09838 emit_jump_insn (gen_rtx_SET (VOIDmode,
09839 pc_rtx,
09840 gen_rtx_IF_THEN_ELSE (VOIDmode,
09841 gen_rtx_UNLE (CCmode,
09842 cc0_rtx,
09843 const0_rtx),
09844 gen_rtx_LABEL_REF (VOIDmode,
09845 operand0),
09846 pc_rtx)));
09847 _val = get_insns ();
09848 end_sequence ();
09849 return _val;
09850 }
09851
09852
09853 rtx
09854 gen_bungt (operand0)
09855 rtx operand0;
09856 {
09857 rtx _val = 0;
09858 start_sequence ();
09859 {
09860 rtx operands[1];
09861 operands[0] = operand0;
09862
09863 {
09864 gen_conditional_branch (operands, UNGT);
09865 DONE;
09866 }
09867 operand0 = operands[0];
09868 }
09869 emit_jump_insn (gen_rtx_SET (VOIDmode,
09870 pc_rtx,
09871 gen_rtx_IF_THEN_ELSE (VOIDmode,
09872 gen_rtx_UNGT (CCmode,
09873 cc0_rtx,
09874 const0_rtx),
09875 gen_rtx_LABEL_REF (VOIDmode,
09876 operand0),
09877 pc_rtx)));
09878 _val = get_insns ();
09879 end_sequence ();
09880 return _val;
09881 }
09882
09883
09884 rtx
09885 gen_beq (operand0)
09886 rtx operand0;
09887 {
09888 rtx _val = 0;
09889 start_sequence ();
09890 {
09891 rtx operands[1];
09892 operands[0] = operand0;
09893
09894 {
09895 if (operands[0])
09896 {
09897 gen_conditional_branch (operands, EQ);
09898 DONE;
09899 }
09900 }
09901 operand0 = operands[0];
09902 }
09903 emit_jump_insn (gen_rtx_SET (VOIDmode,
09904 pc_rtx,
09905 gen_rtx_IF_THEN_ELSE (VOIDmode,
09906 gen_rtx_EQ (CCmode,
09907 cc0_rtx,
09908 const0_rtx),
09909 gen_rtx_LABEL_REF (VOIDmode,
09910 operand0),
09911 pc_rtx)));
09912 _val = get_insns ();
09913 end_sequence ();
09914 return _val;
09915 }
09916
09917
09918 rtx
09919 gen_bne (operand0)
09920 rtx operand0;
09921 {
09922 rtx _val = 0;
09923 start_sequence ();
09924 {
09925 rtx operands[1];
09926 operands[0] = operand0;
09927
09928 {
09929 if (operands[0])
09930 {
09931 gen_conditional_branch (operands, NE);
09932 DONE;
09933 }
09934 }
09935 operand0 = operands[0];
09936 }
09937 emit_jump_insn (gen_rtx_SET (VOIDmode,
09938 pc_rtx,
09939 gen_rtx_IF_THEN_ELSE (VOIDmode,
09940 gen_rtx_NE (CCmode,
09941 cc0_rtx,
09942 const0_rtx),
09943 gen_rtx_LABEL_REF (VOIDmode,
09944 operand0),
09945 pc_rtx)));
09946 _val = get_insns ();
09947 end_sequence ();
09948 return _val;
09949 }
09950
09951
09952 rtx
09953 gen_bgt (operand0)
09954 rtx operand0;
09955 {
09956 rtx _val = 0;
09957 start_sequence ();
09958 {
09959 rtx operands[1];
09960 operands[0] = operand0;
09961
09962 {
09963 if (operands[0])
09964 {
09965 gen_conditional_branch (operands, GT);
09966 DONE;
09967 }
09968 }
09969 operand0 = operands[0];
09970 }
09971 emit_jump_insn (gen_rtx_SET (VOIDmode,
09972 pc_rtx,
09973 gen_rtx_IF_THEN_ELSE (VOIDmode,
09974 gen_rtx_GT (CCmode,
09975 cc0_rtx,
09976 const0_rtx),
09977 gen_rtx_LABEL_REF (VOIDmode,
09978 operand0),
09979 pc_rtx)));
09980 _val = get_insns ();
09981 end_sequence ();
09982 return _val;
09983 }
09984
09985
09986 rtx
09987 gen_bge (operand0)
09988 rtx operand0;
09989 {
09990 rtx _val = 0;
09991 start_sequence ();
09992 {
09993 rtx operands[1];
09994 operands[0] = operand0;
09995
09996 {
09997 if (operands[0])
09998 {
09999 gen_conditional_branch (operands, GE);
10000 DONE;
10001 }
10002 }
10003 operand0 = operands[0];
10004 }
10005 emit_jump_insn (gen_rtx_SET (VOIDmode,
10006 pc_rtx,
10007 gen_rtx_IF_THEN_ELSE (VOIDmode,
10008 gen_rtx_GE (CCmode,
10009 cc0_rtx,
10010 const0_rtx),
10011 gen_rtx_LABEL_REF (VOIDmode,
10012 operand0),
10013 pc_rtx)));
10014 _val = get_insns ();
10015 end_sequence ();
10016 return _val;
10017 }
10018
10019
10020 rtx
10021 gen_blt (operand0)
10022 rtx operand0;
10023 {
10024 rtx _val = 0;
10025 start_sequence ();
10026 {
10027 rtx operands[1];
10028 operands[0] = operand0;
10029
10030 {
10031 if (operands[0])
10032 {
10033 gen_conditional_branch (operands, LT);
10034 DONE;
10035 }
10036 }
10037 operand0 = operands[0];
10038 }
10039 emit_jump_insn (gen_rtx_SET (VOIDmode,
10040 pc_rtx,
10041 gen_rtx_IF_THEN_ELSE (VOIDmode,
10042 gen_rtx_LT (CCmode,
10043 cc0_rtx,
10044 const0_rtx),
10045 gen_rtx_LABEL_REF (VOIDmode,
10046 operand0),
10047 pc_rtx)));
10048 _val = get_insns ();
10049 end_sequence ();
10050 return _val;
10051 }
10052
10053
10054 rtx
10055 gen_ble (operand0)
10056 rtx operand0;
10057 {
10058 rtx _val = 0;
10059 start_sequence ();
10060 {
10061 rtx operands[1];
10062 operands[0] = operand0;
10063
10064 {
10065 if (operands[0])
10066 {
10067 gen_conditional_branch (operands, LE);
10068 DONE;
10069 }
10070 }
10071 operand0 = operands[0];
10072 }
10073 emit_jump_insn (gen_rtx_SET (VOIDmode,
10074 pc_rtx,
10075 gen_rtx_IF_THEN_ELSE (VOIDmode,
10076 gen_rtx_LE (CCmode,
10077 cc0_rtx,
10078 const0_rtx),
10079 gen_rtx_LABEL_REF (VOIDmode,
10080 operand0),
10081 pc_rtx)));
10082 _val = get_insns ();
10083 end_sequence ();
10084 return _val;
10085 }
10086
10087
10088 rtx
10089 gen_bgtu (operand0)
10090 rtx operand0;
10091 {
10092 rtx _val = 0;
10093 start_sequence ();
10094 {
10095 rtx operands[1];
10096 operands[0] = operand0;
10097
10098 {
10099 if (operands[0])
10100 {
10101 gen_conditional_branch (operands, GTU);
10102 DONE;
10103 }
10104 }
10105 operand0 = operands[0];
10106 }
10107 emit_jump_insn (gen_rtx_SET (VOIDmode,
10108 pc_rtx,
10109 gen_rtx_IF_THEN_ELSE (VOIDmode,
10110 gen_rtx_GTU (CCmode,
10111 cc0_rtx,
10112 const0_rtx),
10113 gen_rtx_LABEL_REF (VOIDmode,
10114 operand0),
10115 pc_rtx)));
10116 _val = get_insns ();
10117 end_sequence ();
10118 return _val;
10119 }
10120
10121
10122 rtx
10123 gen_bgeu (operand0)
10124 rtx operand0;
10125 {
10126 rtx _val = 0;
10127 start_sequence ();
10128 {
10129 rtx operands[1];
10130 operands[0] = operand0;
10131
10132 {
10133 if (operands[0])
10134 {
10135 gen_conditional_branch (operands, GEU);
10136 DONE;
10137 }
10138 }
10139 operand0 = operands[0];
10140 }
10141 emit_jump_insn (gen_rtx_SET (VOIDmode,
10142 pc_rtx,
10143 gen_rtx_IF_THEN_ELSE (VOIDmode,
10144 gen_rtx_GEU (CCmode,
10145 cc0_rtx,
10146 const0_rtx),
10147 gen_rtx_LABEL_REF (VOIDmode,
10148 operand0),
10149 pc_rtx)));
10150 _val = get_insns ();
10151 end_sequence ();
10152 return _val;
10153 }
10154
10155
10156 rtx
10157 gen_bltu (operand0)
10158 rtx operand0;
10159 {
10160 rtx _val = 0;
10161 start_sequence ();
10162 {
10163 rtx operands[1];
10164 operands[0] = operand0;
10165
10166 {
10167 if (operands[0])
10168 {
10169 gen_conditional_branch (operands, LTU);
10170 DONE;
10171 }
10172 }
10173 operand0 = operands[0];
10174 }
10175 emit_jump_insn (gen_rtx_SET (VOIDmode,
10176 pc_rtx,
10177 gen_rtx_IF_THEN_ELSE (VOIDmode,
10178 gen_rtx_LTU (CCmode,
10179 cc0_rtx,
10180 const0_rtx),
10181 gen_rtx_LABEL_REF (VOIDmode,
10182 operand0),
10183 pc_rtx)));
10184 _val = get_insns ();
10185 end_sequence ();
10186 return _val;
10187 }
10188
10189
10190 rtx
10191 gen_bleu (operand0)
10192 rtx operand0;
10193 {
10194 rtx _val = 0;
10195 start_sequence ();
10196 {
10197 rtx operands[1];
10198 operands[0] = operand0;
10199
10200 {
10201 if (operands[0])
10202 {
10203 gen_conditional_branch (operands, LEU);
10204 DONE;
10205 }
10206 }
10207 operand0 = operands[0];
10208 }
10209 emit_jump_insn (gen_rtx_SET (VOIDmode,
10210 pc_rtx,
10211 gen_rtx_IF_THEN_ELSE (VOIDmode,
10212 gen_rtx_LEU (CCmode,
10213 cc0_rtx,
10214 const0_rtx),
10215 gen_rtx_LABEL_REF (VOIDmode,
10216 operand0),
10217 pc_rtx)));
10218 _val = get_insns ();
10219 end_sequence ();
10220 return _val;
10221 }
10222
10223
10224 rtx
10225 gen_seq (operand0)
10226 rtx operand0;
10227 {
10228 rtx operand1;
10229 rtx operand2;
10230 rtx _val = 0;
10231 start_sequence ();
10232 {
10233 rtx operands[3];
10234 operands[0] = operand0;
10235
10236 {
10237 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10238 FAIL;
10239
10240
10241 operands[1] = branch_cmp[0];
10242 operands[2] = branch_cmp[1];
10243
10244 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10245 {
10246 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
10247 DONE;
10248 }
10249
10250 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
10251 operands[2] = force_reg (SImode, operands[2]);
10252
10253
10254 }
10255 operand0 = operands[0];
10256 operand1 = operands[1];
10257 operand2 = operands[2];
10258 }
10259 emit_insn (gen_rtx_SET (VOIDmode,
10260 operand0,
10261 gen_rtx_EQ (SImode,
10262 operand1,
10263 operand2)));
10264 _val = get_insns ();
10265 end_sequence ();
10266 return _val;
10267 }
10268
10269
10270 rtx
10271 gen_sne (operand0)
10272 rtx operand0;
10273 {
10274 rtx operand1;
10275 rtx operand2;
10276 rtx _val = 0;
10277 start_sequence ();
10278 {
10279 rtx operands[3];
10280 operands[0] = operand0;
10281
10282 {
10283 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10284 FAIL;
10285
10286
10287 operands[1] = branch_cmp[0];
10288 operands[2] = branch_cmp[1];
10289
10290 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
10291 {
10292 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
10293 DONE;
10294 }
10295
10296 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
10297 operands[2] = force_reg (SImode, operands[2]);
10298
10299
10300 }
10301 operand0 = operands[0];
10302 operand1 = operands[1];
10303 operand2 = operands[2];
10304 }
10305 emit_insn (gen_rtx_SET (VOIDmode,
10306 operand0,
10307 gen_rtx_NE (SImode,
10308 operand1,
10309 operand2)));
10310 _val = get_insns ();
10311 end_sequence ();
10312 return _val;
10313 }
10314
10315
10316 rtx
10317 gen_sgt (operand0)
10318 rtx operand0;
10319 {
10320 rtx operand1;
10321 rtx operand2;
10322 rtx _val = 0;
10323 start_sequence ();
10324 {
10325 rtx operands[3];
10326 operands[0] = operand0;
10327
10328 {
10329 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10330 FAIL;
10331
10332
10333 operands[1] = branch_cmp[0];
10334 operands[2] = branch_cmp[1];
10335
10336 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10337 {
10338 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
10339 DONE;
10340 }
10341
10342 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
10343 operands[2] = force_reg (SImode, operands[2]);
10344
10345
10346 }
10347 operand0 = operands[0];
10348 operand1 = operands[1];
10349 operand2 = operands[2];
10350 }
10351 emit_insn (gen_rtx_SET (VOIDmode,
10352 operand0,
10353 gen_rtx_GT (SImode,
10354 operand1,
10355 operand2)));
10356 _val = get_insns ();
10357 end_sequence ();
10358 return _val;
10359 }
10360
10361
10362 rtx
10363 gen_sge (operand0)
10364 rtx operand0;
10365 {
10366 rtx operand1;
10367 rtx operand2;
10368 rtx _val = 0;
10369 start_sequence ();
10370 {
10371 rtx operands[3];
10372 operands[0] = operand0;
10373
10374 {
10375 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10376 FAIL;
10377
10378
10379 operands[1] = branch_cmp[0];
10380 operands[2] = branch_cmp[1];
10381
10382 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10383 {
10384 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
10385 DONE;
10386 }
10387
10388
10389 }
10390 operand0 = operands[0];
10391 operand1 = operands[1];
10392 operand2 = operands[2];
10393 }
10394 emit_insn (gen_rtx_SET (VOIDmode,
10395 operand0,
10396 gen_rtx_GE (SImode,
10397 operand1,
10398 operand2)));
10399 _val = get_insns ();
10400 end_sequence ();
10401 return _val;
10402 }
10403
10404
10405 rtx
10406 gen_slt (operand0)
10407 rtx operand0;
10408 {
10409 rtx operand1;
10410 rtx operand2;
10411 rtx _val = 0;
10412 start_sequence ();
10413 {
10414 rtx operands[3];
10415 operands[0] = operand0;
10416
10417 {
10418 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10419 FAIL;
10420
10421
10422 operands[1] = branch_cmp[0];
10423 operands[2] = branch_cmp[1];
10424
10425 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10426 {
10427 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
10428 DONE;
10429 }
10430
10431
10432 }
10433 operand0 = operands[0];
10434 operand1 = operands[1];
10435 operand2 = operands[2];
10436 }
10437 emit_insn (gen_rtx_SET (VOIDmode,
10438 operand0,
10439 gen_rtx_LT (SImode,
10440 operand1,
10441 operand2)));
10442 _val = get_insns ();
10443 end_sequence ();
10444 return _val;
10445 }
10446
10447
10448 rtx
10449 gen_sle (operand0)
10450 rtx operand0;
10451 {
10452 rtx operand1;
10453 rtx operand2;
10454 rtx _val = 0;
10455 start_sequence ();
10456 {
10457 rtx operands[3];
10458 operands[0] = operand0;
10459
10460 {
10461 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10462 FAIL;
10463
10464
10465 operands[1] = branch_cmp[0];
10466 operands[2] = branch_cmp[1];
10467
10468 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10469 {
10470 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
10471 DONE;
10472 }
10473
10474 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
10475 operands[2] = force_reg (SImode, operands[2]);
10476
10477
10478 }
10479 operand0 = operands[0];
10480 operand1 = operands[1];
10481 operand2 = operands[2];
10482 }
10483 emit_insn (gen_rtx_SET (VOIDmode,
10484 operand0,
10485 gen_rtx_LE (SImode,
10486 operand1,
10487 operand2)));
10488 _val = get_insns ();
10489 end_sequence ();
10490 return _val;
10491 }
10492
10493
10494 rtx
10495 gen_sgtu (operand0)
10496 rtx operand0;
10497 {
10498 rtx operand1;
10499 rtx operand2;
10500 rtx _val = 0;
10501 start_sequence ();
10502 {
10503 rtx operands[3];
10504 operands[0] = operand0;
10505
10506 {
10507 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10508 FAIL;
10509
10510
10511 operands[1] = branch_cmp[0];
10512 operands[2] = branch_cmp[1];
10513
10514 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10515 {
10516 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
10517 DONE;
10518 }
10519
10520 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
10521 operands[2] = force_reg (SImode, operands[2]);
10522
10523
10524 }
10525 operand0 = operands[0];
10526 operand1 = operands[1];
10527 operand2 = operands[2];
10528 }
10529 emit_insn (gen_rtx_SET (VOIDmode,
10530 operand0,
10531 gen_rtx_GTU (SImode,
10532 operand1,
10533 operand2)));
10534 _val = get_insns ();
10535 end_sequence ();
10536 return _val;
10537 }
10538
10539
10540 rtx
10541 gen_sgeu (operand0)
10542 rtx operand0;
10543 {
10544 rtx operand1;
10545 rtx operand2;
10546 rtx _val = 0;
10547 start_sequence ();
10548 {
10549 rtx operands[3];
10550 operands[0] = operand0;
10551
10552 {
10553 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10554 FAIL;
10555
10556
10557 operands[1] = branch_cmp[0];
10558 operands[2] = branch_cmp[1];
10559
10560 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10561 {
10562 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
10563 DONE;
10564 }
10565
10566
10567 }
10568 operand0 = operands[0];
10569 operand1 = operands[1];
10570 operand2 = operands[2];
10571 }
10572 emit_insn (gen_rtx_SET (VOIDmode,
10573 operand0,
10574 gen_rtx_GEU (SImode,
10575 operand1,
10576 operand2)));
10577 _val = get_insns ();
10578 end_sequence ();
10579 return _val;
10580 }
10581
10582
10583 rtx
10584 gen_sltu (operand0)
10585 rtx operand0;
10586 {
10587 rtx operand1;
10588 rtx operand2;
10589 rtx _val = 0;
10590 start_sequence ();
10591 {
10592 rtx operands[3];
10593 operands[0] = operand0;
10594
10595 {
10596 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10597 FAIL;
10598
10599
10600 operands[1] = branch_cmp[0];
10601 operands[2] = branch_cmp[1];
10602
10603 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10604 {
10605 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
10606 DONE;
10607 }
10608
10609
10610 }
10611 operand0 = operands[0];
10612 operand1 = operands[1];
10613 operand2 = operands[2];
10614 }
10615 emit_insn (gen_rtx_SET (VOIDmode,
10616 operand0,
10617 gen_rtx_LTU (SImode,
10618 operand1,
10619 operand2)));
10620 _val = get_insns ();
10621 end_sequence ();
10622 return _val;
10623 }
10624
10625
10626 rtx
10627 gen_sleu (operand0)
10628 rtx operand0;
10629 {
10630 rtx operand1;
10631 rtx operand2;
10632 rtx _val = 0;
10633 start_sequence ();
10634 {
10635 rtx operands[3];
10636 operands[0] = operand0;
10637
10638 {
10639 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
10640 FAIL;
10641
10642
10643 operands[1] = branch_cmp[0];
10644 operands[2] = branch_cmp[1];
10645
10646 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
10647 {
10648 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
10649 DONE;
10650 }
10651
10652 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
10653 operands[2] = force_reg (SImode, operands[2]);
10654
10655
10656 }
10657 operand0 = operands[0];
10658 operand1 = operands[1];
10659 operand2 = operands[2];
10660 }
10661 emit_insn (gen_rtx_SET (VOIDmode,
10662 operand0,
10663 gen_rtx_LEU (SImode,
10664 operand1,
10665 operand2)));
10666 _val = get_insns ();
10667 end_sequence ();
10668 return _val;
10669 }
10670
10671
10672 rtx
10673 gen_indirect_jump (operand0)
10674 rtx operand0;
10675 {
10676 rtx _val = 0;
10677 start_sequence ();
10678 {
10679 rtx operands[1];
10680 operands[0] = operand0;
10681
10682 {
10683 rtx dest;
10684
10685 if (operands[0])
10686 {
10687 dest = operands[0];
10688 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
10689 operands[0] = copy_to_mode_reg (Pmode, dest);
10690
10691 if (!(Pmode == DImode))
10692 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
10693 else
10694 emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
10695
10696 DONE;
10697 }
10698 }
10699 operand0 = operands[0];
10700 }
10701 emit_jump_insn (gen_rtx_SET (VOIDmode,
10702 pc_rtx,
10703 operand0));
10704 _val = get_insns ();
10705 end_sequence ();
10706 return _val;
10707 }
10708
10709
10710 rtx
10711 gen_tablejump (operand0, operand1)
10712 rtx operand0;
10713 rtx operand1;
10714 {
10715 rtx _val = 0;
10716 start_sequence ();
10717 {
10718 rtx operands[2];
10719 operands[0] = operand0;
10720 operands[1] = operand1;
10721
10722 {
10723 if (operands[0])
10724 {
10725 if (TARGET_MIPS16)
10726 {
10727 if (GET_MODE (operands[0]) != HImode)
10728 abort ();
10729 if (!(Pmode == DImode))
10730 emit_insn (gen_tablejump_mips161 (operands[0], operands[1]));
10731 else
10732 emit_insn (gen_tablejump_mips162 (operands[0], operands[1]));
10733 DONE;
10734 }
10735
10736 if (GET_MODE (operands[0]) != Pmode)
10737 abort ();
10738
10739 if (! flag_pic)
10740 {
10741 if (!(Pmode == DImode))
10742 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
10743 else
10744 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
10745 }
10746 else
10747 {
10748 if (!(Pmode == DImode))
10749 emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
10750 else
10751 emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
10752 }
10753
10754 DONE;
10755 }
10756 }
10757 operand0 = operands[0];
10758 operand1 = operands[1];
10759 }
10760 emit_jump_insn (gen_rtx_SET (VOIDmode,
10761 pc_rtx,
10762 operand0));
10763 emit_insn (gen_rtx_USE (VOIDmode,
10764 gen_rtx_LABEL_REF (VOIDmode,
10765 operand1)));
10766 _val = get_insns ();
10767 end_sequence ();
10768 return _val;
10769 }
10770
10771
10772 rtx
10773 gen_tablejump_internal3 (operand0, operand1)
10774 rtx operand0;
10775 rtx operand1;
10776 {
10777 return gen_rtx_PARALLEL (VOIDmode,
10778 gen_rtvec (2,
10779 gen_rtx_SET (VOIDmode,
10780 pc_rtx,
10781 gen_rtx_PLUS (SImode,
10782 operand0,
10783 gen_rtx_LABEL_REF (SImode,
10784 operand1))),
10785 gen_rtx_USE (VOIDmode,
10786 gen_rtx_LABEL_REF (SImode,
10787 operand1))));
10788 }
10789
10790
10791 rtx
10792 gen_tablejump_mips161 (operand0, operand1)
10793 rtx operand0;
10794 rtx operand1;
10795 {
10796 rtx _val = 0;
10797 start_sequence ();
10798 {
10799 rtx operands[2];
10800 operands[0] = operand0;
10801 operands[1] = operand1;
10802
10803 {
10804 if (operands[0])
10805 {
10806 rtx t1, t2, t3;
10807
10808 t1 = gen_reg_rtx (SImode);
10809 t2 = gen_reg_rtx (SImode);
10810 t3 = gen_reg_rtx (SImode);
10811 emit_insn (gen_extendhisi2 (t1, operands[0]));
10812 emit_move_insn (t2, gen_rtx_LABEL_REF (SImode, operands[1]));
10813 emit_insn (gen_addsi3 (t3, t1, t2));
10814 emit_jump_insn (gen_tablejump_internal1 (t3, operands[1]));
10815 DONE;
10816 }
10817 }
10818 operand0 = operands[0];
10819 operand1 = operands[1];
10820 }
10821 emit_jump_insn (gen_rtx_SET (VOIDmode,
10822 pc_rtx,
10823 gen_rtx_PLUS (SImode,
10824 gen_rtx_SIGN_EXTEND (SImode,
10825 operand0),
10826 gen_rtx_LABEL_REF (SImode,
10827 operand1))));
10828 _val = get_insns ();
10829 end_sequence ();
10830 return _val;
10831 }
10832
10833
10834 rtx
10835 gen_tablejump_mips162 (operand0, operand1)
10836 rtx operand0;
10837 rtx operand1;
10838 {
10839 rtx _val = 0;
10840 start_sequence ();
10841 {
10842 rtx operands[2];
10843 operands[0] = operand0;
10844 operands[1] = operand1;
10845
10846 {
10847 if (operands[0])
10848 {
10849 rtx t1, t2, t3;
10850
10851 t1 = gen_reg_rtx (DImode);
10852 t2 = gen_reg_rtx (DImode);
10853 t3 = gen_reg_rtx (DImode);
10854 emit_insn (gen_extendhidi2 (t1, operands[0]));
10855 emit_move_insn (t2, gen_rtx_LABEL_REF (DImode, operands[1]));
10856 emit_insn (gen_adddi3 (t3, t1, t2));
10857 emit_jump_insn (gen_tablejump_internal2 (t3, operands[1]));
10858 DONE;
10859 }
10860 }
10861 operand0 = operands[0];
10862 operand1 = operands[1];
10863 }
10864 emit_jump_insn (gen_rtx_SET (VOIDmode,
10865 pc_rtx,
10866 gen_rtx_PLUS (DImode,
10867 gen_rtx_SIGN_EXTEND (DImode,
10868 operand0),
10869 gen_rtx_LABEL_REF (DImode,
10870 operand1))));
10871 _val = get_insns ();
10872 end_sequence ();
10873 return _val;
10874 }
10875
10876
10877 rtx
10878 gen_tablejump_internal4 (operand0, operand1)
10879 rtx operand0;
10880 rtx operand1;
10881 {
10882 return gen_rtx_PARALLEL (VOIDmode,
10883 gen_rtvec (2,
10884 gen_rtx_SET (VOIDmode,
10885 pc_rtx,
10886 gen_rtx_PLUS (DImode,
10887 operand0,
10888 gen_rtx_LABEL_REF (DImode,
10889 operand1))),
10890 gen_rtx_USE (VOIDmode,
10891 gen_rtx_LABEL_REF (DImode,
10892 operand1))));
10893 }
10894
10895
10896 rtx
10897 gen_casesi (operand0, operand1, operand2, operand3, operand4)
10898 rtx operand0;
10899 rtx operand1;
10900 rtx operand2;
10901 rtx operand3;
10902 rtx operand4;
10903 {
10904 rtx operand5;
10905 rtx operand6 ATTRIBUTE_UNUSED;
10906 rtx _val = 0;
10907 start_sequence ();
10908 {
10909 rtx operands[7];
10910 operands[0] = operand0;
10911 operands[1] = operand1;
10912 operands[2] = operand2;
10913 operands[3] = operand3;
10914 operands[4] = operand4;
10915
10916 {
10917 if (operands[0])
10918 {
10919 rtx reg = gen_reg_rtx (SImode);
10920
10921
10922 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
10923 emit_insn (gen_cmpsi (reg, operands[2]));
10924 emit_insn (gen_bgtu (operands[4]));
10925
10926
10927 if (Pmode != DImode)
10928 emit_jump_insn (gen_casesi_internal (reg, operands[3],
10929 gen_reg_rtx (SImode)));
10930 else
10931 emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
10932 gen_reg_rtx (DImode)));
10933
10934 DONE;
10935 }
10936 }
10937 operand0 = operands[0];
10938 operand1 = operands[1];
10939 operand2 = operands[2];
10940 operand3 = operands[3];
10941 operand4 = operands[4];
10942 operand5 = operands[5];
10943 operand6 = operands[6];
10944 }
10945 emit_insn (gen_rtx_SET (VOIDmode,
10946 operand5,
10947 gen_rtx_MINUS (SImode,
10948 operand0,
10949 operand1)));
10950 emit_insn (gen_rtx_SET (VOIDmode,
10951 cc0_rtx,
10952 gen_rtx_COMPARE (CCmode,
10953 operand5,
10954 operand2)));
10955 emit_jump_insn (gen_rtx_SET (VOIDmode,
10956 pc_rtx,
10957 gen_rtx_IF_THEN_ELSE (VOIDmode,
10958 gen_rtx_GTU (VOIDmode,
10959 cc0_rtx,
10960 const0_rtx),
10961 gen_rtx_LABEL_REF (VOIDmode,
10962 operand4),
10963 pc_rtx)));
10964 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode,
10965 gen_rtvec (3,
10966 gen_rtx_SET (VOIDmode,
10967 pc_rtx,
10968 gen_rtx_MEM (SImode,
10969 gen_rtx_PLUS (SImode,
10970 gen_rtx_MULT (SImode,
10971 operand5,
10972 GEN_INT (4LL)),
10973 gen_rtx_LABEL_REF (VOIDmode,
10974 operand3)))),
10975 gen_rtx_CLOBBER (VOIDmode,
10976 gen_rtx_SCRATCH (SImode)),
10977 gen_rtx_CLOBBER (VOIDmode,
10978 gen_rtx_REG (SImode,
10979 31)))));
10980 _val = get_insns ();
10981 end_sequence ();
10982 return _val;
10983 }
10984
10985
10986 rtx
10987 gen_builtin_setjmp_setup (operand0)
10988 rtx operand0;
10989 {
10990 rtx _val = 0;
10991 start_sequence ();
10992 {
10993 rtx operands[1];
10994 operands[0] = operand0;
10995
10996 {
10997 if (Pmode == DImode)
10998 emit_insn (gen_builtin_setjmp_setup_64 (operands[0]));
10999 else
11000 emit_insn (gen_builtin_setjmp_setup_32 (operands[0]));
11001 DONE;
11002 }
11003 operand0 = operands[0];
11004 }
11005 emit_insn (gen_rtx_UNSPEC (VOIDmode,
11006 gen_rtvec (1,
11007 operand0),
11008 8));
11009 _val = get_insns ();
11010 end_sequence ();
11011 return _val;
11012 }
11013
11014
11015 rtx
11016 gen_builtin_setjmp_setup_32 (operand0)
11017 rtx operand0;
11018 {
11019 return gen_rtx_SET (VOIDmode,
11020 gen_rtx_MEM (SImode,
11021 gen_rtx_PLUS (SImode,
11022 operand0,
11023 GEN_INT (12LL))),
11024 gen_rtx_REG (SImode,
11025 28));
11026 }
11027
11028
11029 rtx
11030 gen_builtin_setjmp_setup_64 (operand0)
11031 rtx operand0;
11032 {
11033 return gen_rtx_SET (VOIDmode,
11034 gen_rtx_MEM (DImode,
11035 gen_rtx_PLUS (DImode,
11036 operand0,
11037 GEN_INT (24LL))),
11038 gen_rtx_REG (DImode,
11039 28));
11040 }
11041
11042
11043 rtx
11044 gen_builtin_longjmp (operand0)
11045 rtx operand0;
11046 {
11047 rtx _val = 0;
11048 start_sequence ();
11049 {
11050 rtx operands[1];
11051 operands[0] = operand0;
11052
11053 {
11054
11055 int W = (Pmode == DImode ? 8 : 4);
11056 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
11057 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
11058 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
11059 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
11060 rtx pv = gen_rtx_REG (Pmode, 25);
11061 rtx gp = gen_rtx_REG (Pmode, 28);
11062
11063
11064 emit_move_insn (hard_frame_pointer_rtx, fp);
11065 emit_move_insn (pv, lab);
11066 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
11067 emit_move_insn (gp, gpv);
11068 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
11069 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
11070 emit_insn (gen_rtx_USE (VOIDmode, gp));
11071 emit_indirect_jump (pv);
11072 DONE;
11073 }
11074 operand0 = operands[0];
11075 }
11076 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
11077 gen_rtvec (1,
11078 operand0),
11079 9));
11080 _val = get_insns ();
11081 end_sequence ();
11082 return _val;
11083 }
11084
11085
11086 rtx
11087 gen_prologue ()
11088 {
11089 rtx _val = 0;
11090 start_sequence ();
11091 {
11092
11093 {
11094 if (mips_isa >= 0)
11095 {
11096 mips_expand_prologue ();
11097 DONE;
11098 }
11099 }
11100 }
11101 emit_insn (const1_rtx);
11102 _val = get_insns ();
11103 end_sequence ();
11104 return _val;
11105 }
11106
11107
11108 rtx
11109 gen_epilogue ()
11110 {
11111 rtx _val = 0;
11112 start_sequence ();
11113 {
11114
11115 {
11116 if (mips_isa >= 0)
11117 {
11118 mips_expand_epilogue ();
11119 DONE;
11120 }
11121 }
11122 }
11123 emit_insn (GEN_INT (2LL));
11124 _val = get_insns ();
11125 end_sequence ();
11126 return _val;
11127 }
11128
11129
11130 rtx
11131 gen_eh_return (operand0)
11132 rtx operand0;
11133 {
11134 rtx _val = 0;
11135 start_sequence ();
11136 {
11137 rtx operands[1];
11138 operands[0] = operand0;
11139
11140 {
11141 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
11142
11143 if (GET_MODE (operands[0]) != gpr_mode)
11144 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
11145 if (TARGET_64BIT)
11146 emit_insn (gen_eh_set_lr_di (operands[0]));
11147 else
11148 emit_insn (gen_eh_set_lr_si (operands[0]));
11149
11150 DONE;
11151 }
11152 operand0 = operands[0];
11153 }
11154 emit_insn (gen_rtx_USE (VOIDmode,
11155 operand0));
11156 _val = get_insns ();
11157 end_sequence ();
11158 return _val;
11159 }
11160
11161
11162 extern rtx gen_split_517 PARAMS ((rtx *));
11163 rtx
11164 gen_split_517 (operands)
11165 rtx *operands ATTRIBUTE_UNUSED;
11166 {
11167 rtx _val = 0;
11168 start_sequence ();
11169
11170 {
11171 mips_set_return_address (operands[0], operands[1]);
11172 DONE;
11173 }
11174 emit_insn (const0_rtx);
11175 _val = get_insns ();
11176 end_sequence ();
11177 return _val;
11178 }
11179
11180
11181 rtx
11182 gen_call (operand0, operand1, operand2, operand3)
11183 rtx operand0;
11184 rtx operand1;
11185 rtx operand2;
11186 rtx operand3;
11187 {
11188 rtx _val = 0;
11189 start_sequence ();
11190 {
11191 rtx operands[4];
11192 operands[0] = operand0;
11193 operands[1] = operand1;
11194 operands[2] = operand2;
11195 operands[3] = operand3;
11196
11197 {
11198 rtx addr;
11199
11200 if (operands[0])
11201 {
11202 addr = XEXP (operands[0], 0);
11203 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
11204 || ! call_insn_operand (addr, VOIDmode))
11205 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
11206
11207
11208
11209
11210
11211
11212
11213
11214 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
11215 {
11216 rtvec adjust = XVEC (operands[2], 0);
11217 int num = GET_NUM_ELEM (adjust);
11218 int i;
11219
11220 for (i = 0; i < num; i++)
11221 emit_insn (RTVEC_ELT (adjust, i));
11222 }
11223
11224 if (TARGET_MIPS16
11225 && mips16_hard_float
11226 && operands[2] != 0
11227 && (int) GET_MODE (operands[2]) != 0)
11228 {
11229 if (build_mips16_call_stub (NULL_RTX, operands[0], operands[1],
11230 (int) GET_MODE (operands[2])))
11231 DONE;
11232 }
11233
11234 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
11235 gen_rtx_REG (SImode,
11236 GP_REG_FIRST + 31)));
11237 DONE;
11238 }
11239 }
11240 operand0 = operands[0];
11241 operand1 = operands[1];
11242 operand2 = operands[2];
11243 operand3 = operands[3];
11244 }
11245 emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
11246 gen_rtvec (4,
11247 gen_rtx_CALL (VOIDmode,
11248 operand0,
11249 operand1),
11250 gen_rtx_CLOBBER (VOIDmode,
11251 gen_rtx_REG (SImode,
11252 31)),
11253 gen_rtx_USE (VOIDmode,
11254 operand2),
11255 gen_rtx_USE (VOIDmode,
11256 operand3))));
11257 _val = get_insns ();
11258 end_sequence ();
11259 return _val;
11260 }
11261
11262
11263 rtx
11264 gen_call_internal0 (operand0, operand1, operand2)
11265 rtx operand0;
11266 rtx operand1;
11267 rtx operand2;
11268 {
11269 return gen_rtx_PARALLEL (VOIDmode,
11270 gen_rtvec (2,
11271 gen_rtx_CALL (VOIDmode,
11272 operand0,
11273 operand1),
11274 gen_rtx_CLOBBER (VOIDmode,
11275 operand2)));
11276 }
11277
11278
11279 rtx
11280 gen_call_value (operand0, operand1, operand2, operand3)
11281 rtx operand0;
11282 rtx operand1;
11283 rtx operand2;
11284 rtx operand3;
11285 {
11286 rtx _val = 0;
11287 start_sequence ();
11288 {
11289 rtx operands[4];
11290 operands[0] = operand0;
11291 operands[1] = operand1;
11292 operands[2] = operand2;
11293 operands[3] = operand3;
11294
11295 {
11296 rtx addr;
11297
11298 if (operands[0])
11299 {
11300 addr = XEXP (operands[1], 0);
11301 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
11302 || ! call_insn_operand (addr, VOIDmode))
11303 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
11304
11305
11306
11307
11308
11309
11310
11311
11312 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
11313 {
11314 rtvec adjust = XVEC (operands[3], 0);
11315 int num = GET_NUM_ELEM (adjust);
11316 int i;
11317
11318 for (i = 0; i < num; i++)
11319 emit_insn (RTVEC_ELT (adjust, i));
11320 }
11321
11322 if (TARGET_MIPS16
11323 && mips16_hard_float
11324 && ((operands[3] != 0
11325 && (int) GET_MODE (operands[3]) != 0)
11326 || GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT))
11327 {
11328 if (build_mips16_call_stub (operands[0], operands[1], operands[2],
11329 (operands[3] == 0 ? 0
11330 : (int) GET_MODE (operands[3]))))
11331 DONE;
11332 }
11333
11334
11335
11336 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
11337 {
11338 emit_call_insn (gen_call_value_multiple_internal0
11339 (XEXP (XVECEXP (operands[0], 0, 0), 0),
11340 operands[1], operands[2],
11341 XEXP (XVECEXP (operands[0], 0, 1), 0),
11342 gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
11343 DONE;
11344 }
11345
11346
11347
11348 if (GET_CODE (operands[0]) == PARALLEL)
11349 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
11350
11351 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
11352 gen_rtx_REG (SImode,
11353 GP_REG_FIRST + 31)));
11354
11355 DONE;
11356 }
11357 }
11358 operand0 = operands[0];
11359 operand1 = operands[1];
11360 operand2 = operands[2];
11361 operand3 = operands[3];
11362 }
11363 emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
11364 gen_rtvec (3,
11365 gen_rtx_SET (VOIDmode,
11366 operand0,
11367 gen_rtx_CALL (VOIDmode,
11368 operand1,
11369 operand2)),
11370 gen_rtx_CLOBBER (VOIDmode,
11371 gen_rtx_REG (SImode,
11372 31)),
11373 gen_rtx_USE (VOIDmode,
11374 operand3))));
11375 _val = get_insns ();
11376 end_sequence ();
11377 return _val;
11378 }
11379
11380
11381 rtx
11382 gen_call_value_internal0 (operand0, operand1, operand2, operand3)
11383 rtx operand0;
11384 rtx operand1;
11385 rtx operand2;
11386 rtx operand3;
11387 {
11388 return gen_rtx_PARALLEL (VOIDmode,
11389 gen_rtvec (2,
11390 gen_rtx_SET (VOIDmode,
11391 operand0,
11392 gen_rtx_CALL (VOIDmode,
11393 operand1,
11394 operand2)),
11395 gen_rtx_CLOBBER (VOIDmode,
11396 operand3)));
11397 }
11398
11399
11400 rtx
11401 gen_call_value_multiple_internal0 (operand0, operand1, operand2, operand3, operand4)
11402 rtx operand0;
11403 rtx operand1;
11404 rtx operand2;
11405 rtx operand3;
11406 rtx operand4;
11407 {
11408 return gen_rtx_PARALLEL (VOIDmode,
11409 gen_rtvec (3,
11410 gen_rtx_SET (VOIDmode,
11411 operand0,
11412 gen_rtx_CALL (VOIDmode,
11413 operand1,
11414 operand2)),
11415 gen_rtx_SET (VOIDmode,
11416 operand3,
11417 gen_rtx_CALL (VOIDmode,
11418 operand1,
11419 operand2)),
11420 gen_rtx_CLOBBER (VOIDmode,
11421 operand4)));
11422 }
11423
11424
11425 rtx
11426 gen_untyped_call (operand0, operand1, operand2)
11427 rtx operand0;
11428 rtx operand1;
11429 rtx operand2;
11430 {
11431 rtx _val = 0;
11432 start_sequence ();
11433 {
11434 rtx operands[3];
11435 operands[0] = operand0;
11436 operands[1] = operand1;
11437 operands[2] = operand2;
11438
11439 {
11440 if (operands[0])
11441 {
11442 int i;
11443
11444 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
11445
11446 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11447 {
11448 rtx set = XVECEXP (operands[2], 0, i);
11449 emit_move_insn (SET_DEST (set), SET_SRC (set));
11450 }
11451
11452 emit_insn (gen_blockage ());
11453 DONE;
11454 }
11455 }
11456 operand0 = operands[0];
11457 operand1 = operands[1];
11458 operand2 = operands[2];
11459 }
11460 emit_call_insn (gen_rtx_PARALLEL (VOIDmode,
11461 gen_rtvec (3,
11462 gen_rtx_CALL (VOIDmode,
11463 operand0,
11464 const0_rtx),
11465 operand1,
11466 operand2)));
11467 _val = get_insns ();
11468 end_sequence ();
11469 return _val;
11470 }
11471
11472
11473 rtx
11474 gen_prefetch (operand0, operand1, operand2)
11475 rtx operand0;
11476 rtx operand1;
11477 rtx operand2;
11478 {
11479 rtx _val = 0;
11480 start_sequence ();
11481 {
11482 rtx operands[3];
11483 operands[0] = operand0;
11484 operands[1] = operand1;
11485 operands[2] = operand2;
11486 {
11487 if (symbolic_operand (operands[0], GET_MODE (operands[0])))
11488 operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
11489 }
11490 operand0 = operands[0];
11491 operand1 = operands[1];
11492 operand2 = operands[2];
11493 }
11494 emit_insn (gen_rtx_PREFETCH (VOIDmode,
11495 operand0,
11496 operand1,
11497 operand2));
11498 _val = get_insns ();
11499 end_sequence ();
11500 return _val;
11501 }
11502
11503
11504 rtx
11505 gen_movsicc (operand0, operand1, operand2, operand3)
11506 rtx operand0;
11507 rtx operand1;
11508 rtx operand2;
11509 rtx operand3;
11510 {
11511 rtx operand4;
11512 rtx operand5;
11513 rtx _val = 0;
11514 start_sequence ();
11515 {
11516 rtx operands[6];
11517 operands[0] = operand0;
11518 operands[1] = operand1;
11519 operands[2] = operand2;
11520 operands[3] = operand3;
11521
11522 {
11523 gen_conditional_move (operands);
11524 DONE;
11525 }
11526 operand0 = operands[0];
11527 operand1 = operands[1];
11528 operand2 = operands[2];
11529 operand3 = operands[3];
11530 operand4 = operands[4];
11531 operand5 = operands[5];
11532 }
11533 emit_insn (gen_rtx_SET (VOIDmode,
11534 operand4,
11535 operand1));
11536 emit_insn (gen_rtx_SET (VOIDmode,
11537 operand0,
11538 gen_rtx_IF_THEN_ELSE (SImode,
11539 operand5,
11540 operand2,
11541 operand3)));
11542 _val = get_insns ();
11543 end_sequence ();
11544 return _val;
11545 }
11546
11547
11548 rtx
11549 gen_movdicc (operand0, operand1, operand2, operand3)
11550 rtx operand0;
11551 rtx operand1;
11552 rtx operand2;
11553 rtx operand3;
11554 {
11555 rtx operand4;
11556 rtx operand5;
11557 rtx _val = 0;
11558 start_sequence ();
11559 {
11560 rtx operands[6];
11561 operands[0] = operand0;
11562 operands[1] = operand1;
11563 operands[2] = operand2;
11564 operands[3] = operand3;
11565
11566 {
11567 gen_conditional_move (operands);
11568 DONE;
11569 }
11570 operand0 = operands[0];
11571 operand1 = operands[1];
11572 operand2 = operands[2];
11573 operand3 = operands[3];
11574 operand4 = operands[4];
11575 operand5 = operands[5];
11576 }
11577 emit_insn (gen_rtx_SET (VOIDmode,
11578 operand4,
11579 operand1));
11580 emit_insn (gen_rtx_SET (VOIDmode,
11581 operand0,
11582 gen_rtx_IF_THEN_ELSE (DImode,
11583 operand5,
11584 operand2,
11585 operand3)));
11586 _val = get_insns ();
11587 end_sequence ();
11588 return _val;
11589 }
11590
11591
11592 rtx
11593 gen_movsfcc (operand0, operand1, operand2, operand3)
11594 rtx operand0;
11595 rtx operand1;
11596 rtx operand2;
11597 rtx operand3;
11598 {
11599 rtx operand4;
11600 rtx operand5;
11601 rtx _val = 0;
11602 start_sequence ();
11603 {
11604 rtx operands[6];
11605 operands[0] = operand0;
11606 operands[1] = operand1;
11607 operands[2] = operand2;
11608 operands[3] = operand3;
11609
11610 {
11611 gen_conditional_move (operands);
11612 DONE;
11613 }
11614 operand0 = operands[0];
11615 operand1 = operands[1];
11616 operand2 = operands[2];
11617 operand3 = operands[3];
11618 operand4 = operands[4];
11619 operand5 = operands[5];
11620 }
11621 emit_insn (gen_rtx_SET (VOIDmode,
11622 operand4,
11623 operand1));
11624 emit_insn (gen_rtx_SET (VOIDmode,
11625 operand0,
11626 gen_rtx_IF_THEN_ELSE (SFmode,
11627 operand5,
11628 operand2,
11629 operand3)));
11630 _val = get_insns ();
11631 end_sequence ();
11632 return _val;
11633 }
11634
11635
11636 rtx
11637 gen_movdfcc (operand0, operand1, operand2, operand3)
11638 rtx operand0;
11639 rtx operand1;
11640 rtx operand2;
11641 rtx operand3;
11642 {
11643 rtx operand4;
11644 rtx operand5;
11645 rtx _val = 0;
11646 start_sequence ();
11647 {
11648 rtx operands[6];
11649 operands[0] = operand0;
11650 operands[1] = operand1;
11651 operands[2] = operand2;
11652 operands[3] = operand3;
11653
11654 {
11655 gen_conditional_move (operands);
11656 DONE;
11657 }
11658 operand0 = operands[0];
11659 operand1 = operands[1];
11660 operand2 = operands[2];
11661 operand3 = operands[3];
11662 operand4 = operands[4];
11663 operand5 = operands[5];
11664 }
11665 emit_insn (gen_rtx_SET (VOIDmode,
11666 operand4,
11667 operand1));
11668 emit_insn (gen_rtx_SET (VOIDmode,
11669 operand0,
11670 gen_rtx_IF_THEN_ELSE (DFmode,
11671 operand5,
11672 operand2,
11673 operand3)));
11674 _val = get_insns ();
11675 end_sequence ();
11676 return _val;
11677 }
11678
11679
11680
11681 void
11682 add_clobbers (pattern, insn_code_number)
11683 rtx pattern ATTRIBUTE_UNUSED;
11684 int insn_code_number;
11685 {
11686 switch (insn_code_number)
11687 {
11688 case 294:
11689 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11690 gen_rtx_SCRATCH (DImode));
11691 break;
11692
11693 case 292:
11694 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11695 gen_rtx_REG (SImode,
11696 31));
11697 break;
11698
11699 case 288:
11700 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11701 gen_rtx_REG (DImode,
11702 31));
11703 break;
11704
11705 case 287:
11706 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11707 gen_rtx_REG (SImode,
11708 31));
11709 break;
11710
11711 case 189:
11712 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11713 gen_rtx_REG (DImode,
11714 1));
11715 break;
11716
11717 case 146:
11718 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11719 gen_rtx_SCRATCH (SFmode));
11720 break;
11721
11722 case 144:
11723 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11724 gen_rtx_SCRATCH (DFmode));
11725 break;
11726
11727 case 72:
11728 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11729 gen_rtx_REG (SImode,
11730 24));
11731 break;
11732
11733 case 70:
11734 case 68:
11735 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11736 gen_rtx_SCRATCH (DImode));
11737 break;
11738
11739 case 69:
11740 case 67:
11741 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11742 gen_rtx_SCRATCH (SImode));
11743 break;
11744
11745 case 293:
11746 case 53:
11747 case 43:
11748 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11749 gen_rtx_SCRATCH (SImode));
11750 break;
11751
11752 case 42:
11753 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11754 gen_rtx_SCRATCH (DImode));
11755 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11756 gen_rtx_SCRATCH (DImode));
11757 XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
11758 gen_rtx_SCRATCH (DImode));
11759 break;
11760
11761 case 90:
11762 case 51:
11763 case 50:
11764 case 44:
11765 case 41:
11766 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11767 gen_rtx_SCRATCH (DImode));
11768 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11769 gen_rtx_SCRATCH (DImode));
11770 break;
11771
11772 case 40:
11773 case 38:
11774 case 37:
11775 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11776 gen_rtx_SCRATCH (SImode));
11777 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11778 gen_rtx_SCRATCH (SImode));
11779 XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
11780 gen_rtx_SCRATCH (SImode));
11781 XVECEXP (pattern, 0, 4) = gen_rtx_CLOBBER (VOIDmode,
11782 gen_rtx_SCRATCH (SImode));
11783 break;
11784
11785 case 89:
11786 case 80:
11787 case 79:
11788 case 78:
11789 case 77:
11790 case 76:
11791 case 75:
11792 case 74:
11793 case 73:
11794 case 54:
11795 case 52:
11796 case 47:
11797 case 46:
11798 case 45:
11799 case 35:
11800 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11801 gen_rtx_SCRATCH (SImode));
11802 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11803 gen_rtx_SCRATCH (SImode));
11804 break;
11805
11806 case 49:
11807 case 48:
11808 case 39:
11809 case 36:
11810 case 34:
11811 XVECEXP (pattern, 0, 1) = gen_rtx_CLOBBER (VOIDmode,
11812 gen_rtx_SCRATCH (SImode));
11813 XVECEXP (pattern, 0, 2) = gen_rtx_CLOBBER (VOIDmode,
11814 gen_rtx_SCRATCH (SImode));
11815 XVECEXP (pattern, 0, 3) = gen_rtx_CLOBBER (VOIDmode,
11816 gen_rtx_SCRATCH (SImode));
11817 break;
11818
11819 default:
11820 abort ();
11821 }
11822 }
11823
11824
11825 int
11826 added_clobbers_hard_reg_p (insn_code_number)
11827 int insn_code_number;
11828 {
11829 switch (insn_code_number)
11830 {
11831 case 294:
11832 case 146:
11833 case 144:
11834 case 70:
11835 case 68:
11836 case 69:
11837 case 67:
11838 case 293:
11839 case 53:
11840 case 43:
11841 case 42:
11842 case 90:
11843 case 51:
11844 case 50:
11845 case 44:
11846 case 41:
11847 case 40:
11848 case 38:
11849 case 37:
11850 case 89:
11851 case 80:
11852 case 79:
11853 case 78:
11854 case 77:
11855 case 76:
11856 case 75:
11857 case 74:
11858 case 73:
11859 case 54:
11860 case 52:
11861 case 47:
11862 case 46:
11863 case 45:
11864 case 35:
11865 case 49:
11866 case 48:
11867 case 39:
11868 case 36:
11869 case 34:
11870 return 0;
11871
11872 case 292:
11873 case 288:
11874 case 287:
11875 case 189:
11876 case 72:
11877 return 1;
11878
11879 default:
11880 abort ();
11881 }
11882 }