Open64: osprey/arith/convert.c Source File

00001 /*
00002  * Copyright 2004 PathScale, Inc.  All Rights Reserved.
00003  */
00004 
00005 /*
00006 
00007   Copyright (C) 2000, 2001 Silicon Graphics, Inc.  All Rights Reserved.
00008 
00009   This program is free software; you can redistribute it and/or modify it
00010   under the terms of version 2 of the GNU General Public License as
00011   published by the Free Software Foundation.
00012 
00013   This program is distributed in the hope that it would be useful, but
00014   WITHOUT ANY WARRANTY; without even the implied warranty of
00015   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
00016 
00017   Further, this software is distributed without any warranty that it is
00018   free of the rightful claim of any third person regarding infringement 
00019   or the like.  Any license provided herein, whether implied or 
00020   otherwise, applies only to this software file.  Patent licenses, if 
00021   any, provided herein do not apply to combinations of this program with 
00022   other software, or any other product whatsoever.  
00023 
00024   You should have received a copy of the GNU General Public License along
00025   with this program; if not, write the Free Software Foundation, Inc., 59
00026   Temple Place - Suite 330, Boston MA 02111-1307, USA.
00027 
00028   Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pky,
00029   Mountain View, CA 94043, or:
00030 
00031   http://www.sgi.com
00032 
00033   For further information regarding this notice, see:
00034 
00035   http://oss.sgi.com/projects/GenInfo/NoticeExplan
00036 
00037 */
00038 
00039 
00040 /*
00041  *  Conversions between floating-point and two's-complement fixed
00042  *  point representations. All rounding is toward zero (i.e. chopped)
00043  *  for the Cray format conversions.
00044  */
00045 
00046 #include <string.h>
00047 #include "arith.internal.h"
00048 #include "int64.h"
00049 
00050 
00051 /* Cray single -> integer */
00052 int
00053 ar_cfix64 (AR_INT_64 *fix,
00054      const AR_CRAY_64 *flt,
00055      int bitsize) {
00056 
00057   int res = AR_STAT_OK, neg;
00058   int shift = AR_CRAY_EXPO_BIAS + AR_CRAY64_COEFF_BITS - flt->expo - 1;
00059   AR_CRAY_64 a = *flt;
00060 
00061   if (!(a.coeff0 | a.coeff1 | a.coeff2)) {
00062     ZERO64 (*fix);
00063     return AR_STAT_ZERO;
00064   }
00065   if (shift >= AR_CRAY64_COEFF_BITS) {
00066     ZERO64 (*fix);
00067     return AR_STAT_ZERO | AR_STAT_UNDERFLOW;
00068   }
00069   if (shift < AR_CRAY64_COEFF_BITS - bitsize)
00070     res |= AR_STAT_OVERFLOW;
00071 
00072   neg = a.sign;
00073   a.sign = 0;
00074   a.expo = 0;
00075   CRAY64TOINT64 (*fix, a);
00076 
00077   for ( ; shift < 0; shift++)
00078     SHLEFT64 (*fix);
00079   for ( ; shift > 0; shift--) {
00080     if (fix->part4 & 1)
00081       res |= AR_STAT_INEXACT;
00082     SHRIGHT64X (*fix);
00083   }
00084 
00085   if (fix->part1&0x8000)
00086     res |= (AR_STAT_OVERFLOW|AR_STAT_SEMIVALID);
00087 
00088   if (neg) {
00089     NOT64 (*fix);
00090     INC64 (*fix);
00091   }
00092 
00093   if (!(fix->part1 | fix->part2 | fix->part3 | fix->part4))
00094     res |= AR_STAT_ZERO;
00095   else if (neg)
00096     res |= AR_STAT_NEGATIVE;
00097 
00098   return res;
00099 }
00100 
00101 
00102 /* integer -> Cray single */
00103 int
00104 ar_cflt64 (AR_CRAY_64 *flt,
00105      const AR_INT_64 *fix,
00106      int is_unsigned) {
00107 
00108   int res = AR_STAT_OK, neg = 0;
00109   long expo = AR_CRAY_EXPO_BIAS + AR_CRAY64_COEFF_BITS - 1;
00110   AR_INT_64 val;
00111 
00112   if (!(fix->part1 | fix->part2 | fix->part3 | fix->part4)) {
00113     ZEROCRAY64 (*flt);
00114     return AR_STAT_ZERO;
00115   }
00116 
00117   COPY64 (val, *fix);
00118   if (SIGNBIT (*fix) && !is_unsigned) {
00119     NEG64 (val);
00120     neg = 1;
00121     res |= AR_STAT_NEGATIVE;
00122   }
00123 
00124   while (val.part1 >> (16 - (AR_CRAY_EXPO_BITS + 1))) {
00125     if (val.part4 & 1)
00126       res |= AR_STAT_INEXACT;
00127     expo++;
00128     SHRIGHT64 (val);
00129   }
00130 
00131   INT64TOCRAY64 (*flt, val);
00132   while (!(flt->coeff0 >> (AR_CRAY_C0_BITS - 1))) {
00133     expo--;
00134     SHLEFTCRAY64 (*flt);
00135   }
00136 
00137   flt->sign = neg;
00138   flt->expo = expo;
00139   return res;
00140 }
00141 
00142 
00143 /* Cray double -> integer */
00144 int
00145 ar_cfix128 (AR_INT_64 *fix,
00146       const AR_CRAY_128 *flt,
00147       int bitsize) {
00148 
00149   int res = AR_STAT_OK, neg;
00150   int shift = AR_CRAY_EXPO_BIAS + AR_CRAY64_COEFF_BITS - flt->expo - 1;
00151   AR_CRAY_128 a = *flt;
00152   AR_CRAY_64 b;
00153 
00154   if (!(a.coeff0 | a.coeff1 | a.coeff2 |
00155         a.coeff3 | a.coeff4 | a.coeff5)) {
00156     ZERO64 (*fix);
00157     return AR_STAT_ZERO;
00158   }
00159   if (shift >= AR_CRAY64_COEFF_BITS) {
00160     ZERO64 (*fix);
00161     return AR_STAT_ZERO | AR_STAT_UNDERFLOW;
00162   }
00163   if (shift < AR_CRAY64_COEFF_BITS - bitsize)
00164     res |= AR_STAT_OVERFLOW;
00165 
00166   neg = a.sign;
00167   a.sign = 0;
00168   a.expo = 0;
00169   CRAY128TO64 (b, a);
00170   CRAY64TOINT64 (*fix, b);
00171 
00172   for ( ; shift < 0; shift++) {
00173     SHLEFT64 (*fix);
00174     SHLEFTCRAY128 (a);
00175     fix->part4 |= a.coeff2 & 1;
00176   }
00177   if (a.coeff3 | a.coeff4 | a.coeff5)
00178     res |= AR_STAT_INEXACT;
00179   for ( ; shift > 0; shift--) {
00180     if (fix->part4 & 1)
00181       res |= AR_STAT_INEXACT;
00182     SHRIGHT64X (*fix);
00183   }
00184 
00185   if (fix->part1&0x8000)
00186     res |= (AR_STAT_OVERFLOW|AR_STAT_SEMIVALID);
00187 
00188   if (neg) {
00189     NOT64 (*fix);
00190     INC64 (*fix);
00191   }
00192 
00193   if (!(fix->part1 | fix->part2 | fix->part3 | fix->part4))
00194     res |= AR_STAT_ZERO;
00195   else if (neg)
00196     res |= AR_STAT_NEGATIVE;
00197 
00198   return res;
00199 }
00200 
00201 
00202 /* integer -> Cray double */
00203 int
00204 ar_cflt128 (AR_CRAY_128 *flt,
00205       const AR_INT_64 *fix,
00206       int is_unsigned) {
00207 
00208   int res = AR_STAT_OK, neg = 0;
00209   long expo = AR_CRAY_EXPO_BIAS + AR_CRAY64_COEFF_BITS - 1;
00210   AR_INT_64 val;
00211   AR_CRAY_64 sing;
00212   unsigned long chop = 0;
00213 
00214   if (!(fix->part1 | fix->part2 | fix->part3 | fix->part4)) {
00215     ZEROCRAY128 (*flt);
00216     return AR_STAT_ZERO;
00217   }
00218 
00219   COPY64 (val, *fix);
00220   if (SIGNBIT (*fix) && !is_unsigned) {
00221     NEG64 (val);
00222     neg = 1;
00223     res |= AR_STAT_NEGATIVE;
00224   }
00225 
00226   while (val.part1 >> (16 - (AR_CRAY_EXPO_BITS + 1))) {
00227     chop = (chop >> 1) |
00228            ((val.part4 & 1) << (AR_CRAY_C3_BITS - 1));
00229     expo++;
00230     SHRIGHT64 (val);
00231   }
00232 
00233   INT64TOCRAY64 (sing, val);
00234   CRAY64TO128 (*flt, sing);
00235   flt->coeff3 = chop;
00236   while (!(flt->coeff0 >> (AR_CRAY_C0_BITS - 1))) {
00237     expo--;
00238     SHLEFTCRAY128 (*flt);
00239   }
00240 
00241   flt->sign = neg;
00242   flt->expo = expo;
00243   return res;
00244 }
00245 
00246 
00247 /* IEEE 32 bit -> integer */
00248 int
00249 ar_ifix32 (AR_INT_64 *fix,
00250      const AR_IEEE_32 *flt,
00251      int bitsize,
00252      int roundmode) {
00253 
00254   int res = AR_STAT_OK, neg;
00255   int shift = AR_IEEE32_EXPO_BIAS + AR_IEEE32_COEFF_BITS - flt->expo;
00256   unsigned long rbits = 0;
00257   AR_IEEE_32 a = *flt;
00258 
00259   if (a.expo == 0 && !IS_IEEE32_NZ_COEFF(&a)) {
00260     ZERO64 (*fix);
00261     return AR_STAT_ZERO;
00262   }
00263   if (shift > AR_IEEE32_COEFF_BITS + AR_IEEE32_ROUND_BITS)
00264     shift = AR_IEEE32_COEFF_BITS + AR_IEEE32_ROUND_BITS;
00265 
00266   if (shift < AR_IEEE32_COEFF_BITS + 1 - bitsize)
00267     res |= AR_STAT_OVERFLOW;
00268 
00269   neg = a.sign;
00270   a.sign = 0;
00271   a.expo = !!a.expo;
00272   IEEE32TOINT64 (*fix, a);
00273 
00274   for ( ; shift < 0; shift++)
00275     SHLEFT64 (*fix);
00276   for ( ; shift > 0; shift--) {
00277     rbits = rbits & 1 | (rbits >> 1) |
00278       ((fix->part4 & 1) << (AR_IEEE32_ROUND_BITS - 1));
00279     SHRIGHT64 (*fix);
00280   }
00281   if (rbits)
00282     res |= AR_STAT_INEXACT;
00283 
00284   switch (roundmode) {
00285   case AR_ROUND_PLUS_INFINITY:
00286     if (!a.sign && rbits)
00287       INC64 (*fix);
00288     break;
00289   case AR_ROUND_MINUS_INFINITY:
00290     if (a.sign && rbits)
00291       DEC64 (*fix);
00292     break;
00293   case AR_ROUND_ZERO:
00294     break;
00295   default:
00296     if (rbits >> (AR_IEEE32_ROUND_BITS - 1) &&
00297         (rbits & MASKR (AR_IEEE32_ROUND_BITS - 1) ||
00298          fix->part4 & 1))
00299       INC64 (*fix);
00300     break;
00301   }
00302 
00303   if (fix->part1&0x8000)
00304     res |= (AR_STAT_OVERFLOW|AR_STAT_SEMIVALID);
00305 
00306   if (neg) {
00307     NOT64 (*fix);
00308     INC64 (*fix);
00309   }
00310 
00311   if (!(fix->part1 | fix->part2 | fix->part3 | fix->part4))
00312     res |= AR_STAT_ZERO;
00313   else if (neg)
00314     res |= AR_STAT_NEGATIVE;
00315 
00316   return res;
00317 }
00318 
00319 
00320 /* IEEE 64 bit -> integer */
00321 int
00322 ar_ifix64 (AR_INT_64 *fix,
00323      const AR_IEEE_64 *flt,
00324      int bitsize,
00325      int roundmode) {
00326 
00327   int res = AR_STAT_OK, neg;
00328   int shift = AR_IEEE64_EXPO_BIAS + AR_IEEE64_COEFF_BITS - flt->expo;
00329   unsigned long rbits = 0;
00330   AR_IEEE_64 a = *flt;
00331 
00332   if (a.expo == 0 && !IS_IEEE64_NZ_COEFF(&a)) {
00333     ZERO64 (*fix);
00334     return AR_STAT_ZERO;
00335   }
00336   if (shift > AR_IEEE64_COEFF_BITS + AR_IEEE64_ROUND_BITS)
00337     shift = AR_IEEE64_COEFF_BITS + AR_IEEE64_ROUND_BITS;
00338 
00339   if (shift < AR_IEEE64_COEFF_BITS + 1 - bitsize)
00340     res |= AR_STAT_OVERFLOW;
00341 
00342   neg = a.sign;
00343   a.sign = 0;
00344   a.expo = !!a.expo;
00345   IEEE64TOINT64 (*fix, a);
00346 
00347   for ( ; shift < 0; shift++)
00348     SHLEFT64 (*fix);
00349   for ( ; shift > 0; shift--) {
00350     rbits = rbits & 1 | (rbits >> 1) |
00351       ((fix->part4 & 1) << (AR_IEEE64_ROUND_BITS - 1));
00352     SHRIGHT64 (*fix);
00353   }
00354   if (rbits)
00355     res |= AR_STAT_INEXACT;
00356 
00357   switch (roundmode) {
00358   case AR_ROUND_PLUS_INFINITY:
00359     if (!a.sign && rbits)
00360       INC64 (*fix);
00361     break;
00362   case AR_ROUND_MINUS_INFINITY:
00363     if (a.sign && rbits)
00364       DEC64 (*fix);
00365     break;
00366   case AR_ROUND_ZERO:
00367     break;
00368   default:
00369     if (rbits >> (AR_IEEE64_ROUND_BITS - 1) &&
00370         (rbits & MASKR (AR_IEEE64_ROUND_BITS - 1) ||
00371          fix->part4 & 1))
00372       INC64 (*fix);
00373     break;
00374   }
00375 
00376   if (fix->part1&0x8000)
00377     res |= (AR_STAT_OVERFLOW|AR_STAT_SEMIVALID);
00378 
00379   if (neg) {
00380     NOT64 (*fix);
00381     INC64 (*fix);
00382   }
00383 
00384   if (!(fix->part1 | fix->part2 | fix->part3 | fix->part4))
00385     res |= AR_STAT_ZERO;
00386   else if (neg)
00387     res |= AR_STAT_NEGATIVE;
00388 
00389   return res;
00390 }
00391 
00392 
00393 /* IEEE 128 bit -> integer */
00394 int
00395 ar_ifix128 (AR_INT_64 *fix,
00396       const AR_IEEE_128 *flt,
00397       int bitsize,
00398       int roundmode)
00399 {
00400   int res = AR_STAT_OK, neg;
00401   int shift = AR_IEEE128_EXPO_BIAS + AR_IEEE128_COEFF_BITS-64+15 - flt->expo;
00402   unsigned long rbits = 0;
00403   AR_IEEE_128 a = *flt;
00404 
00405   /*
00406    * Use native arithmetic for MIPS.
00407    */
00408   if (HOST_IS_MIPS) {
00409     AR_TYPE ty = AR_Int_64_S;
00410     long double ld;
00411 
00412     ld = *(long double *) flt;
00413     *(long long *) fix = ld;
00414     return AR_status ((AR_DATA *) fix, &ty);
00415   }
00416 
00417   if (a.expo == 0 && !IS_IEEE128_NZ_COEFF(&a)) {
00418     ZERO64 (*fix);
00419     return AR_STAT_ZERO;
00420   }
00421   if (shift > AR_IEEE128_COEFF_BITS-64+15 + AR_IEEE128_ROUND_BITS)
00422     shift = AR_IEEE128_COEFF_BITS-64+15 + AR_IEEE128_ROUND_BITS;
00423 
00424   if (shift <= 0) {
00425     if(shift == 0)
00426       res |= AR_STAT_SEMIVALID;
00427     res |= AR_STAT_OVERFLOW;
00428     shift = 0;
00429   }
00430 
00431   neg = a.sign;
00432   fix->part1 = ((!!a.expo)<<15) | (a.coeff0>>1);
00433   fix->part2 =   (a.coeff0<<15) | (a.coeff1>>1);
00434   fix->part3 =   (a.coeff1<<15) | (a.coeff2>>1);
00435   fix->part4 =   (a.coeff2<<15) | (a.coeff3>>1);
00436 
00437   for ( ; shift > 0; shift--) {
00438     rbits = rbits & 1 | (rbits >> 1) |
00439       ((fix->part4 & 1) << (AR_IEEE128_ROUND_BITS - 1));
00440     SHRIGHT64 (*fix);
00441   }
00442   if (rbits)
00443     res |= AR_STAT_INEXACT;
00444 
00445   switch (roundmode) {
00446   case AR_ROUND_PLUS_INFINITY:
00447     if (!a.sign && rbits)
00448       INC64 (*fix);
00449     break;
00450   case AR_ROUND_MINUS_INFINITY:
00451     if (a.sign && rbits)
00452       DEC64 (*fix);
00453     break;
00454   case AR_ROUND_ZERO:
00455     break;
00456   default:
00457     if (rbits >> (AR_IEEE128_ROUND_BITS - 1) &&
00458         (rbits & MASKR (AR_IEEE128_ROUND_BITS - 1) ||
00459          fix->part4 & 1))
00460       INC64 (*fix);
00461     break;
00462   }
00463 
00464   if (neg) {
00465     NOT64 (*fix);
00466     INC64 (*fix);
00467   }
00468 
00469   if (!(fix->part1 | fix->part2 | fix->part3 | fix->part4))
00470     res |= AR_STAT_ZERO;
00471   else if (neg)
00472     res |= AR_STAT_NEGATIVE;
00473 
00474   return res;
00475 }
00476 
00477 
00478 /* integer -> IEEE 32 bit */
00479 int
00480 ar_iflt32 (AR_IEEE_32 *flt,
00481      const AR_INT_64 *fix,
00482      int is_unsigned,
00483      int roundmode) {
00484 
00485   int neg = 0;
00486   unsigned long lbits, rbits;
00487   AR_INT_64 val;
00488 
00489   COPY64 (val, *fix);
00490   if (SIGNBIT (val) && !is_unsigned) {
00491     NEG64 (val);
00492     neg = 1;
00493   }
00494 
00495   rbits = 0;
00496   while (val.part1 | val.part2) {
00497     rbits = rbits & 1 | (rbits >> 1) |
00498             ((val.part4 & 1) << (AR_IEEE32_ROUND_BITS - 1));
00499     SHRIGHT64 (val);
00500   }
00501 
00502   INT64TOIEEE32 (*flt, val);
00503   lbits = val.part3 >> (16 - (AR_IEEE32_EXPO_BITS + 1));
00504   flt->sign = neg;
00505 
00506   return ar_i32norm (AR_IEEE32_EXPO_BIAS + AR_IEEE32_COEFF_BITS,
00507          lbits,
00508          rbits,
00509          flt,
00510          roundmode);
00511 }
00512 
00513 
00514 /* integer -> IEEE 64 bit */
00515 int
00516 ar_iflt64 (AR_IEEE_64 *flt,
00517      const AR_INT_64 *fix,
00518      int is_unsigned,
00519      int roundmode) {
00520 
00521   int neg = 0;
00522   unsigned long lbits;
00523   AR_INT_64 val;
00524 
00525   if (SIGNBIT (*fix) && !is_unsigned) {
00526     COPY64 (val, *fix);
00527     NEG64 (val);
00528     fix = &val;
00529     neg = 1;
00530   }
00531 
00532   INT64TOIEEE64 (*flt, *fix);
00533   lbits = fix->part1 >> (16 - (AR_IEEE64_EXPO_BITS + 1));
00534   flt->sign = neg;
00535 
00536   return ar_i64norm (AR_IEEE64_EXPO_BIAS + AR_IEEE64_COEFF_BITS,
00537          lbits,
00538          0, /* rbits */
00539          flt,
00540          roundmode);
00541 }
00542 
00543 
00544 /* integer -> IEEE 128 bit */
00545 int
00546 ar_iflt128 (AR_IEEE_128 *flt,
00547      const AR_INT_64 *fix,
00548      int is_unsigned,
00549      int roundmode) {
00550 
00551   int neg = 0;
00552   unsigned long lbits;
00553   AR_INT_64 val;
00554 
00555   /*
00556    * Use native arithmetic for MIPS.
00557    */
00558   if (HOST_IS_MIPS) {
00559     long double ld;
00560     long long li;
00561     AR_TYPE ty = AR_Float_IEEE_NR_128;
00562 
00563     li = *(long long *) fix;
00564     ld = li;
00565     memcpy(flt,&ld,sizeof(long double));
00566     return AR_status ((AR_DATA *) flt, &ty);
00567   }
00568 
00569   if (SIGNBIT (*fix) && !is_unsigned) {
00570     COPY64 (val, *fix);
00571     NEG64 (val);
00572     fix = &val;
00573     neg = 1;
00574   }
00575 
00576   flt->coeff3 = flt->coeff4 = flt->coeff5 = flt->coeff6 = 0;
00577   INT64TOIEEE128 (*flt, *fix);
00578   lbits = fix->part1 >> (16 - (AR_IEEE128_EXPO_BITS + 1));
00579   flt->sign = neg;
00580 
00581   return ar_i128norm (AR_IEEE128_EXPO_BIAS + AR_IEEE128_COEFF_BITS-64,
00582          lbits,
00583          0, /* rbits */
00584          flt,
00585          roundmode);
00586 }
00587 
00588 
00589 /* IEEE 64 -> Cray single */
00590 int
00591 ar_itoc64 (AR_CRAY_64 *to,
00592      const AR_IEEE_64 *from,
00593      int roundmode) {
00594 
00595   int toexpo;
00596   AR_INT_64 coeff;
00597   AR_IEEE_64 v, fact;
00598   AR_CRAY_64 zero;
00599 
00600   if (from->expo > AR_IEEE64_MAX_EXPO) {
00601     to->expo = AR_CRAY_MAX_EXPO + 1;
00602     to->coeff0 = 1 << (AR_CRAY_C0_BITS - 1);
00603     to->coeff1 = to->coeff2 = 0;
00604     return AR_STAT_OVERFLOW;
00605   }
00606 
00607   /* Extract the coefficient as an unsigned integer, rounded to
00608    * Cray precision.
00609    */
00610   v = *from;
00611   v.sign = 0;
00612   toexpo = from->expo + AR_CRAY_EXPO_BIAS - AR_IEEE64_EXPO_BIAS;
00613   if (!v.expo) {
00614     /* Denormalized value; try to normalize it */
00615     ZEROIEEE64 (fact);
00616     fact.expo = AR_IEEE64_EXPO_BIAS + AR_IEEE64_COEFF_BITS;
00617     (void) ar_ifmul64 (&v, &v, &fact, roundmode);
00618     if (!v.expo) {
00619       ZEROCRAY64 (*to);
00620       return AR_STAT_ZERO;
00621     }
00622     toexpo = v.expo + 1 + AR_CRAY_EXPO_BIAS - AR_IEEE64_EXPO_BIAS -
00623         AR_IEEE64_COEFF_BITS;
00624   }
00625   v.expo = AR_IEEE64_EXPO_BIAS + AR_CRAY64_COEFF_BITS - 1;
00626   (void) ar_ifix64 (&coeff, &v, AR_IEEE64_COEFF_BITS, roundmode);
00627   INT64TOCRAY64 (*to, coeff);
00628   if (to->expo) {
00629     SHRIGHTCRAY64 (*to);
00630     to->coeff0 |= 1 << (AR_CRAY_C0_BITS - 1);
00631     toexpo++;
00632   }
00633   to->sign = from->sign;
00634   to->expo = toexpo;
00635 
00636   /* Normalize and return */
00637   ZEROCRAY64 (zero);
00638   return ar_cfadd64 (to, to, &zero);
00639 }
00640 
00641 
00642 /* IEEE 128 -> Cray double */
00643 int
00644 ar_itoc128(AR_CRAY_128 *to,
00645      const AR_IEEE_128 *from,
00646      int roundmode) {
00647 
00648   int toexpo;
00649   AR_IEEE_128 v, fact;
00650   AR_CRAY_128 zero;
00651 
00652   if (from->expo > AR_IEEE128_MAX_EXPO) {
00653     to->expo = AR_CRAY_MAX_EXPO + 1;
00654     to->coeff0 = 1 << (AR_CRAY_C0_BITS - 1);
00655     to->coeff1 = to->coeff2 = to->coeff3 = to->coeff4 = to->coeff5 = 0;
00656     return AR_STAT_OVERFLOW;
00657   }
00658 
00659   v = *from;
00660   v.sign = 0;
00661   toexpo = from->expo + AR_CRAY_EXPO_BIAS - AR_IEEE128_EXPO_BIAS;
00662   if (!v.expo) {
00663     /* Denormalized value; try to normalize it */
00664     ZEROIEEE128 (fact);
00665     fact.expo = AR_IEEE128_EXPO_BIAS + AR_IEEE128_COEFF_BITS;
00666     (void) ar_ifmul128 (&v, &v, &fact, roundmode);
00667     if (!v.expo) {
00668       ZEROCRAY128 (*to);
00669       return AR_STAT_ZERO;
00670     }
00671     toexpo = v.expo + 2 + AR_CRAY_EXPO_BIAS - AR_IEEE128_EXPO_BIAS -
00672         AR_IEEE128_COEFF_BITS;
00673   }
00674 
00675   if(toexpo > AR_CRAY_MAX_EXPO) {
00676     to->expo = AR_CRAY_MAX_EXPO + 1;
00677     to->coeff0 = 1 << (AR_CRAY_C0_BITS - 1);
00678     to->coeff1 = to->coeff2 = to->coeff3 = to->coeff4 = to->coeff5 = 0;
00679     return AR_STAT_OVERFLOW;
00680   }
00681 
00682   to->coeff0 = v.coeff0;
00683   to->coeff1 = v.coeff1;
00684   to->coeff2 = v.coeff2;
00685   to->zero   = 0;
00686   to->coeff3 = v.coeff3;
00687   to->coeff4 = v.coeff4;
00688   to->coeff5 = v.coeff5;
00689   SHRIGHTCRAY128(*to);
00690   to->coeff0 |= 1 << (AR_CRAY_C0_BITS - 1);
00691 
00692   to->sign = from->sign;
00693   to->expo = toexpo;
00694 
00695   /* Normalize, set status, and return */
00696   ZEROCRAY128 (zero);
00697   return ar_cfadd128(to, to, &zero);
00698 }
00699 
00700 
00701 /* IEEE 64 -> Cray double */
00702 int
00703 ar_i64toc128 (AR_CRAY_128 *to, const AR_IEEE_64 *from) {
00704 
00705   int res, toexpo;
00706   AR_INT_64 coeff;
00707   AR_IEEE_64 v, fact;
00708   AR_CRAY_64 sing;
00709   AR_CRAY_128 zero;
00710 
00711   if (from->expo > AR_IEEE64_MAX_EXPO) {
00712     to->expo = AR_CRAY_MAX_EXPO + 1;
00713     to->coeff0 = 1 << (AR_CRAY_C0_BITS - 1);
00714     to->coeff1 = to->coeff2 = 0;
00715     return AR_STAT_OVERFLOW;
00716   }
00717 
00718   /* Extract the coefficient as an unsigned integer */
00719   v = *from;
00720   v.sign = 0;
00721   toexpo = from->expo + AR_CRAY_EXPO_BIAS - AR_IEEE64_EXPO_BIAS;
00722   if (!v.expo) {
00723     /* Denormalized value; try to normalize it */
00724     ZEROIEEE64 (fact);
00725     fact.expo = AR_IEEE64_EXPO_BIAS + AR_IEEE64_COEFF_BITS;
00726     (void) ar_ifmul64 (&v, &v, &fact, AR_ROUND_NEAREST);
00727     if (!v.expo) {
00728       ZEROCRAY128 (*to);
00729       return AR_STAT_ZERO;
00730     }
00731     toexpo = v.expo + 1 + AR_CRAY_EXPO_BIAS - AR_IEEE64_EXPO_BIAS -
00732         AR_IEEE64_COEFF_BITS;
00733   }
00734   v.expo = AR_IEEE64_EXPO_BIAS + AR_IEEE64_COEFF_BITS;
00735   (void) ar_ifix64 (&coeff, &v, AR_IEEE64_COEFF_BITS, AR_ROUND_NEAREST);
00736   INT64TOCRAY64 (sing, coeff);
00737   CRAY64TO128 (*to, sing);
00738   toexpo -= AR_IEEE64_COEFF_BITS + 1 - AR_CRAY64_COEFF_BITS;
00739   while (to->expo) {
00740     SHRIGHTCRAY128 (*to);
00741     to->coeff0 |= to->expo << (AR_CRAY_C0_BITS - 1);
00742     to->expo >>= 1;
00743     toexpo++;
00744   }
00745   to->sign = from->sign;
00746   to->expo = toexpo;
00747 
00748   /* Normalize and return */
00749   ZEROCRAY128 (zero);
00750   return ar_cfadd128 (to, to, &zero);
00751 }
00752 
00753 
00754 /* Cray 64 -> IEEE 64 */
00755 int
00756 ar_ctoi64 (AR_IEEE_64 *to, const AR_CRAY_64 *from) {
00757 
00758   int res = AR_STAT_OK;
00759   AR_INT_64 coeff;
00760   AR_CRAY_64 v = *from;
00761   int expo;
00762 
00763   if (from->expo > AR_CRAY_MAX_EXPO) {
00764     /* Overflow yields a quiet NaN */
00765     if (HOST_IS_MIPS) {
00766       QNaNIEEE64 (to);
00767     }
00768     else {
00769       ZEROIEEE64 (*to);
00770       if (to->sign = v.sign)
00771         res |= AR_STAT_NEGATIVE;
00772       to->expo = AR_IEEE64_MAX_EXPO + 1;
00773       to->coeff0 = 1 << (AR_IEEE64_C0_BITS - 1);
00774     }
00775     return res | AR_STAT_OVERFLOW;
00776   }
00777 
00778   v.sign = 0;
00779   v.expo = 0;
00780   CRAY64TOINT64 (coeff, v);
00781   INT64TOIEEE64 (*to, coeff);
00782   to->sign = from->sign;
00783   expo = from->expo + AR_IEEE64_EXPO_BIAS - AR_CRAY_EXPO_BIAS +
00784           AR_IEEE64_COEFF_BITS + 1 - AR_CRAY64_COEFF_BITS;
00785   if (expo <= 0)
00786     expo--;
00787 
00788   return ar_i64norm (expo,
00789          0, /* lbits */
00790          0, /* rbits */
00791          to,
00792          AR_ROUND_NEAREST);
00793 }
00794 
00795 
00796 /* Cray 128 -> IEEE 128 */
00797 int
00798 ar_ctoi128 (AR_IEEE_128 *to, const AR_CRAY_128 *from) {
00799 
00800   int res = AR_STAT_OK;
00801   AR_CRAY_128 v = *from;
00802   int expo;
00803 
00804   if (from->expo > AR_CRAY_MAX_EXPO) {
00805     /* Overflow yields a quiet NaN */
00806     if (HOST_IS_MIPS) {
00807       QNaNIEEE128 (to);
00808     }
00809     else {
00810       ZEROIEEE128 (*to);
00811       if (to->sign = v.sign)
00812         res |= AR_STAT_NEGATIVE;
00813       to->expo = AR_IEEE128_MAX_EXPO + 1;
00814       to->coeff0 = 1 << (AR_IEEE128_C0_BITS - 1);
00815     }
00816     return res | AR_STAT_OVERFLOW;
00817   }
00818 
00819   to->sign = v.sign;
00820   to->expo = 0;
00821   to->coeff0 = v.coeff0;
00822   to->coeff1 = v.coeff1;
00823   to->coeff2 = v.coeff2;
00824   to->coeff3 = v.coeff3;
00825   to->coeff4 = v.coeff4;
00826   to->coeff5 = v.coeff5;
00827   to->coeff6 = 0;
00828   expo = v.expo + AR_IEEE128_EXPO_BIAS - AR_CRAY_EXPO_BIAS +
00829           AR_IEEE128_COEFF_BITS + 1 - AR_CRAY128_COEFF_BITS;
00830   if (expo <= 0)
00831     expo--;
00832 
00833   return ar_i128norm (expo,
00834          0, /* lbits */
00835          0, /* rbits */
00836          to,
00837          AR_ROUND_NEAREST);
00838 }
00839 
00840 
00841 /* Cray 128 -> IEEE 64 */
00842 int
00843 ar_c128toi64 (AR_IEEE_64 *to, const AR_CRAY_128 *from) {
00844 
00845   int res = AR_STAT_OK;
00846   AR_INT_64 coeff;
00847   AR_CRAY_128 v = *from;
00848   AR_CRAY_64 v64;
00849   int i;
00850   int rbits;
00851   int expo;
00852 
00853   if (from->expo > AR_CRAY_MAX_EXPO) {
00854     /* Overflow yields a quiet NaN */
00855     if (HOST_IS_MIPS) {
00856       QNaNIEEE64 (to);
00857     }
00858     else {
00859       ZEROIEEE64 (*to);
00860       if (to->sign = v.sign)
00861         res |= AR_STAT_NEGATIVE;
00862       to->expo = AR_IEEE64_MAX_EXPO + 1;
00863       to->coeff0 = 1 << (AR_IEEE64_C0_BITS - 1);
00864     }
00865     return res | AR_STAT_OVERFLOW;
00866   }
00867 
00868   v.sign = 0;
00869   v.expo = 0;
00870   CRAY128TO64 (v64, v);
00871   CRAY64TOINT64 (coeff, v64);
00872   INT64TOIEEE64 (*to, coeff);
00873 
00874   /* Move upper bits of second part into low bits */
00875   for (i = 0; i < AR_IEEE64_COEFF_BITS - AR_CRAY64_COEFF_BITS; i++)
00876     SHLEFTIEEE64 (*to);
00877   to->coeff3 |= v.coeff3 >> (AR_CRAY_C3_BITS -
00878            (AR_IEEE64_COEFF_BITS -
00879             AR_CRAY64_COEFF_BITS));
00880 
00881   /* Compute guard, round, and sticky bits */
00882   rbits = (v.coeff3 >> (AR_CRAY_C3_BITS - AR_IEEE64_ROUND_BITS -
00883             (AR_IEEE64_COEFF_BITS - AR_CRAY64_COEFF_BITS))) &
00884     MASKR (AR_IEEE64_ROUND_BITS);
00885   rbits |= !!(v.coeff3 & MASKR (AR_CRAY_C3_BITS - AR_IEEE64_ROUND_BITS -
00886               (AR_IEEE64_COEFF_BITS -
00887                AR_CRAY64_COEFF_BITS) - 1) |
00888         v.coeff4 | v.coeff5);
00889 
00890   to->sign = from->sign;
00891   expo = from->expo + AR_IEEE64_EXPO_BIAS - AR_CRAY_EXPO_BIAS + 1;
00892   if (expo <= 0)
00893     expo--;
00894 
00895   return ar_i64norm (expo,
00896          0, /* lbits */
00897          rbits,
00898          to,
00899          AR_ROUND_NEAREST);
00900 }
00901 
00902 
00903 /* Cray double -> single */
00904 int
00905 ar_c128to64 (AR_CRAY_64 *s, const AR_CRAY_128 *d) {
00906 
00907   int res = AR_STAT_OK;
00908 
00909   if (!(d->sign | d->expo | d->coeff0 | d->coeff1 | d->coeff2))
00910     res |= AR_STAT_ZERO;
00911   else if (d->sign)
00912     res |= AR_STAT_NEGATIVE;
00913 
00914   /* Truncated value is returned since that is what all compilers do */
00915   CRAY128TO64 (*s, *d);
00916 
00917   return res;
00918 }
00919 
00920 /* Cray single -> double */
00921 int
00922 ar_c64to128 (AR_CRAY_128 *d, const AR_CRAY_64 *s) {
00923 
00924   int res = AR_STAT_OK;
00925 
00926   if (!(s->sign | s->expo | s->coeff0 | s->coeff1 | s->coeff2))
00927     res |= AR_STAT_ZERO;
00928   else if (s->sign)
00929     res |= AR_STAT_NEGATIVE;
00930 
00931   CRAY64TO128(*d, *s);
00932 
00933   return res;
00934 }
00935 
00936 
00937 /* IEEE 64 -> IEEE 32 */
00938 int
00939 ar_i64to32 (AR_IEEE_32 *s, const AR_IEEE_64 *d, const int roundmode) {
00940 
00941   int res = AR_STAT_OK;
00942   int expo;
00943   unsigned long lbits, rbits;
00944 
00945 # if AR_IEEE32_C0_BITS < AR_IEEE64_C0_BITS
00946 #   error ar_i64to32 has coefficient shifts miscoded.
00947 # else
00948 #   define COEFF_BIT_OFF  (AR_IEEE32_C0_BITS - AR_IEEE64_C0_BITS)
00949 # endif
00950 
00951   if (d->expo > AR_IEEE64_MAX_EXPO) {
00952     if (IS_IEEE64_NZ_COEFF(d)) {
00953       /* WARNING: the following code makes some assumptions about
00954        * bit field sizes!
00955        *
00956        * Incoming quantity is a NaN; return a NaN with the
00957        * same high AR_IEEE32_COEFF_BITS bits.  The result
00958        * must have at least one non-zero coefficient bit.
00959        */
00960       ZEROIEEE32 (*s);
00961       s->sign    = d->sign;
00962       s->expo    = AR_IEEE32_MAX_EXPO + 1;
00963       s->coeff1  = (d->coeff2 >> (AR_IEEE64_C2_BITS - COEFF_BIT_OFF)) |
00964              (d->coeff1 << COEFF_BIT_OFF);
00965       s->coeff0  = (d->coeff1 >> (AR_IEEE64_C1_BITS - COEFF_BIT_OFF)) |
00966              (d->coeff0 << COEFF_BIT_OFF);
00967       if (!IS_IEEE32_NZ_COEFF(s)) {
00968         s->coeff1 = 1;
00969       }
00970       return AR_STAT_UNDEFINED;
00971     } else {
00972       /* It's +/-Inf */
00973       ZEROIEEE32 (*s);
00974       s->expo = AR_IEEE32_MAX_EXPO + 1;
00975       if (s->sign = d->sign)
00976         res |= AR_STAT_NEGATIVE;
00977       return res | AR_STAT_OVERFLOW;
00978     }
00979   }
00980 
00981   if (d->sign)
00982     res |= AR_STAT_NEGATIVE;
00983 
00984   /* Incoming denorm must underflow to zero. */
00985   if (!d->expo) {
00986     s->sign = d->sign;
00987     s->zero = s->expo = s->coeff0 = s->coeff1 = 0;
00988     res |= AR_STAT_ZERO;
00989     if (IS_IEEE64_NZ_COEFF(d))
00990         if(ar_state_register.ar_denorms_trap)
00991         res |= AR_STAT_UNDERFLOW;
00992         else
00993         res |= AR_STAT_UNDEFINED;
00994     return res;
00995   }
00996 
00997   lbits = 1;
00998   expo = d->expo - AR_IEEE64_EXPO_BIAS + AR_IEEE32_EXPO_BIAS;
00999   if (expo <= 0)
01000     expo--;
01001 
01002   /* WARNING: the following code makes some assumptions about
01003    * bit field sizes!
01004    *
01005    * Compress rightmost 29 bits of incoming coefficient into
01006    * a 3-bit guard/round/sticky set of rounding bits.
01007    */
01008   rbits = ((d->coeff2 >> 10) & 07) |      /* G and R */
01009     !!(d->coeff2 & MASKR (10) | d->coeff3);   /* sticky  */
01010 
01011   /* Move upper 23 bits of incoming coefficient into place */
01012   s->coeff1 = (d->coeff2 >> (AR_IEEE64_C2_BITS - COEFF_BIT_OFF)) |
01013         (d->coeff1 << COEFF_BIT_OFF);
01014   s->coeff0 = (d->coeff1 >> (AR_IEEE64_C2_BITS - COEFF_BIT_OFF)) |
01015         (d->coeff0 << COEFF_BIT_OFF);
01016 
01017   s->sign = d->sign;
01018         s->zero = 0;
01019 
01020   return ar_i32norm (expo, lbits, rbits, s, roundmode);
01021 
01022 # undef COEFF_BIT_OFF
01023 }
01024 
01025 
01026 /* IEEE 32 -> IEEE 64 */
01027 int
01028 ar_i32to64 (AR_IEEE_64 *d, const AR_IEEE_32 *s) {
01029 
01030   int expo;
01031 
01032 # if AR_IEEE32_C0_BITS < AR_IEEE64_C0_BITS
01033 #   error ar_i32to64 has coefficient shifts miscoded.
01034 # else
01035 #   define COEFF_BIT_OFF  (AR_IEEE32_C0_BITS - AR_IEEE64_C0_BITS)
01036 # endif
01037 
01038   if (s->expo > AR_IEEE32_MAX_EXPO) {
01039     if (IS_IEEE32_NZ_COEFF(s)) {
01040       /* WARNING: the following code makes some assumptions about
01041        * bit field sizes!
01042        *
01043        * Incoming quantity is a NaN; return a NaN with the
01044        * same high AR_IEEE32_COEFF_BITS bits.  The result
01045        * must have at least one non-zero coefficient bit.
01046        */
01047       ZEROIEEE64 (*d);
01048       d->sign   = s->sign;
01049       d->expo   = AR_IEEE64_MAX_EXPO + 1;
01050       d->coeff0 = s->coeff0 >> COEFF_BIT_OFF;
01051       d->coeff1 = (s->coeff0 << (AR_IEEE64_C1_BITS - COEFF_BIT_OFF)) |
01052             (s->coeff1 >> COEFF_BIT_OFF);
01053       d->coeff2 = s->coeff1 << (AR_IEEE64_C2_BITS - COEFF_BIT_OFF);
01054       d->coeff3 = 0;
01055       if (!IS_IEEE64_NZ_COEFF(d)) {
01056         d->coeff3 = 1;
01057       }
01058       return AR_STAT_UNDEFINED;
01059     } else {
01060       /* It's +/-Inf */
01061       ZEROIEEE64 (*d);
01062       d->expo = AR_IEEE64_MAX_EXPO + 1;
01063       if (d->sign = s->sign)
01064         return AR_STAT_OVERFLOW | AR_STAT_NEGATIVE;
01065       return AR_STAT_OVERFLOW;
01066     }
01067   }
01068 
01069   d->sign = s->sign;
01070   if (s->expo)
01071     expo = s->expo - AR_IEEE32_EXPO_BIAS + AR_IEEE64_EXPO_BIAS;
01072   else
01073     expo = 0;
01074 
01075   /* WARNING: the following code makes some assumptions about
01076    * bit field sizes!
01077    *
01078    * Copy incoming coefficient into the upper 23 bits of the result.
01079    */
01080   d->coeff0 = s->coeff0 >> COEFF_BIT_OFF;
01081   d->coeff1 = (s->coeff0 << (AR_IEEE64_C1_BITS - COEFF_BIT_OFF)) |
01082         (s->coeff1 >> COEFF_BIT_OFF);
01083   d->coeff2 = s->coeff1 << (AR_IEEE64_C2_BITS - COEFF_BIT_OFF);
01084   d->coeff3 = 0;
01085 
01086   return ar_i64norm (expo,
01087          !!s->expo /* lbits */,
01088          0 /* rbits */,
01089          d,
01090          AR_ROUND_NEAREST /* ignored */);
01091 
01092 # undef COEFF_BIT_OFF
01093 }
01094 
01095 
01096 /* IEEE 128 -> IEEE 64 */
01097 int
01098 ar_i128to64 (AR_IEEE_64 *d, const AR_IEEE_128 *q, const int roundmode) {
01099 
01100   int res = AR_STAT_OK;
01101   int expo;
01102   unsigned long lbits, rbits;
01103 
01104   /*
01105    * Use native arithmetic for MIPS.
01106    */
01107   if (HOST_IS_MIPS) {
01108     AR_TYPE ty = AR_Float_IEEE_NR_64;
01109 
01110     *(double *) d = *(long double *) q;
01111     return AR_status ((AR_DATA *) d, &ty);
01112   }
01113 
01114 # if AR_IEEE128_C0_BITS < AR_IEEE64_C0_BITS
01115 #   error ar_i128to64 has coefficient shifts miscoded.
01116 # else
01117 #   define COEFF_BIT_OFF  (AR_IEEE128_C0_BITS - AR_IEEE64_C0_BITS)
01118 # endif
01119 
01120   if (q->expo > AR_IEEE128_MAX_EXPO) {
01121     if (IS_IEEE128_NZ_COEFF(q)) {
01122       /* WARNING: the following code makes some assumptions about
01123        * bit field sizes!
01124        *
01125        * Incoming quantity is a NaN; return a NaN with the
01126        * same high AR_IEEE64_COEFF_BITS bits.  The result
01127        * must have at least one non-zero coefficient bit.
01128        */
01129       ZEROIEEE64 (*d);
01130       d->sign    = q->sign;
01131       d->expo    = AR_IEEE64_MAX_EXPO + 1;
01132       d->coeff3 = (q->coeff3 >> COEFF_BIT_OFF) |
01133             (q->coeff2 << AR_IEEE64_C0_BITS);
01134       d->coeff2 = (q->coeff2 >> COEFF_BIT_OFF) |
01135             (q->coeff1 << AR_IEEE64_C0_BITS);
01136       d->coeff1 = (q->coeff1 >> COEFF_BIT_OFF) |
01137             (q->coeff0 << AR_IEEE64_C0_BITS);
01138       d->coeff0 = (q->coeff0 >> COEFF_BIT_OFF);
01139       if (!IS_IEEE64_NZ_COEFF(d)) {
01140         d->coeff3 = 1;
01141       }
01142       return AR_STAT_UNDEFINED;
01143     } else {
01144       /* It's +/-Inf */
01145       ZEROIEEE64 (*d);
01146       d->expo = AR_IEEE64_MAX_EXPO + 1;
01147       if (d->sign = q->sign)
01148         res |= AR_STAT_NEGATIVE;
01149       return res | AR_STAT_OVERFLOW;
01150     }
01151   }
01152 
01153   if (q->sign)
01154     res |= AR_STAT_NEGATIVE;
01155 
01156   /* Incoming denorm must underflow to zero. */
01157   if (!q->expo) {
01158     d->sign = q->sign;
01159     d->expo = d->coeff0 = d->coeff1 = d->coeff2 = d->coeff3 = 0;
01160     res |= AR_STAT_ZERO;
01161     if (IS_IEEE128_NZ_COEFF(q))
01162         if(ar_state_register.ar_denorms_trap)
01163         res |= AR_STAT_UNDERFLOW;
01164         else
01165         res |= AR_STAT_UNDEFINED;
01166     return res;
01167   }
01168 
01169   lbits = 1;
01170   expo = q->expo - AR_IEEE128_EXPO_BIAS + AR_IEEE64_EXPO_BIAS;
01171   if (expo <= 0)
01172     expo--;
01173 
01174   /* WARNING: the following code makes some assumptions about
01175    * bit field sizes!
01176    *
01177    * Compress rightmost bits of incoming coefficient into
01178    * a 3-bit guard/round/sticky set of rounding bits.
01179    */
01180   rbits = ((q->coeff3 >> 9) & 07) |     /* G and R */
01181     !!(q->coeff3 & MASKR (9) |
01182        q->coeff4 | q->coeff5 | q->coeff6);    /* sticky */
01183 
01184   /* Move upper bits of incoming coefficient into place */
01185   d->coeff3 = (q->coeff3 >> COEFF_BIT_OFF) |
01186         (q->coeff2 << AR_IEEE64_C0_BITS);
01187   d->coeff2 = (q->coeff2 >> COEFF_BIT_OFF) |
01188         (q->coeff1 << AR_IEEE64_C0_BITS);
01189   d->coeff1 = (q->coeff1 >> COEFF_BIT_OFF) |
01190         (q->coeff0 << AR_IEEE64_C0_BITS);
01191   d->coeff0 = (q->coeff0 >> COEFF_BIT_OFF);
01192 
01193   d->sign = q->sign;
01194 
01195   return ar_i64norm (expo, lbits, rbits, d, roundmode);
01196 
01197 # undef COEFF_BIT_OFF
01198 }
01199 
01200 
01201 /* IEEE 64 -> IEEE 128 */
01202 int
01203 ar_i64to128 (AR_IEEE_128 *q, const AR_IEEE_64 *d) {
01204 
01205   int expo;
01206 
01207   /*
01208    * Use native arithmetic for MIPS.
01209    */
01210   if (HOST_IS_MIPS) {
01211     AR_TYPE ty = AR_Float_IEEE_NR_128;
01212 
01213     *(long double *) q = *(double *) d;
01214     return AR_status ((AR_DATA *) q, &ty);
01215   }
01216 
01217 # if AR_IEEE128_C0_BITS < AR_IEEE64_C0_BITS
01218 #   error ar_i64to128 has coefficient shifts miscoded.
01219 # else
01220 #   define COEFF_BIT_OFF  (AR_IEEE128_C0_BITS - AR_IEEE64_C0_BITS)
01221 # endif
01222 
01223   if (d->expo > AR_IEEE64_MAX_EXPO) {
01224     if (IS_IEEE64_NZ_COEFF(d)) {
01225       /* WARNING: the following code makes some assumptions about
01226        * bit field sizes!
01227        *
01228        * Incoming quantity is a NaN; return a NaN with the
01229        * same high AR_IEEE64_COEFF_BITS bits.  The result
01230        * must have at least one non-zero coefficient bit.
01231        */
01232       ZEROIEEE128 (*q);
01233       q->sign   = d->sign;
01234       q->expo   = AR_IEEE128_MAX_EXPO + 1;
01235       q->coeff0 = (d->coeff0 << COEFF_BIT_OFF) |
01236             (d->coeff1 >> AR_IEEE64_C0_BITS);
01237       q->coeff1 = (d->coeff1 << COEFF_BIT_OFF) |
01238             (d->coeff2 >> AR_IEEE64_C0_BITS);
01239       q->coeff2 = (d->coeff2 << COEFF_BIT_OFF) |
01240             (d->coeff3 >> AR_IEEE64_C0_BITS);
01241       q->coeff3 = (d->coeff3 << COEFF_BIT_OFF);
01242       q->coeff4 = 0;
01243       q->coeff5 = 0;
01244       q->coeff6 = 0;
01245       if (!IS_IEEE128_NZ_COEFF(q)) {
01246         q->coeff6 = 1;
01247       }
01248       return AR_STAT_UNDEFINED;
01249     } else {
01250       /* It's +/-Inf */
01251       ZEROIEEE128 (*q);
01252       q->expo = AR_IEEE128_MAX_EXPO + 1;
01253       if (q->sign = d->sign)
01254         return AR_STAT_OVERFLOW | AR_STAT_NEGATIVE;
01255       return AR_STAT_OVERFLOW;
01256     }
01257   }
01258 
01259   q->sign = d->sign;
01260   if (d->expo)
01261     expo = d->expo - AR_IEEE64_EXPO_BIAS + AR_IEEE128_EXPO_BIAS;
01262   else
01263     expo = 0;
01264 
01265   /* WARNING: the following code makes some assumptions about
01266    * bit field sizes!
01267    *
01268    * Copy incoming coefficient into the upper bits of the result.
01269    */
01270   q->coeff0 = (d->coeff0 << COEFF_BIT_OFF) |
01271         (d->coeff1 >> AR_IEEE64_C0_BITS);
01272   q->coeff1 = (d->coeff1 << COEFF_BIT_OFF) |
01273         (d->coeff2 >> AR_IEEE64_C0_BITS);
01274   q->coeff2 = (d->coeff2 << COEFF_BIT_OFF) |
01275         (d->coeff3 >> AR_IEEE64_C0_BITS);
01276   q->coeff3 = (d->coeff3 << COEFF_BIT_OFF);
01277   q->coeff4 = 0;
01278   q->coeff5 = 0;
01279   q->coeff6 = 0;
01280 
01281   return ar_i128norm (expo,
01282          !!d->expo /* lbits */,
01283          0 /* rbits */,
01284          q,
01285          AR_ROUND_NEAREST /* ignored */);
01286 
01287 # undef COEFF_BIT_OFF
01288 }
01289 
01290 #ifdef __mips
01291 #if 0 
01292 /* Conversions to/from MIPS quad to IEEE quad */
01293  
01294 int
01295 ar_m128toi128(AR_IEEE_128 *out, long double *in)
01296 {
01297   int res;
01298 
01299   AR_IEEE_128 lo, hi;
01300 
01301   /* A MIPS quad is 2 doubles, so to convert to an IEEE
01302    * quad, just add them.
01303    */
01304 
01305   res  = ar_i64to128(&hi, &((AR_IEEE_64 *) in)[0]);
01306   res |= ar_i64to128(&lo, &((AR_IEEE_64 *) in)[1]);
01307   res |= ar_ifadd128(out, &lo, &hi, AR_ROUND_NEAREST);
01308 
01309   return (res);
01310 }
01311  
01312 int
01313 ar_i128tom128(long double *out, AR_IEEE_128 *in)
01314 {
01315   int res;
01316 
01317   AR_IEEE_64  lo64,   hi64;
01318   AR_IEEE_128 low128, hi128;
01319   long double lo1,    hi1;
01320 
01321   /* Convert by setting hi part of out to 
01322    * (double) in, low part of out to the rest.
01323    */
01324   res = ar_i128to64(&hi64, in, AR_ROUND_NEAREST);
01325   res |= ar_i64to128(&hi128, &hi64);
01326   res |= ar_ifsub128(&low128, in, &hi128, AR_ROUND_NEAREST);
01327   res |= ar_i128to64(&lo64, &low128, AR_ROUND_NEAREST);
01328 
01329   lo1 = *((double *) &lo64);
01330   hi1 = *((double *) &hi64);
01331   *out = lo1 + hi1;
01332   return (res);
01333 }
01334  
01335 /* Fortran interfaces for above 2 routines */
01336 void ar_m128toi128_(AR_IEEE_128 *out, long double *in)
01337 {
01338    (void) ar_m128toi128(out,in);
01339 }
01340 
01341 void ar_i128tom128_(AR_IEEE_128 *out, long double *in)
01342 {
01343    (void) ar_i128tom128(out,in);
01344 }
01345 #endif
01346 
01347 #endif /* __mips */
01348 
01349 /* Cray single strange rounding for "rounded integer division", per
01350  * code sequences in the CMCS backend.
01351  */
01352 int
01353 ar_crnd64 (AR_CRAY_64 *rnd,
01354        const AR_CRAY_64 *flt) {
01355 
01356   int res;
01357   AR_CRAY_64 a = *flt;
01358 
01359   /* Construct a floating value with only the low-order four bits
01360    * left in the mantissa.
01361    */
01362   a = *flt;
01363   a.coeff0 = 0;
01364   a.coeff1 = 0;
01365   a.coeff2 &= 017;
01366 
01367   res = ar_cfadd64 (rnd, flt, &a);
01368 
01369   /* Trim off the low-order four bits */
01370   rnd->coeff2 &= ~017;
01371 
01372   return res;
01373 }
01374 
01375 int
01376 ar_crnd128 (AR_CRAY_128 *rnd,
01377       const AR_CRAY_128 *flt) {
01378 
01379   int res;
01380   AR_CRAY_128 a = *flt;
01381 
01382   /* Construct a floating value with only the low-order four bits
01383    * left in the mantissa.
01384    */
01385   a = *flt;
01386   a.coeff0 = 0;
01387   a.coeff1 = 0;
01388   a.coeff2 = 0;
01389   a.coeff3 = 0;
01390   a.coeff4 = 0;
01391   a.coeff5 &= 017;
01392 
01393   res = ar_cfadd128 (rnd, flt, &a);
01394 
01395   /* Trim off the low-order four bits */
01396   rnd->coeff5 &= ~017;
01397 
01398   return res;
01399 }
01400 
01401 
01402 static char USMID [] = "\n%Z%%M%  %I% %G% %U%\n";
01403 static char rcsid [] = "$Id: convert.c,v 1.1.1.1 2005/10/21 19:00:00 marcel Exp $";