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00007 #include "config.h"
00008 #include "system.h"
00009 #include "obstack.h"
00010 #include "rtl.h"
00011 #include "ggc.h"
00012
00013 extern struct obstack *rtl_obstack;
00014
00015 rtx
00016 gen_rtx_fmt_s (code, mode, arg0)
00017 RTX_CODE code;
00018 enum machine_mode mode;
00019 const char *arg0;
00020 {
00021 rtx rt;
00022 rt = ggc_alloc_rtx (1);
00023 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00024
00025 PUT_CODE (rt, code);
00026 PUT_MODE (rt, mode);
00027 XSTR (rt, 0) = arg0;
00028
00029 return rt;
00030 }
00031
00032 rtx
00033 gen_rtx_fmt_ee (code, mode, arg0, arg1)
00034 RTX_CODE code;
00035 enum machine_mode mode;
00036 rtx arg0;
00037 rtx arg1;
00038 {
00039 rtx rt;
00040 rt = ggc_alloc_rtx (2);
00041 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00042
00043 PUT_CODE (rt, code);
00044 PUT_MODE (rt, mode);
00045 XEXP (rt, 0) = arg0;
00046 XEXP (rt, 1) = arg1;
00047
00048 return rt;
00049 }
00050
00051 rtx
00052 gen_rtx_fmt_ue (code, mode, arg0, arg1)
00053 RTX_CODE code;
00054 enum machine_mode mode;
00055 rtx arg0;
00056 rtx arg1;
00057 {
00058 rtx rt;
00059 rt = ggc_alloc_rtx (2);
00060 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00061
00062 PUT_CODE (rt, code);
00063 PUT_MODE (rt, mode);
00064 XEXP (rt, 0) = arg0;
00065 XEXP (rt, 1) = arg1;
00066
00067 return rt;
00068 }
00069
00070 rtx
00071 gen_rtx_fmt_iss (code, mode, arg0, arg1, arg2)
00072 RTX_CODE code;
00073 enum machine_mode mode;
00074 int arg0;
00075 const char *arg1;
00076 const char *arg2;
00077 {
00078 rtx rt;
00079 rt = ggc_alloc_rtx (3);
00080 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00081
00082 PUT_CODE (rt, code);
00083 PUT_MODE (rt, mode);
00084 XINT (rt, 0) = arg0;
00085 XSTR (rt, 1) = arg1;
00086 XSTR (rt, 2) = arg2;
00087
00088 return rt;
00089 }
00090
00091 rtx
00092 gen_rtx_fmt_is (code, mode, arg0, arg1)
00093 RTX_CODE code;
00094 enum machine_mode mode;
00095 int arg0;
00096 const char *arg1;
00097 {
00098 rtx rt;
00099 rt = ggc_alloc_rtx (2);
00100 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00101
00102 PUT_CODE (rt, code);
00103 PUT_MODE (rt, mode);
00104 XINT (rt, 0) = arg0;
00105 XSTR (rt, 1) = arg1;
00106
00107 return rt;
00108 }
00109
00110 rtx
00111 gen_rtx_fmt_i (code, mode, arg0)
00112 RTX_CODE code;
00113 enum machine_mode mode;
00114 int arg0;
00115 {
00116 rtx rt;
00117 rt = ggc_alloc_rtx (1);
00118 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00119
00120 PUT_CODE (rt, code);
00121 PUT_MODE (rt, mode);
00122 XINT (rt, 0) = arg0;
00123
00124 return rt;
00125 }
00126
00127 rtx
00128 gen_rtx_fmt_isE (code, mode, arg0, arg1, arg2)
00129 RTX_CODE code;
00130 enum machine_mode mode;
00131 int arg0;
00132 const char *arg1;
00133 rtvec arg2;
00134 {
00135 rtx rt;
00136 rt = ggc_alloc_rtx (3);
00137 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00138
00139 PUT_CODE (rt, code);
00140 PUT_MODE (rt, mode);
00141 XINT (rt, 0) = arg0;
00142 XSTR (rt, 1) = arg1;
00143 XVEC (rt, 2) = arg2;
00144
00145 return rt;
00146 }
00147
00148 rtx
00149 gen_rtx_fmt_iE (code, mode, arg0, arg1)
00150 RTX_CODE code;
00151 enum machine_mode mode;
00152 int arg0;
00153 rtvec arg1;
00154 {
00155 rtx rt;
00156 rt = ggc_alloc_rtx (2);
00157 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00158
00159 PUT_CODE (rt, code);
00160 PUT_MODE (rt, mode);
00161 XINT (rt, 0) = arg0;
00162 XVEC (rt, 1) = arg1;
00163
00164 return rt;
00165 }
00166
00167 rtx
00168 gen_rtx_fmt_Ess (code, mode, arg0, arg1, arg2)
00169 RTX_CODE code;
00170 enum machine_mode mode;
00171 rtvec arg0;
00172 const char *arg1;
00173 const char *arg2;
00174 {
00175 rtx rt;
00176 rt = ggc_alloc_rtx (3);
00177 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00178
00179 PUT_CODE (rt, code);
00180 PUT_MODE (rt, mode);
00181 XVEC (rt, 0) = arg0;
00182 XSTR (rt, 1) = arg1;
00183 XSTR (rt, 2) = arg2;
00184
00185 return rt;
00186 }
00187
00188 rtx
00189 gen_rtx_fmt_sEss (code, mode, arg0, arg1, arg2, arg3)
00190 RTX_CODE code;
00191 enum machine_mode mode;
00192 const char *arg0;
00193 rtvec arg1;
00194 const char *arg2;
00195 const char *arg3;
00196 {
00197 rtx rt;
00198 rt = ggc_alloc_rtx (4);
00199 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00200
00201 PUT_CODE (rt, code);
00202 PUT_MODE (rt, mode);
00203 XSTR (rt, 0) = arg0;
00204 XVEC (rt, 1) = arg1;
00205 XSTR (rt, 2) = arg2;
00206 XSTR (rt, 3) = arg3;
00207
00208 return rt;
00209 }
00210
00211 rtx
00212 gen_rtx_fmt_eE (code, mode, arg0, arg1)
00213 RTX_CODE code;
00214 enum machine_mode mode;
00215 rtx arg0;
00216 rtvec arg1;
00217 {
00218 rtx rt;
00219 rt = ggc_alloc_rtx (2);
00220 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00221
00222 PUT_CODE (rt, code);
00223 PUT_MODE (rt, mode);
00224 XEXP (rt, 0) = arg0;
00225 XVEC (rt, 1) = arg1;
00226
00227 return rt;
00228 }
00229
00230 rtx
00231 gen_rtx_fmt_E (code, mode, arg0)
00232 RTX_CODE code;
00233 enum machine_mode mode;
00234 rtvec arg0;
00235 {
00236 rtx rt;
00237 rt = ggc_alloc_rtx (1);
00238 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00239
00240 PUT_CODE (rt, code);
00241 PUT_MODE (rt, mode);
00242 XVEC (rt, 0) = arg0;
00243
00244 return rt;
00245 }
00246
00247 rtx
00248 gen_rtx_fmt_e (code, mode, arg0)
00249 RTX_CODE code;
00250 enum machine_mode mode;
00251 rtx arg0;
00252 {
00253 rtx rt;
00254 rt = ggc_alloc_rtx (1);
00255 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00256
00257 PUT_CODE (rt, code);
00258 PUT_MODE (rt, mode);
00259 XEXP (rt, 0) = arg0;
00260
00261 return rt;
00262 }
00263
00264 rtx
00265 gen_rtx_fmt_ss (code, mode, arg0, arg1)
00266 RTX_CODE code;
00267 enum machine_mode mode;
00268 const char *arg0;
00269 const char *arg1;
00270 {
00271 rtx rt;
00272 rt = ggc_alloc_rtx (2);
00273 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00274
00275 PUT_CODE (rt, code);
00276 PUT_MODE (rt, mode);
00277 XSTR (rt, 0) = arg0;
00278 XSTR (rt, 1) = arg1;
00279
00280 return rt;
00281 }
00282
00283 rtx
00284 gen_rtx_fmt_sies (code, mode, arg0, arg1, arg2, arg3)
00285 RTX_CODE code;
00286 enum machine_mode mode;
00287 const char *arg0;
00288 int arg1;
00289 rtx arg2;
00290 const char *arg3;
00291 {
00292 rtx rt;
00293 rt = ggc_alloc_rtx (4);
00294 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00295
00296 PUT_CODE (rt, code);
00297 PUT_MODE (rt, mode);
00298 XSTR (rt, 0) = arg0;
00299 XINT (rt, 1) = arg1;
00300 XEXP (rt, 2) = arg2;
00301 XSTR (rt, 3) = arg3;
00302
00303 return rt;
00304 }
00305
00306 rtx
00307 gen_rtx_fmt_sse (code, mode, arg0, arg1, arg2)
00308 RTX_CODE code;
00309 enum machine_mode mode;
00310 const char *arg0;
00311 const char *arg1;
00312 rtx arg2;
00313 {
00314 rtx rt;
00315 rt = ggc_alloc_rtx (3);
00316 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00317
00318 PUT_CODE (rt, code);
00319 PUT_MODE (rt, mode);
00320 XSTR (rt, 0) = arg0;
00321 XSTR (rt, 1) = arg1;
00322 XEXP (rt, 2) = arg2;
00323
00324 return rt;
00325 }
00326
00327 rtx
00328 gen_rtx_fmt_sE (code, mode, arg0, arg1)
00329 RTX_CODE code;
00330 enum machine_mode mode;
00331 const char *arg0;
00332 rtvec arg1;
00333 {
00334 rtx rt;
00335 rt = ggc_alloc_rtx (2);
00336 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00337
00338 PUT_CODE (rt, code);
00339 PUT_MODE (rt, mode);
00340 XSTR (rt, 0) = arg0;
00341 XVEC (rt, 1) = arg1;
00342
00343 return rt;
00344 }
00345
00346 rtx
00347 gen_rtx_fmt_iuuBteiee (code, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
00348 RTX_CODE code;
00349 enum machine_mode mode;
00350 int arg0;
00351 rtx arg1;
00352 rtx arg2;
00353 struct basic_block_def *arg3;
00354 union tree_node *arg4;
00355 rtx arg5;
00356 int arg6;
00357 rtx arg7;
00358 rtx arg8;
00359 {
00360 rtx rt;
00361 rt = ggc_alloc_rtx (9);
00362 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00363
00364 PUT_CODE (rt, code);
00365 PUT_MODE (rt, mode);
00366 XINT (rt, 0) = arg0;
00367 XEXP (rt, 1) = arg1;
00368 XEXP (rt, 2) = arg2;
00369 XBBDEF (rt, 3) = arg3;
00370 XTREE (rt, 4) = arg4;
00371 XEXP (rt, 5) = arg5;
00372 XINT (rt, 6) = arg6;
00373 XEXP (rt, 7) = arg7;
00374 XEXP (rt, 8) = arg8;
00375
00376 return rt;
00377 }
00378
00379 rtx
00380 gen_rtx_fmt_iuuBteiee0 (code, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8)
00381 RTX_CODE code;
00382 enum machine_mode mode;
00383 int arg0;
00384 rtx arg1;
00385 rtx arg2;
00386 struct basic_block_def *arg3;
00387 union tree_node *arg4;
00388 rtx arg5;
00389 int arg6;
00390 rtx arg7;
00391 rtx arg8;
00392 {
00393 rtx rt;
00394 rt = ggc_alloc_rtx (10);
00395 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00396
00397 PUT_CODE (rt, code);
00398 PUT_MODE (rt, mode);
00399 XINT (rt, 0) = arg0;
00400 XEXP (rt, 1) = arg1;
00401 XEXP (rt, 2) = arg2;
00402 XBBDEF (rt, 3) = arg3;
00403 XTREE (rt, 4) = arg4;
00404 XEXP (rt, 5) = arg5;
00405 XINT (rt, 6) = arg6;
00406 XEXP (rt, 7) = arg7;
00407 XEXP (rt, 8) = arg8;
00408 X0EXP (rt, 9) = NULL_RTX;
00409
00410 return rt;
00411 }
00412
00413 rtx
00414 gen_rtx_fmt_iuuBteieee (code, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9)
00415 RTX_CODE code;
00416 enum machine_mode mode;
00417 int arg0;
00418 rtx arg1;
00419 rtx arg2;
00420 struct basic_block_def *arg3;
00421 union tree_node *arg4;
00422 rtx arg5;
00423 int arg6;
00424 rtx arg7;
00425 rtx arg8;
00426 rtx arg9;
00427 {
00428 rtx rt;
00429 rt = ggc_alloc_rtx (10);
00430 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00431
00432 PUT_CODE (rt, code);
00433 PUT_MODE (rt, mode);
00434 XINT (rt, 0) = arg0;
00435 XEXP (rt, 1) = arg1;
00436 XEXP (rt, 2) = arg2;
00437 XBBDEF (rt, 3) = arg3;
00438 XTREE (rt, 4) = arg4;
00439 XEXP (rt, 5) = arg5;
00440 XINT (rt, 6) = arg6;
00441 XEXP (rt, 7) = arg7;
00442 XEXP (rt, 8) = arg8;
00443 XEXP (rt, 9) = arg9;
00444
00445 return rt;
00446 }
00447
00448 rtx
00449 gen_rtx_fmt_iuu000000 (code, mode, arg0, arg1, arg2)
00450 RTX_CODE code;
00451 enum machine_mode mode;
00452 int arg0;
00453 rtx arg1;
00454 rtx arg2;
00455 {
00456 rtx rt;
00457 rt = ggc_alloc_rtx (9);
00458 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00459
00460 PUT_CODE (rt, code);
00461 PUT_MODE (rt, mode);
00462 XINT (rt, 0) = arg0;
00463 XEXP (rt, 1) = arg1;
00464 XEXP (rt, 2) = arg2;
00465 X0EXP (rt, 3) = NULL_RTX;
00466 X0EXP (rt, 4) = NULL_RTX;
00467 X0EXP (rt, 5) = NULL_RTX;
00468 X0EXP (rt, 6) = NULL_RTX;
00469 X0EXP (rt, 7) = NULL_RTX;
00470 X0EXP (rt, 8) = NULL_RTX;
00471
00472 return rt;
00473 }
00474
00475 rtx
00476 gen_rtx_fmt_iuuB00is (code, mode, arg0, arg1, arg2, arg3, arg4, arg5)
00477 RTX_CODE code;
00478 enum machine_mode mode;
00479 int arg0;
00480 rtx arg1;
00481 rtx arg2;
00482 struct basic_block_def *arg3;
00483 int arg4;
00484 const char *arg5;
00485 {
00486 rtx rt;
00487 rt = ggc_alloc_rtx (8);
00488 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00489
00490 PUT_CODE (rt, code);
00491 PUT_MODE (rt, mode);
00492 XINT (rt, 0) = arg0;
00493 XEXP (rt, 1) = arg1;
00494 XEXP (rt, 2) = arg2;
00495 XBBDEF (rt, 3) = arg3;
00496 X0EXP (rt, 4) = NULL_RTX;
00497 X0EXP (rt, 5) = NULL_RTX;
00498 XINT (rt, 6) = arg4;
00499 XSTR (rt, 7) = arg5;
00500
00501 return rt;
00502 }
00503
00504 rtx
00505 gen_rtx_fmt_ssiEEsi (code, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6)
00506 RTX_CODE code;
00507 enum machine_mode mode;
00508 const char *arg0;
00509 const char *arg1;
00510 int arg2;
00511 rtvec arg3;
00512 rtvec arg4;
00513 const char *arg5;
00514 int arg6;
00515 {
00516 rtx rt;
00517 rt = ggc_alloc_rtx (7);
00518 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00519
00520 PUT_CODE (rt, code);
00521 PUT_MODE (rt, mode);
00522 XSTR (rt, 0) = arg0;
00523 XSTR (rt, 1) = arg1;
00524 XINT (rt, 2) = arg2;
00525 XVEC (rt, 3) = arg3;
00526 XVEC (rt, 4) = arg4;
00527 XSTR (rt, 5) = arg5;
00528 XINT (rt, 6) = arg6;
00529
00530 return rt;
00531 }
00532
00533 rtx
00534 gen_rtx_fmt_Ei (code, mode, arg0, arg1)
00535 RTX_CODE code;
00536 enum machine_mode mode;
00537 rtvec arg0;
00538 int arg1;
00539 {
00540 rtx rt;
00541 rt = ggc_alloc_rtx (2);
00542 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00543
00544 PUT_CODE (rt, code);
00545 PUT_MODE (rt, mode);
00546 XVEC (rt, 0) = arg0;
00547 XINT (rt, 1) = arg1;
00548
00549 return rt;
00550 }
00551
00552 rtx
00553 gen_rtx_fmt_eEee0 (code, mode, arg0, arg1, arg2, arg3)
00554 RTX_CODE code;
00555 enum machine_mode mode;
00556 rtx arg0;
00557 rtvec arg1;
00558 rtx arg2;
00559 rtx arg3;
00560 {
00561 rtx rt;
00562 rt = ggc_alloc_rtx (5);
00563 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00564
00565 PUT_CODE (rt, code);
00566 PUT_MODE (rt, mode);
00567 XEXP (rt, 0) = arg0;
00568 XVEC (rt, 1) = arg1;
00569 XEXP (rt, 2) = arg2;
00570 XEXP (rt, 3) = arg3;
00571 X0EXP (rt, 4) = NULL_RTX;
00572
00573 return rt;
00574 }
00575
00576 rtx
00577 gen_rtx_fmt_eee (code, mode, arg0, arg1, arg2)
00578 RTX_CODE code;
00579 enum machine_mode mode;
00580 rtx arg0;
00581 rtx arg1;
00582 rtx arg2;
00583 {
00584 rtx rt;
00585 rt = ggc_alloc_rtx (3);
00586 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00587
00588 PUT_CODE (rt, code);
00589 PUT_MODE (rt, mode);
00590 XEXP (rt, 0) = arg0;
00591 XEXP (rt, 1) = arg1;
00592 XEXP (rt, 2) = arg2;
00593
00594 return rt;
00595 }
00596
00597 rtx
00598 gen_rtx_fmt_ (code, mode)
00599 RTX_CODE code;
00600 enum machine_mode mode;
00601 {
00602 rtx rt;
00603 rt = ggc_alloc_rtx (0);
00604 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00605
00606 PUT_CODE (rt, code);
00607 PUT_MODE (rt, mode);
00608
00609 return rt;
00610 }
00611
00612 rtx
00613 gen_rtx_fmt_w (code, mode, arg0)
00614 RTX_CODE code;
00615 enum machine_mode mode;
00616 HOST_WIDE_INT arg0;
00617 {
00618 rtx rt;
00619 rt = ggc_alloc_rtx (1);
00620 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00621
00622 PUT_CODE (rt, code);
00623 PUT_MODE (rt, mode);
00624 XWINT (rt, 0) = arg0;
00625
00626 return rt;
00627 }
00628
00629 rtx
00630 gen_rtx_fmt_www (code, mode, arg0, arg1, arg2)
00631 RTX_CODE code;
00632 enum machine_mode mode;
00633 HOST_WIDE_INT arg0;
00634 HOST_WIDE_INT arg1;
00635 HOST_WIDE_INT arg2;
00636 {
00637 rtx rt;
00638 rt = ggc_alloc_rtx (3);
00639 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00640
00641 PUT_CODE (rt, code);
00642 PUT_MODE (rt, mode);
00643 XWINT (rt, 0) = arg0;
00644 XWINT (rt, 1) = arg1;
00645 XWINT (rt, 2) = arg2;
00646
00647 return rt;
00648 }
00649
00650 rtx
00651 gen_rtx_fmt_0 (code, mode)
00652 RTX_CODE code;
00653 enum machine_mode mode;
00654 {
00655 rtx rt;
00656 rt = ggc_alloc_rtx (1);
00657 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00658
00659 PUT_CODE (rt, code);
00660 PUT_MODE (rt, mode);
00661 X0EXP (rt, 0) = NULL_RTX;
00662
00663 return rt;
00664 }
00665
00666 rtx
00667 gen_rtx_fmt_i0 (code, mode, arg0)
00668 RTX_CODE code;
00669 enum machine_mode mode;
00670 int arg0;
00671 {
00672 rtx rt;
00673 rt = ggc_alloc_rtx (2);
00674 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00675
00676 PUT_CODE (rt, code);
00677 PUT_MODE (rt, mode);
00678 XINT (rt, 0) = arg0;
00679 X0EXP (rt, 1) = NULL_RTX;
00680
00681 return rt;
00682 }
00683
00684 rtx
00685 gen_rtx_fmt_ei (code, mode, arg0, arg1)
00686 RTX_CODE code;
00687 enum machine_mode mode;
00688 rtx arg0;
00689 int arg1;
00690 {
00691 rtx rt;
00692 rt = ggc_alloc_rtx (2);
00693 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00694
00695 PUT_CODE (rt, code);
00696 PUT_MODE (rt, mode);
00697 XEXP (rt, 0) = arg0;
00698 XINT (rt, 1) = arg1;
00699
00700 return rt;
00701 }
00702
00703 rtx
00704 gen_rtx_fmt_e0 (code, mode, arg0)
00705 RTX_CODE code;
00706 enum machine_mode mode;
00707 rtx arg0;
00708 {
00709 rtx rt;
00710 rt = ggc_alloc_rtx (2);
00711 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00712
00713 PUT_CODE (rt, code);
00714 PUT_MODE (rt, mode);
00715 XEXP (rt, 0) = arg0;
00716 X0EXP (rt, 1) = NULL_RTX;
00717
00718 return rt;
00719 }
00720
00721 rtx
00722 gen_rtx_fmt_u00 (code, mode, arg0)
00723 RTX_CODE code;
00724 enum machine_mode mode;
00725 rtx arg0;
00726 {
00727 rtx rt;
00728 rt = ggc_alloc_rtx (3);
00729 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00730
00731 PUT_CODE (rt, code);
00732 PUT_MODE (rt, mode);
00733 XEXP (rt, 0) = arg0;
00734 X0EXP (rt, 1) = NULL_RTX;
00735 X0EXP (rt, 2) = NULL_RTX;
00736
00737 return rt;
00738 }
00739
00740 rtx
00741 gen_rtx_fmt_eit (code, mode, arg0, arg1, arg2)
00742 RTX_CODE code;
00743 enum machine_mode mode;
00744 rtx arg0;
00745 int arg1;
00746 union tree_node *arg2;
00747 {
00748 rtx rt;
00749 rt = ggc_alloc_rtx (3);
00750 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00751
00752 PUT_CODE (rt, code);
00753 PUT_MODE (rt, mode);
00754 XEXP (rt, 0) = arg0;
00755 XINT (rt, 1) = arg1;
00756 XTREE (rt, 2) = arg2;
00757
00758 return rt;
00759 }
00760
00761 rtx
00762 gen_rtx_fmt_eeeee (code, mode, arg0, arg1, arg2, arg3, arg4)
00763 RTX_CODE code;
00764 enum machine_mode mode;
00765 rtx arg0;
00766 rtx arg1;
00767 rtx arg2;
00768 rtx arg3;
00769 rtx arg4;
00770 {
00771 rtx rt;
00772 rt = ggc_alloc_rtx (5);
00773 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00774
00775 PUT_CODE (rt, code);
00776 PUT_MODE (rt, mode);
00777 XEXP (rt, 0) = arg0;
00778 XEXP (rt, 1) = arg1;
00779 XEXP (rt, 2) = arg2;
00780 XEXP (rt, 3) = arg3;
00781 XEXP (rt, 4) = arg4;
00782
00783 return rt;
00784 }
00785
00786 rtx
00787 gen_rtx_fmt_Ee (code, mode, arg0, arg1)
00788 RTX_CODE code;
00789 enum machine_mode mode;
00790 rtvec arg0;
00791 rtx arg1;
00792 {
00793 rtx rt;
00794 rt = ggc_alloc_rtx (2);
00795 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00796
00797 PUT_CODE (rt, code);
00798 PUT_MODE (rt, mode);
00799 XVEC (rt, 0) = arg0;
00800 XEXP (rt, 1) = arg1;
00801
00802 return rt;
00803 }
00804
00805 rtx
00806 gen_rtx_fmt_uuEiiiiiibbii (code, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12)
00807 RTX_CODE code;
00808 enum machine_mode mode;
00809 rtx arg0;
00810 rtx arg1;
00811 rtvec arg2;
00812 int arg3;
00813 int arg4;
00814 int arg5;
00815 int arg6;
00816 int arg7;
00817 int arg8;
00818 struct bitmap_head_def *arg9;
00819 struct bitmap_head_def *arg10;
00820 int arg11;
00821 int arg12;
00822 {
00823 rtx rt;
00824 rt = ggc_alloc_rtx (13);
00825 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00826
00827 PUT_CODE (rt, code);
00828 PUT_MODE (rt, mode);
00829 XEXP (rt, 0) = arg0;
00830 XEXP (rt, 1) = arg1;
00831 XVEC (rt, 2) = arg2;
00832 XINT (rt, 3) = arg3;
00833 XINT (rt, 4) = arg4;
00834 XINT (rt, 5) = arg5;
00835 XINT (rt, 6) = arg6;
00836 XINT (rt, 7) = arg7;
00837 XINT (rt, 8) = arg8;
00838 XBITMAP (rt, 9) = arg9;
00839 XBITMAP (rt, 10) = arg10;
00840 XINT (rt, 11) = arg11;
00841 XINT (rt, 12) = arg12;
00842
00843 return rt;
00844 }
00845
00846 rtx
00847 gen_rtx_fmt_iiiiiiiitt (code, mode, arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8, arg9)
00848 RTX_CODE code;
00849 enum machine_mode mode;
00850 int arg0;
00851 int arg1;
00852 int arg2;
00853 int arg3;
00854 int arg4;
00855 int arg5;
00856 int arg6;
00857 int arg7;
00858 union tree_node *arg8;
00859 union tree_node *arg9;
00860 {
00861 rtx rt;
00862 rt = ggc_alloc_rtx (10);
00863 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00864
00865 PUT_CODE (rt, code);
00866 PUT_MODE (rt, mode);
00867 XINT (rt, 0) = arg0;
00868 XINT (rt, 1) = arg1;
00869 XINT (rt, 2) = arg2;
00870 XINT (rt, 3) = arg3;
00871 XINT (rt, 4) = arg4;
00872 XINT (rt, 5) = arg5;
00873 XINT (rt, 6) = arg6;
00874 XINT (rt, 7) = arg7;
00875 XTREE (rt, 8) = arg8;
00876 XTREE (rt, 9) = arg9;
00877
00878 return rt;
00879 }
00880
00881 rtx
00882 gen_rtx_fmt_eti (code, mode, arg0, arg1, arg2)
00883 RTX_CODE code;
00884 enum machine_mode mode;
00885 rtx arg0;
00886 union tree_node *arg1;
00887 int arg2;
00888 {
00889 rtx rt;
00890 rt = ggc_alloc_rtx (3);
00891 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00892
00893 PUT_CODE (rt, code);
00894 PUT_MODE (rt, mode);
00895 XEXP (rt, 0) = arg0;
00896 XTREE (rt, 1) = arg1;
00897 XINT (rt, 2) = arg2;
00898
00899 return rt;
00900 }
00901
00902 rtx
00903 gen_rtx_fmt_bi (code, mode, arg0, arg1)
00904 RTX_CODE code;
00905 enum machine_mode mode;
00906 struct bitmap_head_def *arg0;
00907 int arg1;
00908 {
00909 rtx rt;
00910 rt = ggc_alloc_rtx (2);
00911 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00912
00913 PUT_CODE (rt, code);
00914 PUT_MODE (rt, mode);
00915 XBITMAP (rt, 0) = arg0;
00916 XINT (rt, 1) = arg1;
00917
00918 return rt;
00919 }
00920
00921 rtx
00922 gen_rtx_fmt_uuuu (code, mode, arg0, arg1, arg2, arg3)
00923 RTX_CODE code;
00924 enum machine_mode mode;
00925 rtx arg0;
00926 rtx arg1;
00927 rtx arg2;
00928 rtx arg3;
00929 {
00930 rtx rt;
00931 rt = ggc_alloc_rtx (4);
00932 memset (rt, 0, sizeof (struct rtx_def) - sizeof (rtunion));
00933
00934 PUT_CODE (rt, code);
00935 PUT_MODE (rt, mode);
00936 XEXP (rt, 0) = arg0;
00937 XEXP (rt, 1) = arg1;
00938 XEXP (rt, 2) = arg2;
00939 XEXP (rt, 3) = arg3;
00940
00941 return rt;
00942 }
00943
