osprey-gcc/gcc/config/i386/i386.c

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/*
 * Copyright (C) 2006. QLogic Corporation. All Rights Reserved.
 */

/* Subroutines used for code generation on IA-32.
   Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
   2002, 2003, 2004, 2005 Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

#include "config.h"
#include "system.h"
#include "coretypes.h"
#include "tm.h"
#include "rtl.h"
#include "tree.h"
#include "tm_p.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "real.h"
#include "insn-config.h"
#include "conditions.h"
#include "output.h"
#include "insn-codes.h"
#include "insn-attr.h"
#include "flags.h"
#include "except.h"
#include "function.h"
#include "recog.h"
#include "expr.h"
#include "optabs.h"
#include "toplev.h"
#include "basic-block.h"
#include "ggc.h"
#include "target.h"
#include "target-def.h"
#include "langhooks.h"
#include "cgraph.h"
#include "tree-gimple.h"

#ifndef CHECK_STACK_LIMIT
#define CHECK_STACK_LIMIT (-1)
#endif

/* Return index of given mode in mult and division cost tables.  */
#define MODE_INDEX(mode)          \
  ((mode) == QImode ? 0           \
   : (mode) == HImode ? 1         \
   : (mode) == SImode ? 2         \
   : (mode) == DImode ? 3         \
   : 4)

/* Processor costs (relative to an add) */
static const
struct processor_costs size_cost = {  /* costs for tunning for size */
  2,          /* cost of an add instruction */
  3,          /* cost of a lea instruction */
  2,          /* variable shift costs */
  3,          /* constant shift costs */
  {3, 3, 3, 3, 5},      /* cost of starting a multiply */
  0,          /* cost of multiply per each bit set */
  {3, 3, 3, 3, 5},      /* cost of a divide/mod */
  3,          /* cost of movsx */
  3,          /* cost of movzx */
  0,          /* "large" insn */
  2,          /* MOVE_RATIO */
  2,          /* cost for loading QImode using movzbl */
  {2, 2, 2},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {2, 2, 2},        /* cost of storing integer registers */
  2,          /* cost of reg,reg fld/fst */
  {2, 2, 2},        /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {2, 2, 2},        /* cost of loading integer registers */
  3,          /* cost of moving MMX register */
  {3, 3},       /* cost of loading MMX registers
             in SImode and DImode */
  {3, 3},       /* cost of storing MMX registers
             in SImode and DImode */
  3,          /* cost of moving SSE register */
  {3, 3, 3},        /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {3, 3, 3},        /* cost of storing SSE registers
             in SImode, DImode and TImode */
  3,          /* MMX or SSE register to integer */
  0,          /* size of prefetch block */
  0,          /* number of parallel prefetches */
  1,          /* Branch cost */
  2,          /* cost of FADD and FSUB insns.  */
  2,          /* cost of FMUL instruction.  */
  2,          /* cost of FDIV instruction.  */
  2,          /* cost of FABS instruction.  */
  2,          /* cost of FCHS instruction.  */
  2,          /* cost of FSQRT instruction.  */
};

/* Processor costs (relative to an add) */
static const
struct processor_costs i386_cost = {  /* 386 specific costs */
  1,          /* cost of an add instruction */
  1,          /* cost of a lea instruction */
  3,          /* variable shift costs */
  2,          /* constant shift costs */
  {6, 6, 6, 6, 6},      /* cost of starting a multiply */
  1,          /* cost of multiply per each bit set */
  {23, 23, 23, 23, 23},     /* cost of a divide/mod */
  3,          /* cost of movsx */
  2,          /* cost of movzx */
  15,         /* "large" insn */
  3,          /* MOVE_RATIO */
  4,          /* cost for loading QImode using movzbl */
  {2, 4, 2},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {2, 4, 2},        /* cost of storing integer registers */
  2,          /* cost of reg,reg fld/fst */
  {8, 8, 8},        /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {8, 8, 8},        /* cost of loading integer registers */
  2,          /* cost of moving MMX register */
  {4, 8},       /* cost of loading MMX registers
             in SImode and DImode */
  {4, 8},       /* cost of storing MMX registers
             in SImode and DImode */
  2,          /* cost of moving SSE register */
  {4, 8, 16},       /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {4, 8, 16},       /* cost of storing SSE registers
             in SImode, DImode and TImode */
  3,          /* MMX or SSE register to integer */
  0,          /* size of prefetch block */
  0,          /* number of parallel prefetches */
  1,          /* Branch cost */
  23,         /* cost of FADD and FSUB insns.  */
  27,         /* cost of FMUL instruction.  */
  88,         /* cost of FDIV instruction.  */
  22,         /* cost of FABS instruction.  */
  24,         /* cost of FCHS instruction.  */
  122,          /* cost of FSQRT instruction.  */
};

static const
struct processor_costs i486_cost = {  /* 486 specific costs */
  1,          /* cost of an add instruction */
  1,          /* cost of a lea instruction */
  3,          /* variable shift costs */
  2,          /* constant shift costs */
  {12, 12, 12, 12, 12},     /* cost of starting a multiply */
  1,          /* cost of multiply per each bit set */
  {40, 40, 40, 40, 40},     /* cost of a divide/mod */
  3,          /* cost of movsx */
  2,          /* cost of movzx */
  15,         /* "large" insn */
  3,          /* MOVE_RATIO */
  4,          /* cost for loading QImode using movzbl */
  {2, 4, 2},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {2, 4, 2},        /* cost of storing integer registers */
  2,          /* cost of reg,reg fld/fst */
  {8, 8, 8},        /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {8, 8, 8},        /* cost of loading integer registers */
  2,          /* cost of moving MMX register */
  {4, 8},       /* cost of loading MMX registers
             in SImode and DImode */
  {4, 8},       /* cost of storing MMX registers
             in SImode and DImode */
  2,          /* cost of moving SSE register */
  {4, 8, 16},       /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {4, 8, 16},       /* cost of storing SSE registers
             in SImode, DImode and TImode */
  3,          /* MMX or SSE register to integer */
  0,          /* size of prefetch block */
  0,          /* number of parallel prefetches */
  1,          /* Branch cost */
  8,          /* cost of FADD and FSUB insns.  */
  16,         /* cost of FMUL instruction.  */
  73,         /* cost of FDIV instruction.  */
  3,          /* cost of FABS instruction.  */
  3,          /* cost of FCHS instruction.  */
  83,         /* cost of FSQRT instruction.  */
};

static const
struct processor_costs pentium_cost = {
  1,          /* cost of an add instruction */
  1,          /* cost of a lea instruction */
  4,          /* variable shift costs */
  1,          /* constant shift costs */
  {11, 11, 11, 11, 11},     /* cost of starting a multiply */
  0,          /* cost of multiply per each bit set */
  {25, 25, 25, 25, 25},     /* cost of a divide/mod */
  3,          /* cost of movsx */
  2,          /* cost of movzx */
  8,          /* "large" insn */
  6,          /* MOVE_RATIO */
  6,          /* cost for loading QImode using movzbl */
  {2, 4, 2},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {2, 4, 2},        /* cost of storing integer registers */
  2,          /* cost of reg,reg fld/fst */
  {2, 2, 6},        /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {4, 4, 6},        /* cost of loading integer registers */
  8,          /* cost of moving MMX register */
  {8, 8},       /* cost of loading MMX registers
             in SImode and DImode */
  {8, 8},       /* cost of storing MMX registers
             in SImode and DImode */
  2,          /* cost of moving SSE register */
  {4, 8, 16},       /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {4, 8, 16},       /* cost of storing SSE registers
             in SImode, DImode and TImode */
  3,          /* MMX or SSE register to integer */
  0,          /* size of prefetch block */
  0,          /* number of parallel prefetches */
  2,          /* Branch cost */
  3,          /* cost of FADD and FSUB insns.  */
  3,          /* cost of FMUL instruction.  */
  39,         /* cost of FDIV instruction.  */
  1,          /* cost of FABS instruction.  */
  1,          /* cost of FCHS instruction.  */
  70,         /* cost of FSQRT instruction.  */
};

static const
struct processor_costs pentiumpro_cost = {
  1,          /* cost of an add instruction */
  1,          /* cost of a lea instruction */
  1,          /* variable shift costs */
  1,          /* constant shift costs */
  {4, 4, 4, 4, 4},      /* cost of starting a multiply */
  0,          /* cost of multiply per each bit set */
  {17, 17, 17, 17, 17},     /* cost of a divide/mod */
  1,          /* cost of movsx */
  1,          /* cost of movzx */
  8,          /* "large" insn */
  6,          /* MOVE_RATIO */
  2,          /* cost for loading QImode using movzbl */
  {4, 4, 4},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {2, 2, 2},        /* cost of storing integer registers */
  2,          /* cost of reg,reg fld/fst */
  {2, 2, 6},        /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {4, 4, 6},        /* cost of loading integer registers */
  2,          /* cost of moving MMX register */
  {2, 2},       /* cost of loading MMX registers
             in SImode and DImode */
  {2, 2},       /* cost of storing MMX registers
             in SImode and DImode */
  2,          /* cost of moving SSE register */
  {2, 2, 8},        /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {2, 2, 8},        /* cost of storing SSE registers
             in SImode, DImode and TImode */
  3,          /* MMX or SSE register to integer */
  32,         /* size of prefetch block */
  6,          /* number of parallel prefetches */
  2,          /* Branch cost */
  3,          /* cost of FADD and FSUB insns.  */
  5,          /* cost of FMUL instruction.  */
  56,         /* cost of FDIV instruction.  */
  2,          /* cost of FABS instruction.  */
  2,          /* cost of FCHS instruction.  */
  56,         /* cost of FSQRT instruction.  */
};

static const
struct processor_costs k6_cost = {
  1,          /* cost of an add instruction */
  2,          /* cost of a lea instruction */
  1,          /* variable shift costs */
  1,          /* constant shift costs */
  {3, 3, 3, 3, 3},      /* cost of starting a multiply */
  0,          /* cost of multiply per each bit set */
  {18, 18, 18, 18, 18},     /* cost of a divide/mod */
  2,          /* cost of movsx */
  2,          /* cost of movzx */
  8,          /* "large" insn */
  4,          /* MOVE_RATIO */
  3,          /* cost for loading QImode using movzbl */
  {4, 5, 4},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {2, 3, 2},        /* cost of storing integer registers */
  4,          /* cost of reg,reg fld/fst */
  {6, 6, 6},        /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {4, 4, 4},        /* cost of loading integer registers */
  2,          /* cost of moving MMX register */
  {2, 2},       /* cost of loading MMX registers
             in SImode and DImode */
  {2, 2},       /* cost of storing MMX registers
             in SImode and DImode */
  2,          /* cost of moving SSE register */
  {2, 2, 8},        /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {2, 2, 8},        /* cost of storing SSE registers
             in SImode, DImode and TImode */
  6,          /* MMX or SSE register to integer */
  32,         /* size of prefetch block */
  1,          /* number of parallel prefetches */
  1,          /* Branch cost */
  2,          /* cost of FADD and FSUB insns.  */
  2,          /* cost of FMUL instruction.  */
  56,         /* cost of FDIV instruction.  */
  2,          /* cost of FABS instruction.  */
  2,          /* cost of FCHS instruction.  */
  56,         /* cost of FSQRT instruction.  */
};

static const
struct processor_costs athlon_cost = {
  1,          /* cost of an add instruction */
  2,          /* cost of a lea instruction */
  1,          /* variable shift costs */
  1,          /* constant shift costs */
  {5, 5, 5, 5, 5},      /* cost of starting a multiply */
  0,          /* cost of multiply per each bit set */
  {18, 26, 42, 74, 74},     /* cost of a divide/mod */
  1,          /* cost of movsx */
  1,          /* cost of movzx */
  8,          /* "large" insn */
  9,          /* MOVE_RATIO */
  4,          /* cost for loading QImode using movzbl */
  {3, 4, 3},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {3, 4, 3},        /* cost of storing integer registers */
  4,          /* cost of reg,reg fld/fst */
  {4, 4, 12},       /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {6, 6, 8},        /* cost of loading integer registers */
  2,          /* cost of moving MMX register */
  {4, 4},       /* cost of loading MMX registers
             in SImode and DImode */
  {4, 4},       /* cost of storing MMX registers
             in SImode and DImode */
  2,          /* cost of moving SSE register */
  {4, 4, 6},        /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {4, 4, 5},        /* cost of storing SSE registers
             in SImode, DImode and TImode */
  5,          /* MMX or SSE register to integer */
  64,         /* size of prefetch block */
  6,          /* number of parallel prefetches */
  5,          /* Branch cost */
  4,          /* cost of FADD and FSUB insns.  */
  4,          /* cost of FMUL instruction.  */
  24,         /* cost of FDIV instruction.  */
  2,          /* cost of FABS instruction.  */
  2,          /* cost of FCHS instruction.  */
  35,         /* cost of FSQRT instruction.  */
};

static const
struct processor_costs k8_cost = {
  1,          /* cost of an add instruction */
  2,          /* cost of a lea instruction */
  1,          /* variable shift costs */
  1,          /* constant shift costs */
  {3, 4, 3, 4, 5},      /* cost of starting a multiply */
  0,          /* cost of multiply per each bit set */
  {18, 26, 42, 74, 74},     /* cost of a divide/mod */
  1,          /* cost of movsx */
  1,          /* cost of movzx */
  8,          /* "large" insn */
  9,          /* MOVE_RATIO */
  4,          /* cost for loading QImode using movzbl */
  {3, 4, 3},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {3, 4, 3},        /* cost of storing integer registers */
  4,          /* cost of reg,reg fld/fst */
  {4, 4, 12},       /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {6, 6, 8},        /* cost of loading integer registers */
  2,          /* cost of moving MMX register */
  {3, 3},       /* cost of loading MMX registers
             in SImode and DImode */
  {4, 4},       /* cost of storing MMX registers
             in SImode and DImode */
  2,          /* cost of moving SSE register */
  {4, 3, 6},        /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {4, 4, 5},        /* cost of storing SSE registers
             in SImode, DImode and TImode */
  5,          /* MMX or SSE register to integer */
  64,         /* size of prefetch block */
  6,          /* number of parallel prefetches */
  5,          /* Branch cost */
  4,          /* cost of FADD and FSUB insns.  */
  4,          /* cost of FMUL instruction.  */
  19,         /* cost of FDIV instruction.  */
  2,          /* cost of FABS instruction.  */
  2,          /* cost of FCHS instruction.  */
  35,         /* cost of FSQRT instruction.  */
};

static const
struct processor_costs pentium4_cost = {
  1,          /* cost of an add instruction */
  3,          /* cost of a lea instruction */
  4,          /* variable shift costs */
  4,          /* constant shift costs */
  {15, 15, 15, 15, 15},     /* cost of starting a multiply */
  0,          /* cost of multiply per each bit set */
  {56, 56, 56, 56, 56},     /* cost of a divide/mod */
  1,          /* cost of movsx */
  1,          /* cost of movzx */
  16,         /* "large" insn */
  6,          /* MOVE_RATIO */
  2,          /* cost for loading QImode using movzbl */
  {4, 5, 4},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {2, 3, 2},        /* cost of storing integer registers */
  2,          /* cost of reg,reg fld/fst */
  {2, 2, 6},        /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {4, 4, 6},        /* cost of loading integer registers */
  2,          /* cost of moving MMX register */
  {2, 2},       /* cost of loading MMX registers
             in SImode and DImode */
  {2, 2},       /* cost of storing MMX registers
             in SImode and DImode */
  12,         /* cost of moving SSE register */
  {12, 12, 12},       /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {2, 2, 8},        /* cost of storing SSE registers
             in SImode, DImode and TImode */
  10,         /* MMX or SSE register to integer */
  64,         /* size of prefetch block */
  6,          /* number of parallel prefetches */
  2,          /* Branch cost */
  5,          /* cost of FADD and FSUB insns.  */
  7,          /* cost of FMUL instruction.  */
  43,         /* cost of FDIV instruction.  */
  2,          /* cost of FABS instruction.  */
  2,          /* cost of FCHS instruction.  */
  43,         /* cost of FSQRT instruction.  */
};

static const
struct processor_costs nocona_cost = {
  1,          /* cost of an add instruction */
  1,          /* cost of a lea instruction */
  1,          /* variable shift costs */
  1,          /* constant shift costs */
  {10, 10, 10, 10, 10},     /* cost of starting a multiply */
  0,          /* cost of multiply per each bit set */
  {66, 66, 66, 66, 66},     /* cost of a divide/mod */
  1,          /* cost of movsx */
  1,          /* cost of movzx */
  16,         /* "large" insn */
  9,          /* MOVE_RATIO */
  4,          /* cost for loading QImode using movzbl */
  {4, 4, 4},        /* cost of loading integer registers
             in QImode, HImode and SImode.
             Relative to reg-reg move (2).  */
  {4, 4, 4},        /* cost of storing integer registers */
  3,          /* cost of reg,reg fld/fst */
  {12, 12, 12},       /* cost of loading fp registers
             in SFmode, DFmode and XFmode */
  {4, 4, 4},        /* cost of loading integer registers */
  6,          /* cost of moving MMX register */
  {12, 12},       /* cost of loading MMX registers
             in SImode and DImode */
  {12, 12},       /* cost of storing MMX registers
             in SImode and DImode */
  6,          /* cost of moving SSE register */
  {12, 12, 12},       /* cost of loading SSE registers
             in SImode, DImode and TImode */
  {12, 12, 12},       /* cost of storing SSE registers
             in SImode, DImode and TImode */
  8,          /* MMX or SSE register to integer */
  128,          /* size of prefetch block */
  8,          /* number of parallel prefetches */
  1,          /* Branch cost */
  6,          /* cost of FADD and FSUB insns.  */
  8,          /* cost of FMUL instruction.  */
  40,         /* cost of FDIV instruction.  */
  3,          /* cost of FABS instruction.  */
  3,          /* cost of FCHS instruction.  */
  44,         /* cost of FSQRT instruction.  */
};

const struct processor_costs *ix86_cost = &pentium_cost;

/* Processor feature/optimization bitmasks.  */
#define m_386 (1<<PROCESSOR_I386)
#define m_486 (1<<PROCESSOR_I486)
#define m_PENT (1<<PROCESSOR_PENTIUM)
#define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
#define m_K6  (1<<PROCESSOR_K6)
#define m_ATHLON  (1<<PROCESSOR_ATHLON)
#define m_PENT4  (1<<PROCESSOR_PENTIUM4)
#define m_K8  (1<<PROCESSOR_K8)
#define m_ATHLON_K8  (m_K8 | m_ATHLON)
#define m_NOCONA  (1<<PROCESSOR_NOCONA)

const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8;
const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_zero_extend_with_and = m_486 | m_PENT;
const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA /* m_386 | m_K6 */;
const int x86_double_with_add = ~m_386;
const int x86_use_bit_test = m_386;
const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6;
const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_3dnow_a = m_ATHLON_K8;
const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
/* Branch hints were put in P4 based on simulation result. But
   after P4 was made, no performance benefit was observed with
   branch hints. It also increases the code size. As the result,
   icc never generates branch hints.  */
const int x86_branch_hints = 0;
const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA;
const int x86_partial_reg_stall = m_PPRO;
const int x86_use_loop = m_K6;
const int x86_use_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT);
const int x86_use_mov0 = m_K6;
const int x86_use_cltd = ~(m_PENT | m_K6);
const int x86_read_modify_write = ~m_PENT;
const int x86_read_modify = ~(m_PENT | m_PPRO);
const int x86_split_long_moves = m_PPRO;
const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8;
const int x86_fast_prefix = ~(m_PENT | m_486 | m_386);
const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA;
const int x86_qimode_math = ~(0);
const int x86_promote_qi_regs = 0;
const int x86_himode_math = ~(m_PPRO);
const int x86_promote_hi_regs = m_PPRO;
const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA;
const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA;
const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA;
const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA;
const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO);
const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO;
const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO;
const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO;
const int x86_decompose_lea = m_PENT4 | m_NOCONA;
const int x86_shift1 = ~m_486;
const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO;
/* Set for machines where the type and dependencies are resolved on SSE
   register parts instead of whole registers, so we may maintain just
   lower part of scalar values in proper format leaving the upper part
   undefined.  */
const int x86_sse_split_regs = m_ATHLON_K8;
const int x86_sse_typeless_stores = m_ATHLON_K8;
const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
const int x86_use_ffreep = m_ATHLON_K8;
const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;

/* ??? Allowing interunit moves makes it all too easy for the compiler to put
   integer data in xmm registers.  Which results in pretty abysmal code.  */
const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */;

const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO;
/* Some CPU cores are not able to predict more than 4 branch instructions in
   the 16 byte window.  */
const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT;
const int x86_use_bt = m_ATHLON_K8;

/* In case the average insn count for single function invocation is
   lower than this constant, emit fast (but longer) prologue and
   epilogue code.  */
#define FAST_PROLOGUE_INSN_COUNT 20

/* Names for 8 (low), 8 (high), and 16-bit registers, respectively.  */
static const char *const qi_reg_name[] = QI_REGISTER_NAMES;
static const char *const qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES;
static const char *const hi_reg_name[] = HI_REGISTER_NAMES;

/* Array of the smallest class containing reg number REGNO, indexed by
   REGNO.  Used by REGNO_REG_CLASS in i386.h.  */

enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
{
  /* ax, dx, cx, bx */
  AREG, DREG, CREG, BREG,
  /* si, di, bp, sp */
  SIREG, DIREG, NON_Q_REGS, NON_Q_REGS,
  /* FP registers */
  FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS,
  FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
  /* arg pointer */
  NON_Q_REGS,
  /* flags, fpsr, dirflag, frame */
  NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
  SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
  SSE_REGS, SSE_REGS,
  MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
  MMX_REGS, MMX_REGS,
  NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
  NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
  SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
  SSE_REGS, SSE_REGS,
};

/* The "default" register map used in 32bit mode.  */

int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
{
  0, 2, 1, 3, 6, 7, 4, 5,   /* general regs */
  12, 13, 14, 15, 16, 17, 18, 19, /* fp regs */
  -1, -1, -1, -1, -1,     /* arg, flags, fpsr, dir, frame */
  21, 22, 23, 24, 25, 26, 27, 28, /* SSE */
  29, 30, 31, 32, 33, 34, 35, 36,       /* MMX */
  -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
  -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
};

static int const x86_64_int_parameter_registers[6] =
{
  5 /*RDI*/, 4 /*RSI*/, 1 /*RDX*/, 2 /*RCX*/,
  FIRST_REX_INT_REG /*R8 */, FIRST_REX_INT_REG + 1 /*R9 */
};

static int const x86_64_int_return_registers[4] =
{
  0 /*RAX*/, 1 /*RDI*/, 5 /*RDI*/, 4 /*RSI*/
};

/* The "default" register map used in 64bit mode.  */
int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
{
  0, 1, 2, 3, 4, 5, 6, 7,   /* general regs */
  33, 34, 35, 36, 37, 38, 39, 40, /* fp regs */
  -1, -1, -1, -1, -1,     /* arg, flags, fpsr, dir, frame */
  17, 18, 19, 20, 21, 22, 23, 24, /* SSE */
  41, 42, 43, 44, 45, 46, 47, 48,       /* MMX */
  8,9,10,11,12,13,14,15,    /* extended integer registers */
  25, 26, 27, 28, 29, 30, 31, 32, /* extended SSE registers */
};

/* Define the register numbers to be used in Dwarf debugging information.
   The SVR4 reference port C compiler uses the following register numbers
   in its Dwarf output code:
  0 for %eax (gcc regno = 0)
  1 for %ecx (gcc regno = 2)
  2 for %edx (gcc regno = 1)
  3 for %ebx (gcc regno = 3)
  4 for %esp (gcc regno = 7)
  5 for %ebp (gcc regno = 6)
  6 for %esi (gcc regno = 4)
  7 for %edi (gcc regno = 5)
   The following three DWARF register numbers are never generated by
   the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
   believes these numbers have these meanings.
  8  for %eip    (no gcc equivalent)
  9  for %eflags (gcc regno = 17)
  10 for %trapno (no gcc equivalent)
   It is not at all clear how we should number the FP stack registers
   for the x86 architecture.  If the version of SDB on x86/svr4 were
   a bit less brain dead with respect to floating-point then we would
   have a precedent to follow with respect to DWARF register numbers
   for x86 FP registers, but the SDB on x86/svr4 is so completely
   broken with respect to FP registers that it is hardly worth thinking
   of it as something to strive for compatibility with.
   The version of x86/svr4 SDB I have at the moment does (partially)
   seem to believe that DWARF register number 11 is associated with
   the x86 register %st(0), but that's about all.  Higher DWARF
   register numbers don't seem to be associated with anything in
   particular, and even for DWARF regno 11, SDB only seems to under-
   stand that it should say that a variable lives in %st(0) (when
   asked via an `=' command) if we said it was in DWARF regno 11,
   but SDB still prints garbage when asked for the value of the
   variable in question (via a `/' command).
   (Also note that the labels SDB prints for various FP stack regs
   when doing an `x' command are all wrong.)
   Note that these problems generally don't affect the native SVR4
   C compiler because it doesn't allow the use of -O with -g and
   because when it is *not* optimizing, it allocates a memory
   location for each floating-point variable, and the memory
   location is what gets described in the DWARF AT_location
   attribute for the variable in question.
   Regardless of the severe mental illness of the x86/svr4 SDB, we
   do something sensible here and we use the following DWARF
   register numbers.  Note that these are all stack-top-relative
   numbers.
  11 for %st(0) (gcc regno = 8)
  12 for %st(1) (gcc regno = 9)
  13 for %st(2) (gcc regno = 10)
  14 for %st(3) (gcc regno = 11)
  15 for %st(4) (gcc regno = 12)
  16 for %st(5) (gcc regno = 13)
  17 for %st(6) (gcc regno = 14)
  18 for %st(7) (gcc regno = 15)
*/
int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
{
  0, 2, 1, 3, 6, 7, 5, 4,   /* general regs */
  11, 12, 13, 14, 15, 16, 17, 18, /* fp regs */
  -1, 9, -1, -1, -1,      /* arg, flags, fpsr, dir, frame */
  21, 22, 23, 24, 25, 26, 27, 28, /* SSE registers */
  29, 30, 31, 32, 33, 34, 35, 36, /* MMX registers */
  -1, -1, -1, -1, -1, -1, -1, -1, /* extended integer registers */
  -1, -1, -1, -1, -1, -1, -1, -1, /* extended SSE registers */
};

/* Test and compare insns in i386.md store the information needed to
   generate branch and scc insns here.  */

rtx ix86_compare_op0 = NULL_RTX;
rtx ix86_compare_op1 = NULL_RTX;

#define MAX_386_STACK_LOCALS 3
/* Size of the register save area.  */
#define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16)

/* Define the structure for the machine field in struct function.  */

struct stack_local_entry GTY(())
{
  unsigned short mode;
  unsigned short n;
  rtx rtl;
  struct stack_local_entry *next;
};

/* Structure describing stack frame layout.
   Stack grows downward:

   [arguments]
                <- ARG_POINTER
   saved pc

   saved frame pointer if frame_pointer_needed
                <- HARD_FRAME_POINTER
   [saved regs]

   [padding1]          \
            )
   [va_arg registers]  (
            > to_allocate       <- FRAME_POINTER
   [frame]         (
            )
   [padding2]        /
  */
struct ix86_frame
{
  int nregs;
  int padding1;
  int va_arg_size;
  HOST_WIDE_INT frame;
  int padding2;
  int outgoing_arguments_size;
  int red_zone_size;

  HOST_WIDE_INT to_allocate;
  /* The offsets relative to ARG_POINTER.  */
  HOST_WIDE_INT frame_pointer_offset;
  HOST_WIDE_INT hard_frame_pointer_offset;
  HOST_WIDE_INT stack_pointer_offset;

  /* When save_regs_using_mov is set, emit prologue using
     move instead of push instructions.  */
  bool save_regs_using_mov;
};

/* Used to enable/disable debugging features.  */
const char *ix86_debug_arg_string, *ix86_debug_addr_string;
/* Code model option as passed by user.  */
const char *ix86_cmodel_string;
/* Parsed value.  */
enum cmodel ix86_cmodel;
/* Asm dialect.  */
const char *ix86_asm_string;
enum asm_dialect ix86_asm_dialect = ASM_ATT;
/* TLS dialext.  */
const char *ix86_tls_dialect_string;
enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU;

/* Which unit we are generating floating point math for.  */
enum fpmath_unit ix86_fpmath;

/* Which cpu are we scheduling for.  */
enum processor_type ix86_tune;
/* Which instruction set architecture to use.  */
enum processor_type ix86_arch;

/* Strings to hold which cpu and instruction set architecture  to use.  */
const char *ix86_tune_string;   /* for -mtune=<xxx> */
const char *ix86_arch_string;   /* for -march=<xxx> */
const char *ix86_fpmath_string;   /* for -mfpmath=<xxx> */

/* # of registers to use to pass arguments.  */
const char *ix86_regparm_string;

/* true if sse prefetch instruction is not NOOP.  */
int x86_prefetch_sse;

/* ix86_regparm_string as a number */
int ix86_regparm;

/* Alignment to use for loops and jumps:  */

/* Power of two alignment for loops.  */
const char *ix86_align_loops_string;

/* Power of two alignment for non-loop jumps.  */
const char *ix86_align_jumps_string;

/* Power of two alignment for stack boundary in bytes.  */
const char *ix86_preferred_stack_boundary_string;

/* Preferred alignment for stack boundary in bits.  */
unsigned int ix86_preferred_stack_boundary;

/* Values 1-5: see jump.c */
int ix86_branch_cost;
const char *ix86_branch_cost_string;

/* Power of two alignment for functions.  */
const char *ix86_align_funcs_string;

/* Prefix built by ASM_GENERATE_INTERNAL_LABEL.  */
char internal_label_prefix[16];
int internal_label_prefix_len;

static void output_pic_addr_const (FILE *, rtx, int);
static void put_condition_code (enum rtx_code, enum machine_mode,
        int, int, FILE *);
static const char *get_some_local_dynamic_name (void);
static int get_some_local_dynamic_name_1 (rtx *, void *);
static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx);
static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *,
               rtx *);
static bool ix86_fixed_condition_code_regs (unsigned int *, unsigned int *);
static enum machine_mode ix86_cc_modes_compatible (enum machine_mode,
               enum machine_mode);
static rtx get_thread_pointer (int);
static rtx legitimize_tls_address (rtx, enum tls_model, int);
static void get_pc_thunk_name (char [32], unsigned int);
static rtx gen_push (rtx);
static int ix86_flags_dependant (rtx, rtx, enum attr_type);
static int ix86_agi_dependant (rtx, rtx, enum attr_type);
static struct machine_function * ix86_init_machine_status (void);
static int ix86_split_to_parts (rtx, rtx *, enum machine_mode);
static int ix86_nsaved_regs (void);
static void ix86_emit_save_regs (void);
static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT);
static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int);
static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT);
static HOST_WIDE_INT ix86_GOT_alias_set (void);
static void ix86_adjust_counter (rtx, HOST_WIDE_INT);
static rtx ix86_expand_aligntest (rtx, int);
static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx);
static int ix86_issue_rate (void);
static int ix86_adjust_cost (rtx, rtx, rtx, int);
static int ia32_multipass_dfa_lookahead (void);
static void ix86_init_mmx_sse_builtins (void);
static rtx x86_this_parameter (tree);
static void x86_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
         HOST_WIDE_INT, tree);
static bool x86_can_output_mi_thunk (tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
static void x86_file_start (void);
static void ix86_reorg (void);
static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*);
static tree ix86_build_builtin_va_list (void);
static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
           tree, int *, int);
static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *);
static bool ix86_vector_mode_supported_p (enum machine_mode);

static int ix86_address_cost (rtx);
static bool ix86_cannot_force_const_mem (rtx);
static rtx ix86_delegitimize_address (rtx);

struct builtin_description;
static rtx ix86_expand_sse_comi (const struct builtin_description *,
         tree, rtx);
static rtx ix86_expand_sse_compare (const struct builtin_description *,
            tree, rtx);
static rtx ix86_expand_unop1_builtin (enum insn_code, tree, rtx);
static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int);
static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx);
static rtx ix86_expand_store_builtin (enum insn_code, tree);
static rtx safe_vector_operand (rtx, enum machine_mode);
static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *);
static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code);
static int ix86_fp_comparison_fcomi_cost (enum rtx_code code);
static int ix86_fp_comparison_sahf_cost (enum rtx_code code);
static int ix86_fp_comparison_cost (enum rtx_code code);
static unsigned int ix86_select_alt_pic_regnum (void);
static int ix86_save_reg (unsigned int, int);
static void ix86_compute_frame_layout (struct ix86_frame *);
static int ix86_comp_type_attributes (tree, tree);
static int ix86_function_regparm (tree, tree);
const struct attribute_spec ix86_attribute_table[];
static bool ix86_function_ok_for_sibcall (tree, tree);
static tree ix86_handle_cdecl_attribute (tree *, tree, tree, int, bool *);
static tree ix86_handle_regparm_attribute (tree *, tree, tree, int, bool *);
static int ix86_value_regno (enum machine_mode);
static bool contains_128bit_aligned_vector_p (tree);
static rtx ix86_struct_value_rtx (tree, int);
static bool ix86_ms_bitfield_layout_p (tree);
static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *);
static int extended_reg_mentioned_1 (rtx *, void *);
static bool ix86_rtx_costs (rtx, int, int, int *);
static int min_insn_size (rtx);
static tree ix86_md_asm_clobbers (tree clobbers);
static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type);
static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
            tree, bool);
static void ix86_init_builtins (void);
static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int);

/* This function is only used on Solaris.  */
static void i386_solaris_elf_named_section (const char *, unsigned int, tree)
  ATTRIBUTE_UNUSED;

/* Register class used for passing given 64bit part of the argument.
   These represent classes as documented by the PS ABI, with the exception
   of SSESF, SSEDF classes, that are basically SSE class, just gcc will
   use SF or DFmode move instead of DImode to avoid reformatting penalties.

   Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
   whenever possible (upper half does contain padding).
 */
enum x86_64_reg_class
  {
    X86_64_NO_CLASS,
    X86_64_INTEGER_CLASS,
    X86_64_INTEGERSI_CLASS,
    X86_64_SSE_CLASS,
    X86_64_SSESF_CLASS,
    X86_64_SSEDF_CLASS,
    X86_64_SSEUP_CLASS,
    X86_64_X87_CLASS,
    X86_64_X87UP_CLASS,
    X86_64_COMPLEX_X87_CLASS,
    X86_64_MEMORY_CLASS
  };
static const char * const x86_64_reg_class_name[] = {
  "no", "integer", "integerSI", "sse", "sseSF", "sseDF",
  "sseup", "x87", "x87up", "cplx87", "no"
};

#define MAX_CLASSES 4

/* Table of constants used by fldpi, fldln2, etc....  */
static REAL_VALUE_TYPE ext_80387_constants_table [5];
static bool ext_80387_constants_init = 0;
static void init_ext_80387_constants (void);

/* Initialize the GCC target structure.  */
#undef TARGET_ATTRIBUTE_TABLE
#define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
#  undef TARGET_MERGE_DECL_ATTRIBUTES
#  define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
#endif

#undef TARGET_COMP_TYPE_ATTRIBUTES
#define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes

#undef TARGET_INIT_BUILTINS
#define TARGET_INIT_BUILTINS ix86_init_builtins
#undef TARGET_EXPAND_BUILTIN
#define TARGET_EXPAND_BUILTIN ix86_expand_builtin

#undef TARGET_ASM_FUNCTION_EPILOGUE
#define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue

#undef TARGET_ASM_OPEN_PAREN
#define TARGET_ASM_OPEN_PAREN ""
#undef TARGET_ASM_CLOSE_PAREN
#define TARGET_ASM_CLOSE_PAREN ""

#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
#undef TARGET_ASM_ALIGNED_SI_OP
#define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
#ifdef ASM_QUAD
#undef TARGET_ASM_ALIGNED_DI_OP
#define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
#endif

#undef TARGET_ASM_UNALIGNED_HI_OP
#define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
#undef TARGET_ASM_UNALIGNED_SI_OP
#define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
#undef TARGET_ASM_UNALIGNED_DI_OP
#define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP

#undef TARGET_SCHED_ADJUST_COST
#define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
  ia32_multipass_dfa_lookahead

#undef TARGET_FUNCTION_OK_FOR_SIBCALL
#define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall

#ifdef HAVE_AS_TLS
#undef TARGET_HAVE_TLS
#define TARGET_HAVE_TLS true
#endif
#undef TARGET_CANNOT_FORCE_CONST_MEM
#define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem

#undef TARGET_DELEGITIMIZE_ADDRESS
#define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address

#undef TARGET_MS_BITFIELD_LAYOUT_P
#define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p

#undef TARGET_ASM_OUTPUT_MI_THUNK
#define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk

#undef TARGET_ASM_FILE_START
#define TARGET_ASM_FILE_START x86_file_start

#undef TARGET_RTX_COSTS
#define TARGET_RTX_COSTS ix86_rtx_costs
#undef TARGET_ADDRESS_COST
#define TARGET_ADDRESS_COST ix86_address_cost

#undef TARGET_FIXED_CONDITION_CODE_REGS
#define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
#undef TARGET_CC_MODES_COMPATIBLE
#define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible

#undef TARGET_MACHINE_DEPENDENT_REORG
#define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg

#undef TARGET_BUILD_BUILTIN_VA_LIST
#define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list

#undef TARGET_MD_ASM_CLOBBERS
#define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers

#undef TARGET_PROMOTE_PROTOTYPES
#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
#undef TARGET_STRUCT_VALUE_RTX
#define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
#undef TARGET_MUST_PASS_IN_STACK
#define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
#undef TARGET_PASS_BY_REFERENCE
#define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference

#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg

#undef TARGET_VECTOR_MODE_SUPPORTED_P
#define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p

#ifdef SUBTARGET_INSERT_ATTRIBUTES
#undef TARGET_INSERT_ATTRIBUTES
#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
#endif

struct gcc_target targetm = TARGET_INITIALIZER;


/* The svr4 ABI for the i386 says that records and unions are returned
   in memory.  */
#ifndef DEFAULT_PCC_STRUCT_RETURN
#define DEFAULT_PCC_STRUCT_RETURN 1
#endif

/* Sometimes certain combinations of command options do not make
   sense on a particular target machine.  You can define a macro
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
   defined, is executed once just after all the command options have
   been parsed.

   Don't use this macro to turn on various extra optimizations for
   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */

void
override_options (void)
{
  int i;
  int ix86_tune_defaulted = 0;

  /* Comes from final.c -- no real reason to change it.  */
#define MAX_CODE_ALIGN 16

  static struct ptt
    {
      const struct processor_costs *cost; /* Processor costs */
      const int target_enable;      /* Target flags to enable.  */
      const int target_disable;     /* Target flags to disable.  */
      const int align_loop;     /* Default alignments.  */
      const int align_loop_max_skip;
      const int align_jump;
      const int align_jump_max_skip;
      const int align_func;
    }
  const processor_target_table[PROCESSOR_max] =
    {
      {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
      {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
      {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
      {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
      {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
      {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
      {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
      {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
      {&nocona_cost, 0, 0, 0, 0, 0, 0, 0}
    };

  static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
  static struct pta
    {
      const char *const name;   /* processor name or nickname.  */
      const enum processor_type processor;
      const enum pta_flags
  {
    PTA_SSE = 1,
    PTA_SSE2 = 2,
    PTA_SSE3 = 4,
    PTA_MMX = 8,
    PTA_PREFETCH_SSE = 16,
    PTA_3DNOW = 32,
    PTA_3DNOW_A = 64,
    PTA_64BIT = 128
  } flags;
    }
  const processor_alias_table[] =
    {
      {"i386", PROCESSOR_I386, 0},
      {"i486", PROCESSOR_I486, 0},
      {"i586", PROCESSOR_PENTIUM, 0},
      {"pentium", PROCESSOR_PENTIUM, 0},
      {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
      {"winchip-c6", PROCESSOR_I486, PTA_MMX},
      {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
      {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
      {"c3-2", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_PREFETCH_SSE | PTA_SSE},
      {"i686", PROCESSOR_PENTIUMPRO, 0},
      {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
      {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
      {"pentium3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
      {"pentium3m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE},
      {"pentium-m", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_SSE | PTA_PREFETCH_SSE | PTA_SSE2},
      {"pentium4", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
               | PTA_MMX | PTA_PREFETCH_SSE},
      {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2
                | PTA_MMX | PTA_PREFETCH_SSE},
      {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3
                | PTA_MMX | PTA_PREFETCH_SSE},
      {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT
                | PTA_MMX | PTA_PREFETCH_SSE},
      {"k6", PROCESSOR_K6, PTA_MMX},
      {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
      {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW},
      {"athlon", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
           | PTA_3DNOW_A},
      {"athlon-tbird", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE
           | PTA_3DNOW | PTA_3DNOW_A},
      {"athlon-4", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
            | PTA_3DNOW_A | PTA_SSE},
      {"athlon-xp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
              | PTA_3DNOW_A | PTA_SSE},
      {"athlon-mp", PROCESSOR_ATHLON, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW
              | PTA_3DNOW_A | PTA_SSE},
      {"x86-64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_64BIT
             | PTA_SSE | PTA_SSE2 },
      {"k8", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
              | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
      {"opteron", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
              | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
      {"athlon64", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
              | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
      {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT
              | PTA_3DNOW_A | PTA_SSE | PTA_SSE2},
    };

  int const pta_size = ARRAY_SIZE (processor_alias_table);

#ifdef SUBTARGET_OVERRIDE_OPTIONS
  SUBTARGET_OVERRIDE_OPTIONS;
#endif

  /* Set the default values for switches whose default depends on TARGET_64BIT
     in case they weren't overwritten by command line options.  */
  if (TARGET_64BIT)
    {
      if (flag_omit_frame_pointer == 2)
  flag_omit_frame_pointer = 1;
      if (flag_asynchronous_unwind_tables == 2)
  flag_asynchronous_unwind_tables = 1;
      if (flag_pcc_struct_return == 2)
  flag_pcc_struct_return = 0;
    }
  else
    {
      if (flag_omit_frame_pointer == 2)
  flag_omit_frame_pointer = 0;
      if (flag_asynchronous_unwind_tables == 2)
  flag_asynchronous_unwind_tables = 0;
      if (flag_pcc_struct_return == 2)
  flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN;
    }

  if (!ix86_tune_string && ix86_arch_string)
    ix86_tune_string = ix86_arch_string;
  if (!ix86_tune_string)
    {
      ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT];
      ix86_tune_defaulted = 1;
    }
  if (!ix86_arch_string)
    ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386";

  if (ix86_cmodel_string != 0)
    {
      if (!strcmp (ix86_cmodel_string, "small"))
  ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
      else if (flag_pic)
  sorry ("code model %s not supported in PIC mode", ix86_cmodel_string);
      else if (!strcmp (ix86_cmodel_string, "32"))
  ix86_cmodel = CM_32;
      else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic)
  ix86_cmodel = CM_KERNEL;
      else if (!strcmp (ix86_cmodel_string, "medium") && !flag_pic)
  ix86_cmodel = CM_MEDIUM;
      else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic)
  ix86_cmodel = CM_LARGE;
      else
  error ("bad value (%s) for -mcmodel= switch", ix86_cmodel_string);
    }
  else
    {
      ix86_cmodel = CM_32;
      if (TARGET_64BIT)
  ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL;
    }
  if (ix86_asm_string != 0)
    {
      if (!strcmp (ix86_asm_string, "intel"))
  ix86_asm_dialect = ASM_INTEL;
      else if (!strcmp (ix86_asm_string, "att"))
  ix86_asm_dialect = ASM_ATT;
      else
  error ("bad value (%s) for -masm= switch", ix86_asm_string);
    }
  if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
    error ("code model %qs not supported in the %s bit mode",
     ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
  if (ix86_cmodel == CM_LARGE)
    sorry ("code model %<large%> not supported yet");
  if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
    sorry ("%i-bit mode not compiled in",
     (target_flags & MASK_64BIT) ? 64 : 32);

  for (i = 0; i < pta_size; i++)
    if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
      {
  ix86_arch = processor_alias_table[i].processor;
  /* Default cpu tuning to the architecture.  */
  ix86_tune = ix86_arch;
  if (processor_alias_table[i].flags & PTA_MMX
      && !(target_flags_explicit & MASK_MMX))
    target_flags |= MASK_MMX;
  if (processor_alias_table[i].flags & PTA_3DNOW
      && !(target_flags_explicit & MASK_3DNOW))
    target_flags |= MASK_3DNOW;
  if (processor_alias_table[i].flags & PTA_3DNOW_A
      && !(target_flags_explicit & MASK_3DNOW_A))
    target_flags |= MASK_3DNOW_A;
  if (processor_alias_table[i].flags & PTA_SSE
      && !(target_flags_explicit & MASK_SSE))
    target_flags |= MASK_SSE;
  if (processor_alias_table[i].flags & PTA_SSE2
      && !(target_flags_explicit & MASK_SSE2))
    target_flags |= MASK_SSE2;
  if (processor_alias_table[i].flags & PTA_SSE3
      && !(target_flags_explicit & MASK_SSE3))
    target_flags |= MASK_SSE3;
  if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
    x86_prefetch_sse = true;
  if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
    error ("CPU you selected does not support x86-64 "
     "instruction set");
  break;
      }

  if (i == pta_size)
    error ("bad value (%s) for -march= switch", ix86_arch_string);

  for (i = 0; i < pta_size; i++)
    if (! strcmp (ix86_tune_string, processor_alias_table[i].name))
      {
  ix86_tune = processor_alias_table[i].processor;
  if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
    {
      if (ix86_tune_defaulted)
        {
    ix86_tune_string = "x86-64";
    for (i = 0; i < pta_size; i++)
      if (! strcmp (ix86_tune_string,
        processor_alias_table[i].name))
        break;
    ix86_tune = processor_alias_table[i].processor;
        }
      else
        error ("CPU you selected does not support x86-64 "
         "instruction set");
    }
        /* Intel CPUs have always interpreted SSE prefetch instructions as
     NOPs; so, we can enable SSE prefetch instructions even when
     -mtune (rather than -march) points us to a processor that has them.
     However, the VIA C3 gives a SIGILL, so we only do that for i686 and
     higher processors.  */
  if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
    x86_prefetch_sse = true;
  break;
      }
  if (i == pta_size)
    error ("bad value (%s) for -mtune= switch", ix86_tune_string);

  if (optimize_size)
    ix86_cost = &size_cost;
  else
    ix86_cost = processor_target_table[ix86_tune].cost;
  target_flags |= processor_target_table[ix86_tune].target_enable;
  target_flags &= ~processor_target_table[ix86_tune].target_disable;

  /* Arrange to set up i386_stack_locals for all functions.  */
  init_machine_status = ix86_init_machine_status;

  /* Validate -mregparm= value.  */
  if (ix86_regparm_string)
    {
      i = atoi (ix86_regparm_string);
      if (i < 0 || i > REGPARM_MAX)
  error ("-mregparm=%d is not between 0 and %d", i, REGPARM_MAX);
      else
  ix86_regparm = i;
    }
  else
   if (TARGET_64BIT)
     ix86_regparm = REGPARM_MAX;

  /* If the user has provided any of the -malign-* options,
     warn and use that value only if -falign-* is not set.
     Remove this code in GCC 3.2 or later.  */
  if (ix86_align_loops_string)
    {
      warning ("-malign-loops is obsolete, use -falign-loops");
      if (align_loops == 0)
  {
    i = atoi (ix86_align_loops_string);
    if (i < 0 || i > MAX_CODE_ALIGN)
      error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
    else
      align_loops = 1 << i;
  }
    }

  if (ix86_align_jumps_string)
    {
      warning ("-malign-jumps is obsolete, use -falign-jumps");
      if (align_jumps == 0)
  {
    i = atoi (ix86_align_jumps_string);
    if (i < 0 || i > MAX_CODE_ALIGN)
      error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
    else
      align_jumps = 1 << i;
  }
    }

  if (ix86_align_funcs_string)
    {
      warning ("-malign-functions is obsolete, use -falign-functions");
      if (align_functions == 0)
  {
    i = atoi (ix86_align_funcs_string);
    if (i < 0 || i > MAX_CODE_ALIGN)
      error ("-malign-loops=%d is not between 0 and %d", i, MAX_CODE_ALIGN);
    else
      align_functions = 1 << i;
  }
    }

  /* Default align_* from the processor table.  */
  if (align_loops == 0)
    {
      align_loops = processor_target_table[ix86_tune].align_loop;
      align_loops_max_skip = processor_target_table[ix86_tune].align_loop_max_skip;
    }
  if (align_jumps == 0)
    {
      align_jumps = processor_target_table[ix86_tune].align_jump;
      align_jumps_max_skip = processor_target_table[ix86_tune].align_jump_max_skip;
    }
  if (align_functions == 0)
    {
      align_functions = processor_target_table[ix86_tune].align_func;
    }

  /* Validate -mpreferred-stack-boundary= value, or provide default.
     The default of 128 bits is for Pentium III's SSE __m128, but we
     don't want additional code to keep the stack aligned when
     optimizing for code size.  */
  ix86_preferred_stack_boundary = (optimize_size
           ? TARGET_64BIT ? 128 : 32
           : 128);
  if (ix86_preferred_stack_boundary_string)
    {
      i = atoi (ix86_preferred_stack_boundary_string);
      if (i < (TARGET_64BIT ? 4 : 2) || i > 12)
  error ("-mpreferred-stack-boundary=%d is not between %d and 12", i,
         TARGET_64BIT ? 4 : 2);
      else
  ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT;
    }

  /* Validate -mbranch-cost= value, or provide default.  */
  ix86_branch_cost = processor_target_table[ix86_tune].cost->branch_cost;
  if (ix86_branch_cost_string)
    {
      i = atoi (ix86_branch_cost_string);
      if (i < 0 || i > 5)
  error ("-mbranch-cost=%d is not between 0 and 5", i);
      else
  ix86_branch_cost = i;
    }

  if (ix86_tls_dialect_string)
    {
      if (strcmp (ix86_tls_dialect_string, "gnu") == 0)
  ix86_tls_dialect = TLS_DIALECT_GNU;
      else if (strcmp (ix86_tls_dialect_string, "sun") == 0)
  ix86_tls_dialect = TLS_DIALECT_SUN;
      else
  error ("bad value (%s) for -mtls-dialect= switch",
         ix86_tls_dialect_string);
    }

  /* Keep nonleaf frame pointers.  */
  if (flag_omit_frame_pointer)
    target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER;
  else if (TARGET_OMIT_LEAF_FRAME_POINTER)
    flag_omit_frame_pointer = 1;

  /* If we're doing fast math, we don't care about comparison order
     wrt NaNs.  This lets us use a shorter comparison sequence.  */
  if (flag_unsafe_math_optimizations)
    target_flags &= ~MASK_IEEE_FP;

  /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
     since the insns won't need emulation.  */
  if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
    target_flags &= ~MASK_NO_FANCY_MATH_387;

  /* Likewise, if the target doesn't have a 387, or we've specified
     software floating point, don't use 387 inline instrinsics.  */
  if (!TARGET_80387)
    target_flags |= MASK_NO_FANCY_MATH_387;

  /* Turn on SSE2 builtins for -msse3.  */
  if (TARGET_SSE3)
    target_flags |= MASK_SSE2;

  /* Turn on SSE builtins for -msse2.  */
  if (TARGET_SSE2)
    target_flags |= MASK_SSE;

  /* Turn on MMX builtins for -msse.  */
  if (TARGET_SSE)
    {
      target_flags |= MASK_MMX & ~target_flags_explicit;
      x86_prefetch_sse = true;
    }

  /* Turn on MMX builtins for 3Dnow.  */
  if (TARGET_3DNOW)
    target_flags |= MASK_MMX;

  if (TARGET_64BIT)
    {
      if (TARGET_ALIGN_DOUBLE)
  error ("-malign-double makes no sense in the 64bit mode");
      if (TARGET_RTD)
  error ("-mrtd calling convention not supported in the 64bit mode");

      /* Enable by default the SSE and MMX builtins.  Do allow the user to
   explicitly disable any of these.  In particular, disabling SSE and
   MMX for kernel code is extremely useful.  */
      target_flags
  |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE)
      & ~target_flags_explicit);

      if (TARGET_SSE)
  ix86_fpmath = FPMATH_SSE;
     }
  else
    {
      ix86_fpmath = FPMATH_387;
      /* i386 ABI does not specify red zone.  It still makes sense to use it
         when programmer takes care to stack from being destroyed.  */
      if (!(target_flags_explicit & MASK_NO_RED_ZONE))
        target_flags |= MASK_NO_RED_ZONE;
    }

  if (ix86_fpmath_string != 0)
    {
      if (! strcmp (ix86_fpmath_string, "387"))
  ix86_fpmath = FPMATH_387;
      else if (! strcmp (ix86_fpmath_string, "sse"))
  {
    if (!TARGET_SSE)
      {
        warning ("SSE instruction set disabled, using 387 arithmetics");
        ix86_fpmath = FPMATH_387;
      }
    else
      ix86_fpmath = FPMATH_SSE;
  }
      else if (! strcmp (ix86_fpmath_string, "387,sse")
         || ! strcmp (ix86_fpmath_string, "sse,387"))
  {
    if (!TARGET_SSE)
      {
        warning ("SSE instruction set disabled, using 387 arithmetics");
        ix86_fpmath = FPMATH_387;
      }
    else if (!TARGET_80387)
      {
        warning ("387 instruction set disabled, using SSE arithmetics");
        ix86_fpmath = FPMATH_SSE;
      }
    else
      ix86_fpmath = FPMATH_SSE | FPMATH_387;
  }
      else
  error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string);
    }

  /* If the i387 is disabled, then do not return values in it. */
  if (!TARGET_80387)
    target_flags &= ~MASK_FLOAT_RETURNS;

  if ((x86_accumulate_outgoing_args & TUNEMASK)
      && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS)
      && !optimize_size)
    target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS;

  /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix.  */
  {
    char *p;
    ASM_GENERATE_INTERNAL_LABEL (internal_label_prefix, "LX", 0);
    p = strchr (internal_label_prefix, 'X');
    internal_label_prefix_len = p - internal_label_prefix;
    *p = '\0';
  }

  /* When scheduling description is not available, disable scheduler pass
     so it won't slow down the compilation and make x87 code slower.  */
  if (!TARGET_SCHEDULE)
    flag_schedule_insns_after_reload = flag_schedule_insns = 0;
}

void
optimization_options (int level, int size ATTRIBUTE_UNUSED)
{
  /* For -O2 and beyond, turn off -fschedule-insns by default.  It tends to
     make the problem with not enough registers even worse.  */
#ifdef INSN_SCHEDULING
  if (level > 1)
    flag_schedule_insns = 0;
#endif

  /* The default values of these switches depend on the TARGET_64BIT
     that is not known at this moment.  Mark these values with 2 and
     let user the to override these.  In case there is no command line option
     specifying them, we will set the defaults in override_options.  */
  if (optimize >= 1)
    flag_omit_frame_pointer = 2;
  flag_pcc_struct_return = 2;
  flag_asynchronous_unwind_tables = 2;
#ifdef SUBTARGET_OPTIMIZATION_OPTIONS
  SUBTARGET_OPTIMIZATION_OPTIONS;
#endif
}

/* Table of valid machine attributes.  */
const struct attribute_spec ix86_attribute_table[] =
{
  /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
  /* Stdcall attribute says callee is responsible for popping arguments
     if they are not variable.  */
  { "stdcall",   0, 0, false, true,  true,  ix86_handle_cdecl_attribute },
  /* Fastcall attribute says callee is responsible for popping arguments
     if they are not variable.  */
  { "fastcall",  0, 0, false, true,  true,  ix86_handle_cdecl_attribute },
  /* Cdecl attribute says the callee is a normal C declaration */
  { "cdecl",     0, 0, false, true,  true,  ix86_handle_cdecl_attribute },
  /* Regparm attribute specifies how many integer arguments are to be
     passed in registers.  */
  { "regparm",   1, 1, false, true,  true,  ix86_handle_regparm_attribute },
#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
  { "dllimport", 0, 0, false, false, false, handle_dll_attribute },
  { "dllexport", 0, 0, false, false, false, handle_dll_attribute },
  { "shared",    0, 0, true,  false, false, ix86_handle_shared_attribute },
#endif
  { "ms_struct", 0, 0, false, false,  false, ix86_handle_struct_attribute },
  { "gcc_struct", 0, 0, false, false,  false, ix86_handle_struct_attribute },
#ifdef SUBTARGET_ATTRIBUTE_TABLE
  SUBTARGET_ATTRIBUTE_TABLE,
#endif
  { NULL,        0, 0, false, false, false, NULL }
};

/* Decide whether we can make a sibling call to a function.  DECL is the
   declaration of the function being targeted by the call and EXP is the
   CALL_EXPR representing the call.  */

static bool
ix86_function_ok_for_sibcall (tree decl, tree exp)
{
  /* If we are generating position-independent code, we cannot sibcall
     optimize any indirect call, or a direct call to a global function,
     as the PLT requires %ebx be live.  */
  if (!TARGET_64BIT && flag_pic && (!decl || TREE_PUBLIC (decl)))
    return false;

  /* If we are returning floats on the 80387 register stack, we cannot
     make a sibcall from a function that doesn't return a float to a
     function that does or, conversely, from a function that does return
     a float to a function that doesn't; the necessary stack adjustment
     would not be executed.  */
  if (STACK_REG_P (ix86_function_value (TREE_TYPE (exp)))
      != STACK_REG_P (ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)))))
    return false;

  /* If this call is indirect, we'll need to be able to use a call-clobbered
     register for the address of the target function.  Make sure that all
     such registers are not used for passing parameters.  */
  if (!decl && !TARGET_64BIT)
    {
      tree type;

      /* We're looking at the CALL_EXPR, we need the type of the function.  */
      type = TREE_OPERAND (exp, 0);   /* pointer expression */
      type = TREE_TYPE (type);      /* pointer type */
      type = TREE_TYPE (type);      /* function type */

      if (ix86_function_regparm (type, NULL) >= 3)
  {
    /* ??? Need to count the actual number of registers to be used,
       not the possible number of registers.  Fix later.  */
    return false;
  }
    }

#if TARGET_DLLIMPORT_DECL_ATTRIBUTES
  /* Dllimport'd functions are also called indirectly.  */
  if (decl && lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl))
      && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3)
    return false;
#endif

  /* Otherwise okay.  That also includes certain types of indirect calls.  */
  return true;
}

/* Handle a "cdecl", "stdcall", or "fastcall" attribute;
   arguments as in struct attribute_spec.handler.  */
static tree
ix86_handle_cdecl_attribute (tree *node, tree name,
           tree args ATTRIBUTE_UNUSED,
           int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
{
  if (TREE_CODE (*node) != FUNCTION_TYPE
      && TREE_CODE (*node) != METHOD_TYPE
      && TREE_CODE (*node) != FIELD_DECL
      && TREE_CODE (*node) != TYPE_DECL)
    {
      warning ("%qs attribute only applies to functions",
         IDENTIFIER_POINTER (name));
      *no_add_attrs = true;
    }
  else
    {
      if (is_attribute_p ("fastcall", name))
        {
          if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node)))
            {
              error ("fastcall and stdcall attributes are not compatible");
            }
           else if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node)))
            {
              error ("fastcall and regparm attributes are not compatible");
            }
        }
      else if (is_attribute_p ("stdcall", name))
        {
          if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
            {
              error ("fastcall and stdcall attributes are not compatible");
            }
        }
    }

  if (TARGET_64BIT)
    {
      warning ("%qs attribute ignored", IDENTIFIER_POINTER (name));
      *no_add_attrs = true;
    }

  return NULL_TREE;
}

/* Handle a "regparm" attribute;
   arguments as in struct attribute_spec.handler.  */
static tree
ix86_handle_regparm_attribute (tree *node, tree name, tree args,
             int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
{
  if (TREE_CODE (*node) != FUNCTION_TYPE
      && TREE_CODE (*node) != METHOD_TYPE
      && TREE_CODE (*node) != FIELD_DECL
      && TREE_CODE (*node) != TYPE_DECL)
    {
      warning ("%qs attribute only applies to functions",
         IDENTIFIER_POINTER (name));
      *no_add_attrs = true;
    }
  else
    {
      tree cst;

      cst = TREE_VALUE (args);
      if (TREE_CODE (cst) != INTEGER_CST)
  {
    warning ("%qs attribute requires an integer constant argument",
       IDENTIFIER_POINTER (name));
    *no_add_attrs = true;
  }
      else if (compare_tree_int (cst, REGPARM_MAX) > 0)
  {
    warning ("argument to %qs attribute larger than %d",
       IDENTIFIER_POINTER (name), REGPARM_MAX);
    *no_add_attrs = true;
  }

      if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
  {
    error ("fastcall and regparm attributes are not compatible");
  }
    }

  return NULL_TREE;
}

/* Return 0 if the attributes for two types are incompatible, 1 if they
   are compatible, and 2 if they are nearly compatible (which causes a
   warning to be generated).  */

static int
ix86_comp_type_attributes (tree type1, tree type2)
{
  /* Check for mismatch of non-default calling convention.  */
  const char *const rtdstr = TARGET_RTD ? "cdecl" : "stdcall";

  if (TREE_CODE (type1) != FUNCTION_TYPE)
    return 1;

  /*  Check for mismatched fastcall types */
  if (!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1))
      != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2)))
    return 0;

  /* Check for mismatched return types (cdecl vs stdcall).  */
  if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1))
      != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2)))
    return 0;
  if (ix86_function_regparm (type1, NULL)
      != ix86_function_regparm (type2, NULL))
    return 0;
  return 1;
}

/* Return the regparm value for a fuctio with the indicated TYPE and DECL.
   DECL may be NULL when calling function indirectly
   or considering a libcall.  */

static int
ix86_function_regparm (tree type, tree decl)
{
  tree attr;
  int regparm = ix86_regparm;
  bool user_convention = false;

  if (!TARGET_64BIT)
    {
      attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
      if (attr)
  {
    regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
    user_convention = true;
  }

      if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
  {
    regparm = 2;
    user_convention = true;
  }

      /* Use register calling convention for local functions when possible.  */
      if (!TARGET_64BIT && !user_convention && decl
    && flag_unit_at_a_time && !profile_flag)
  {
    struct cgraph_local_info *i = cgraph_local_info (decl);
    if (i && i->local)
      {
        int local_regparm, globals = 0, regno;

        /* Make sure no regparm register is taken by a global register
     variable.  */
        for (local_regparm = 0; local_regparm < 3; local_regparm++)
    if (global_regs[local_regparm])
      break;
        /* We can't use regparm(3) for nested functions as these use
     static chain pointer in third argument.  */
        if (local_regparm == 3
      && DECL_CONTEXT (decl) && !DECL_NO_STATIC_CHAIN (decl))
    local_regparm = 2;
        /* Each global register variable increases register preassure,
     so the more global reg vars there are, the smaller regparm
     optimization use, unless requested by the user explicitly.  */
        for (regno = 0; regno < 6; regno++)
    if (global_regs[regno])
      globals++;
        local_regparm
    = globals < local_regparm ? local_regparm - globals : 0;

        if (local_regparm > regparm)
    regparm = local_regparm;
      }
  }
    }
  return regparm;
}

/* Return true if EAX is live at the start of the function.  Used by
   ix86_expand_prologue to determine if we need special help before
   calling allocate_stack_worker.  */

static bool
ix86_eax_live_at_start_p (void)
{
  /* Cheat.  Don't bother working forward from ix86_function_regparm
     to the function type to whether an actual argument is located in
     eax.  Instead just look at cfg info, which is still close enough
     to correct at this point.  This gives false positives for broken
     functions that might use uninitialized data that happens to be
     allocated in eax, but who cares?  */
  return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->global_live_at_end, 0);
}

/* Value is the number of bytes of arguments automatically
   popped when returning from a subroutine call.
   FUNDECL is the declaration node of the function (as a tree),
   FUNTYPE is the data type of the function (as a tree),
   or for a library call it is an identifier node for the subroutine name.
   SIZE is the number of bytes of arguments passed on the stack.

   On the 80386, the RTD insn may be used to pop them if the number
     of args is fixed, but if the number is variable then the caller
     must pop them all.  RTD can't be used for library calls now
     because the library is compiled with the Unix compiler.
   Use of RTD is a selectable option, since it is incompatible with
   standard Unix calling sequences.  If the option is not selected,
   the caller must always pop the args.

   The attribute stdcall is equivalent to RTD on a per module basis.  */

int
ix86_return_pops_args (tree fundecl, tree funtype, int size)
{
  int rtd = TARGET_RTD && (!fundecl || TREE_CODE (fundecl) != IDENTIFIER_NODE);

  /* Cdecl functions override -mrtd, and never pop the stack.  */
  if (! lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) {

    /* Stdcall and fastcall functions will pop the stack if not
       variable args.  */
    if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))
        || lookup_attribute ("fastcall", TYPE_ATTRIBUTES (funtype)))
      rtd = 1;

    if (rtd
        && (TYPE_ARG_TYPES (funtype) == NULL_TREE
      || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype)))
    == void_type_node)))
      return size;
  }

  /* Lose any fake structure return argument if it is passed on the stack.  */
  if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
      && !TARGET_64BIT
      && !KEEP_AGGREGATE_RETURN_POINTER)
    {
      int nregs = ix86_function_regparm (funtype, fundecl);

      if (!nregs)
  return GET_MODE_SIZE (Pmode);
    }

  return 0;
}

/* Argument support functions.  */

/* Return true when register may be used to pass function parameters.  */
bool
ix86_function_arg_regno_p (int regno)
{
  int i;
  if (!TARGET_64BIT)
    return (regno < REGPARM_MAX
      || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno]));
  if (SSE_REGNO_P (regno) && TARGET_SSE)
    return true;
  /* RAX is used as hidden argument to va_arg functions.  */
  if (!regno)
    return true;
  for (i = 0; i < REGPARM_MAX; i++)
    if (regno == x86_64_int_parameter_registers[i])
      return true;
  return false;
}

/* Return if we do not know how to pass TYPE solely in registers.  */

static bool
ix86_must_pass_in_stack (enum machine_mode mode, tree type)
{
  if (must_pass_in_stack_var_size_or_pad (mode, type))
    return true;

  /* For 32-bit, we want TImode aggregates to go on the stack.  But watch out!
     The layout_type routine is crafty and tries to trick us into passing
     currently unsupported vector types on the stack by using TImode.  */
  return (!TARGET_64BIT && mode == TImode
    && type && TREE_CODE (type) != VECTOR_TYPE);
}

/* Initialize a variable CUM of type CUMULATIVE_ARGS
   for a call to a function whose data type is FNTYPE.
   For a library call, FNTYPE is 0.  */

void
init_cumulative_args (CUMULATIVE_ARGS *cum,  /* Argument info to initialize */
          tree fntype,  /* tree ptr for function decl */
          rtx libname,  /* SYMBOL_REF of library name or 0 */
          tree fndecl)
{
  static CUMULATIVE_ARGS zero_cum;
  tree param, next_param;

  if (TARGET_DEBUG_ARG)
    {
      fprintf (stderr, "\ninit_cumulative_args (");
      if (fntype)
  fprintf (stderr, "fntype code = %s, ret code = %s",
     tree_code_name[(int) TREE_CODE (fntype)],
     tree_code_name[(int) TREE_CODE (TREE_TYPE (fntype))]);
      else
  fprintf (stderr, "no fntype");

      if (libname)
  fprintf (stderr, ", libname = %s", XSTR (libname, 0));
    }

  *cum = zero_cum;

  /* Set up the number of registers to use for passing arguments.  */
  if (fntype)
    cum->nregs = ix86_function_regparm (fntype, fndecl);
  else
    cum->nregs = ix86_regparm;
  if (TARGET_SSE)
    cum->sse_nregs = SSE_REGPARM_MAX;
  if (TARGET_MMX)
    cum->mmx_nregs = MMX_REGPARM_MAX;
  cum->warn_sse = true;
  cum->warn_mmx = true;
  cum->maybe_vaarg = false;

  /* Use ecx and edx registers if function has fastcall attribute */
  if (fntype && !TARGET_64BIT)
    {
      if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype)))
  {
    cum->nregs = 2;
    cum->fastcall = 1;
  }
    }

  /* Determine if this function has variable arguments.  This is
     indicated by the last argument being 'void_type_mode' if there
     are no variable arguments.  If there are variable arguments, then
     we won't pass anything in registers in 32-bit mode. */

  if (cum->nregs || cum->mmx_nregs || cum->sse_nregs)
    {
      for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
     param != 0; param = next_param)
  {
    next_param = TREE_CHAIN (param);
    if (next_param == 0 && TREE_VALUE (param) != void_type_node)
      {
        if (!TARGET_64BIT)
    {
      cum->nregs = 0;
      cum->sse_nregs = 0;
      cum->mmx_nregs = 0;
      cum->warn_sse = 0;
      cum->warn_mmx = 0;
      cum->fastcall = 0;
    }
        cum->maybe_vaarg = true;
      }
  }
    }
  if ((!fntype && !libname)
      || (fntype && !TYPE_ARG_TYPES (fntype)))
    cum->maybe_vaarg = 1;

  if (TARGET_DEBUG_ARG)
    fprintf (stderr, ", nregs=%d )\n", cum->nregs);

  return;
}

/* Return the "natural" mode for TYPE.  In most cases, this is just TYPE_MODE.
   But in the case of vector types, it is some vector mode.

   When we have only some of our vector isa extensions enabled, then there
   are some modes for which vector_mode_supported_p is false.  For these
   modes, the generic vector support in gcc will choose some non-vector mode
   in order to implement the type.  By computing the natural mode, we'll 
   select the proper ABI location for the operand and not depend on whatever
   the middle-end decides to do with these vector types.  */

static enum machine_mode
type_natural_mode (tree type)
{
  enum machine_mode mode = TYPE_MODE (type);

  if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode))
    {
      HOST_WIDE_INT size = int_size_in_bytes (type);
      if ((size == 8 || size == 16)
    /* ??? Generic code allows us to create width 1 vectors.  Ignore.  */
    && TYPE_VECTOR_SUBPARTS (type) > 1)
  {
    enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type));

    if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE)
      mode = MIN_MODE_VECTOR_FLOAT;
    else
      mode = MIN_MODE_VECTOR_INT;

    /* Get the mode which has this inner mode and number of units.  */
    for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode))
      if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type)
    && GET_MODE_INNER (mode) == innermode)
        return mode;

    abort ();
  }
    }

  return mode;
}

/* We want to pass a value in REGNO whose "natural" mode is MODE.  However,
   this may not agree with the mode that the type system has chosen for the
   register, which is ORIG_MODE.  If ORIG_MODE is not BLKmode, then we can
   go ahead and use it.  Otherwise we have to build a PARALLEL instead.  */

static rtx
gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode,
         unsigned int regno)
{
  rtx tmp;

  if (orig_mode != BLKmode)
    tmp = gen_rtx_REG (orig_mode, regno);
  else
    {
      tmp = gen_rtx_REG (mode, regno);
      tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx);
      tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp));
    }

  return tmp;
}

/* x86-64 register passing implementation.  See x86-64 ABI for details.  Goal
   of this code is to classify each 8bytes of incoming argument by the register
   class and assign registers accordingly.  */

/* Return the union class of CLASS1 and CLASS2.
   See the x86-64 PS ABI for details.  */

static enum x86_64_reg_class
merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
{
  /* Rule #1: If both classes are equal, this is the resulting class.  */
  if (class1 == class2)
    return class1;

  /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
     the other class.  */
  if (class1 == X86_64_NO_CLASS)
    return class2;
  if (class2 == X86_64_NO_CLASS)
    return class1;

  /* Rule #3: If one of the classes is MEMORY, the result is MEMORY.  */
  if (class1 == X86_64_MEMORY_CLASS || class2 == X86_64_MEMORY_CLASS)
    return X86_64_MEMORY_CLASS;

  /* Rule #4: If one of the classes is INTEGER, the result is INTEGER.  */
  if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
      || (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
    return X86_64_INTEGERSI_CLASS;
  if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
      || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
    return X86_64_INTEGER_CLASS;

  /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
     MEMORY is used.  */
  if (class1 == X86_64_X87_CLASS
      || class1 == X86_64_X87UP_CLASS
      || class1 == X86_64_COMPLEX_X87_CLASS
      || class2 == X86_64_X87_CLASS
      || class2 == X86_64_X87UP_CLASS
      || class2 == X86_64_COMPLEX_X87_CLASS)
    return X86_64_MEMORY_CLASS;

  /* Rule #6: Otherwise class SSE is used.  */
  return X86_64_SSE_CLASS;
}

/* Classify the argument of type TYPE and mode MODE.
   CLASSES will be filled by the register class used to pass each word
   of the operand.  The number of words is returned.  In case the parameter
   should be passed in memory, 0 is returned. As a special case for zero
   sized containers, classes[0] will be NO_CLASS and 1 is returned.

   BIT_OFFSET is used internally for handling records and specifies offset
   of the offset in bits modulo 256 to avoid overflow cases.

   See the x86-64 PS ABI for details.
*/

static int
classify_argument (enum machine_mode mode, tree type,
       enum x86_64_reg_class classes[MAX_CLASSES], int bit_offset)
{
  HOST_WIDE_INT bytes =
    (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
  int words = (bytes + (bit_offset % 64) / 8 + UNITS_PER_WORD - 1) / UNITS_PER_WORD;

  /* Variable sized entities are always passed/returned in memory.  */
  if (bytes < 0)
    return 0;

  if (mode != VOIDmode
      && targetm.calls.must_pass_in_stack (mode, type))
    return 0;

  if (type && AGGREGATE_TYPE_P (type))
    {
      int i;
      tree field;
      enum x86_64_reg_class subclasses[MAX_CLASSES];

      /* On x86-64 we pass structures larger than 16 bytes on the stack.  */
      if (bytes > 16)
  return 0;

      for (i = 0; i < words; i++)
  classes[i] = X86_64_NO_CLASS;

      /* Zero sized arrays or structures are NO_CLASS.  We return 0 to
   signalize memory class, so handle it as special case.  */
      if (!words)
  {
    classes[0] = X86_64_NO_CLASS;
    return 1;
  }

      /* Classify each field of record and merge classes.  */
      if (TREE_CODE (type) == RECORD_TYPE)
  {
    /* For classes first merge in the field of the subclasses.  */
    if (TYPE_BINFO (type))
      {
        tree binfo, base_binfo;
        int basenum;

        for (binfo = TYPE_BINFO (type), basenum = 0;
       BINFO_BASE_ITERATE (binfo, basenum, base_binfo); basenum++)
    {
       int num;
       int offset = tree_low_cst (BINFO_OFFSET (base_binfo), 0) * 8;
       tree type = BINFO_TYPE (base_binfo);

       num = classify_argument (TYPE_MODE (type),
              type, subclasses,
              (offset + bit_offset) % 256);
       if (!num)
         return 0;
       for (i = 0; i < num; i++)
         {
           int pos = (offset + (bit_offset % 64)) / 8 / 8;
           classes[i + pos] =
       merge_classes (subclasses[i], classes[i + pos]);
         }
    }
      }
    /* And now merge the fields of structure.  */
    for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
      {
        if (TREE_CODE (field) == FIELD_DECL)
    {
      int num;

      /* Bitfields are always classified as integer.  Handle them
         early, since later code would consider them to be
         misaligned integers.  */
      if (DECL_BIT_FIELD (field))
        {
          for (i = int_bit_position (field) / 8 / 8;
         i < (int_bit_position (field)
              + tree_low_cst (DECL_SIZE (field), 0)
        + 63) / 8 / 8; i++)
      classes[i] =
        merge_classes (X86_64_INTEGER_CLASS,
           classes[i]);
        }
      else
        {
          num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
                 TREE_TYPE (field), subclasses,
                 (int_bit_position (field)
            + bit_offset) % 256);
          if (!num)
      return 0;
          for (i = 0; i < num; i++)
      {
        int pos =
          (int_bit_position (field) + (bit_offset % 64)) / 8 / 8;
        classes[i + pos] =
          merge_classes (subclasses[i], classes[i + pos]);
      }
        }
    }
      }
  }
      /* Arrays are handled as small records.  */
      else if (TREE_CODE (type) == ARRAY_TYPE)
  {
    int num;
    num = classify_argument (TYPE_MODE (TREE_TYPE (type)),
           TREE_TYPE (type), subclasses, bit_offset);
    if (!num)
      return 0;

    /* The partial classes are now full classes.  */
    if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
      subclasses[0] = X86_64_SSE_CLASS;
    if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4)
      subclasses[0] = X86_64_INTEGER_CLASS;

    for (i = 0; i < words; i++)
      classes[i] = subclasses[i % num];
  }
      /* Unions are similar to RECORD_TYPE but offset is always 0.  */
      else if (TREE_CODE (type) == UNION_TYPE
         || TREE_CODE (type) == QUAL_UNION_TYPE)
  {
    /* For classes first merge in the field of the subclasses.  */
    if (TYPE_BINFO (type))
      {
        tree binfo, base_binfo;
        int basenum;

        for (binfo = TYPE_BINFO (type), basenum = 0;
       BINFO_BASE_ITERATE (binfo, basenum, base_binfo); basenum++)
    {
       int num;
       int offset = tree_low_cst (BINFO_OFFSET (base_binfo), 0) * 8;
       tree type = BINFO_TYPE (base_binfo);

       num = classify_argument (TYPE_MODE (type),
              type, subclasses,
              (offset + (bit_offset % 64)) % 256);
       if (!num)
         return 0;
       for (i = 0; i < num; i++)
         {
           int pos = (offset + (bit_offset % 64)) / 8 / 8;
           classes[i + pos] =
       merge_classes (subclasses[i], classes[i + pos]);
         }
    }
      }
    for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
      {
        if (TREE_CODE (field) == FIELD_DECL)
    {
      int num;
      num = classify_argument (TYPE_MODE (TREE_TYPE (field)),
             TREE_TYPE (field), subclasses,
             bit_offset);
      if (!num)
        return 0;
      for (i = 0; i < num; i++)
        classes[i] = merge_classes (subclasses[i], classes[i]);
    }
      }
  }
      else
  abort ();

      /* Final merger cleanup.  */
      for (i = 0; i < words; i++)
  {
    /* If one class is MEMORY, everything should be passed in
       memory.  */
    if (classes[i] == X86_64_MEMORY_CLASS)
      return 0;

    /* The X86_64_SSEUP_CLASS should be always preceded by
       X86_64_SSE_CLASS.  */
    if (classes[i] == X86_64_SSEUP_CLASS
        && (i == 0 || classes[i - 1] != X86_64_SSE_CLASS))
      classes[i] = X86_64_SSE_CLASS;

    /*  X86_64_X87UP_CLASS should be preceded by X86_64_X87_CLASS.  */
    if (classes[i] == X86_64_X87UP_CLASS
        && (i == 0 || classes[i - 1] != X86_64_X87_CLASS))
      classes[i] = X86_64_SSE_CLASS;
  }
      return words;
    }

  /* Compute alignment needed.  We align all types to natural boundaries with
     exception of XFmode that is aligned to 64bits.  */
  if (mode != VOIDmode && mode != BLKmode)
    {
      int mode_alignment = GET_MODE_BITSIZE (mode);

      if (mode == XFmode)
  mode_alignment = 128;
      else if (mode == XCmode)
  mode_alignment = 256;
      if (COMPLEX_MODE_P (mode))
  mode_alignment /= 2;
      /* Misaligned fields are always returned in memory.  */
      if (bit_offset % mode_alignment)
  return 0;
    }

  /* for V1xx modes, just use the base mode */
  if (VECTOR_MODE_P (mode)
      && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes)
    mode = GET_MODE_INNER (mode);

  /* Classification of atomic types.  */
  switch (mode)
    {
    case DImode:
    case SImode:
    case HImode:
    case QImode:
    case CSImode:
    case CHImode:
    case CQImode:
      if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
  classes[0] = X86_64_INTEGERSI_CLASS;
      else
  classes[0] = X86_64_INTEGER_CLASS;
      return 1;
    case CDImode:
    case TImode:
      classes[0] = classes[1] = X86_64_INTEGER_CLASS;
      return 2;
    case CTImode:
      return 0;
    case SFmode:
      if (!(bit_offset % 64))
  classes[0] = X86_64_SSESF_CLASS;
      else
  classes[0] = X86_64_SSE_CLASS;
      return 1;
    case DFmode:
      classes[0] = X86_64_SSEDF_CLASS;
      return 1;
    case XFmode:
      classes[0] = X86_64_X87_CLASS;
      classes[1] = X86_64_X87UP_CLASS;
      return 2;
    case TFmode:
      classes[0] = X86_64_SSE_CLASS;
      classes[1] = X86_64_SSEUP_CLASS;
      return 2;
    case SCmode:
      classes[0] = X86_64_SSE_CLASS;
      return 1;
    case DCmode:
      classes[0] = X86_64_SSEDF_CLASS;
      classes[1] = X86_64_SSEDF_CLASS;
      return 2;
    case XCmode:
      classes[0] = X86_64_COMPLEX_X87_CLASS;
      return 1;
    case TCmode:
      /* This modes is larger than 16 bytes.  */
      return 0;
    case V4SFmode:
    case V4SImode:
    case V16QImode:
    case V8HImode:
    case V2DFmode:
    case V2DImode:
      classes[0] = X86_64_SSE_CLASS;
      classes[1] = X86_64_SSEUP_CLASS;
      return 2;
    case V2SFmode:
    case V2SImode:
    case V4HImode:
    case V8QImode:
      classes[0] = X86_64_SSE_CLASS;
      return 1;
    case BLKmode:
    case VOIDmode:
      return 0;
    default:
      if (VECTOR_MODE_P (mode))
  {
    if (bytes > 16)
      return 0;
    if (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT)
      {
        if (bit_offset + GET_MODE_BITSIZE (mode) <= 32)
    classes[0] = X86_64_INTEGERSI_CLASS;
        else
    classes[0] = X86_64_INTEGER_CLASS;
        classes[1] = X86_64_INTEGER_CLASS;
        return 1 + (bytes > 8);
      }
  }
      abort ();
    }
}

/* Examine the argument and return set number of register required in each
   class.  Return 0 iff parameter should be passed in memory.  */
static int
examine_argument (enum machine_mode mode, tree type, int in_return,
      int *int_nregs, int *sse_nregs)
{
  enum x86_64_reg_class class[MAX_CLASSES];
  int n = classify_argument (mode, type, class, 0);

  *int_nregs = 0;
  *sse_nregs = 0;
  if (!n)
    return 0;
  for (n--; n >= 0; n--)
    switch (class[n])
      {
      case X86_64_INTEGER_CLASS:
      case X86_64_INTEGERSI_CLASS:
  (*int_nregs)++;
  break;
      case X86_64_SSE_CLASS:
      case X86_64_SSESF_CLASS:
      case X86_64_SSEDF_CLASS:
  (*sse_nregs)++;
  break;
      case X86_64_NO_CLASS:
      case X86_64_SSEUP_CLASS:
  break;
      case X86_64_X87_CLASS:
      case X86_64_X87UP_CLASS:
  if (!in_return)
    return 0;
  break;
      case X86_64_COMPLEX_X87_CLASS:
  return in_return ? 2 : 0;
      case X86_64_MEMORY_CLASS:
  abort ();
      }
  return 1;
}

/* Construct container for the argument used by GCC interface.  See
   FUNCTION_ARG for the detailed description.  */

static rtx
construct_container (enum machine_mode mode, enum machine_mode orig_mode,
         tree type, int in_return, int nintregs, int nsseregs,
         const int *intreg, int sse_regno)
{
  enum machine_mode tmpmode;
  int bytes =
    (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
  enum x86_64_reg_class class[MAX_CLASSES];
  int n;
  int i;
  int nexps = 0;
  int needed_sseregs, needed_intregs;
  rtx exp[MAX_CLASSES];
  rtx ret;

  n = classify_argument (mode, type, class, 0);
  if (TARGET_DEBUG_ARG)
    {
      if (!n)
  fprintf (stderr, "Memory class\n");
      else
  {
    fprintf (stderr, "Classes:");
    for (i = 0; i < n; i++)
      {
        fprintf (stderr, " %s", x86_64_reg_class_name[class[i]]);
      }
     fprintf (stderr, "\n");
  }
    }
  if (!n)
    return NULL;
  if (!examine_argument (mode, type, in_return, &needed_intregs,
       &needed_sseregs))
    return NULL;
  if (needed_intregs > nintregs || needed_sseregs > nsseregs)
    return NULL;

  /* We allowed the user to turn off SSE for kernel mode.  Don't crash if
     some less clueful developer tries to use floating-point anyway.  */
  if (needed_sseregs && !TARGET_SSE)
    {
      static bool issued_error;
      if (!issued_error)
  {
    issued_error = true;
    if (in_return)
      error ("SSE register return with SSE disabled");
    else
      error ("SSE register argument with SSE disabled");
  }
      return NULL;
    }

  /* First construct simple cases.  Avoid SCmode, since we want to use
     single register to pass this type.  */
  if (n == 1 && mode != SCmode)
    switch (class[0])
      {
      case X86_64_INTEGER_CLASS:
      case X86_64_INTEGERSI_CLASS:
  return gen_rtx_REG (mode, intreg[0]);
      case X86_64_SSE_CLASS:
      case X86_64_SSESF_CLASS:
      case X86_64_SSEDF_CLASS:
  return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno));
      case X86_64_X87_CLASS:
      case X86_64_COMPLEX_X87_CLASS:
  return gen_rtx_REG (mode, FIRST_STACK_REG);
      case X86_64_NO_CLASS:
  /* Zero sized array, struct or class.  */
  return NULL;
      default:
  abort ();
      }
  if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS
      && mode != BLKmode)
    return gen_rtx_REG (mode, SSE_REGNO (sse_regno));
  if (n == 2
      && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS)
    return gen_rtx_REG (XFmode, FIRST_STACK_REG);
  if (n == 2 && class[0] == X86_64_INTEGER_CLASS
      && class[1] == X86_64_INTEGER_CLASS
      && (mode == CDImode || mode == TImode || mode == TFmode)
      && intreg[0] + 1 == intreg[1])
    return gen_rtx_REG (mode, intreg[0]);

  /* Otherwise figure out the entries of the PARALLEL.  */
  for (i = 0; i < n; i++)
    {
      switch (class[i])
        {
    case X86_64_NO_CLASS:
      break;
    case X86_64_INTEGER_CLASS:
    case X86_64_INTEGERSI_CLASS:
      /* Merge TImodes on aligned occasions here too.  */
      if (i * 8 + 8 > bytes)
        tmpmode = mode_for_size ((bytes - i * 8) * BITS_PER_UNIT, MODE_INT, 0);
      else if (class[i] == X86_64_INTEGERSI_CLASS)
        tmpmode = SImode;
      else
        tmpmode = DImode;
      /* We've requested 24 bytes we don't have mode for.  Use DImode.  */
      if (tmpmode == BLKmode)
        tmpmode = DImode;
      exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
                 gen_rtx_REG (tmpmode, *intreg),
                 GEN_INT (i*8));
      intreg++;
      break;
    case X86_64_SSESF_CLASS:
      exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
                 gen_rtx_REG (SFmode,
                  SSE_REGNO (sse_regno)),
                 GEN_INT (i*8));
      sse_regno++;
      break;
    case X86_64_SSEDF_CLASS:
      exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
                 gen_rtx_REG (DFmode,
                  SSE_REGNO (sse_regno)),
                 GEN_INT (i*8));
      sse_regno++;
      break;
    case X86_64_SSE_CLASS:
      if (i < n - 1 && class[i + 1] == X86_64_SSEUP_CLASS)
        tmpmode = TImode;
      else
        tmpmode = DImode;
      exp [nexps++] = gen_rtx_EXPR_LIST (VOIDmode,
                 gen_rtx_REG (tmpmode,
                  SSE_REGNO (sse_regno)),
                 GEN_INT (i*8));
      if (tmpmode == TImode)
        i++;
      sse_regno++;
      break;
    default:
      abort ();
  }
    }

  /* Empty aligned struct, union or class.  */
  if (nexps == 0)
    return NULL;

  ret =  gen_rtx_PARALLEL (mode, rtvec_alloc (nexps));
  for (i = 0; i < nexps; i++)
    XVECEXP (ret, 0, i) = exp [i];
  return ret;
}

/* Update the data in CUM to advance over an argument
   of mode MODE and data type TYPE.
   (TYPE is null for libcalls where that information may not be available.)  */

void
function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
          tree type, int named)
{
  int bytes =
    (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
  int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;

  if (type)
    mode = type_natural_mode (type);

  if (TARGET_DEBUG_ARG)
    fprintf (stderr, "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, "
       "mode=%s, named=%d)\n\n",
       words, cum->words, cum->nregs, cum->sse_nregs,
       GET_MODE_NAME (mode), named);

  if (TARGET_64BIT)
    {
      int int_nregs, sse_nregs;
      if (!examine_argument (mode, type, 0, &int_nregs, &sse_nregs))
  cum->words += words;
      else if (sse_nregs <= cum->sse_nregs && int_nregs <= cum->nregs)
  {
    cum->nregs -= int_nregs;
    cum->sse_nregs -= sse_nregs;
    cum->regno += int_nregs;
    cum->sse_regno += sse_nregs;
  }
      else
  cum->words += words;
    }
  else
    {
      switch (mode)
  {
  default:
    break;

  case BLKmode:
    if (bytes < 0)
      break;
    /* FALLTHRU */

  case DImode:
  case SImode:
  case HImode:
  case QImode:
    cum->words += words;
    cum->nregs -= words;
    cum->regno += words;

    if (cum->nregs <= 0)
      {
        cum->nregs = 0;
        cum->regno = 0;
      }
    break;

  case TImode:
  case V16QImode:
  case V8HImode:
  case V4SImode:
  case V2DImode:
  case V4SFmode:
  case V2DFmode:
    if (!type || !AGGREGATE_TYPE_P (type))
      {
        cum->sse_words += words;
        cum->sse_nregs -= 1;
        cum->sse_regno += 1;
        if (cum->sse_nregs <= 0)
    {
      cum->sse_nregs = 0;
      cum->sse_regno = 0;
    }
      }
    break;

  case V8QImode:
  case V4HImode:
  case V2SImode:
  case V2SFmode:
    if (!type || !AGGREGATE_TYPE_P (type))
      {
        cum->mmx_words += words;
        cum->mmx_nregs -= 1;
        cum->mmx_regno += 1;
        if (cum->mmx_nregs <= 0)
    {
      cum->mmx_nregs = 0;
      cum->mmx_regno = 0;
    }
      }
    break;
  }
    }
}

/* Define where to put the arguments to a function.
   Value is zero to push the argument on the stack,
   or a hard register in which to store the argument.

   MODE is the argument's machine mode.
   TYPE is the data type of the argument (as a tree).
    This is null for libcalls where that information may
    not be available.
   CUM is a variable of type CUMULATIVE_ARGS which gives info about
    the preceding args and about the function being called.
   NAMED is nonzero if this argument is a named parameter
    (otherwise it is an extra parameter matching an ellipsis).  */

rtx
function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode,
        tree type, int named)
{
  enum machine_mode mode = orig_mode;
  rtx ret = NULL_RTX;
  int bytes =
    (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode);
  int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
  static bool warnedsse, warnedmmx;

  /* To simplify the code below, represent vector types with a vector mode
     even if MMX/SSE are not active.  */
  if (type && TREE_CODE (type) == VECTOR_TYPE)
    mode = type_natural_mode (type);

  /* Handle a hidden AL argument containing number of registers for varargs
     x86-64 functions.  For i386 ABI just return constm1_rtx to avoid
     any AL settings.  */
  if (mode == VOIDmode)
    {
      if (TARGET_64BIT)
  return GEN_INT (cum->maybe_vaarg
      ? (cum->sse_nregs < 0
         ? SSE_REGPARM_MAX
         : cum->sse_regno)
      : -1);
      else
  return constm1_rtx;
    }
  if (TARGET_64BIT)
    ret = construct_container (mode, orig_mode, type, 0, cum->nregs,
             cum->sse_nregs,
             &x86_64_int_parameter_registers [cum->regno],
             cum->sse_regno);
  else
    switch (mode)
      {
  /* For now, pass fp/complex values on the stack.  */
      default:
  break;

      case BLKmode:
  if (bytes < 0)
    break;
  /* FALLTHRU */
      case DImode:
      case SImode:
      case HImode:
      case QImode:
  if (words <= cum->nregs)
    {
      int regno = cum->regno;

      /* Fastcall allocates the first two DWORD (SImode) or
         smaller arguments to ECX and EDX.  */
      if (cum->fastcall)
        {
          if (mode == BLKmode || mode == DImode)
            break;

          /* ECX not EAX is the first allocated register.  */
          if (regno == 0)
      regno = 2;
        }
      ret = gen_rtx_REG (mode, regno);
    }
  break;
      case TImode:
      case V16QImode:
      case V8HImode:
      case V4SImode:
      case V2DImode:
      case V4SFmode:
      case V2DFmode:
  if (!type || !AGGREGATE_TYPE_P (type))
    {
      if (!TARGET_SSE && !warnedsse && cum->warn_sse)
        {
    warnedsse = true;
    warning ("SSE vector argument without SSE enabled "
       "changes the ABI");
        }
      if (cum->sse_nregs)
        ret = gen_reg_or_parallel (mode, orig_mode,
           cum->sse_regno + FIRST_SSE_REG);
    }
  break;
      case V8QImode:
      case V4HImode:
      case V2SImode:
      case V2SFmode:
  if (!type || !AGGREGATE_TYPE_P (type))
    {
      if (!TARGET_MMX && !warnedmmx && cum->warn_mmx)
        {
    warnedmmx = true;
    warning ("MMX vector argument without MMX enabled "
       "changes the ABI");
        }
      if (cum->mmx_nregs)
        ret = gen_reg_or_parallel (mode, orig_mode,
           cum->mmx_regno + FIRST_MMX_REG);
    }
  break;
      }

  if (TARGET_DEBUG_ARG)
    {
      fprintf (stderr,
         "function_arg (size=%d, wds=%2d, nregs=%d, mode=%4s, named=%d, ",
         words, cum->words, cum->nregs, GET_MODE_NAME (mode), named);

      if (ret)
  print_simple_rtl (stderr, ret);
      else
  fprintf (stderr, ", stack");

      fprintf (stderr, " )\n");
    }

  return ret;
}

/* A C expression that indicates when an argument must be passed by
   reference.  If nonzero for an argument, a copy of that argument is
   made in memory and a pointer to the argument is passed instead of
   the argument itself.  The pointer is passed in whatever way is
   appropriate for passing a pointer to that type.  */

static bool
ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
      enum machine_mode mode ATTRIBUTE_UNUSED,
      tree type, bool named ATTRIBUTE_UNUSED)
{
  if (!TARGET_64BIT)
    return 0;

  if (type && int_size_in_bytes (type) == -1)
    {
      if (TARGET_DEBUG_ARG)
  fprintf (stderr, "function_arg_pass_by_reference\n");
      return 1;
    }

  return 0;
}

/* Return true when TYPE should be 128bit aligned for 32bit argument passing
   ABI.  Only called if TARGET_SSE.  */
static bool
contains_128bit_aligned_vector_p (tree type)
{
  enum machine_mode mode = TYPE_MODE (type);
  if (SSE_REG_MODE_P (mode)
      && (!TYPE_USER_ALIGN (type) || TYPE_ALIGN (type) > 128))
    return true;
  if (TYPE_ALIGN (type) < 128)
    return false;

  if (AGGREGATE_TYPE_P (type))
    {
      /* Walk the aggregates recursively.  */
      if (TREE_CODE (type) == RECORD_TYPE
    || TREE_CODE (type) == UNION_TYPE
    || TREE_CODE (type) == QUAL_UNION_TYPE)
  {
    tree field;

    if (TYPE_BINFO (type))
      {
        tree binfo, base_binfo;
        int i;

        for (binfo = TYPE_BINFO (type), i = 0;
       BINFO_BASE_ITERATE (binfo, i, base_binfo); i++)
    if (contains_128bit_aligned_vector_p (BINFO_TYPE (base_binfo)))
      return true;
      }
    /* And now merge the fields of structure.  */
    for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
      {
        if (TREE_CODE (field) == FIELD_DECL
      && contains_128bit_aligned_vector_p (TREE_TYPE (field)))
    return true;
      }
  }
      /* Just for use if some languages passes arrays by value.  */
      else if (TREE_CODE (type) == ARRAY_TYPE)
  {
    if (contains_128bit_aligned_vector_p (TREE_TYPE (type)))
      return true;
  }
      else
  abort ();
    }
  return false;
}

/* Gives the alignment boundary, in bits, of an argument with the
   specified mode and type.  */

int
ix86_function_arg_boundary (enum machine_mode mode, tree type)
{
  int align;
  if (type)
    align = TYPE_ALIGN (type);
  else
    align = GET_MODE_ALIGNMENT (mode);
  if (align < PARM_BOUNDARY)
    align = PARM_BOUNDARY;
  if (!TARGET_64BIT)
    {
      /* i386 ABI defines all arguments to be 4 byte aligned.  We have to
   make an exception for SSE modes since these require 128bit
   alignment.

   The handling here differs from field_alignment.  ICC aligns MMX
   arguments to 4 byte boundaries, while structure fields are aligned
   to 8 byte boundaries.  */
      if (!TARGET_SSE)
  align = PARM_BOUNDARY;
      else if (!type)
  {
    if (!SSE_REG_MODE_P (mode))
      align = PARM_BOUNDARY;
  }
      else
  {
    if (!contains_128bit_aligned_vector_p (type))
      align = PARM_BOUNDARY;
  }
    }
  if (align > 128)
    align = 128;
  return align;
}

/* Return true if N is a possible register number of function value.  */
bool
ix86_function_value_regno_p (int regno)
{
  if (!TARGET_64BIT)
    {
      return ((regno) == 0
        || ((regno) == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)
        || ((regno) == FIRST_SSE_REG && TARGET_SSE));
    }
  return ((regno) == 0 || (regno) == FIRST_FLOAT_REG
    || ((regno) == FIRST_SSE_REG && TARGET_SSE)
    || ((regno) == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387));
}

/* Define how to find the value returned by a function.
   VALTYPE is the data type of the value (as a tree).
   If the precise function being called is known, FUNC is its FUNCTION_DECL;
   otherwise, FUNC is 0.  */
rtx
ix86_function_value (tree valtype)
{
  enum machine_mode natmode = type_natural_mode (valtype);

  if (TARGET_64BIT)
    {
      rtx ret = construct_container (natmode, TYPE_MODE (valtype), valtype,
             1, REGPARM_MAX, SSE_REGPARM_MAX,
             x86_64_int_return_registers, 0);
      /* For zero sized structures, construct_container return NULL, but we
   need to keep rest of compiler happy by returning meaningful value.  */
      if (!ret)
  ret = gen_rtx_REG (TYPE_MODE (valtype), 0);
      return ret;
    }
  else
    return gen_rtx_REG (TYPE_MODE (valtype), ix86_value_regno (natmode));
}

/* Return false iff type is returned in memory.  */
int
ix86_return_in_memory (tree type)
{
  int needed_intregs, needed_sseregs, size;
  enum machine_mode mode = type_natural_mode (type);

  if (TARGET_64BIT)
    return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);

  if (mode == BLKmode)
    return 1;

  size = int_size_in_bytes (type);

  if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
    return 0;

  if (VECTOR_MODE_P (mode) || mode == TImode)
    {
      /* User-created vectors small enough to fit in EAX.  */
      if (size < 8)
  return 0;

      /* MMX/3dNow values are returned on the stack, since we've
   got to EMMS/FEMMS before returning.  */
      if (size == 8)
  return 1;

      /* SSE values are returned in XMM0, except when it doesn't exist.  */
      if (size == 16)
  return (TARGET_SSE ? 0 : 1);
    }

  if (mode == XFmode)
    return 0;

  if (size > 12)
    return 1;
  return 0;
}

/* When returning SSE vector types, we have a choice of either
     (1) being abi incompatible with a -march switch, or
     (2) generating an error.
   Given no good solution, I think the safest thing is one warning.
   The user won't be able to use -Werror, but....

   Choose the STRUCT_VALUE_RTX hook because that's (at present) only
   called in response to actually generating a caller or callee that
   uses such a type.  As opposed to RETURN_IN_MEMORY, which is called
   via aggregate_value_p for general type probing from tree-ssa.  */

static rtx
ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED)
{
  static bool warned;

  if (!TARGET_SSE && type && !warned)
    {
      /* Look at the return type of the function, not the function type.  */
      enum machine_mode mode = TYPE_MODE (TREE_TYPE (type));

      if (mode == TImode
    || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
  {
    warned = true;
    warning ("SSE vector return without SSE enabled changes the ABI");
  }
    }

  return NULL;
}

/* Define how to find the value returned by a library function
   assuming the value has mode MODE.  */
rtx
ix86_libcall_value (enum machine_mode mode)
{
  if (TARGET_64BIT)
    {
      switch (mode)
  {
  case SFmode:
  case SCmode:
  case DFmode:
  case DCmode:
  case TFmode:
    return gen_rtx_REG (mode, FIRST_SSE_REG);
  case XFmode:
  case XCmode:
    return gen_rtx_REG (mode, FIRST_FLOAT_REG);
  case TCmode:
    return NULL;
  default:
    return gen_rtx_REG (mode, 0);
  }
    }
  else
    return gen_rtx_REG (mode, ix86_value_regno (mode));
}

/* Given a mode, return the register to use for a return value.  */

static int
ix86_value_regno (enum machine_mode mode)
{
  /* Floating point return values in %st(0).  */
  if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_FLOAT_RETURNS_IN_80387)
    return FIRST_FLOAT_REG;
  /* 16-byte vector modes in %xmm0.  See ix86_return_in_memory for where
     we prevent this case when sse is not available.  */
  if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
    return FIRST_SSE_REG;
  /* Everything else in %eax.  */
  return 0;
}

/* Create the va_list data type.  */

static tree
ix86_build_builtin_va_list (void)
{
  tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;

  /* For i386 we use plain pointer to argument area.  */
  if (!TARGET_64BIT)
    return build_pointer_type (char_type_node);

  record = (*lang_hooks.types.make_type) (RECORD_TYPE);
  type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);

  f_gpr = build_decl (FIELD_DECL, get_identifier ("gp_offset"),
          unsigned_type_node);
  f_fpr = build_decl (FIELD_DECL, get_identifier ("fp_offset"),
          unsigned_type_node);
  f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
          ptr_type_node);
  f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
          ptr_type_node);

  DECL_FIELD_CONTEXT (f_gpr) = record;
  DECL_FIELD_CONTEXT (f_fpr) = record;
  DECL_FIELD_CONTEXT (f_ovf) = record;
  DECL_FIELD_CONTEXT (f_sav) = record;

  TREE_CHAIN (record) = type_decl;
  TYPE_NAME (record) = type_decl;
  TYPE_FIELDS (record) = f_gpr;
  TREE_CHAIN (f_gpr) = f_fpr;
  TREE_CHAIN (f_fpr) = f_ovf;
  TREE_CHAIN (f_ovf) = f_sav;

  layout_type (record);

  /* The correct type is an array type of one element.  */
  return build_array_type (record, build_index_type (size_zero_node));
}

/* Worker function for TARGET_SETUP_INCOMING_VARARGS.  */

static void
ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
           tree type, int *pretend_size ATTRIBUTE_UNUSED,
           int no_rtl)
{
  CUMULATIVE_ARGS next_cum;
  rtx save_area = NULL_RTX, mem;
  rtx label;
  rtx label_ref;
  rtx tmp_reg;
  rtx nsse_reg;
  int set;
  tree fntype;
  int stdarg_p;
  int i;

  if (!TARGET_64BIT)
    return;

  /* Indicate to allocate space on the stack for varargs save area.  */
  ix86_save_varrargs_registers = 1;

  cfun->stack_alignment_needed = 128;

  fntype = TREE_TYPE (current_function_decl);
  stdarg_p = (TYPE_ARG_TYPES (fntype) != 0
        && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
      != void_type_node));

  /* For varargs, we do not want to skip the dummy va_dcl argument.
     For stdargs, we do want to skip the last named argument.  */
  next_cum = *cum;
  if (stdarg_p)
    function_arg_advance (&next_cum, mode, type, 1);

  if (!no_rtl)
    save_area = frame_pointer_rtx;

  set = get_varargs_alias_set ();

  for (i = next_cum.regno; i < ix86_regparm; i++)
    {
      mem = gen_rtx_MEM (Pmode,
       plus_constant (save_area, i * UNITS_PER_WORD));
      set_mem_alias_set (mem, set);
      emit_move_insn (mem, gen_rtx_REG (Pmode,
          x86_64_int_parameter_registers[i]));
    }

  if (next_cum.sse_nregs)
    {
      /* Now emit code to save SSE registers.  The AX parameter contains number
   of SSE parameter registers used to call this function.  We use
   sse_prologue_save insn template that produces computed jump across
   SSE saves.  We need some preparation work to get this working.  */

      label = gen_label_rtx ();
      label_ref = gen_rtx_LABEL_REF (Pmode, label);

      /* Compute address to jump to :
         label - 5*eax + nnamed_sse_arguments*5  */
      tmp_reg = gen_reg_rtx (Pmode);
      nsse_reg = gen_reg_rtx (Pmode);
      emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, 0)));
      emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
            gen_rtx_MULT (Pmode, nsse_reg,
              GEN_INT (4))));
      if (next_cum.sse_regno)
  emit_move_insn
    (nsse_reg,
     gen_rtx_CONST (DImode,
        gen_rtx_PLUS (DImode,
          label_ref,
          GEN_INT (next_cum.sse_regno * 4))));
      else
  emit_move_insn (nsse_reg, label_ref);
      emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));

      /* Compute address of memory block we save into.  We always use pointer
   pointing 127 bytes after first byte to store - this is needed to keep
   instruction size limited by 4 bytes.  */
      tmp_reg = gen_reg_rtx (Pmode);
      emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
            plus_constant (save_area,
               8 * REGPARM_MAX + 127)));
      mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127));
      set_mem_alias_set (mem, set);
      set_mem_align (mem, BITS_PER_WORD);

      /* And finally do the dirty job!  */
      emit_insn (gen_sse_prologue_save (mem, nsse_reg,
          GEN_INT (next_cum.sse_regno), label));
    }

}

/* Implement va_start.  */

void
ix86_va_start (tree valist, rtx nextarg)
{
  HOST_WIDE_INT words, n_gpr, n_fpr;
  tree f_gpr, f_fpr, f_ovf, f_sav;
  tree gpr, fpr, ovf, sav, t;

  /* Only 64bit target needs something special.  */
  if (!TARGET_64BIT)
    {
      std_expand_builtin_va_start (valist, nextarg);
      return;
    }

  f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
  f_fpr = TREE_CHAIN (f_gpr);
  f_ovf = TREE_CHAIN (f_fpr);
  f_sav = TREE_CHAIN (f_ovf);

  valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
  gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
  fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
  ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
  sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);

  /* Count number of gp and fp argument registers used.  */
  words = current_function_args_info.words;
  n_gpr = current_function_args_info.regno;
  n_fpr = current_function_args_info.sse_regno;

  if (TARGET_DEBUG_ARG)
    fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n",
       (int) words, (int) n_gpr, (int) n_fpr);

  t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
       build_int_cst (NULL_TREE, n_gpr * 8));
  TREE_SIDE_EFFECTS (t) = 1;
  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);

  t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
       build_int_cst (NULL_TREE, n_fpr * 16 + 8*REGPARM_MAX));
  TREE_SIDE_EFFECTS (t) = 1;
  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);

  /* Find the overflow area.  */
  t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
  if (words != 0)
    t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
         build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
  t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
  TREE_SIDE_EFFECTS (t) = 1;
  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);

  /* Find the register save area.
     Prologue of the function save it right above stack frame.  */
  t = make_tree (TREE_TYPE (sav), frame_pointer_rtx);
  t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
  TREE_SIDE_EFFECTS (t) = 1;
  expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
}

/* Implement va_arg.  */

tree
ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
{
  static const int intreg[6] = { 0, 1, 2, 3, 4, 5 };
  tree f_gpr, f_fpr, f_ovf, f_sav;
  tree gpr, fpr, ovf, sav, t;
  int size, rsize;
  tree lab_false, lab_over = NULL_TREE;
  tree addr, t2;
  rtx container;
  int indirect_p = 0;
  tree ptrtype;
  enum machine_mode nat_mode;

  /* Only 64bit target needs something special.  */
  if (!TARGET_64BIT)
    return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);

  f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
  f_fpr = TREE_CHAIN (f_gpr);
  f_ovf = TREE_CHAIN (f_fpr);
  f_sav = TREE_CHAIN (f_ovf);

  valist = build_va_arg_indirect_ref (valist);
  gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
  fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
  ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
  sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);

  indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false);
  if (indirect_p)
    type = build_pointer_type (type);
  size = int_size_in_bytes (type);
  rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;

  nat_mode = type_natural_mode (type);
  container = construct_container (nat_mode, TYPE_MODE (type), type, 0,
           REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0);

  /* Pull the value out of the saved registers.  */

  addr = create_tmp_var (ptr_type_node, "addr");
  DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();

  if (container)
    {
      int needed_intregs, needed_sseregs;
      bool need_temp;
      tree int_addr, sse_addr;

      lab_false = create_artificial_label ();
      lab_over = create_artificial_label ();

      examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs);

      need_temp = (!REG_P (container)
       && ((needed_intregs && TYPE_ALIGN (type) > 64)
           || TYPE_ALIGN (type) > 128));

      /* In case we are passing structure, verify that it is consecutive block
         on the register save area.  If not we need to do moves.  */
      if (!need_temp && !REG_P (container))
  {
    /* Verify that all registers are strictly consecutive  */
    if (SSE_REGNO_P (REGNO (XEXP (XVECEXP (container, 0, 0), 0))))
      {
        int i;

        for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
    {
      rtx slot = XVECEXP (container, 0, i);
      if (REGNO (XEXP (slot, 0)) != FIRST_SSE_REG + (unsigned int) i
          || INTVAL (XEXP (slot, 1)) != i * 16)
        need_temp = 1;
    }
      }
    else
      {
        int i;

        for (i = 0; i < XVECLEN (container, 0) && !need_temp; i++)
    {
      rtx slot = XVECEXP (container, 0, i);
      if (REGNO (XEXP (slot, 0)) != (unsigned int) i
          || INTVAL (XEXP (slot, 1)) != i * 8)
        need_temp = 1;
    }
      }
  }
      if (!need_temp)
  {
    int_addr = addr;
    sse_addr = addr;
  }
      else
  {
    int_addr = create_tmp_var (ptr_type_node, "int_addr");
    DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set ();
    sse_addr = create_tmp_var (ptr_type_node, "sse_addr");
    DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set ();
  }

      /* First ensure that we fit completely in registers.  */
      if (needed_intregs)
  {
    t = build_int_cst (TREE_TYPE (gpr),
           (REGPARM_MAX - needed_intregs + 1) * 8);
    t = build2 (GE_EXPR, boolean_type_node, gpr, t);
    t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
    t = build (COND_EXPR, void_type_node, t, t2, NULL_TREE);
    gimplify_and_add (t, pre_p);
  }
      if (needed_sseregs)
  {
    t = build_int_cst (TREE_TYPE (fpr),
           (SSE_REGPARM_MAX - needed_sseregs + 1) * 16
           + REGPARM_MAX * 8);
    t = build2 (GE_EXPR, boolean_type_node, fpr, t);
    t2 = build1 (GOTO_EXPR, void_type_node, lab_false);
    t = build (COND_EXPR, void_type_node, t, t2, NULL_TREE);
    gimplify_and_add (t, pre_p);
  }

      /* Compute index to start of area used for integer regs.  */
      if (needed_intregs)
  {
    /* int_addr = gpr + sav; */
    t = fold_convert (ptr_type_node, gpr);
    t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
    t = build2 (MODIFY_EXPR, void_type_node, int_addr, t);
    gimplify_and_add (t, pre_p);
  }
      if (needed_sseregs)
  {
    /* sse_addr = fpr + sav; */
    t = fold_convert (ptr_type_node, fpr);
    t = build2 (PLUS_EXPR, ptr_type_node, sav, t);
    t = build2 (MODIFY_EXPR, void_type_node, sse_addr, t);
    gimplify_and_add (t, pre_p);
  }
      if (need_temp)
  {
    int i;
    tree temp = create_tmp_var (type, "va_arg_tmp");

    /* addr = &temp; */
    t = build1 (ADDR_EXPR, build_pointer_type (type), temp);
    t = build2 (MODIFY_EXPR, void_type_node, addr, t);
    gimplify_and_add (t, pre_p);

    for (i = 0; i < XVECLEN (container, 0); i++)
      {
        rtx slot = XVECEXP (container, 0, i);
        rtx reg = XEXP (slot, 0);
        enum machine_mode mode = GET_MODE (reg);
        tree piece_type = lang_hooks.types.type_for_mode (mode, 1);
        tree addr_type = build_pointer_type (piece_type);
        tree src_addr, src;
        int src_offset;
        tree dest_addr, dest;

        if (SSE_REGNO_P (REGNO (reg)))
    {
      src_addr = sse_addr;
      src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16;
    }
        else
    {
      src_addr = int_addr;
      src_offset = REGNO (reg) * 8;
    }
        src_addr = fold_convert (addr_type, src_addr);
        src_addr = fold (build2 (PLUS_EXPR, addr_type, src_addr,
               size_int (src_offset)));
        src = build_va_arg_indirect_ref (src_addr);

        dest_addr = fold_convert (addr_type, addr);
        dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr,
          size_int (INTVAL (XEXP (slot, 1)))));
        dest = build_va_arg_indirect_ref (dest_addr);

        t = build2 (MODIFY_EXPR, void_type_node, dest, src);
        gimplify_and_add (t, pre_p);
      }
  }

      if (needed_intregs)
  {
    t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr,
          build_int_cst (TREE_TYPE (gpr), needed_intregs * 8));
    t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t);
    gimplify_and_add (t, pre_p);
  }
      if (needed_sseregs)
  {
    t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr,
          build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16));
    t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t);
    gimplify_and_add (t, pre_p);
  }

      t = build1 (GOTO_EXPR, void_type_node, lab_over);
      gimplify_and_add (t, pre_p);

      t = build1 (LABEL_EXPR, void_type_node, lab_false);
      append_to_statement_list (t, pre_p);
    }

  /* ... otherwise out of the overflow area.  */

  /* Care for on-stack alignment if needed.  */
  if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64)
    t = ovf;
  else
    {
      HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8;
      t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf,
     build_int_cst (TREE_TYPE (ovf), align - 1));
      t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
     build_int_cst (TREE_TYPE (t), -align));
    }
  gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);

  t2 = build2 (MODIFY_EXPR, void_type_node, addr, t);
  gimplify_and_add (t2, pre_p);

  t = build2 (PLUS_EXPR, TREE_TYPE (t), t,
        build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD));
  t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
  gimplify_and_add (t, pre_p);

  if (container)
    {
      t = build1 (LABEL_EXPR, void_type_node, lab_over);
      append_to_statement_list (t, pre_p);
    }

  ptrtype = build_pointer_type (type);
  addr = fold_convert (ptrtype, addr);

  if (indirect_p)
    addr = build_va_arg_indirect_ref (addr);
  return build_va_arg_indirect_ref (addr);
}

/* Return nonzero if OPNUM's MEM should be matched
   in movabs* patterns.  */

int
ix86_check_movabs (rtx insn, int opnum)
{
  rtx set, mem;

  set = PATTERN (insn);
  if (GET_CODE (set) == PARALLEL)
    set = XVECEXP (set, 0, 0);
  if (GET_CODE (set) != SET)
    abort ();
  mem = XEXP (set, opnum);
  while (GET_CODE (mem) == SUBREG)
    mem = SUBREG_REG (mem);
  if (GET_CODE (mem) != MEM)
    abort ();
  return (volatile_ok || !MEM_VOLATILE_P (mem));
}

/* Initialize the table of extra 80387 mathematical constants.  */

static void
init_ext_80387_constants (void)
{
  static const char * cst[5] =
  {
    "0.3010299956639811952256464283594894482",  /* 0: fldlg2  */
    "0.6931471805599453094286904741849753009",  /* 1: fldln2  */
    "1.4426950408889634073876517827983434472",  /* 2: fldl2e  */
    "3.3219280948873623478083405569094566090",  /* 3: fldl2t  */
    "3.1415926535897932385128089594061862044",  /* 4: fldpi   */
  };
  int i;

  for (i = 0; i < 5; i++)
    {
      real_from_string (&ext_80387_constants_table[i], cst[i]);
      /* Ensure each constant is rounded to XFmode precision.  */
      real_convert (&ext_80387_constants_table[i],
        XFmode, &ext_80387_constants_table[i]);
    }

  ext_80387_constants_init = 1;
}

/* Return true if the constant is something that can be loaded with
   a special instruction.  */

int
standard_80387_constant_p (rtx x)
{
  if (GET_CODE (x) != CONST_DOUBLE || !FLOAT_MODE_P (GET_MODE (x)))
    return -1;

  if (x == CONST0_RTX (GET_MODE (x)))
    return 1;
  if (x == CONST1_RTX (GET_MODE (x)))
    return 2;

  /* For XFmode constants, try to find a special 80387 instruction when
     optimizing for size or on those CPUs that benefit from them.  */
  if (GET_MODE (x) == XFmode
      && (optimize_size || x86_ext_80387_constants & TUNEMASK))
    {
      REAL_VALUE_TYPE r;
      int i;

      if (! ext_80387_constants_init)
  init_ext_80387_constants ();

      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
      for (i = 0; i < 5; i++)
        if (real_identical (&r, &ext_80387_constants_table[i]))
    return i + 3;
    }

  return 0;
}

/* Return the opcode of the special instruction to be used to load
   the constant X.  */

const char *
standard_80387_constant_opcode (rtx x)
{
  switch (standard_80387_constant_p (x))
    {
    case 1:
      return "fldz";
    case 2:
      return "fld1";
    case 3:
      return "fldlg2";
    case 4:
      return "fldln2";
    case 5:
      return "fldl2e";
    case 6:
      return "fldl2t";
    case 7:
      return "fldpi";
    }
  abort ();
}

/* Return the CONST_DOUBLE representing the 80387 constant that is
   loaded by the specified special instruction.  The argument IDX
   matches the return value from standard_80387_constant_p.  */

rtx
standard_80387_constant_rtx (int idx)
{
  int i;

  if (! ext_80387_constants_init)
    init_ext_80387_constants ();

  switch (idx)
    {
    case 3:
    case 4:
    case 5:
    case 6:
    case 7:
      i = idx - 3;
      break;

    default:
      abort ();
    }

  return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i],
               XFmode);
}

/* Return 1 if X is FP constant we can load to SSE register w/o using memory.
 */
int
standard_sse_constant_p (rtx x)
{
  if (x == const0_rtx)
    return 1;
  return (x == CONST0_RTX (GET_MODE (x)));
}

/* Returns 1 if OP contains a symbol reference */

int
symbolic_reference_mentioned_p (rtx op)
{
  const char *fmt;
  int i;

  if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
    return 1;

  fmt = GET_RTX_FORMAT (GET_CODE (op));
  for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
    {
      if (fmt[i] == 'E')
  {
    int j;

    for (j = XVECLEN (op, i) - 1; j >= 0; j--)
      if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
        return 1;
  }

      else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
  return 1;
    }

  return 0;
}

/* Return 1 if it is appropriate to emit `ret' instructions in the
   body of a function.  Do this only if the epilogue is simple, needing a
   couple of insns.  Prior to reloading, we can't tell how many registers
   must be saved, so return 0 then.  Return 0 if there is no frame
   marker to de-allocate.  */

int
ix86_can_use_return_insn_p (void)
{
  struct ix86_frame frame;

  if (! reload_completed || frame_pointer_needed)
    return 0;

  /* Don't allow more than 32 pop, since that's all we can do
     with one instruction.  */
  if (current_function_pops_args
      && current_function_args_size >= 32768)
    return 0;

  ix86_compute_frame_layout (&frame);
  return frame.to_allocate == 0 && frame.nregs == 0;
}

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms may
   be accessed via the stack pointer) in functions that seem suitable.  */

int
ix86_frame_pointer_required (void)
{
  /* If we accessed previous frames, then the generated code expects
     to be able to access the saved ebp value in our frame.  */
  if (cfun->machine->accesses_prev_frame)
    return 1;

  /* Several x86 os'es need a frame pointer for other reasons,
     usually pertaining to setjmp.  */
  if (SUBTARGET_FRAME_POINTER_REQUIRED)
    return 1;

  /* In override_options, TARGET_OMIT_LEAF_FRAME_POINTER turns off
     the frame pointer by default.  Turn it back on now if we've not
     got a leaf function.  */
  if (TARGET_OMIT_LEAF_FRAME_POINTER
      && (!current_function_is_leaf))
    return 1;

  if (current_function_profile)
    return 1;

  return 0;
}

/* Record that the current function accesses previous call frames.  */

void
ix86_setup_frame_addresses (void)
{
  cfun->machine->accesses_prev_frame = 1;
}

#if defined(HAVE_GAS_HIDDEN) && defined(SUPPORTS_ONE_ONLY)
# define USE_HIDDEN_LINKONCE 1
#else
# define USE_HIDDEN_LINKONCE 0
#endif

static int pic_labels_used;

/* Fills in the label name that should be used for a pc thunk for
   the given register.  */

static void
get_pc_thunk_name (char name[32], unsigned int regno)
{
  if (USE_HIDDEN_LINKONCE)
    sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]);
  else
    ASM_GENERATE_INTERNAL_LABEL (name, "LPR", regno);
}


/* This function generates code for -fpic that loads %ebx with
   the return address of the caller and then returns.  */

void
ix86_file_end (void)
{
  rtx xops[2];
  int regno;

  for (regno = 0; regno < 8; ++regno)
    {
      char name[32];

      if (! ((pic_labels_used >> regno) & 1))
  continue;

      get_pc_thunk_name (name, regno);

      if (USE_HIDDEN_LINKONCE)
  {
    tree decl;

    decl = build_decl (FUNCTION_DECL, get_identifier (name),
           error_mark_node);
    TREE_PUBLIC (decl) = 1;
    TREE_STATIC (decl) = 1;
    DECL_ONE_ONLY (decl) = 1;

    (*targetm.asm_out.unique_section) (decl, 0);
    named_section (decl, NULL, 0);

    (*targetm.asm_out.globalize_label) (asm_out_file, name);
    fputs ("\t.hidden\t", asm_out_file);
    assemble_name (asm_out_file, name);
    fputc ('\n', asm_out_file);
    ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
  }
      else
  {
    text_section ();
    ASM_OUTPUT_LABEL (asm_out_file, name);
  }

      xops[0] = gen_rtx_REG (SImode, regno);
      xops[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
      output_asm_insn ("mov{l}\t{%1, %0|%0, %1}", xops);
      output_asm_insn ("ret", xops);
    }

  if (NEED_INDICATE_EXEC_STACK)
    file_end_indicate_exec_stack ();
}

/* Emit code for the SET_GOT patterns.  */

const char *
output_set_got (rtx dest)
{
  rtx xops[3];

  xops[0] = dest;
  xops[1] = gen_rtx_SYMBOL_REF (Pmode, GOT_SYMBOL_NAME);

  if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic)
    {
      xops[2] = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ());

      if (!flag_pic)
  output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops);
      else
  output_asm_insn ("call\t%a2", xops);

#if TARGET_MACHO
      /* Output the "canonical" label name ("Lxx$pb") here too.  This
         is what will be referred to by the Mach-O PIC subsystem.  */
      ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ());
#endif
      (*targetm.asm_out.internal_label) (asm_out_file, "L",
         CODE_LABEL_NUMBER (XEXP (xops[2], 0)));

      if (flag_pic)
  output_asm_insn ("pop{l}\t%0", xops);
    }
  else
    {
      char name[32];
      get_pc_thunk_name (name, REGNO (dest));
      pic_labels_used |= 1 << REGNO (dest);

      xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
      xops[2] = gen_rtx_MEM (QImode, xops[2]);
      output_asm_insn ("call\t%X2", xops);
    }

  if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION)
    output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops);
  else if (!TARGET_MACHO)
    output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops);

  return "";
}

/* Generate an "push" pattern for input ARG.  */

static rtx
gen_push (rtx arg)
{
  return gen_rtx_SET (VOIDmode,
          gen_rtx_MEM (Pmode,
           gen_rtx_PRE_DEC (Pmode,
                stack_pointer_rtx)),
          arg);
}

/* Return >= 0 if there is an unused call-clobbered register available
   for the entire function.  */

static unsigned int
ix86_select_alt_pic_regnum (void)
{
  if (current_function_is_leaf && !current_function_profile)
    {
      int i;
      for (i = 2; i >= 0; --i)
        if (!regs_ever_live[i])
    return i;
    }

  return INVALID_REGNUM;
}

/* Return 1 if we need to save REGNO.  */
static int
ix86_save_reg (unsigned int regno, int maybe_eh_return)
{
  if (pic_offset_table_rtx
      && regno == REAL_PIC_OFFSET_TABLE_REGNUM
      && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
    || current_function_profile
    || current_function_calls_eh_return
    || current_function_uses_const_pool))
    {
      if (ix86_select_alt_pic_regnum () != INVALID_REGNUM)
  return 0;
      return 1;
    }

  if (current_function_calls_eh_return && maybe_eh_return)
    {
      unsigned i;
      for (i = 0; ; i++)
  {
    unsigned test = EH_RETURN_DATA_REGNO (i);
    if (test == INVALID_REGNUM)
      break;
    if (test == regno)
      return 1;
  }
    }

  return (regs_ever_live[regno]
    && !call_used_regs[regno]
    && !fixed_regs[regno]
    && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed));
}

/* Return number of registers to be saved on the stack.  */

static int
ix86_nsaved_regs (void)
{
  int nregs = 0;
  int regno;

  for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
    if (ix86_save_reg (regno, true))
      nregs++;
  return nregs;
}

/* Return the offset between two registers, one to be eliminated, and the other
   its replacement, at the start of a routine.  */

HOST_WIDE_INT
ix86_initial_elimination_offset (int from, int to)
{
  struct ix86_frame frame;
  ix86_compute_frame_layout (&frame);

  if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
    return frame.hard_frame_pointer_offset;
  else if (from == FRAME_POINTER_REGNUM
     && to == HARD_FRAME_POINTER_REGNUM)
    return frame.hard_frame_pointer_offset - frame.frame_pointer_offset;
  else
    {
      if (to != STACK_POINTER_REGNUM)
  abort ();
      else if (from == ARG_POINTER_REGNUM)
  return frame.stack_pointer_offset;
      else if (from != FRAME_POINTER_REGNUM)
  abort ();
      else
  return frame.stack_pointer_offset - frame.frame_pointer_offset;
    }
}

/* Fill structure ix86_frame about frame of currently computed function.  */

static void
ix86_compute_frame_layout (struct ix86_frame *frame)
{
  HOST_WIDE_INT total_size;
  unsigned int stack_alignment_needed;
  HOST_WIDE_INT offset;
  unsigned int preferred_alignment;
  HOST_WIDE_INT size = get_frame_size ();

  frame->nregs = ix86_nsaved_regs ();
  total_size = size;

  stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT;
  preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT;

  /* During reload iteration the amount of registers saved can change.
     Recompute the value as needed.  Do not recompute when amount of registers
     didn't change as reload does mutiple calls to the function and does not
     expect the decision to change within single iteration.  */
  if (!optimize_size
      && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
    {
      int count = frame->nregs;

      cfun->machine->use_fast_prologue_epilogue_nregs = count;
      /* The fast prologue uses move instead of push to save registers.  This
         is significantly longer, but also executes faster as modern hardware
         can execute the moves in parallel, but can't do that for push/pop.

   Be careful about choosing what prologue to emit:  When function takes
   many instructions to execute we may use slow version as well as in
   case function is known to be outside hot spot (this is known with
   feedback only).  Weight the size of function by number of registers
   to save as it is cheap to use one or two push instructions but very
   slow to use many of them.  */
      if (count)
  count = (count - 1) * FAST_PROLOGUE_INSN_COUNT;
      if (cfun->function_frequency < FUNCTION_FREQUENCY_NORMAL
    || (flag_branch_probabilities
        && cfun->function_frequency < FUNCTION_FREQUENCY_HOT))
        cfun->machine->use_fast_prologue_epilogue = false;
      else
        cfun->machine->use_fast_prologue_epilogue
     = !expensive_function_p (count);
    }
  if (TARGET_PROLOGUE_USING_MOVE
      && cfun->machine->use_fast_prologue_epilogue)
    frame->save_regs_using_mov = true;
  else
    frame->save_regs_using_mov = false;


  /* Skip return address and saved base pointer.  */
  offset = frame_pointer_needed ? UNITS_PER_WORD * 2 : UNITS_PER_WORD;

  frame->hard_frame_pointer_offset = offset;

  /* Do some sanity checking of stack_alignment_needed and
     preferred_alignment, since i386 port is the only using those features
     that may break easily.  */

  if (size && !stack_alignment_needed)
    abort ();
  if (preferred_alignment < STACK_BOUNDARY / BITS_PER_UNIT)
    abort ();
  if (preferred_alignment > PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT)
    abort ();
  if (stack_alignment_needed > PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT)
    abort ();

  if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT)
    stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT;

  /* Register save area */
  offset += frame->nregs * UNITS_PER_WORD;

  /* Va-arg area */
  if (ix86_save_varrargs_registers)
    {
      offset += X86_64_VARARGS_SIZE;
      frame->va_arg_size = X86_64_VARARGS_SIZE;
    }
  else
    frame->va_arg_size = 0;

  /* Align start of frame for local function.  */
  frame->padding1 = ((offset + stack_alignment_needed - 1)
         & -stack_alignment_needed) - offset;

  offset += frame->padding1;

  /* Frame pointer points here.  */
  frame->frame_pointer_offset = offset;

  offset += size;

  /* Add outgoing arguments area.  Can be skipped if we eliminated
     all the function calls as dead code.
     Skipping is however impossible when function calls alloca.  Alloca
     expander assumes that last current_function_outgoing_args_size
     of stack frame are unused.  */
  if (ACCUMULATE_OUTGOING_ARGS
      && (!current_function_is_leaf || current_function_calls_alloca))
    {
      offset += current_function_outgoing_args_size;
      frame->outgoing_arguments_size = current_function_outgoing_args_size;
    }
  else
    frame->outgoing_arguments_size = 0;

  /* Align stack boundary.  Only needed if we're calling another function
     or using alloca.  */
  if (!current_function_is_leaf || current_function_calls_alloca)
    frame->padding2 = ((offset + preferred_alignment - 1)
           & -preferred_alignment) - offset;
  else
    frame->padding2 = 0;

  offset += frame->padding2;

  /* We've reached end of stack frame.  */
  frame->stack_pointer_offset = offset;

  /* Size prologue needs to allocate.  */
  frame->to_allocate =
    (size + frame->padding1 + frame->padding2
     + frame->outgoing_arguments_size + frame->va_arg_size);

  if ((!frame->to_allocate && frame->nregs <= 1)
      || (TARGET_64BIT && frame->to_allocate >= (HOST_WIDE_INT) 0x80000000))
    frame->save_regs_using_mov = false;

  if (TARGET_RED_ZONE && current_function_sp_is_unchanging
      && current_function_is_leaf)
    {
      frame->red_zone_size = frame->to_allocate;
      if (frame->save_regs_using_mov)
  frame->red_zone_size += frame->nregs * UNITS_PER_WORD;
      if (frame->red_zone_size > RED_ZONE_SIZE - RED_ZONE_RESERVE)
  frame->red_zone_size = RED_ZONE_SIZE - RED_ZONE_RESERVE;
    }
  else
    frame->red_zone_size = 0;
  frame->to_allocate -= frame->red_zone_size;
  frame->stack_pointer_offset -= frame->red_zone_size;
#if 0
  fprintf (stderr, "nregs: %i\n", frame->nregs);
  fprintf (stderr, "size: %i\n", size);
  fprintf (stderr, "alignment1: %i\n", stack_alignment_needed);
  fprintf (stderr, "padding1: %i\n", frame->padding1);
  fprintf (stderr, "va_arg: %i\n", frame->va_arg_size);
  fprintf (stderr, "padding2: %i\n", frame->padding2);
  fprintf (stderr, "to_allocate: %i\n", frame->to_allocate);
  fprintf (stderr, "red_zone_size: %i\n", frame->red_zone_size);
  fprintf (stderr, "frame_pointer_offset: %i\n", frame->frame_pointer_offset);
  fprintf (stderr, "hard_frame_pointer_offset: %i\n",
     frame->hard_frame_pointer_offset);
  fprintf (stderr, "stack_pointer_offset: %i\n", frame->stack_pointer_offset);
#endif
}

/* Emit code to save registers in the prologue.  */

static void
ix86_emit_save_regs (void)
{
  int regno;
  rtx insn;

  for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--)
    if (ix86_save_reg (regno, true))
      {
  insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno)));
  RTX_FRAME_RELATED_P (insn) = 1;
      }
}

/* Emit code to save registers using MOV insns.  First register
   is restored from POINTER + OFFSET.  */
static void
ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset)
{
  int regno;
  rtx insn;

  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
    if (ix86_save_reg (regno, true))
      {
  insn = emit_move_insn (adjust_address (gen_rtx_MEM (Pmode, pointer),
                 Pmode, offset),
             gen_rtx_REG (Pmode, regno));
  RTX_FRAME_RELATED_P (insn) = 1;
  offset += UNITS_PER_WORD;
      }
}

/* Expand prologue or epilogue stack adjustment.
   The pattern exist to put a dependency on all ebp-based memory accesses.
   STYLE should be negative if instructions should be marked as frame related,
   zero if %r11 register is live and cannot be freely used and positive
   otherwise.  */

static void
pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style)
{
  rtx insn;

  if (! TARGET_64BIT)
    insn = emit_insn (gen_pro_epilogue_adjust_stack_1 (dest, src, offset));
  else if (x86_64_immediate_operand (offset, DImode))
    insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64 (dest, src, offset));
  else
    {
      rtx r11;
      /* r11 is used by indirect sibcall return as well, set before the
   epilogue and used after the epilogue.  ATM indirect sibcall
   shouldn't be used together with huge frame sizes in one
   function because of the frame_size check in sibcall.c.  */
      if (style == 0)
  abort ();
      r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
      insn = emit_insn (gen_rtx_SET (DImode, r11, offset));
      if (style < 0)
  RTX_FRAME_RELATED_P (insn) = 1;
      insn = emit_insn (gen_pro_epilogue_adjust_stack_rex64_2 (dest, src, r11,
                     offset));
    }
  if (style < 0)
    RTX_FRAME_RELATED_P (insn) = 1;
}

/* Expand the prologue into a bunch of separate insns.  */

void
ix86_expand_prologue (void)
{
  rtx insn;
  bool pic_reg_used;
  struct ix86_frame frame;
  HOST_WIDE_INT allocate;

  ix86_compute_frame_layout (&frame);

  /* Note: AT&T enter does NOT have reversed args.  Enter is probably
     slower on all targets.  Also sdb doesn't like it.  */

  if (frame_pointer_needed)
    {
      insn = emit_insn (gen_push (hard_frame_pointer_rtx));
      RTX_FRAME_RELATED_P (insn) = 1;

      insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
      RTX_FRAME_RELATED_P (insn) = 1;
    }

  allocate = frame.to_allocate;

  if (!frame.save_regs_using_mov)
    ix86_emit_save_regs ();
  else
    allocate += frame.nregs * UNITS_PER_WORD;

  /* When using red zone we may start register saving before allocating
     the stack frame saving one cycle of the prologue.  */
  if (TARGET_RED_ZONE && frame.save_regs_using_mov)
    ix86_emit_save_regs_using_mov (frame_pointer_needed ? hard_frame_pointer_rtx
           : stack_pointer_rtx,
           -frame.nregs * UNITS_PER_WORD);

  if (allocate == 0)
    ;
  else if (! TARGET_STACK_PROBE || allocate < CHECK_STACK_LIMIT)
    pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
             GEN_INT (-allocate), -1);
  else
    {
      /* Only valid for Win32.  */
      rtx eax = gen_rtx_REG (SImode, 0);
      bool eax_live = ix86_eax_live_at_start_p ();
      rtx t;

      if (TARGET_64BIT)
        abort ();

      if (eax_live)
  {
    emit_insn (gen_push (eax));
    allocate -= 4;
  }

      emit_move_insn (eax, GEN_INT (allocate));

      insn = emit_insn (gen_allocate_stack_worker (eax));
      RTX_FRAME_RELATED_P (insn) = 1;
      t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate));
      t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t);
      REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
              t, REG_NOTES (insn));

      if (eax_live)
  {
    if (frame_pointer_needed)
      t = plus_constant (hard_frame_pointer_rtx,
             allocate
             - frame.to_allocate
             - frame.nregs * UNITS_PER_WORD);
    else
      t = plus_constant (stack_pointer_rtx, allocate);
    emit_move_insn (eax, gen_rtx_MEM (SImode, t));
  }
    }

  if (frame.save_regs_using_mov && !TARGET_RED_ZONE)
    {
      if (!frame_pointer_needed || !frame.to_allocate)
        ix86_emit_save_regs_using_mov (stack_pointer_rtx, frame.to_allocate);
      else
        ix86_emit_save_regs_using_mov (hard_frame_pointer_rtx,
               -frame.nregs * UNITS_PER_WORD);
    }

  pic_reg_used = false;
  if (pic_offset_table_rtx
      && (regs_ever_live[REAL_PIC_OFFSET_TABLE_REGNUM]
    || current_function_profile))
    {
      unsigned int alt_pic_reg_used = ix86_select_alt_pic_regnum ();

      if (alt_pic_reg_used != INVALID_REGNUM)
  REGNO (pic_offset_table_rtx) = alt_pic_reg_used;

      pic_reg_used = true;
    }

  if (pic_reg_used)
    {
      insn = emit_insn (gen_set_got (pic_offset_table_rtx));

      /* Even with accurate pre-reload life analysis, we can wind up
   deleting all references to the pic register after reload.
   Consider if cross-jumping unifies two sides of a branch
   controlled by a comparison vs the only read from a global.
   In which case, allow the set_got to be deleted, though we're
   too late to do anything about the ebx save in the prologue.  */
      REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, const0_rtx, NULL);
    }

  /* Prevent function calls from be scheduled before the call to mcount.
     In the pic_reg_used case, make sure that the got load isn't deleted.  */
  if (current_function_profile)
    emit_insn (gen_blockage (pic_reg_used ? pic_offset_table_rtx : const0_rtx));
}

/* Emit code to restore saved registers using MOV insns.  First register
   is restored from POINTER + OFFSET.  */
static void
ix86_emit_restore_regs_using_mov (rtx pointer, HOST_WIDE_INT offset,
          int maybe_eh_return)
{
  int regno;
  rtx base_address = gen_rtx_MEM (Pmode, pointer);

  for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
    if (ix86_save_reg (regno, maybe_eh_return))
      {
  /* Ensure that adjust_address won't be forced to produce pointer
     out of range allowed by x86-64 instruction set.  */
  if (TARGET_64BIT && offset != trunc_int_for_mode (offset, SImode))
    {
      rtx r11;

      r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */);
      emit_move_insn (r11, GEN_INT (offset));
      emit_insn (gen_adddi3 (r11, r11, pointer));
      base_address = gen_rtx_MEM (Pmode, r11);
      offset = 0;
    }
  emit_move_insn (gen_rtx_REG (Pmode, regno),
      adjust_address (base_address, Pmode, offset));
  offset += UNITS_PER_WORD;
      }
}

/* Restore function stack, frame, and registers.  */

void
ix86_expand_epilogue (int style)
{
  int regno;
  int sp_valid = !frame_pointer_needed || current_function_sp_is_unchanging;
  struct ix86_frame frame;
  HOST_WIDE_INT offset;

  ix86_compute_frame_layout (&frame);

  /* Calculate start of saved registers relative to ebp.  Special care
     must be taken for the normal return case of a function using
     eh_return: the eax and edx registers are marked as saved, but not
     restored along this path.  */
  offset = frame.nregs;
  if (current_function_calls_eh_return && style != 2)
    offset -= 2;
  offset *= -UNITS_PER_WORD;

  /* If we're only restoring one register and sp is not valid then
     using a move instruction to restore the register since it's
     less work than reloading sp and popping the register.

     The default code result in stack adjustment using add/lea instruction,
     while this code results in LEAVE instruction (or discrete equivalent),
     so it is profitable in some other cases as well.  Especially when there
     are no registers to restore.  We also use this code when TARGET_USE_LEAVE
     and there is exactly one register to pop. This heuristic may need some
     tuning in future.  */
  if ((!sp_valid && frame.nregs <= 1)
      || (TARGET_EPILOGUE_USING_MOVE
    && cfun->machine->use_fast_prologue_epilogue
    && (frame.nregs > 1 || frame.to_allocate))
      || (frame_pointer_needed && !frame.nregs && frame.to_allocate)
      || (frame_pointer_needed && TARGET_USE_LEAVE
    && cfun->machine->use_fast_prologue_epilogue
    && frame.nregs == 1)
      || current_function_calls_eh_return)
    {
      /* Restore registers.  We can use ebp or esp to address the memory
   locations.  If both are available, default to ebp, since offsets
   are known to be small.  Only exception is esp pointing directly to the
   end of block of saved registers, where we may simplify addressing
   mode.  */

      if (!frame_pointer_needed || (sp_valid && !frame.to_allocate))
  ix86_emit_restore_regs_using_mov (stack_pointer_rtx,
            frame.to_allocate, style == 2);
      else
  ix86_emit_restore_regs_using_mov (hard_frame_pointer_rtx,
            offset, style == 2);

      /* eh_return epilogues need %ecx added to the stack pointer.  */
      if (style == 2)
  {
    rtx tmp, sa = EH_RETURN_STACKADJ_RTX;

    if (frame_pointer_needed)
      {
        tmp = gen_rtx_PLUS (Pmode, hard_frame_pointer_rtx, sa);
        tmp = plus_constant (tmp, UNITS_PER_WORD);
        emit_insn (gen_rtx_SET (VOIDmode, sa, tmp));

        tmp = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
        emit_move_insn (hard_frame_pointer_rtx, tmp);

        pro_epilogue_adjust_stack (stack_pointer_rtx, sa,
           const0_rtx, style);
      }
    else
      {
        tmp = gen_rtx_PLUS (Pmode, stack_pointer_rtx, sa);
        tmp = plus_constant (tmp, (frame.to_allocate
                                         + frame.nregs * UNITS_PER_WORD));
        emit_insn (gen_rtx_SET (VOIDmode, stack_pointer_rtx, tmp));
      }
  }
      else if (!frame_pointer_needed)
  pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
           GEN_INT (frame.to_allocate
              + frame.nregs * UNITS_PER_WORD),
           style);
      /* If not an i386, mov & pop is faster than "leave".  */
      else if (TARGET_USE_LEAVE || optimize_size
         || !cfun->machine->use_fast_prologue_epilogue)
  emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
      else
  {
    pro_epilogue_adjust_stack (stack_pointer_rtx,
             hard_frame_pointer_rtx,
             const0_rtx, style);
    if (TARGET_64BIT)
      emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
    else
      emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
  }
    }
  else
    {
      /* First step is to deallocate the stack frame so that we can
   pop the registers.  */
      if (!sp_valid)
  {
    if (!frame_pointer_needed)
      abort ();
    pro_epilogue_adjust_stack (stack_pointer_rtx,
             hard_frame_pointer_rtx,
             GEN_INT (offset), style);
  }
      else if (frame.to_allocate)
  pro_epilogue_adjust_stack (stack_pointer_rtx, stack_pointer_rtx,
           GEN_INT (frame.to_allocate), style);

      for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
  if (ix86_save_reg (regno, false))
    {
      if (TARGET_64BIT)
        emit_insn (gen_popdi1 (gen_rtx_REG (Pmode, regno)));
      else
        emit_insn (gen_popsi1 (gen_rtx_REG (Pmode, regno)));
    }
      if (frame_pointer_needed)
  {
    /* Leave results in shorter dependency chains on CPUs that are
       able to grok it fast.  */
    if (TARGET_USE_LEAVE)
      emit_insn (TARGET_64BIT ? gen_leave_rex64 () : gen_leave ());
    else if (TARGET_64BIT)
      emit_insn (gen_popdi1 (hard_frame_pointer_rtx));
    else
      emit_insn (gen_popsi1 (hard_frame_pointer_rtx));
  }
    }

  /* Sibcall epilogues don't want a return instruction.  */
  if (style == 0)
    return;

  if (current_function_pops_args && current_function_args_size)
    {
      rtx popc = GEN_INT (current_function_pops_args);

      /* i386 can only pop 64K bytes.  If asked to pop more, pop
   return address, do explicit add, and jump indirectly to the
   caller.  */

      if (current_function_pops_args >= 65536)
  {
    rtx ecx = gen_rtx_REG (SImode, 2);

    /* There is no "pascal" calling convention in 64bit ABI.  */
    if (TARGET_64BIT)
      abort ();

    emit_insn (gen_popsi1 (ecx));
    emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc));
    emit_jump_insn (gen_return_indirect_internal (ecx));
  }
      else
  emit_jump_insn (gen_return_pop_internal (popc));
    }
  else
    emit_jump_insn (gen_return_internal ());
}

/* Reset from the function's potential modifications.  */

static void
ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
             HOST_WIDE_INT size ATTRIBUTE_UNUSED)
{
  if (pic_offset_table_rtx)
    REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM;
}

/* Extract the parts of an RTL expression that is a valid memory address
   for an instruction.  Return 0 if the structure of the address is
   grossly off.  Return -1 if the address contains ASHIFT, so it is not
   strictly valid, but still used for computing length of lea instruction.  */

int
ix86_decompose_address (rtx addr, struct ix86_address *out)
{
  rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX;
  rtx base_reg, index_reg;
  HOST_WIDE_INT scale = 1;
  rtx scale_rtx = NULL_RTX;
  int retval = 1;
  enum ix86_address_seg seg = SEG_DEFAULT;

  if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG)
    base = addr;
  else if (GET_CODE (addr) == PLUS)
    {
      rtx addends[4], op;
      int n = 0, i;

      op = addr;
      do
  {
    if (n >= 4)
      return 0;
    addends[n++] = XEXP (op, 1);
    op = XEXP (op, 0);
  }
      while (GET_CODE (op) == PLUS);
      if (n >= 4)
  return 0;
      addends[n] = op;

      for (i = n; i >= 0; --i)
  {
    op = addends[i];
    switch (GET_CODE (op))
      {
      case MULT:
        if (index)
    return 0;
        index = XEXP (op, 0);
        scale_rtx = XEXP (op, 1);
        break;

      case UNSPEC:
        if (XINT (op, 1) == UNSPEC_TP
            && TARGET_TLS_DIRECT_SEG_REFS
            && seg == SEG_DEFAULT)
    seg = TARGET_64BIT ? SEG_FS : SEG_GS;
        else
    return 0;
        break;

      case REG:
      case SUBREG:
        if (!base)
    base = op;
        else if (!index)
    index = op;
        else
    return 0;
        break;

      case CONST:
      case CONST_INT:
      case SYMBOL_REF:
      case LABEL_REF:
        if (disp)
    return 0;
        disp = op;
        break;

      default:
        return 0;
      }
  }
    }
  else if (GET_CODE (addr) == MULT)
    {
      index = XEXP (addr, 0);   /* index*scale */
      scale_rtx = XEXP (addr, 1);
    }
  else if (GET_CODE (addr) == ASHIFT)
    {
      rtx tmp;

      /* We're called for lea too, which implements ashift on occasion.  */
      index = XEXP (addr, 0);
      tmp = XEXP (addr, 1);
      if (GET_CODE (tmp) != CONST_INT)
  return 0;
      scale = INTVAL (tmp);
      if ((unsigned HOST_WIDE_INT) scale > 3)
  return 0;
      scale = 1 << scale;
      retval = -1;
    }
  else
    disp = addr;      /* displacement */

  /* Extract the integral value of scale.  */
  if (scale_rtx)
    {
      if (GET_CODE (scale_rtx) != CONST_INT)
  return 0;
      scale = INTVAL (scale_rtx);
    }

  base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base;
  index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index;

  /* Allow arg pointer and stack pointer as index if there is not scaling.  */
  if (base_reg && index_reg && scale == 1
      && (index_reg == arg_pointer_rtx
    || index_reg == frame_pointer_rtx
    || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM)))
    {
      rtx tmp;
      tmp = base, base = index, index = tmp;
      tmp = base_reg, base_reg = index_reg, index_reg = tmp;
    }

  /* Special case: %ebp cannot be encoded as a base without a displacement.  */
  if ((base_reg == hard_frame_pointer_rtx
       || base_reg == frame_pointer_rtx
       || base_reg == arg_pointer_rtx) && !disp)
    disp = const0_rtx;

  /* Special case: on K6, [%esi] makes the instruction vector decoded.
     Avoid this by transforming to [%esi+0].  */
  if (ix86_tune == PROCESSOR_K6 && !optimize_size
      && base_reg && !index_reg && !disp
      && REG_P (base_reg)
      && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
    disp = const0_rtx;

  /* Special case: encode reg+reg instead of reg*2.  */
  if (!base && index && scale && scale == 2)
    base = index, base_reg = index_reg, scale = 1;

  /* Special case: scaling cannot be encoded without base or displacement.  */
  if (!base && !disp && index && scale != 1)
    disp = const0_rtx;

  out->base = base;
  out->index = index;
  out->disp = disp;
  out->scale = scale;
  out->seg = seg;

  return retval;
}

/* Return cost of the memory address x.
   For i386, it is better to use a complex address than let gcc copy
   the address into a reg and make a new pseudo.  But not if the address
   requires to two regs - that would mean more pseudos with longer
   lifetimes.  */
static int
ix86_address_cost (rtx x)
{
  struct ix86_address parts;
  int cost = 1;

  if (!ix86_decompose_address (x, &parts))
    abort ();

  if (parts.base && GET_CODE (parts.base) == SUBREG)
    parts.base = SUBREG_REG (parts.base);
  if (parts.index && GET_CODE (parts.index) == SUBREG)
    parts.index = SUBREG_REG (parts.index);

  /* More complex memory references are better.  */
  if (parts.disp && parts.disp != const0_rtx)
    cost--;
  if (parts.seg != SEG_DEFAULT)
    cost--;

  /* Attempt to minimize number of registers in the address.  */
  if ((parts.base
       && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER))
      || (parts.index
    && (!REG_P (parts.index)
        || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)))
    cost++;

  if (parts.base
      && (!REG_P (parts.base) || REGNO (parts.base) >= FIRST_PSEUDO_REGISTER)
      && parts.index
      && (!REG_P (parts.index) || REGNO (parts.index) >= FIRST_PSEUDO_REGISTER)
      && parts.base != parts.index)
    cost++;

  /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
     since it's predecode logic can't detect the length of instructions
     and it degenerates to vector decoded.  Increase cost of such
     addresses here.  The penalty is minimally 2 cycles.  It may be worthwhile
     to split such addresses or even refuse such addresses at all.

     Following addressing modes are affected:
      [base+scale*index]
      [scale*index+disp]
      [base+index]

     The first and last case  may be avoidable by explicitly coding the zero in
     memory address, but I don't have AMD-K6 machine handy to check this
     theory.  */

  if (TARGET_K6
      && ((!parts.disp && parts.base && parts.index && parts.scale != 1)
    || (parts.disp && !parts.base && parts.index && parts.scale != 1)
    || (!parts.disp && parts.base && parts.index && parts.scale == 1)))
    cost += 10;

  return cost;
}

/* If X is a machine specific address (i.e. a symbol or label being
   referenced as a displacement from the GOT implemented using an
   UNSPEC), then return the base term.  Otherwise return X.  */

rtx
ix86_find_base_term (rtx x)
{
  rtx term;

  if (TARGET_64BIT)
    {
      if (GET_CODE (x) != CONST)
  return x;
      term = XEXP (x, 0);
      if (GET_CODE (term) == PLUS
    && (GET_CODE (XEXP (term, 1)) == CONST_INT
        || GET_CODE (XEXP (term, 1)) == CONST_DOUBLE))
  term = XEXP (term, 0);
      if (GET_CODE (term) != UNSPEC
    || XINT (term, 1) != UNSPEC_GOTPCREL)
  return x;

      term = XVECEXP (term, 0, 0);

      if (GET_CODE (term) != SYMBOL_REF
    && GET_CODE (term) != LABEL_REF)
  return x;

      return term;
    }

  term = ix86_delegitimize_address (x);

  if (GET_CODE (term) != SYMBOL_REF
      && GET_CODE (term) != LABEL_REF)
    return x;

  return term;
}

/* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
   this is used for to form addresses to local data when -fPIC is in
   use.  */

static bool
darwin_local_data_pic (rtx disp)
{
  if (GET_CODE (disp) == MINUS)
    {
      if (GET_CODE (XEXP (disp, 0)) == LABEL_REF
          || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF)
        if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
          {
            const char *sym_name = XSTR (XEXP (disp, 1), 0);
            if (! strcmp (sym_name, "<pic base>"))
              return true;
          }
    }

  return false;
}

/* Determine if a given RTX is a valid constant.  We already know this
   satisfies CONSTANT_P.  */

bool
legitimate_constant_p (rtx x)
{
  switch (GET_CODE (x))
    {
    case CONST:
      x = XEXP (x, 0);

      if (GET_CODE (x) == PLUS)
  {
    if (GET_CODE (XEXP (x, 1)) != CONST_INT)
      return false;
    x = XEXP (x, 0);
  }

      if (TARGET_MACHO && darwin_local_data_pic (x))
  return true;

      /* Only some unspecs are valid as "constants".  */
      if (GET_CODE (x) == UNSPEC)
  switch (XINT (x, 1))
    {
    case UNSPEC_TPOFF:
    case UNSPEC_NTPOFF:
      return local_exec_symbolic_operand (XVECEXP (x, 0, 0), Pmode);
    case UNSPEC_DTPOFF:
      return local_dynamic_symbolic_operand (XVECEXP (x, 0, 0), Pmode);
    default:
      return false;
    }

      /* We must have drilled down to a symbol.  */
      if (!symbolic_operand (x, Pmode))
  return false;
      /* FALLTHRU */

    case SYMBOL_REF:
      /* TLS symbols are never valid.  */
      if (tls_symbolic_operand (x, Pmode))
  return false;
      break;

    default:
      break;
    }

  /* Otherwise we handle everything else in the move patterns.  */
  return true;
}

/* Determine if it's legal to put X into the constant pool.  This
   is not possible for the address of thread-local symbols, which
   is checked above.  */

static bool
ix86_cannot_force_const_mem (rtx x)
{
  return !legitimate_constant_p (x);
}

/* Determine if a given RTX is a valid constant address.  */

bool
constant_address_p (rtx x)
{
  return CONSTANT_P (x) && legitimate_address_p (Pmode, x, 1);
}

/* Nonzero if the constant value X is a legitimate general operand
   when generating PIC code.  It is given that flag_pic is on and
   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */

bool
legitimate_pic_operand_p (rtx x)
{
  rtx inner;

  switch (GET_CODE (x))
    {
    case CONST:
      inner = XEXP (x, 0);

      /* Only some unspecs are valid as "constants".  */
      if (GET_CODE (inner) == UNSPEC)
  switch (XINT (inner, 1))
    {
    case UNSPEC_TPOFF:
      return local_exec_symbolic_operand (XVECEXP (inner, 0, 0), Pmode);
    default:
      return false;
    }
      /* FALLTHRU */

    case SYMBOL_REF:
    case LABEL_REF:
      return legitimate_pic_address_disp_p (x);

    default:
      return true;
    }
}

/* Determine if a given CONST RTX is a valid memory displacement
   in PIC mode.  */

int
legitimate_pic_address_disp_p (rtx disp)
{
  bool saw_plus;

  /* In 64bit mode we can allow direct addresses of symbols and labels
     when they are not dynamic symbols.  */
  if (TARGET_64BIT)
    {
      /* TLS references should always be enclosed in UNSPEC.  */
      if (tls_symbolic_operand (disp, GET_MODE (disp)))
  return 0;
      if (GET_CODE (disp) == SYMBOL_REF
    && ix86_cmodel == CM_SMALL_PIC
    && SYMBOL_REF_LOCAL_P (disp))
  return 1;
      if (GET_CODE (disp) == LABEL_REF)
  return 1;
      if (GET_CODE (disp) == CONST
    && GET_CODE (XEXP (disp, 0)) == PLUS)
  {
    rtx op0 = XEXP (XEXP (disp, 0), 0);
    rtx op1 = XEXP (XEXP (disp, 0), 1);

    /* TLS references should always be enclosed in UNSPEC.  */
    if (tls_symbolic_operand (op0, GET_MODE (op0)))
      return 0;
    if (((GET_CODE (op0) == SYMBOL_REF
    && ix86_cmodel == CM_SMALL_PIC
    && SYMBOL_REF_LOCAL_P (op0))
         || GET_CODE (op0) == LABEL_REF)
        && GET_CODE (op1) == CONST_INT
        && INTVAL (op1) < 16*1024*1024
        && INTVAL (op1) >= -16*1024*1024)
      return 1;
  }
    }
  if (GET_CODE (disp) != CONST)
    return 0;
  disp = XEXP (disp, 0);

  if (TARGET_64BIT)
    {
      /* We are unsafe to allow PLUS expressions.  This limit allowed distance
         of GOT tables.  We should not need these anyway.  */
      if (GET_CODE (disp) != UNSPEC
    || XINT (disp, 1) != UNSPEC_GOTPCREL)
  return 0;

      if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
    && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
  return 0;
      return 1;
    }

  saw_plus = false;
  if (GET_CODE (disp) == PLUS)
    {
      if (GET_CODE (XEXP (disp, 1)) != CONST_INT)
  return 0;
      disp = XEXP (disp, 0);
      saw_plus = true;
    }

  if (TARGET_MACHO && darwin_local_data_pic (disp))
    return 1;

  if (GET_CODE (disp) != UNSPEC)
    return 0;

  switch (XINT (disp, 1))
    {
    case UNSPEC_GOT:
      if (saw_plus)
  return false;
      return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF;
    case UNSPEC_GOTOFF:
      if (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
    || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
        return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
      return false;
    case UNSPEC_GOTTPOFF:
    case UNSPEC_GOTNTPOFF:
    case UNSPEC_INDNTPOFF:
      if (saw_plus)
  return false;
      return initial_exec_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
    case UNSPEC_NTPOFF:
      return local_exec_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
    case UNSPEC_DTPOFF:
      return local_dynamic_symbolic_operand (XVECEXP (disp, 0, 0), Pmode);
    }

  return 0;
}

/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid
   memory address for an instruction.  The MODE argument is the machine mode
   for the MEM expression that wants to use this address.

   It only recognizes address in canonical form.  LEGITIMIZE_ADDRESS should
   convert common non-canonical forms to canonical form so that they will
   be recognized.  */

int
legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
{
  struct ix86_address parts;
  rtx base, index, disp;
  HOST_WIDE_INT scale;
  const char *reason = NULL;
  rtx reason_rtx = NULL_RTX;

  if (TARGET_DEBUG_ADDR)
    {
      fprintf (stderr,
         "\n======\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n",
         GET_MODE_NAME (mode), strict);
      debug_rtx (addr);
    }

  if (ix86_decompose_address (addr, &parts) <= 0)
    {
      reason = "decomposition failed";
      goto report_error;
    }

  base = parts.base;
  index = parts.index;
  disp = parts.disp;
  scale = parts.scale;

  /* Validate base register.

     Don't allow SUBREG's that span more than a word here.  It can lead to spill
     failures when the base is one word out of a two word structure, which is
     represented internally as a DImode int.  */

  if (base)
    {
      rtx reg;
      reason_rtx = base;
  
      if (REG_P (base))
    reg = base;
      else if (GET_CODE (base) == SUBREG
         && REG_P (SUBREG_REG (base))
         && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base)))
      <= UNITS_PER_WORD)
    reg = SUBREG_REG (base);
      else
  {
    reason = "base is not a register";
    goto report_error;
  }

      if (GET_MODE (base) != Pmode)
  {
    reason = "base is not in Pmode";
    goto report_error;
  }

      if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg))
    || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg)))
  {
    reason = "base is not valid";
    goto report_error;
  }
    }

  /* Validate index register.

     Don't allow SUBREG's that span more than a word here -- same as above.  */

  if (index)
    {
      rtx reg;
      reason_rtx = index;

      if (REG_P (index))
    reg = index;
      else if (GET_CODE (index) == SUBREG
         && REG_P (SUBREG_REG (index))
         && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index)))
      <= UNITS_PER_WORD)
    reg = SUBREG_REG (index);
      else
  {
    reason = "index is not a register";
    goto report_error;
  }

      if (GET_MODE (index) != Pmode)
  {
    reason = "index is not in Pmode";
    goto report_error;
  }

      if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg))
    || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg)))
  {
    reason = "index is not valid";
    goto report_error;
  }
    }

  /* Validate scale factor.  */
  if (scale != 1)
    {
      reason_rtx = GEN_INT (scale);
      if (!index)
  {
    reason = "scale without index";
    goto report_error;
  }

      if (scale != 2 && scale != 4 && scale != 8)
  {
    reason = "scale is not a valid multiplier";
    goto report_error;
  }
    }

  /* Validate displacement.  */
  if (disp)
    {
      reason_rtx = disp;

      if (GET_CODE (disp) == CONST
    && GET_CODE (XEXP (disp, 0)) == UNSPEC)
  switch (XINT (XEXP (disp, 0), 1))
    {
    case UNSPEC_GOT:
    case UNSPEC_GOTOFF:
    case UNSPEC_GOTPCREL:
      if (!flag_pic)
        abort ();
      goto is_legitimate_pic;

    case UNSPEC_GOTTPOFF:
    case UNSPEC_GOTNTPOFF:
    case UNSPEC_INDNTPOFF:
    case UNSPEC_NTPOFF:
    case UNSPEC_DTPOFF:
      break;

    default:
      reason = "invalid address unspec";
      goto report_error;
    }

      else if (flag_pic && (SYMBOLIC_CONST (disp)
#if TARGET_MACHO
          && !machopic_operand_p (disp)
#endif
          ))
  {
  is_legitimate_pic:
    if (TARGET_64BIT && (index || base))
      {
        /* foo@dtpoff(%rX) is ok.  */
        if (GET_CODE (disp) != CONST
      || GET_CODE (XEXP (disp, 0)) != PLUS
      || GET_CODE (XEXP (XEXP (disp, 0), 0)) != UNSPEC
      || GET_CODE (XEXP (XEXP (disp, 0), 1)) != CONST_INT
      || (XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_DTPOFF
          && XINT (XEXP (XEXP (disp, 0), 0), 1) != UNSPEC_NTPOFF))
    {
      reason = "non-constant pic memory reference";
      goto report_error;
    }
      }
    else if (! legitimate_pic_address_disp_p (disp))
      {
        reason = "displacement is an invalid pic construct";
        goto report_error;
      }

          /* This code used to verify that a symbolic pic displacement
       includes the pic_offset_table_rtx register.

       While this is good idea, unfortunately these constructs may
       be created by "adds using lea" optimization for incorrect
       code like:

       int a;
       int foo(int i)
         {
           return *(&a+i);
         }

       This code is nonsensical, but results in addressing
       GOT table with pic_offset_table_rtx base.  We can't
       just refuse it easily, since it gets matched by
       "addsi3" pattern, that later gets split to lea in the
       case output register differs from input.  While this
       can be handled by separate addsi pattern for this case
       that never results in lea, this seems to be easier and
       correct fix for crash to disable this test.  */
  }
      else if (GET_CODE (disp) != LABEL_REF
         && GET_CODE (disp) != CONST_INT
         && (GET_CODE (disp) != CONST
       || !legitimate_constant_p (disp))
         && (GET_CODE (disp) != SYMBOL_REF
       || !legitimate_constant_p (disp)))
  {
    reason = "displacement is not constant";
    goto report_error;
  }
      else if (TARGET_64BIT
         && !x86_64_immediate_operand (disp, VOIDmode))
  {
    reason = "displacement is out of range";
    goto report_error;
  }
    }

  /* Everything looks valid.  */
  if (TARGET_DEBUG_ADDR)
    fprintf (stderr, "Success.\n");
  return TRUE;

 report_error:
  if (TARGET_DEBUG_ADDR)
    {
      fprintf (stderr, "Error: %s\n", reason);
      debug_rtx (reason_rtx);
    }
  return FALSE;
}

/* Return an unique alias set for the GOT.  */

static HOST_WIDE_INT
ix86_GOT_alias_set (void)
{
  static HOST_WIDE_INT set = -1;
  if (set == -1)
    set = new_alias_set ();
  return set;
}

/* Return a legitimate reference for ORIG (an address) using the
   register REG.  If REG is 0, a new pseudo is generated.

   There are two types of references that must be handled:

   1. Global data references must load the address from the GOT, via
      the PIC reg.  An insn is emitted to do this load, and the reg is
      returned.

   2. Static data references, constant pool addresses, and code labels
      compute the address as an offset from the GOT, whose base is in
      the PIC reg.  Static data objects have SYMBOL_FLAG_LOCAL set to
      differentiate them from global data objects.  The returned
      address is the PIC reg + an unspec constant.

   GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
   reg also appears in the address.  */

static rtx
legitimize_pic_address (rtx orig, rtx reg)
{
  rtx addr = orig;
  rtx new = orig;
  rtx base;

#if TARGET_MACHO
  if (reg == 0)
    reg = gen_reg_rtx (Pmode);
  /* Use the generic Mach-O PIC machinery.  */
  return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg);
#endif

  if (TARGET_64BIT && legitimate_pic_address_disp_p (addr))
    new = addr;
  else if (!TARGET_64BIT && local_symbolic_operand (addr, Pmode))
    {
      /* This symbol may be referenced via a displacement from the PIC
   base address (@GOTOFF).  */

      if (reload_in_progress)
  regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
      if (GET_CODE (addr) == CONST)
  addr = XEXP (addr, 0);
      if (GET_CODE (addr) == PLUS)
    {
            new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF);
      new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1));
    }
  else
          new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
      new = gen_rtx_CONST (Pmode, new);
      new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);

      if (reg != 0)
  {
    emit_move_insn (reg, new);
    new = reg;
  }
    }
  else if (GET_CODE (addr) == SYMBOL_REF)
    {
      if (TARGET_64BIT)
  {
    new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL);
    new = gen_rtx_CONST (Pmode, new);
    new = gen_const_mem (Pmode, new);
    set_mem_alias_set (new, ix86_GOT_alias_set ());

    if (reg == 0)
      reg = gen_reg_rtx (Pmode);
    /* Use directly gen_movsi, otherwise the address is loaded
       into register for CSE.  We don't want to CSE this addresses,
       instead we CSE addresses from the GOT table, so skip this.  */
    emit_insn (gen_movsi (reg, new));
    new = reg;
  }
      else
  {
    /* This symbol must be referenced via a load from the
       Global Offset Table (@GOT).  */

    if (reload_in_progress)
      regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
    new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
    new = gen_rtx_CONST (Pmode, new);
    new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
    new = gen_const_mem (Pmode, new);
    set_mem_alias_set (new, ix86_GOT_alias_set ());

    if (reg == 0)
      reg = gen_reg_rtx (Pmode);
    emit_move_insn (reg, new);
    new = reg;
  }
    }
  else
    {
      if (GET_CODE (addr) == CONST)
  {
    addr = XEXP (addr, 0);

    /* We must match stuff we generate before.  Assume the only
       unspecs that can get here are ours.  Not that we could do
       anything with them anyway....  */
    if (GET_CODE (addr) == UNSPEC
        || (GET_CODE (addr) == PLUS
      && GET_CODE (XEXP (addr, 0)) == UNSPEC))
      return orig;
    if (GET_CODE (addr) != PLUS)
      abort ();
  }
      if (GET_CODE (addr) == PLUS)
  {
    rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);

    /* Check first to see if this is a constant offset from a @GOTOFF
       symbol reference.  */
    if (local_symbolic_operand (op0, Pmode)
        && GET_CODE (op1) == CONST_INT)
      {
        if (!TARGET_64BIT)
    {
      if (reload_in_progress)
        regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
      new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
          UNSPEC_GOTOFF);
      new = gen_rtx_PLUS (Pmode, new, op1);
      new = gen_rtx_CONST (Pmode, new);
      new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);

      if (reg != 0)
        {
          emit_move_insn (reg, new);
          new = reg;
        }
    }
        else
    {
      if (INTVAL (op1) < -16*1024*1024
          || INTVAL (op1) >= 16*1024*1024)
        new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1);
    }
      }
    else
      {
        base = legitimize_pic_address (XEXP (addr, 0), reg);
        new  = legitimize_pic_address (XEXP (addr, 1),
               base == reg ? NULL_RTX : reg);

        if (GET_CODE (new) == CONST_INT)
    new = plus_constant (base, INTVAL (new));
        else
    {
      if (GET_CODE (new) == PLUS && CONSTANT_P (XEXP (new, 1)))
        {
          base = gen_rtx_PLUS (Pmode, base, XEXP (new, 0));
          new = XEXP (new, 1);
        }
      new = gen_rtx_PLUS (Pmode, base, new);
    }
      }
  }
    }
  return new;
}

/* Load the thread pointer.  If TO_REG is true, force it into a register.  */

static rtx
get_thread_pointer (int to_reg)
{
  rtx tp, reg, insn;

  tp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TP);
  if (!to_reg)
    return tp;

  reg = gen_reg_rtx (Pmode);
  insn = gen_rtx_SET (VOIDmode, reg, tp);
  insn = emit_insn (insn);

  return reg;
}

/* A subroutine of legitimize_address and ix86_expand_move.  FOR_MOV is
   false if we expect this to be used for a memory address and true if
   we expect to load the address into a register.  */

static rtx
legitimize_tls_address (rtx x, enum tls_model model, int for_mov)
{
  rtx dest, base, off, pic;
  int type;

  switch (model)
    {
    case TLS_MODEL_GLOBAL_DYNAMIC:
      dest = gen_reg_rtx (Pmode);
      if (TARGET_64BIT)
  {
    rtx rax = gen_rtx_REG (Pmode, 0), insns;

    start_sequence ();
    emit_call_insn (gen_tls_global_dynamic_64 (rax, x));
    insns = get_insns ();
    end_sequence ();

    emit_libcall_block (insns, dest, rax, x);
  }
      else
  emit_insn (gen_tls_global_dynamic_32 (dest, x));
      break;

    case TLS_MODEL_LOCAL_DYNAMIC:
      base = gen_reg_rtx (Pmode);
      if (TARGET_64BIT)
  {
    rtx rax = gen_rtx_REG (Pmode, 0), insns, note;

    start_sequence ();
    emit_call_insn (gen_tls_local_dynamic_base_64 (rax));
    insns = get_insns ();
    end_sequence ();

    note = gen_rtx_EXPR_LIST (VOIDmode, const0_rtx, NULL);
    note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note);
    emit_libcall_block (insns, base, rax, note);
  }
      else
  emit_insn (gen_tls_local_dynamic_base_32 (base));

      off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF);
      off = gen_rtx_CONST (Pmode, off);

      return gen_rtx_PLUS (Pmode, base, off);

    case TLS_MODEL_INITIAL_EXEC:
      if (TARGET_64BIT)
  {
    pic = NULL;
    type = UNSPEC_GOTNTPOFF;
  }
      else if (flag_pic)
  {
    if (reload_in_progress)
      regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
    pic = pic_offset_table_rtx;
    type = TARGET_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF;
  }
      else if (!TARGET_GNU_TLS)
  {
    pic = gen_reg_rtx (Pmode);
    emit_insn (gen_set_got (pic));
    type = UNSPEC_GOTTPOFF;
  }
      else
  {
    pic = NULL;
    type = UNSPEC_INDNTPOFF;
  }

      off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), type);
      off = gen_rtx_CONST (Pmode, off);
      if (pic)
  off = gen_rtx_PLUS (Pmode, pic, off);
      off = gen_const_mem (Pmode, off);
      set_mem_alias_set (off, ix86_GOT_alias_set ());

      if (TARGET_64BIT || TARGET_GNU_TLS)
  {
          base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
    off = force_reg (Pmode, off);
    return gen_rtx_PLUS (Pmode, base, off);
  }
      else
  {
    base = get_thread_pointer (true);
    dest = gen_reg_rtx (Pmode);
    emit_insn (gen_subsi3 (dest, base, off));
  }
      break;

    case TLS_MODEL_LOCAL_EXEC:
      off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x),
          (TARGET_64BIT || TARGET_GNU_TLS)
          ? UNSPEC_NTPOFF : UNSPEC_TPOFF);
      off = gen_rtx_CONST (Pmode, off);

      if (TARGET_64BIT || TARGET_GNU_TLS)
  {
    base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS);
    return gen_rtx_PLUS (Pmode, base, off);
  }
      else
  {
    base = get_thread_pointer (true);
    dest = gen_reg_rtx (Pmode);
    emit_insn (gen_subsi3 (dest, base, off));
  }
      break;

    default:
      abort ();
    }

  return dest;
}

/* Try machine-dependent ways of modifying an illegitimate address
   to be legitimate.  If we find one, return the new, valid address.
   This macro is used in only one place: `memory_address' in explow.c.

   OLDX is the address as it was before break_out_memory_refs was called.
   In some cases it is useful to look at this to decide what needs to be done.

   MODE and WIN are passed so that this macro can use
   GO_IF_LEGITIMATE_ADDRESS.

   It is always safe for this macro to do nothing.  It exists to recognize
   opportunities to optimize the output.

   For the 80386, we handle X+REG by loading X into a register R and
   using R+REG.  R will go in a general reg and indexing will be used.
   However, if REG is a broken-out memory address or multiplication,
   nothing needs to be done because REG can certainly go in a general reg.

   When -fpic is used, special handling is needed for symbolic references.
   See comments by legitimize_pic_address in i386.c for details.  */

rtx
legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
{
  int changed = 0;
  unsigned log;

  if (TARGET_DEBUG_ADDR)
    {
      fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n",
         GET_MODE_NAME (mode));
      debug_rtx (x);
    }

  log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
  if (log)
    return legitimize_tls_address (x, log, false);
  if (GET_CODE (x) == CONST
      && GET_CODE (XEXP (x, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
      && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
    {
      rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false);
      return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1));
    }

  if (flag_pic && SYMBOLIC_CONST (x))
    return legitimize_pic_address (x, 0);

  /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
  if (GET_CODE (x) == ASHIFT
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4)
    {
      changed = 1;
      log = INTVAL (XEXP (x, 1));
      x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)),
      GEN_INT (1 << log));
    }

  if (GET_CODE (x) == PLUS)
    {
      /* Canonicalize shifts by 0, 1, 2, 3 into multiply.  */

      if (GET_CODE (XEXP (x, 0)) == ASHIFT
    && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
    && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4)
  {
    changed = 1;
    log = INTVAL (XEXP (XEXP (x, 0), 1));
    XEXP (x, 0) = gen_rtx_MULT (Pmode,
              force_reg (Pmode, XEXP (XEXP (x, 0), 0)),
              GEN_INT (1 << log));
  }

      if (GET_CODE (XEXP (x, 1)) == ASHIFT
    && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
    && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4)
  {
    changed = 1;
    log = INTVAL (XEXP (XEXP (x, 1), 1));
    XEXP (x, 1) = gen_rtx_MULT (Pmode,
              force_reg (Pmode, XEXP (XEXP (x, 1), 0)),
              GEN_INT (1 << log));
  }

      /* Put multiply first if it isn't already.  */
      if (GET_CODE (XEXP (x, 1)) == MULT)
  {
    rtx tmp = XEXP (x, 0);
    XEXP (x, 0) = XEXP (x, 1);
    XEXP (x, 1) = tmp;
    changed = 1;
  }

      /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
   into (plus (plus (mult (reg) (const)) (reg)) (const)).  This can be
   created by virtual register instantiation, register elimination, and
   similar optimizations.  */
      if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS)
  {
    changed = 1;
    x = gen_rtx_PLUS (Pmode,
          gen_rtx_PLUS (Pmode, XEXP (x, 0),
            XEXP (XEXP (x, 1), 0)),
          XEXP (XEXP (x, 1), 1));
  }

      /* Canonicalize
   (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
   into (plus (plus (mult (reg) (const)) (reg)) (const)).  */
      else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS
         && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
         && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS
         && CONSTANT_P (XEXP (x, 1)))
  {
    rtx constant;
    rtx other = NULL_RTX;

    if (GET_CODE (XEXP (x, 1)) == CONST_INT)
      {
        constant = XEXP (x, 1);
        other = XEXP (XEXP (XEXP (x, 0), 1), 1);
      }
    else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT)
      {
        constant = XEXP (XEXP (XEXP (x, 0), 1), 1);
        other = XEXP (x, 1);
      }
    else
      constant = 0;

    if (constant)
      {
        changed = 1;
        x = gen_rtx_PLUS (Pmode,
        gen_rtx_PLUS (Pmode, XEXP (XEXP (x, 0), 0),
                XEXP (XEXP (XEXP (x, 0), 1), 0)),
        plus_constant (other, INTVAL (constant)));
      }
  }

      if (changed && legitimate_address_p (mode, x, FALSE))
  return x;

      if (GET_CODE (XEXP (x, 0)) == MULT)
  {
    changed = 1;
    XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
  }

      if (GET_CODE (XEXP (x, 1)) == MULT)
  {
    changed = 1;
    XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
  }

      if (changed
    && GET_CODE (XEXP (x, 1)) == REG
    && GET_CODE (XEXP (x, 0)) == REG)
  return x;

      if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1)))
  {
    changed = 1;
    x = legitimize_pic_address (x, 0);
  }

      if (changed && legitimate_address_p (mode, x, FALSE))
  return x;

      if (GET_CODE (XEXP (x, 0)) == REG)
  {
    rtx temp = gen_reg_rtx (Pmode);
    rtx val  = force_operand (XEXP (x, 1), temp);
    if (val != temp)
      emit_move_insn (temp, val);

    XEXP (x, 1) = temp;
    return x;
  }

      else if (GET_CODE (XEXP (x, 1)) == REG)
  {
    rtx temp = gen_reg_rtx (Pmode);
    rtx val  = force_operand (XEXP (x, 0), temp);
    if (val != temp)
      emit_move_insn (temp, val);

    XEXP (x, 0) = temp;
    return x;
  }
    }

  return x;
}

/* Print an integer constant expression in assembler syntax.  Addition
   and subtraction are the only arithmetic that may appear in these
   expressions.  FILE is the stdio stream to write to, X is the rtx, and
   CODE is the operand print code from the output string.  */

static void
output_pic_addr_const (FILE *file, rtx x, int code)
{
  char buf[256];

  switch (GET_CODE (x))
    {
    case PC:
      if (flag_pic)
  putc ('.', file);
      else
  abort ();
      break;

    case SYMBOL_REF:
     /* Mark the decl as referenced so that cgraph will output the function.  */
     if (SYMBOL_REF_DECL (x))
       mark_decl_referenced (SYMBOL_REF_DECL (x));

      assemble_name (file, XSTR (x, 0));
      if (!TARGET_MACHO && code == 'P' && ! SYMBOL_REF_LOCAL_P (x))
  fputs ("@PLT", file);
      break;

    case LABEL_REF:
      x = XEXP (x, 0);
      /* FALLTHRU */
    case CODE_LABEL:
      ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x));
      assemble_name (asm_out_file, buf);
      break;

    case CONST_INT:
      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
      break;

    case CONST:
      /* This used to output parentheses around the expression,
   but that does not work on the 386 (either ATT or BSD assembler).  */
      output_pic_addr_const (file, XEXP (x, 0), code);
      break;

    case CONST_DOUBLE:
      if (GET_MODE (x) == VOIDmode)
  {
    /* We can use %d if the number is <32 bits and positive.  */
    if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0)
      fprintf (file, "0x%lx%08lx",
         (unsigned long) CONST_DOUBLE_HIGH (x),
         (unsigned long) CONST_DOUBLE_LOW (x));
    else
      fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x));
  }
      else
  /* We can't handle floating point constants;
     PRINT_OPERAND must handle them.  */
  output_operand_lossage ("floating constant misused");
      break;

    case PLUS:
      /* Some assemblers need integer constants to appear first.  */
      if (GET_CODE (XEXP (x, 0)) == CONST_INT)
  {
    output_pic_addr_const (file, XEXP (x, 0), code);
    putc ('+', file);
    output_pic_addr_const (file, XEXP (x, 1), code);
  }
      else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
  {
    output_pic_addr_const (file, XEXP (x, 1), code);
    putc ('+', file);
    output_pic_addr_const (file, XEXP (x, 0), code);
  }
      else
  abort ();
      break;

    case MINUS:
      if (!TARGET_MACHO)
  putc (ASSEMBLER_DIALECT == ASM_INTEL ? '(' : '[', file);
      output_pic_addr_const (file, XEXP (x, 0), code);
      putc ('-', file);
      output_pic_addr_const (file, XEXP (x, 1), code);
      if (!TARGET_MACHO)
  putc (ASSEMBLER_DIALECT == ASM_INTEL ? ')' : ']', file);
      break;

     case UNSPEC:
       if (XVECLEN (x, 0) != 1)
   abort ();
       output_pic_addr_const (file, XVECEXP (x, 0, 0), code);
       switch (XINT (x, 1))
  {
  case UNSPEC_GOT:
    fputs ("@GOT", file);
    break;
  case UNSPEC_GOTOFF:
    fputs ("@GOTOFF", file);
    break;
  case UNSPEC_GOTPCREL:
    fputs ("@GOTPCREL(%rip)", file);
    break;
  case UNSPEC_GOTTPOFF:
    /* FIXME: This might be @TPOFF in Sun ld too.  */
    fputs ("@GOTTPOFF", file);
    break;
  case UNSPEC_TPOFF:
    fputs ("@TPOFF", file);
    break;
  case UNSPEC_NTPOFF:
    if (TARGET_64BIT)
      fputs ("@TPOFF", file);
    else
      fputs ("@NTPOFF", file);
    break;
  case UNSPEC_DTPOFF:
    fputs ("@DTPOFF", file);
    break;
  case UNSPEC_GOTNTPOFF:
    if (TARGET_64BIT)
      fputs ("@GOTTPOFF(%rip)", file);
    else
      fputs ("@GOTNTPOFF", file);
    break;
  case UNSPEC_INDNTPOFF:
    fputs ("@INDNTPOFF", file);
    break;
  default:
    output_operand_lossage ("invalid UNSPEC as operand");
    break;
  }
       break;

    default:
      output_operand_lossage ("invalid expression as operand");
    }
}

/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
   We need to emit DTP-relative relocations.  */

void
i386_output_dwarf_dtprel (FILE *file, int size, rtx x)
{
  fputs (ASM_LONG, file);
  output_addr_const (file, x);
  fputs ("@DTPOFF", file);
  switch (size)
    {
    case 4:
      break;
    case 8:
      fputs (", 0", file);
      break;
    default:
      abort ();
   }
}

/* In the name of slightly smaller debug output, and to cater to
   general assembler losage, recognize PIC+GOTOFF and turn it back
   into a direct symbol reference.  */

static rtx
ix86_delegitimize_address (rtx orig_x)
{
  rtx x = orig_x, y;

  if (GET_CODE (x) == MEM)
    x = XEXP (x, 0);

  if (TARGET_64BIT)
    {
      if (GET_CODE (x) != CONST
    || GET_CODE (XEXP (x, 0)) != UNSPEC
    || XINT (XEXP (x, 0), 1) != UNSPEC_GOTPCREL
    || GET_CODE (orig_x) != MEM)
  return orig_x;
      return XVECEXP (XEXP (x, 0), 0, 0);
    }

  if (GET_CODE (x) != PLUS
      || GET_CODE (XEXP (x, 1)) != CONST)
    return orig_x;

  if (GET_CODE (XEXP (x, 0)) == REG
      && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
    /* %ebx + GOT/GOTOFF */
    y = NULL;
  else if (GET_CODE (XEXP (x, 0)) == PLUS)
    {
      /* %ebx + %reg * scale + GOT/GOTOFF */
      y = XEXP (x, 0);
      if (GET_CODE (XEXP (y, 0)) == REG
    && REGNO (XEXP (y, 0)) == PIC_OFFSET_TABLE_REGNUM)
  y = XEXP (y, 1);
      else if (GET_CODE (XEXP (y, 1)) == REG
         && REGNO (XEXP (y, 1)) == PIC_OFFSET_TABLE_REGNUM)
  y = XEXP (y, 0);
      else
  return orig_x;
      if (GET_CODE (y) != REG
    && GET_CODE (y) != MULT
    && GET_CODE (y) != ASHIFT)
  return orig_x;
    }
  else
    return orig_x;

  x = XEXP (XEXP (x, 1), 0);
  if (GET_CODE (x) == UNSPEC
      && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
    || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM)))
    {
      if (y)
  return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0));
      return XVECEXP (x, 0, 0);
    }

  if (GET_CODE (x) == PLUS
      && GET_CODE (XEXP (x, 0)) == UNSPEC
      && GET_CODE (XEXP (x, 1)) == CONST_INT
      && ((XINT (XEXP (x, 0), 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM)
    || (XINT (XEXP (x, 0), 1) == UNSPEC_GOTOFF
        && GET_CODE (orig_x) != MEM)))
    {
      x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1));
      if (y)
  return gen_rtx_PLUS (Pmode, y, x);
      return x;
    }

  return orig_x;
}

static void
put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
        int fp, FILE *file)
{
  const char *suffix;

  if (mode == CCFPmode || mode == CCFPUmode)
    {
      enum rtx_code second_code, bypass_code;
      ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code);
      if (bypass_code != UNKNOWN || second_code != UNKNOWN)
  abort ();
      code = ix86_fp_compare_code_to_integer (code);
      mode = CCmode;
    }
  if (reverse)
    code = reverse_condition (code);

  switch (code)
    {
    case EQ:
      suffix = "e";
      break;
    case NE:
      suffix = "ne";
      break;
    case GT:
      if (mode != CCmode && mode != CCNOmode && mode != CCGCmode)
  abort ();
      suffix = "g";
      break;
    case GTU:
      /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers.
   Those same assemblers have the same but opposite losage on cmov.  */
      if (mode != CCmode)
  abort ();
      suffix = fp ? "nbe" : "a";
      break;
    case LT:
      if (mode == CCNOmode || mode == CCGOCmode)
  suffix = "s";
      else if (mode == CCmode || mode == CCGCmode)
  suffix = "l";
      else
  abort ();
      break;
    case LTU:
      if (mode != CCmode)
  abort ();
      suffix = "b";
      break;
    case GE:
      if (mode == CCNOmode || mode == CCGOCmode)
  suffix = "ns";
      else if (mode == CCmode || mode == CCGCmode)
  suffix = "ge";
      else
  abort ();
      break;
    case GEU:
      /* ??? As above.  */
      if (mode != CCmode)
  abort ();
      suffix = fp ? "nb" : "ae";
      break;
    case LE:
      if (mode != CCmode && mode != CCGCmode && mode != CCNOmode)
  abort ();
      suffix = "le";
      break;
    case LEU:
      if (mode != CCmode)
  abort ();
      suffix = "be";
      break;
    case UNORDERED:
      suffix = fp ? "u" : "p";
      break;
    case ORDERED:
      suffix = fp ? "nu" : "np";
      break;
    default:
      abort ();
    }
  fputs (suffix, file);
}

/* Print the name of register X to FILE based on its machine mode and number.
   If CODE is 'w', pretend the mode is HImode.
   If CODE is 'b', pretend the mode is QImode.
   If CODE is 'k', pretend the mode is SImode.
   If CODE is 'q', pretend the mode is DImode.
   If CODE is 'h', pretend the reg is the `high' byte register.
   If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.  */

void
print_reg (rtx x, int code, FILE *file)
{
  if (REGNO (x) == ARG_POINTER_REGNUM
      || REGNO (x) == FRAME_POINTER_REGNUM
      || REGNO (x) == FLAGS_REG
      || REGNO (x) == FPSR_REG)
    abort ();

  if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
    putc ('%', file);

  if (code == 'w' || MMX_REG_P (x))
    code = 2;
  else if (code == 'b')
    code = 1;
  else if (code == 'k')
    code = 4;
  else if (code == 'q')
    code = 8;
  else if (code == 'y')
    code = 3;
  else if (code == 'h')
    code = 0;
  else
    code = GET_MODE_SIZE (GET_MODE (x));

  /* Irritatingly, AMD extended registers use different naming convention
     from the normal registers.  */
  if (REX_INT_REG_P (x))
    {
      if (!TARGET_64BIT)
  abort ();
      switch (code)
  {
    case 0:
      error ("extended registers have no high halves");
      break;
    case 1:
      fprintf (file, "r%ib", REGNO (x) - FIRST_REX_INT_REG + 8);
      break;
    case 2:
      fprintf (file, "r%iw", REGNO (x) - FIRST_REX_INT_REG + 8);
      break;
    case 4:
      fprintf (file, "r%id", REGNO (x) - FIRST_REX_INT_REG + 8);
      break;
    case 8:
      fprintf (file, "r%i", REGNO (x) - FIRST_REX_INT_REG + 8);
      break;
    default:
      error ("unsupported operand size for extended register");
      break;
  }
      return;
    }
  switch (code)
    {
    case 3:
      if (STACK_TOP_P (x))
  {
    fputs ("st(0)", file);
    break;
  }
      /* FALLTHRU */
    case 8:
    case 4:
    case 12:
      if (! ANY_FP_REG_P (x))
  putc (code == 8 && TARGET_64BIT ? 'r' : 'e', file);
      /* FALLTHRU */
    case 16:
    case 2:
    normal:
      fputs (hi_reg_name[REGNO (x)], file);
      break;
    case 1:
      if (REGNO (x) >= ARRAY_SIZE (qi_reg_name))
  goto normal;
      fputs (qi_reg_name[REGNO (x)], file);
      break;
    case 0:
      if (REGNO (x) >= ARRAY_SIZE (qi_high_reg_name))
  goto normal;
      fputs (qi_high_reg_name[REGNO (x)], file);
      break;
    default:
      abort ();
    }
}

/* Locate some local-dynamic symbol still in use by this function
   so that we can print its name in some tls_local_dynamic_base
   pattern.  */

static const char *
get_some_local_dynamic_name (void)
{
  rtx insn;

  if (cfun->machine->some_ld_name)
    return cfun->machine->some_ld_name;

  for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
    if (INSN_P (insn)
  && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
      return cfun->machine->some_ld_name;

  abort ();
}

static int
get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
{
  rtx x = *px;

  if (GET_CODE (x) == SYMBOL_REF
      && local_dynamic_symbolic_operand (x, Pmode))
    {
      cfun->machine->some_ld_name = XSTR (x, 0);
      return 1;
    }

  return 0;
}

/* Meaning of CODE:
   L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
   C -- print opcode suffix for set/cmov insn.
   c -- like C, but print reversed condition
   F,f -- likewise, but for floating-point.
   O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
        otherwise nothing
   R -- print the prefix for register names.
   z -- print the opcode suffix for the size of the current operand.
   * -- print a star (in certain assembler syntax)
   A -- print an absolute memory reference.
   w -- print the operand as if it's a "word" (HImode) even if it isn't.
   s -- print a shift double count, followed by the assemblers argument
  delimiter.
   b -- print the QImode name of the register for the indicated operand.
  %b0 would print %al if operands[0] is reg 0.
   w --  likewise, print the HImode name of the register.
   k --  likewise, print the SImode name of the register.
   q --  likewise, print the DImode name of the register.
   h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
   y -- print "st(0)" instead of "st" as a register.
   D -- print condition for SSE cmp instruction.
   P -- if PIC, print an @PLT suffix.
   X -- don't print any sort of PIC '@' suffix for a symbol.
   & -- print some in-use local-dynamic symbol name.
   H -- print a memory address offset by 8; used for sse high-parts
 */

void
print_operand (FILE *file, rtx x, int code)
{
  if (code)
    {
      switch (code)
  {
  case '*':
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('*', file);
    return;

  case '&':
    assemble_name (file, get_some_local_dynamic_name ());
    return;

  case 'A':
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('*', file);
    else if (ASSEMBLER_DIALECT == ASM_INTEL)
      {
        /* Intel syntax. For absolute addresses, registers should not
     be surrounded by braces.  */
        if (GET_CODE (x) != REG)
    {
      putc ('[', file);
      PRINT_OPERAND (file, x, 0);
      putc (']', file);
      return;
    }
      }
    else
      abort ();

    PRINT_OPERAND (file, x, 0);
    return;


  case 'L':
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('l', file);
    return;

  case 'W':
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('w', file);
    return;

  case 'B':
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('b', file);
    return;

  case 'Q':
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('l', file);
    return;

  case 'S':
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('s', file);
    return;

  case 'T':
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('t', file);
    return;

  case 'z':
    /* 387 opcodes don't get size suffixes if the operands are
       registers.  */
    if (STACK_REG_P (x))
      return;

    /* Likewise if using Intel opcodes.  */
    if (ASSEMBLER_DIALECT == ASM_INTEL)
      return;

    /* This is the size of op from size of operand.  */
    switch (GET_MODE_SIZE (GET_MODE (x)))
      {
      case 2:
#ifdef HAVE_GAS_FILDS_FISTS
        putc ('s', file);
#endif
        return;

      case 4:
        if (GET_MODE (x) == SFmode)
    {
      putc ('s', file);
      return;
    }
        else
    putc ('l', file);
        return;

      case 12:
      case 16:
        putc ('t', file);
        return;

      case 8:
        if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
    {
#ifdef GAS_MNEMONICS
      putc ('q', file);
#else
      putc ('l', file);
      putc ('l', file);
#endif
    }
        else
          putc ('l', file);
        return;

      default:
        abort ();
      }

  case 'b':
  case 'w':
  case 'k':
  case 'q':
  case 'h':
  case 'y':
  case 'X':
  case 'P':
    break;

  case 's':
    if (GET_CODE (x) == CONST_INT || ! SHIFT_DOUBLE_OMITS_COUNT)
      {
        PRINT_OPERAND (file, x, 0);
        putc (',', file);
      }
    return;

  case 'D':
    /* Little bit of braindamage here.  The SSE compare instructions
       does use completely different names for the comparisons that the
       fp conditional moves.  */
    switch (GET_CODE (x))
      {
      case EQ:
      case UNEQ:
        fputs ("eq", file);
        break;
      case LT:
      case UNLT:
        fputs ("lt", file);
        break;
      case LE:
      case UNLE:
        fputs ("le", file);
        break;
      case UNORDERED:
        fputs ("unord", file);
        break;
      case NE:
      case LTGT:
        fputs ("neq", file);
        break;
      case UNGE:
      case GE:
        fputs ("nlt", file);
        break;
      case UNGT:
      case GT:
        fputs ("nle", file);
        break;
      case ORDERED:
        fputs ("ord", file);
        break;
      default:
        abort ();
        break;
      }
    return;
  case 'O':
#ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
    if (ASSEMBLER_DIALECT == ASM_ATT)
      {
        switch (GET_MODE (x))
    {
    case HImode: putc ('w', file); break;
    case SImode:
    case SFmode: putc ('l', file); break;
    case DImode:
    case DFmode: putc ('q', file); break;
    default: abort ();
    }
        putc ('.', file);
      }
#endif
    return;
  case 'C':
    put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
    return;
  case 'F':
#ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('.', file);
#endif
    put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 1, file);
    return;

    /* Like above, but reverse condition */
  case 'c':
    /* Check to see if argument to %c is really a constant
       and not a condition code which needs to be reversed.  */
    if (!COMPARISON_P (x))
    {
      output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'");
       return;
    }
    put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
    return;
  case 'f':
#ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
    if (ASSEMBLER_DIALECT == ASM_ATT)
      putc ('.', file);
#endif
    put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file);
    return;

  case 'H':
    /* It doesn't actually matter what mode we use here, as we're
       only going to use this for printing.  */
    x = adjust_address_nv (x, DImode, 8);
    break;

  case '+':
    {
      rtx x;

      if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
        return;

      x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
      if (x)
        {
    int pred_val = INTVAL (XEXP (x, 0));

    if (pred_val < REG_BR_PROB_BASE * 45 / 100
        || pred_val > REG_BR_PROB_BASE * 55 / 100)
      {
        int taken = pred_val > REG_BR_PROB_BASE / 2;
        int cputaken = final_forward_branch_p (current_output_insn) == 0;

        /* Emit hints only in the case default branch prediction
           heuristics would fail.  */
        if (taken != cputaken)
          {
      /* We use 3e (DS) prefix for taken branches and
         2e (CS) prefix for not taken branches.  */
      if (taken)
        fputs ("ds ; ", file);
      else
        fputs ("cs ; ", file);
          }
      }
        }
      return;
    }
  default:
      output_operand_lossage ("invalid operand code '%c'", code);
  }
    }

  if (GET_CODE (x) == REG)
    print_reg (x, code, file);

  else if (GET_CODE (x) == MEM)
    {
      /* No `byte ptr' prefix for call instructions.  */
      if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
  {
    const char * size;
    switch (GET_MODE_SIZE (GET_MODE (x)))
      {
      case 1: size = "BYTE"; break;
      case 2: size = "WORD"; break;
      case 4: size = "DWORD"; break;
      case 8: size = "QWORD"; break;
      case 12: size = "XWORD"; break;
      case 16: size = "XMMWORD"; break;
      default:
        abort ();
      }

    /* Check for explicit size override (codes 'b', 'w' and 'k')  */
    if (code == 'b')
      size = "BYTE";
    else if (code == 'w')
      size = "WORD";
    else if (code == 'k')
      size = "DWORD";

    fputs (size, file);
    fputs (" PTR ", file);
  }

      x = XEXP (x, 0);
      /* Avoid (%rip) for call operands.  */
      if (CONSTANT_ADDRESS_P (x) && code == 'P'
         && GET_CODE (x) != CONST_INT)
  output_addr_const (file, x);
      else if (this_is_asm_operands && ! address_operand (x, VOIDmode))
  output_operand_lossage ("invalid constraints for operand");
      else
  output_address (x);
    }

  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
    {
      REAL_VALUE_TYPE r;
      long l;

      REAL_VALUE_FROM_CONST_DOUBLE (r, x);
      REAL_VALUE_TO_TARGET_SINGLE (r, l);

      if (ASSEMBLER_DIALECT == ASM_ATT)
  putc ('$', file);
      fprintf (file, "0x%08lx", l);
    }

  /* These float cases don't actually occur as immediate operands.  */
  else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
    {
      char dstr[30];

      real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
      fprintf (file, "%s", dstr);
    }

  else if (GET_CODE (x) == CONST_DOUBLE
     && GET_MODE (x) == XFmode)
    {
      char dstr[30];

      real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x), sizeof (dstr), 0, 1);
      fprintf (file, "%s", dstr);
    }

  else
    {
      /* We have patterns that allow zero sets of memory, for instance.
   In 64-bit mode, we should probably support all 8-byte vectors,
   since we can in fact encode that into an immediate.  */
      if (GET_CODE (x) == CONST_VECTOR)
  {
    if (x == CONST0_RTX (GET_MODE (x)))
      x = const0_rtx;
    else
      abort ();
  }

      if (code != 'P')
  {
    if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
      {
        if (ASSEMBLER_DIALECT == ASM_ATT)
    putc ('$', file);
      }
    else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
       || GET_CODE (x) == LABEL_REF)
      {
        if (ASSEMBLER_DIALECT == ASM_ATT)
    putc ('$', file);
        else
    fputs ("OFFSET FLAT:", file);
      }
  }
      if (GET_CODE (x) == CONST_INT)
  fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
      else if (flag_pic)
  output_pic_addr_const (file, x, code);
      else
  output_addr_const (file, x);
    }
}

/* Print a memory operand whose address is ADDR.  */

void
print_operand_address (FILE *file, rtx addr)
{
  struct ix86_address parts;
  rtx base, index, disp;
  int scale;

  if (! ix86_decompose_address (addr, &parts))
    abort ();

  base = parts.base;
  index = parts.index;
  disp = parts.disp;
  scale = parts.scale;

  switch (parts.seg)
    {
    case SEG_DEFAULT:
      break;
    case SEG_FS:
    case SEG_GS:
      if (USER_LABEL_PREFIX[0] == 0)
  putc ('%', file);
      fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
      break;
    default:
      abort ();
    }

  if (!base && !index)
    {
      /* Displacement only requires special attention.  */

      if (GET_CODE (disp) == CONST_INT)
  {
    if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
      {
        if (USER_LABEL_PREFIX[0] == 0)
    putc ('%', file);
        fputs ("ds:", file);
      }
    fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
  }
      else if (flag_pic)
  output_pic_addr_const (file, disp, 0);
      else
  output_addr_const (file, disp);

      /* Use one byte shorter RIP relative addressing for 64bit mode.  */
      if (TARGET_64BIT
    && ((GET_CODE (disp) == SYMBOL_REF
         && ! tls_symbolic_operand (disp, GET_MODE (disp)))
        || GET_CODE (disp) == LABEL_REF
        || (GET_CODE (disp) == CONST
      && GET_CODE (XEXP (disp, 0)) == PLUS
      && (GET_CODE (XEXP (XEXP (disp, 0), 0)) == SYMBOL_REF
          || GET_CODE (XEXP (XEXP (disp, 0), 0)) == LABEL_REF)
      && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)))
  fputs ("(%rip)", file);
    }
  else
    {
      if (ASSEMBLER_DIALECT == ASM_ATT)
  {
    if (disp)
      {
        if (flag_pic)
    output_pic_addr_const (file, disp, 0);
        else if (GET_CODE (disp) == LABEL_REF)
    output_asm_label (disp);
        else
    output_addr_const (file, disp);
      }

    putc ('(', file);
    if (base)
      print_reg (base, 0, file);
    if (index)
      {
        putc (',', file);
        print_reg (index, 0, file);
        if (scale != 1)
    fprintf (file, ",%d", scale);
      }
    putc (')', file);
  }
      else
  {
    rtx offset = NULL_RTX;

    if (disp)
      {
        /* Pull out the offset of a symbol; print any symbol itself.  */
        if (GET_CODE (disp) == CONST
      && GET_CODE (XEXP (disp, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
    {
      offset = XEXP (XEXP (disp, 0), 1);
      disp = gen_rtx_CONST (VOIDmode,
          XEXP (XEXP (disp, 0), 0));
    }

        if (flag_pic)
    output_pic_addr_const (file, disp, 0);
        else if (GET_CODE (disp) == LABEL_REF)
    output_asm_label (disp);
        else if (GET_CODE (disp) == CONST_INT)
    offset = disp;
        else
    output_addr_const (file, disp);
      }

    putc ('[', file);
    if (base)
      {
        print_reg (base, 0, file);
        if (offset)
    {
      if (INTVAL (offset) >= 0)
        putc ('+', file);
      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
    }
      }
    else if (offset)
      fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
    else
      putc ('0', file);

    if (index)
      {
        putc ('+', file);
        print_reg (index, 0, file);
        if (scale != 1)
    fprintf (file, "*%d", scale);
      }
    putc (']', file);
  }
    }
}

bool
output_addr_const_extra (FILE *file, rtx x)
{
  rtx op;

  if (GET_CODE (x) != UNSPEC)
    return false;

  op = XVECEXP (x, 0, 0);
  switch (XINT (x, 1))
    {
    case UNSPEC_GOTTPOFF:
      output_addr_const (file, op);
      /* FIXME: This might be @TPOFF in Sun ld.  */
      fputs ("@GOTTPOFF", file);
      break;
    case UNSPEC_TPOFF:
      output_addr_const (file, op);
      fputs ("@TPOFF", file);
      break;
    case UNSPEC_NTPOFF:
      output_addr_const (file, op);
      if (TARGET_64BIT)
  fputs ("@TPOFF", file);
      else
  fputs ("@NTPOFF", file);
      break;
    case