00001 /* 00002 * Copyright 2003, 2004, 2005, 2006 PathScale, Inc. All Rights Reserved. 00003 */ 00004 00005 /* Opcode table header for m680[01234]0/m6888[12]/m68851. 00006 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, 00007 2003, 2004 Free Software Foundation, Inc. 00008 00009 This file is part of GDB, GAS, and the GNU binutils. 00010 00011 GDB, GAS, and the GNU binutils are free software; you can redistribute 00012 them and/or modify them under the terms of the GNU General Public 00013 License as published by the Free Software Foundation; either version 00014 1, or (at your option) any later version. 00015 00016 GDB, GAS, and the GNU binutils are distributed in the hope that they 00017 will be useful, but WITHOUT ANY WARRANTY; without even the implied 00018 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 00019 the GNU General Public License for more details. 00020 00021 You should have received a copy of the GNU General Public License 00022 along with this file; see the file COPYING. If not, write to the Free 00023 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 00024 02111-1307, USA. */ 00025 00026 /* These are used as bit flags for the arch field in the m68k_opcode 00027 structure. */ 00028 #define _m68k_undef 0 00029 #define m68000 0x001 00030 #define m68008 m68000 /* Synonym for -m68000. otherwise unused. */ 00031 #define m68010 0x002 00032 #define m68020 0x004 00033 #define m68030 0x008 00034 #define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences; 00035 gas will deal with the few differences. */ 00036 #define m68040 0x010 00037 /* There is no 68050. */ 00038 #define m68060 0x020 00039 #define m68881 0x040 00040 #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ 00041 #define m68851 0x080 00042 #define cpu32 0x100 /* e.g., 68332 */ 00043 00044 #define mcfmac 0x200 /* ColdFire MAC. */ 00045 #define mcfemac 0x400 /* ColdFire EMAC. */ 00046 #define cfloat 0x800 /* ColdFire FPU. */ 00047 #define mcfhwdiv 0x1000 /* ColdFire hardware divide. */ 00048 00049 #define mcfisa_a 0x2000 /* ColdFire ISA_A. */ 00050 #define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */ 00051 #define mcfisa_b 0x8000 /* ColdFire ISA_B. */ 00052 #define mcfusp 0x10000 /* ColdFire USP instructions. */ 00053 00054 #define mcf5200 0x20000 00055 #define mcf5206e 0x40000 00056 #define mcf521x 0x80000 00057 #define mcf5249 0x100000 00058 #define mcf528x 0x200000 00059 #define mcf5307 0x400000 00060 #define mcf5407 0x800000 00061 #define mcf5470 0x1000000 00062 #define mcf5480 0x2000000 00063 00064 /* Handy aliases. */ 00065 #define m68040up (m68040 | m68060) 00066 #define m68030up (m68030 | m68040up) 00067 #define m68020up (m68020 | m68030up) 00068 #define m68010up (m68010 | cpu32 | m68020up) 00069 #define m68000up (m68000 | m68010up) 00070 00071 #define mfloat (m68881 | m68882 | m68040 | m68060) 00072 #define mmmu (m68851 | m68030 | m68040 | m68060) 00073 00074 /* The structure used to hold information for an opcode. */ 00075 00076 struct m68k_opcode 00077 { 00078 /* The opcode name. */ 00079 const char *name; 00080 /* The pseudo-size of the instruction(in bytes). Used to determine 00081 number of bytes necessary to disassemble the instruction. */ 00082 unsigned int size; 00083 /* The opcode itself. */ 00084 unsigned long opcode; 00085 /* The mask used by the disassembler. */ 00086 unsigned long match; 00087 /* The arguments. */ 00088 const char *args; 00089 /* The architectures which support this opcode. */ 00090 unsigned int arch; 00091 }; 00092 00093 /* The structure used to hold information for an opcode alias. */ 00094 00095 struct m68k_opcode_alias 00096 { 00097 /* The alias name. */ 00098 const char *alias; 00099 /* The instruction for which this is an alias. */ 00100 const char *primary; 00101 }; 00102 00103 /* We store four bytes of opcode for all opcodes because that is the 00104 most any of them need. The actual length of an instruction is 00105 always at least 2 bytes, and is as much longer as necessary to hold 00106 the operands it has. 00107 00108 The match field is a mask saying which bits must match particular 00109 opcode in order for an instruction to be an instance of that 00110 opcode. 00111 00112 The args field is a string containing two characters for each 00113 operand of the instruction. The first specifies the kind of 00114 operand; the second, the place it is stored. */ 00115 00116 /* Kinds of operands: 00117 Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+- 00118 00119 D data register only. Stored as 3 bits. 00120 A address register only. Stored as 3 bits. 00121 a address register indirect only. Stored as 3 bits. 00122 R either kind of register. Stored as 4 bits. 00123 r either kind of register indirect only. Stored as 4 bits. 00124 At the moment, used only for cas2 instruction. 00125 F floating point coprocessor register only. Stored as 3 bits. 00126 O an offset (or width): immediate data 0-31 or data register. 00127 Stored as 6 bits in special format for BF... insns. 00128 + autoincrement only. Stored as 3 bits (number of the address register). 00129 - autodecrement only. Stored as 3 bits (number of the address register). 00130 Q quick immediate data. Stored as 3 bits. 00131 This matches an immediate operand only when value is in range 1 .. 8. 00132 M moveq immediate data. Stored as 8 bits. 00133 This matches an immediate operand only when value is in range -128..127 00134 T trap vector immediate data. Stored as 4 bits. 00135 00136 k K-factor for fmove.p instruction. Stored as a 7-bit constant or 00137 a three bit register offset, depending on the field type. 00138 00139 # immediate data. Stored in special places (b, w or l) 00140 which say how many bits to store. 00141 ^ immediate data for floating point instructions. Special places 00142 are offset by 2 bytes from '#'... 00143 B pc-relative address, converted to an offset 00144 that is treated as immediate data. 00145 d displacement and register. Stores the register as 3 bits 00146 and stores the displacement in the entire second word. 00147 00148 C the CCR. No need to store it; this is just for filtering validity. 00149 S the SR. No need to store, just as with CCR. 00150 U the USP. No need to store, just as with CCR. 00151 E the MAC ACC. No need to store, just as with CCR. 00152 e the EMAC ACC[0123]. 00153 G the MAC/EMAC MACSR. No need to store, just as with CCR. 00154 g the EMAC ACCEXT{01,23}. 00155 H the MASK. No need to store, just as with CCR. 00156 i the MAC/EMAC scale factor. 00157 00158 I Coprocessor ID. Not printed if 1. The Coprocessor ID is always 00159 extracted from the 'd' field of word one, which means that an extended 00160 coprocessor opcode can be skipped using the 'i' place, if needed. 00161 00162 s System Control register for the floating point coprocessor. 00163 00164 J Misc register for movec instruction, stored in 'j' format. 00165 Possible values: 00166 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10] 00167 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10] 00168 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf] 00169 0x003 TC MMU Translation Control [60, 40] 00170 0x004 ITT0 Instruction Transparent 00171 Translation reg 0 [60, 40] 00172 0x005 ITT1 Instruction Transparent 00173 Translation reg 1 [60, 40] 00174 0x006 DTT0 Data Transparent 00175 Translation reg 0 [60, 40] 00176 0x007 DTT1 Data Transparent 00177 Translation reg 1 [60, 40] 00178 0x008 BUSCR Bus Control Register [60] 00179 0x800 USP User Stack Pointer [60, 40, 30, 20, 10] 00180 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf] 00181 0x802 CAAR Cache Address Register [ 30, 20] 00182 0x803 MSP Master Stack Pointer [ 40, 30, 20] 00183 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20] 00184 0x805 MMUSR MMU Status reg [ 40] 00185 0x806 URP User Root Pointer [60, 40] 00186 0x807 SRP Supervisor Root Pointer [60, 40] 00187 0x808 PCR Processor Configuration reg [60] 00188 0xC00 ROMBAR ROM Base Address Register [520X] 00189 0xC04 RAMBAR0 RAM Base Address Register 0 [520X] 00190 0xC05 RAMBAR1 RAM Base Address Register 0 [520X] 00191 0xC0F MBAR0 RAM Base Address Register 0 [520X] 00192 0xC04 FLASHBAR FLASH Base Address Register [mcf528x] 00193 0xC05 RAMBAR Static RAM Base Address Register [mcf528x] 00194 00195 L Register list of the type d0-d7/a0-a7 etc. 00196 (New! Improved! Can also hold fp0-fp7, as well!) 00197 The assembler tries to see if the registers match the insn by 00198 looking at where the insn wants them stored. 00199 00200 l Register list like L, but with all the bits reversed. 00201 Used for going the other way. . . 00202 00203 c cache identifier which may be "nc" for no cache, "ic" 00204 for instruction cache, "dc" for data cache, or "bc" 00205 for both caches. Used in cinv and cpush. Always 00206 stored in position "d". 00207 00208 u Any register, with ``upper'' or ``lower'' specification. Used 00209 in the mac instructions with size word. 00210 00211 The remainder are all stored as 6 bits using an address mode and a 00212 register number; they differ in which addressing modes they match. 00213 00214 * all (modes 0-6,7.0-4) 00215 ~ alterable memory (modes 2-6,7.0,7.1) 00216 (not 0,1,7.2-4) 00217 % alterable (modes 0-6,7.0,7.1) 00218 (not 7.2-4) 00219 ; data (modes 0,2-6,7.0-4) 00220 (not 1) 00221 @ data, but not immediate (modes 0,2-6,7.0-3) 00222 (not 1,7.4) 00223 ! control (modes 2,5,6,7.0-3) 00224 (not 0,1,3,4,7.4) 00225 & alterable control (modes 2,5,6,7.0,7.1) 00226 (not 0,1,3,4,7.2-4) 00227 $ alterable data (modes 0,2-6,7.0,7.1) 00228 (not 1,7.2-4) 00229 ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) 00230 (not 1,3,4,7.2-4) 00231 / control, or data register (modes 0,2,5,6,7.0-3) 00232 (not 1,3,4,7.4) 00233 > *save operands (modes 2,4,5,6,7.0,7.1) 00234 (not 0,1,3,7.2-4) 00235 < *restore operands (modes 2,3,5,6,7.0-3) 00236 (not 0,1,4,7.4) 00237 00238 coldfire move operands: 00239 m (modes 0-4) 00240 n (modes 5,7.2) 00241 o (modes 6,7.0,7.1,7.3,7.4) 00242 p (modes 0-5) 00243 00244 coldfire bset/bclr/btst/mulsl/mulul operands: 00245 q (modes 0,2-5) 00246 v (modes 0,2-5,7.0,7.1) 00247 b (modes 0,2-5,7.2) 00248 w (modes 2-5,7.2) 00249 y (modes 2,5) 00250 z (modes 2,5,7.2) 00251 x mov3q immediate operand. 00252 4 (modes 2,3,4,5) 00253 */ 00254 00255 /* For the 68851: */ 00256 /* I didn't use much imagination in choosing the 00257 following codes, so many of them aren't very 00258 mnemonic. -rab 00259 00260 0 32 bit pmmu register 00261 Possible values: 00262 000 TC Translation Control Register (68030, 68851) 00263 00264 1 16 bit pmmu register 00265 111 AC Access Control (68851) 00266 00267 2 8 bit pmmu register 00268 100 CAL Current Access Level (68851) 00269 101 VAL Validate Access Level (68851) 00270 110 SCC Stack Change Control (68851) 00271 00272 3 68030-only pmmu registers (32 bit) 00273 010 TT0 Transparent Translation reg 0 00274 (aka Access Control reg 0 -- AC0 -- on 68ec030) 00275 011 TT1 Transparent Translation reg 1 00276 (aka Access Control reg 1 -- AC1 -- on 68ec030) 00277 00278 W wide pmmu registers 00279 Possible values: 00280 001 DRP Dma Root Pointer (68851) 00281 010 SRP Supervisor Root Pointer (68030, 68851) 00282 011 CRP Cpu Root Pointer (68030, 68851) 00283 00284 f function code register (68030, 68851) 00285 0 SFC 00286 1 DFC 00287 00288 V VAL register only (68851) 00289 00290 X BADx, BACx (16 bit) 00291 100 BAD Breakpoint Acknowledge Data (68851) 00292 101 BAC Breakpoint Acknowledge Control (68851) 00293 00294 Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030) 00295 Z PCSR (68851) 00296 00297 | memory (modes 2-6, 7.*) 00298 00299 t address test level (68030 only) 00300 Stored as 3 bits, range 0-7. 00301 Also used for breakpoint instruction now. 00302 00303 */ 00304 00305 /* Places to put an operand, for non-general operands: 00306 Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ 00307 00308 s source, low bits of first word. 00309 d dest, shifted 9 in first word 00310 1 second word, shifted 12 00311 2 second word, shifted 6 00312 3 second word, shifted 0 00313 4 third word, shifted 12 00314 5 third word, shifted 6 00315 6 third word, shifted 0 00316 7 second word, shifted 7 00317 8 second word, shifted 10 00318 9 second word, shifted 5 00319 D store in both place 1 and place 3; for divul and divsl. 00320 B first word, low byte, for branch displacements 00321 W second word (entire), for branch displacements 00322 L second and third words (entire), for branch displacements 00323 (also overloaded for move16) 00324 b second word, low byte 00325 w second word (entire) [variable word/long branch offset for dbra] 00326 W second word (entire) (must be signed 16 bit value) 00327 l second and third word (entire) 00328 g variable branch offset for bra and similar instructions. 00329 The place to store depends on the magnitude of offset. 00330 t store in both place 7 and place 8; for floating point operations 00331 c branch offset for cpBcc operations. 00332 The place to store is word two if bit six of word one is zero, 00333 and words two and three if bit six of word one is one. 00334 i Increment by two, to skip over coprocessor extended operands. Only 00335 works with the 'I' format. 00336 k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number. 00337 Also used for dynamic fmovem instruction. 00338 C floating point coprocessor constant - 7 bits. Also used for static 00339 K-factors... 00340 j Movec register #, stored in 12 low bits of second word. 00341 m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word 00342 and remaining 3 bits of register shifted 9 bits in first word. 00343 Indicate upper/lower in 1 bit shifted 7 bits in second word. 00344 Use with `R' or `u' format. 00345 n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split 00346 with MSB shifted 6 bits in first word and remaining 3 bits of 00347 register shifted 9 bits in first word. No upper/lower 00348 indication is done.) Use with `R' or `u' format. 00349 o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). 00350 Indicate upper/lower in 1 bit shifted 7 bits in second word. 00351 Use with `R' or `u' format. 00352 M For M[S]ACw; 4 bits in low bits of first word. Indicate 00353 upper/lower in 1 bit shifted 6 bits in second word. Use with 00354 `R' or `u' format. 00355 N For M[S]ACw; 4 bits in low bits of second word. Indicate 00356 upper/lower in 1 bit shifted 6 bits in second word. Use with 00357 `R' or `u' format. 00358 h shift indicator (scale factor), 1 bit shifted 10 in second word 00359 00360 Places to put operand, for general operands: 00361 d destination, shifted 6 bits in first word 00362 b source, at low bit of first word, and immediate uses one byte 00363 w source, at low bit of first word, and immediate uses two bytes 00364 l source, at low bit of first word, and immediate uses four bytes 00365 s source, at low bit of first word. 00366 Used sometimes in contexts where immediate is not allowed anyway. 00367 f single precision float, low bit of 1st word, immediate uses 4 bytes 00368 F double precision float, low bit of 1st word, immediate uses 8 bytes 00369 x extended precision float, low bit of 1st word, immediate uses 12 bytes 00370 p packed float, low bit of 1st word, immediate uses 12 bytes 00371 G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) 00372 H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) 00373 F EMAC ACCx 00374 f EMAC ACCy 00375 I MAC/EMAC scale factor 00376 / Like 's', but set 2nd word, bit 5 if trailing_ampersand set 00377 ] first word, bit 10 00378 */ 00379 00380 extern const struct m68k_opcode m68k_opcodes[]; 00381 extern const struct m68k_opcode_alias m68k_opcode_aliases[]; 00382 00383 extern const int m68k_numopcodes, m68k_numaliases; 00384 00385 /* end of m68k-opcode.h */
1.5.6