|
Defines |
| #define | CGEN_ARCH iq2000 |
| #define | CGEN_SYM(s) iq2000/**/_cgen_/**/s |
| #define | HAVE_CPU_IQ2000BF |
| #define | HAVE_CPU_IQ10BF |
| #define | CGEN_INSN_LSB0_P 1 |
| #define | CGEN_MIN_INSN_SIZE 4 |
| #define | CGEN_MAX_INSN_SIZE 4 |
| #define | CGEN_INT_INSN_P 1 |
| #define | CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19 |
| #define | CGEN_MNEMONIC_OPERANDS |
| #define | CGEN_ACTUAL_MAX_IFMT_OPERANDS 8 |
| #define | MAX_ISAS 1 |
| #define | MAX_MACHS ((int) MACH_MAX) |
| #define | CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) |
| #define | MAX_IFLD ((int) IQ2000_F_MAX) |
| #define | CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) |
| #define | MAX_HW ((int) HW_MAX) |
| #define | CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) |
| #define | MAX_OPERANDS 32 |
| #define | MAX_OPERAND_INSTANCES 8 |
| #define | CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) |
Typedefs |
| typedef enum gr_names | GR_NAMES |
| typedef enum opcodes | OPCODES |
| typedef enum q10_opcodes | Q10_OPCODES |
| typedef enum regimm_functions | REGIMM_FUNCTIONS |
| typedef enum functions | FUNCTIONS |
| typedef enum q10s_functions | Q10S_FUNCTIONS |
| typedef enum cop_functions | COP_FUNCTIONS |
| typedef enum cop_cm128_4functions | COP_CM128_4FUNCTIONS |
| typedef enum cop_cm128_3functions | COP_CM128_3FUNCTIONS |
| typedef enum cop2_functions | COP2_FUNCTIONS |
| typedef enum cop3_cam_functions | COP3_CAM_FUNCTIONS |
| typedef enum mach_attr | MACH_ATTR |
| typedef enum isa_attr | ISA_ATTR |
| typedef enum cgen_ifld_attr | CGEN_IFLD_ATTR |
| typedef enum ifield_type | IFIELD_TYPE |
| typedef enum cgen_hw_attr | CGEN_HW_ATTR |
| typedef enum cgen_hw_type | CGEN_HW_TYPE |
| typedef enum cgen_operand_attr | CGEN_OPERAND_ATTR |
| typedef enum cgen_operand_type | CGEN_OPERAND_TYPE |
| typedef enum cgen_insn_attr | CGEN_INSN_ATTR |
Enumerations |
| enum | gr_names {
H_GR_R0 = 0,
H_GR_R1 = 1,
H_GR_R2 = 2,
H_GR_R3 = 3,
H_GR_R4 = 4,
H_GR_R5 = 5,
H_GR_R6 = 6,
H_GR_R7 = 7,
H_GR_R8 = 8,
H_GR_R9 = 9,
H_GR_R10 = 10,
H_GR_R11 = 11,
H_GR_R12 = 12,
H_GR_R13 = 13,
H_GR_R14 = 14,
H_GR_R15 = 15,
H_GR_AC = 13,
H_GR_FP = 14,
H_GR_SP = 15,
H_GR_SP = 1,
H_GR_FP = 2,
H_GR_GR0 = 0,
H_GR_GR1 = 1,
H_GR_GR2 = 2,
H_GR_GR3 = 3,
H_GR_GR4 = 4,
H_GR_GR5 = 5,
H_GR_GR6 = 6,
H_GR_GR7 = 7,
H_GR_GR8 = 8,
H_GR_GR9 = 9,
H_GR_GR10 = 10,
H_GR_GR11 = 11,
H_GR_GR12 = 12,
H_GR_GR13 = 13,
H_GR_GR14 = 14,
H_GR_GR15 = 15,
H_GR_GR16 = 16,
H_GR_GR17 = 17,
H_GR_GR18 = 18,
H_GR_GR19 = 19,
H_GR_GR20 = 20,
H_GR_GR21 = 21,
H_GR_GR22 = 22,
H_GR_GR23 = 23,
H_GR_GR24 = 24,
H_GR_GR25 = 25,
H_GR_GR26 = 26,
H_GR_GR27 = 27,
H_GR_GR28 = 28,
H_GR_GR29 = 29,
H_GR_GR30 = 30,
H_GR_GR31 = 31,
H_GR_GR32 = 32,
H_GR_GR33 = 33,
H_GR_GR34 = 34,
H_GR_GR35 = 35,
H_GR_GR36 = 36,
H_GR_GR37 = 37,
H_GR_GR38 = 38,
H_GR_GR39 = 39,
H_GR_GR40 = 40,
H_GR_GR41 = 41,
H_GR_GR42 = 42,
H_GR_GR43 = 43,
H_GR_GR44 = 44,
H_GR_GR45 = 45,
H_GR_GR46 = 46,
H_GR_GR47 = 47,
H_GR_GR48 = 48,
H_GR_GR49 = 49,
H_GR_GR50 = 50,
H_GR_GR51 = 51,
H_GR_GR52 = 52,
H_GR_GR53 = 53,
H_GR_GR54 = 54,
H_GR_GR55 = 55,
H_GR_GR56 = 56,
H_GR_GR57 = 57,
H_GR_GR58 = 58,
H_GR_GR59 = 59,
H_GR_GR60 = 60,
H_GR_GR61 = 61,
H_GR_GR62 = 62,
H_GR_GR63 = 63,
H_GR_R0 = 0,
H_GR__0 = 0,
H_GR_R1 = 1,
H_GR__1 = 1,
H_GR_R2 = 2,
H_GR__2 = 2,
H_GR_R3 = 3,
H_GR__3 = 3,
H_GR_R4 = 4,
H_GR__4 = 4,
H_GR_R5 = 5,
H_GR__5 = 5,
H_GR_R6 = 6,
H_GR__6 = 6,
H_GR_R7 = 7,
H_GR__7 = 7,
H_GR_R8 = 8,
H_GR__8 = 8,
H_GR_R9 = 9,
H_GR__9 = 9,
H_GR_R10 = 10,
H_GR__10 = 10,
H_GR_R11 = 11,
H_GR__11 = 11,
H_GR_R12 = 12,
H_GR__12 = 12,
H_GR_R13 = 13,
H_GR__13 = 13,
H_GR_R14 = 14,
H_GR__14 = 14,
H_GR_R15 = 15,
H_GR__15 = 15,
H_GR_R16 = 16,
H_GR__16 = 16,
H_GR_R17 = 17,
H_GR__17 = 17,
H_GR_R18 = 18,
H_GR__18 = 18,
H_GR_R19 = 19,
H_GR__19 = 19,
H_GR_R20 = 20,
H_GR__20 = 20,
H_GR_R21 = 21,
H_GR__21 = 21,
H_GR_R22 = 22,
H_GR__22 = 22,
H_GR_R23 = 23,
H_GR__23 = 23,
H_GR_R24 = 24,
H_GR__24 = 24,
H_GR_R25 = 25,
H_GR__25 = 25,
H_GR_R26 = 26,
H_GR__26 = 26,
H_GR_R27 = 27,
H_GR__27 = 27,
H_GR_R28 = 28,
H_GR__28 = 28,
H_GR_R29 = 29,
H_GR__29 = 29,
H_GR_R30 = 30,
H_GR__30 = 30,
H_GR_R31 = 31,
H_GR__31 = 31,
H_GR_FP = 13,
H_GR_LR = 14,
H_GR_SP = 15,
H_GR_R0 = 0,
H_GR_R1 = 1,
H_GR_R2 = 2,
H_GR_R3 = 3,
H_GR_R4 = 4,
H_GR_R5 = 5,
H_GR_R6 = 6,
H_GR_R7 = 7,
H_GR_R8 = 8,
H_GR_R9 = 9,
H_GR_R10 = 10,
H_GR_R11 = 11,
H_GR_R12 = 12,
H_GR_R13 = 13,
H_GR_R14 = 14,
H_GR_R15 = 15,
H_GR_R0 = 0,
H_GR_R1 = 1,
H_GR_R2 = 2,
H_GR_R3 = 3,
H_GR_R4 = 4,
H_GR_R5 = 5,
H_GR_R6 = 6,
H_GR_R7 = 7,
H_GR_R8 = 8,
H_GR_R9 = 9,
H_GR_R10 = 10,
H_GR_R11 = 11,
H_GR_R12 = 12,
H_GR_R13 = 13,
H_GR_R14 = 14,
H_GR_R15 = 15,
H_GR_PSW = 14,
H_GR_SP = 15
} |
| enum | opcodes {
OP_SPECIAL = 0,
OP_REGIMM = 1,
OP_J = 2,
OP_JAL = 3,
OP_BEQ = 4,
OP_BNE = 5,
OP_BLEZ = 6,
OP_BGTZ = 7,
OP_ADDI = 8,
OP_ADDIU = 9,
OP_SLTI = 10,
OP_SLTIU = 11,
OP_ANDI = 12,
OP_ORI = 13,
OP_XORI = 14,
OP_LUI = 15,
OP_COP0 = 16,
OP_COP1 = 17,
OP_COP2 = 18,
OP_COP3 = 19,
OP_BEQL = 20,
OP_BNEL = 21,
OP_BLEZL = 22,
OP_BGTZL = 23,
OP_BMB0 = 24,
OP_BMB1 = 25,
OP_BMB2 = 26,
OP_BMB3 = 27,
OP_BBI = 28,
OP_BBV = 29,
OP_BBIN = 30,
OP_BBVN = 31,
OP_LB = 32,
OP_LH = 33,
OP_LW = 35,
OP_LBU = 36,
OP_LHU = 37,
OP_RAM = 39,
OP_SB = 40,
OP_SH = 41,
OP_SW = 43,
OP_ANDOI = 44,
OP_BMB = 45,
OP_ORUI = 47,
OP_LDW = 48,
OP_SDW = 56,
OP_ANDOUI = 63
} |
| enum | q10_opcodes {
OP10_BMB = 6,
OP10_ORUI = 15,
OP10_BMBL = 22,
OP10_ANDOUI = 47,
OP10_BBIL = 60,
OP10_BBVL = 61,
OP10_BBINL = 62,
OP10_BBVNL = 63
} |
| enum | regimm_functions {
FUNC_BLTZ = 0,
FUNC_BGEZ = 1,
FUNC_BLTZL = 2,
FUNC_BGEZL = 3,
FUNC_BLEZ = 4,
FUNC_BGTZ = 5,
FUNC_BLEZL = 6,
FUNC_BGTZL = 7,
FUNC_BRI = 8,
FUNC_BRV = 9,
FUNC_BCTX = 12,
FUNC_BLTZAL = 16,
FUNC_BGEZAL = 17,
FUNC_BLTZALL = 18,
FUNC_BGEZALL = 19,
FUNC_BLEZAL = 20,
FUNC_BGTZAL = 21,
FUNC_BLEZALL = 22,
FUNC_BGTZALL = 23
} |
| enum | functions {
FUNC_SLL = 0,
FUNC_SLMV = 1,
FUNC_SRL = 2,
FUNC_SRA = 3,
FUNC_SLLV = 4,
FUNC_SRMV = 5,
FUNC_SRLV = 6,
FUNC_SRAV = 7,
FUNC_JR = 8,
FUNC_JALR = 9,
FUNC_JCR = 10,
FUNC_SYSCALL = 12,
FUNC_BREAK = 13,
FUNC_SLEEP = 14,
FUNC_ADD = 32,
FUNC_ADDU = 33,
FUNC_SUB = 34,
FUNC_SUBU = 35,
FUNC_AND = 36,
FUNC_OR = 37,
FUNC_XOR = 38,
FUNC_NOR = 39,
FUNC_ADO16 = 41,
FUNC_SLT = 42,
FUNC_SLTU = 43,
FUNC_MRGB = 45
} |
| enum | q10s_functions { FUNC10_YIELD = 14,
FUNC10_CNT1S = 46
} |
| enum | cop_functions {
FUNC10_CFC = 0,
FUNC10_LOCK = 1,
FUNC10_CTC = 2,
FUNC10_UNLK = 3,
FUNC10_SWRD = 4,
FUNC10_SWRDL = 5,
FUNC10_SWWR = 6,
FUNC10_SWWRU = 7,
FUNC10_RBA = 8,
FUNC10_RBAL = 9,
FUNC10_RBAR = 10,
FUNC10_DWRD = 12,
FUNC10_DWRDL = 13,
FUNC10_WBA = 16,
FUNC10_WBAU = 17,
FUNC10_WBAC = 18,
FUNC10_CRC32 = 20,
FUNC10_CRC32B = 21,
FUNC10_MCID = 32,
FUNC10_DBD = 33,
FUNC10_DBA = 34,
FUNC10_DPWT = 35,
FUNC10_AVAIL = 36,
FUNC10_FREE = 37,
FUNC10_CHKHDR = 38,
FUNC10_TSTOD = 39,
FUNC10_PKRLA = 40,
FUNC10_PKRLAU = 41,
FUNC10_PKRLAH = 42,
FUNC10_PKRLAC = 43,
FUNC10_CMPHDR = 44,
FUNC10_CM64RS = 0,
FUNC10_CM64RD = 1,
FUNC10_CM64RI = 4,
FUNC10_CM64CLR = 5,
FUNC10_CM64SS = 8,
FUNC10_CM64SD = 9,
FUNC10_CM64SI = 12,
FUNC10_CM64RA = 16,
FUNC10_CM64RIA2 = 20,
FUNC10_CM128RIA2 = 21,
FUNC10_CM64SA = 24,
FUNC10_CM64SIA2 = 28,
FUNC10_CM128SIA2 = 29,
FUNC10_CM32RS = 32,
FUNC10_CM32RD = 33,
FUNC10_CM32XOR = 34,
FUNC10_CM32ANDN = 35,
FUNC10_CM32RI = 36,
FUNC10_CM128VSA = 38,
FUNC10_CM32SS = 40,
FUNC10_CM32SD = 41,
FUNC10_CM32OR = 42,
FUNC10_CM32AND = 43,
FUNC10_CM32SI = 44,
FUNC10_CM32RA = 48,
FUNC10_CM32SA = 56
} |
| enum | cop_cm128_4functions { FUNC10_CM128RIA3 = 4,
FUNC10_CM128SIA3 = 6
} |
| enum | cop_cm128_3functions { FUNC10_CM128RIA4 = 6,
FUNC10_CM128SIA4 = 7
} |
| enum | cop2_functions {
FUNC10_PKRLI = 0,
FUNC10_PKRLIU = 1,
FUNC10_PKRLIH = 2,
FUNC10_PKRLIC = 3,
FUNC10_RBIR = 1,
FUNC10_RBI = 2,
FUNC10_RBIL = 3,
FUNC10_WBIC = 5,
FUNC10_WBI = 6,
FUNC10_WBIU = 7
} |
| enum | cop3_cam_functions { FUNC10_CAM36 = 16,
FUNC10_CAM72 = 17,
FUNC10_CAM144 = 18,
FUNC10_CAM288 = 19
} |
| enum | mach_attr {
MACH_BASE,
MACH_FR30,
MACH_MAX,
MACH_BASE,
MACH_FRV,
MACH_FR550,
MACH_FR500,
MACH_FR450,
MACH_FR400,
MACH_TOMCAT,
MACH_SIMPLE,
MACH_MAX,
MACH_BASE,
MACH_IP2022,
MACH_IP2022EXT,
MACH_MAX,
MACH_BASE,
MACH_IQ2000,
MACH_IQ10,
MACH_MAX,
MACH_BASE,
MACH_M32R,
MACH_M32RX,
MACH_M32R2,
MACH_MAX,
MACH_BASE,
MACH_OPENRISC,
MACH_OR1300,
MACH_MAX,
MACH_BASE,
MACH_XSTORMY16,
MACH_MAX
} |
| enum | isa_attr {
ISA_FR30,
ISA_MAX,
ISA_FRV,
ISA_MAX,
ISA_IP2K,
ISA_MAX,
ISA_IQ2000,
ISA_MAX,
ISA_M32R,
ISA_MAX,
ISA_OR32,
ISA_MAX,
ISA_XSTORMY16,
ISA_MAX
} |
| enum | cgen_ifld_attr {
CGEN_IFLD_VIRTUAL,
CGEN_IFLD_PCREL_ADDR,
CGEN_IFLD_ABS_ADDR,
CGEN_IFLD_RESERVED,
CGEN_IFLD_SIGN_OPT,
CGEN_IFLD_SIGNED,
CGEN_IFLD_END_BOOLS,
CGEN_IFLD_START_NBOOLS = 31,
CGEN_IFLD_MACH,
CGEN_IFLD_END_NBOOLS,
CGEN_IFLD_VIRTUAL,
CGEN_IFLD_PCREL_ADDR,
CGEN_IFLD_ABS_ADDR,
CGEN_IFLD_RESERVED,
CGEN_IFLD_SIGN_OPT,
CGEN_IFLD_SIGNED,
CGEN_IFLD_END_BOOLS,
CGEN_IFLD_START_NBOOLS = 31,
CGEN_IFLD_MACH,
CGEN_IFLD_END_NBOOLS,
CGEN_IFLD_VIRTUAL,
CGEN_IFLD_PCREL_ADDR,
CGEN_IFLD_ABS_ADDR,
CGEN_IFLD_RESERVED,
CGEN_IFLD_SIGN_OPT,
CGEN_IFLD_SIGNED,
CGEN_IFLD_END_BOOLS,
CGEN_IFLD_START_NBOOLS = 31,
CGEN_IFLD_MACH,
CGEN_IFLD_END_NBOOLS,
CGEN_IFLD_VIRTUAL,
CGEN_IFLD_PCREL_ADDR,
CGEN_IFLD_ABS_ADDR,
CGEN_IFLD_RESERVED,
CGEN_IFLD_SIGN_OPT,
CGEN_IFLD_SIGNED,
CGEN_IFLD_END_BOOLS,
CGEN_IFLD_START_NBOOLS = 31,
CGEN_IFLD_MACH,
CGEN_IFLD_END_NBOOLS,
CGEN_IFLD_VIRTUAL,
CGEN_IFLD_PCREL_ADDR,
CGEN_IFLD_ABS_ADDR,
CGEN_IFLD_RESERVED,
CGEN_IFLD_SIGN_OPT,
CGEN_IFLD_SIGNED,
CGEN_IFLD_RELOC,
CGEN_IFLD_END_BOOLS,
CGEN_IFLD_START_NBOOLS = 31,
CGEN_IFLD_MACH,
CGEN_IFLD_END_NBOOLS,
CGEN_IFLD_VIRTUAL,
CGEN_IFLD_PCREL_ADDR,
CGEN_IFLD_ABS_ADDR,
CGEN_IFLD_RESERVED,
CGEN_IFLD_SIGN_OPT,
CGEN_IFLD_SIGNED,
CGEN_IFLD_END_BOOLS,
CGEN_IFLD_START_NBOOLS = 31,
CGEN_IFLD_MACH,
CGEN_IFLD_END_NBOOLS,
CGEN_IFLD_VIRTUAL,
CGEN_IFLD_PCREL_ADDR,
CGEN_IFLD_ABS_ADDR,
CGEN_IFLD_RESERVED,
CGEN_IFLD_SIGN_OPT,
CGEN_IFLD_SIGNED,
CGEN_IFLD_END_BOOLS,
CGEN_IFLD_START_NBOOLS = 31,
CGEN_IFLD_MACH,
CGEN_IFLD_END_NBOOLS
} |
| enum | ifield_type {
FR30_F_NIL,
FR30_F_ANYOF,
FR30_F_OP1,
FR30_F_OP2,
FR30_F_OP3,
FR30_F_OP4,
FR30_F_OP5,
FR30_F_CC,
FR30_F_CCC,
FR30_F_RJ,
FR30_F_RI,
FR30_F_RS1,
FR30_F_RS2,
FR30_F_RJC,
FR30_F_RIC,
FR30_F_CRJ,
FR30_F_CRI,
FR30_F_U4,
FR30_F_U4C,
FR30_F_I4,
FR30_F_M4,
FR30_F_U8,
FR30_F_I8,
FR30_F_I20_4,
FR30_F_I20_16,
FR30_F_I20,
FR30_F_I32,
FR30_F_UDISP6,
FR30_F_DISP8,
FR30_F_DISP9,
FR30_F_DISP10,
FR30_F_S10,
FR30_F_U10,
FR30_F_REL9,
FR30_F_DIR8,
FR30_F_DIR9,
FR30_F_DIR10,
FR30_F_REL12,
FR30_F_REGLIST_HI_ST,
FR30_F_REGLIST_LOW_ST,
FR30_F_REGLIST_HI_LD,
FR30_F_REGLIST_LOW_LD,
FR30_F_MAX,
FRV_F_NIL,
FRV_F_ANYOF,
FRV_F_PACK,
FRV_F_OP,
FRV_F_OPE1,
FRV_F_OPE2,
FRV_F_OPE3,
FRV_F_OPE4,
FRV_F_GRI,
FRV_F_GRJ,
FRV_F_GRK,
FRV_F_FRI,
FRV_F_FRJ,
FRV_F_FRK,
FRV_F_CPRI,
FRV_F_CPRJ,
FRV_F_CPRK,
FRV_F_ACCGI,
FRV_F_ACCGK,
FRV_F_ACC40SI,
FRV_F_ACC40UI,
FRV_F_ACC40SK,
FRV_F_ACC40UK,
FRV_F_CRI,
FRV_F_CRJ,
FRV_F_CRK,
FRV_F_CCI,
FRV_F_CRJ_INT,
FRV_F_CRJ_FLOAT,
FRV_F_ICCI_1,
FRV_F_ICCI_2,
FRV_F_ICCI_3,
FRV_F_FCCI_1,
FRV_F_FCCI_2,
FRV_F_FCCI_3,
FRV_F_FCCK,
FRV_F_EIR,
FRV_F_S10,
FRV_F_S12,
FRV_F_D12,
FRV_F_U16,
FRV_F_S16,
FRV_F_S6,
FRV_F_S6_1,
FRV_F_U6,
FRV_F_S5,
FRV_F_U12_H,
FRV_F_U12_L,
FRV_F_U12,
FRV_F_INT_CC,
FRV_F_FLT_CC,
FRV_F_COND,
FRV_F_CCOND,
FRV_F_HINT,
FRV_F_LI,
FRV_F_LOCK,
FRV_F_DEBUG,
FRV_F_A,
FRV_F_AE,
FRV_F_SPR_H,
FRV_F_SPR_L,
FRV_F_SPR,
FRV_F_LABEL16,
FRV_F_LABELH6,
FRV_F_LABELL18,
FRV_F_LABEL24,
FRV_F_LRAE,
FRV_F_LRAD,
FRV_F_LRAS,
FRV_F_TLBPROPX,
FRV_F_TLBPRL,
FRV_F_ICCI_1_NULL,
FRV_F_ICCI_2_NULL,
FRV_F_ICCI_3_NULL,
FRV_F_FCCI_1_NULL,
FRV_F_FCCI_2_NULL,
FRV_F_FCCI_3_NULL,
FRV_F_RS_NULL,
FRV_F_GRI_NULL,
FRV_F_GRJ_NULL,
FRV_F_GRK_NULL,
FRV_F_FRI_NULL,
FRV_F_FRJ_NULL,
FRV_F_ACCJ_NULL,
FRV_F_RD_NULL,
FRV_F_COND_NULL,
FRV_F_CCOND_NULL,
FRV_F_S12_NULL,
FRV_F_LABEL16_NULL,
FRV_F_MISC_NULL_1,
FRV_F_MISC_NULL_2,
FRV_F_MISC_NULL_3,
FRV_F_MISC_NULL_4,
FRV_F_MISC_NULL_5,
FRV_F_MISC_NULL_6,
FRV_F_MISC_NULL_7,
FRV_F_MISC_NULL_8,
FRV_F_MISC_NULL_9,
FRV_F_MISC_NULL_10,
FRV_F_MISC_NULL_11,
FRV_F_LRA_NULL,
FRV_F_TLBPR_NULL,
FRV_F_LI_OFF,
FRV_F_LI_ON,
FRV_F_RELOC_ANN,
FRV_F_MAX,
IP2K_F_NIL,
IP2K_F_ANYOF,
IP2K_F_IMM8,
IP2K_F_REG,
IP2K_F_ADDR16CJP,
IP2K_F_DIR,
IP2K_F_BITNO,
IP2K_F_OP3,
IP2K_F_OP4,
IP2K_F_OP4MID,
IP2K_F_OP6,
IP2K_F_OP8,
IP2K_F_OP6_10LOW,
IP2K_F_OP6_7LOW,
IP2K_F_RETI3,
IP2K_F_SKIPB,
IP2K_F_PAGE3,
IP2K_F_MAX,
IQ2000_F_NIL,
IQ2000_F_ANYOF,
IQ2000_F_OPCODE,
IQ2000_F_RS,
IQ2000_F_RT,
IQ2000_F_RD,
IQ2000_F_SHAMT,
IQ2000_F_CP_OP,
IQ2000_F_CP_OP_10,
IQ2000_F_CP_GRP,
IQ2000_F_FUNC,
IQ2000_F_IMM,
IQ2000_F_RD_RS,
IQ2000_F_RD_RT,
IQ2000_F_RT_RS,
IQ2000_F_JTARG,
IQ2000_F_JTARGQ10,
IQ2000_F_OFFSET,
IQ2000_F_COUNT,
IQ2000_F_BYTECOUNT,
IQ2000_F_INDEX,
IQ2000_F_MASK,
IQ2000_F_MASKQ10,
IQ2000_F_MASKL,
IQ2000_F_EXCODE,
IQ2000_F_RSRVD,
IQ2000_F_10_11,
IQ2000_F_24_19,
IQ2000_F_5,
IQ2000_F_10,
IQ2000_F_25,
IQ2000_F_CAM_Z,
IQ2000_F_CAM_Y,
IQ2000_F_CM_3FUNC,
IQ2000_F_CM_4FUNC,
IQ2000_F_CM_3Z,
IQ2000_F_CM_4Z,
IQ2000_F_MAX,
M32R_F_NIL,
M32R_F_ANYOF,
M32R_F_OP1,
M32R_F_OP2,
M32R_F_COND,
M32R_F_R1,
M32R_F_R2,
M32R_F_SIMM8,
M32R_F_SIMM16,
M32R_F_SHIFT_OP2,
M32R_F_UIMM3,
M32R_F_UIMM4,
M32R_F_UIMM5,
M32R_F_UIMM8,
M32R_F_UIMM16,
M32R_F_UIMM24,
M32R_F_HI16,
M32R_F_DISP8,
M32R_F_DISP16,
M32R_F_DISP24,
M32R_F_OP23,
M32R_F_OP3,
M32R_F_ACC,
M32R_F_ACCS,
M32R_F_ACCD,
M32R_F_BITS67,
M32R_F_BIT4,
M32R_F_BIT14,
M32R_F_IMM1,
M32R_F_MAX,
OPENRISC_F_NIL,
OPENRISC_F_ANYOF,
OPENRISC_F_CLASS,
OPENRISC_F_SUB,
OPENRISC_F_R1,
OPENRISC_F_R2,
OPENRISC_F_R3,
OPENRISC_F_SIMM16,
OPENRISC_F_UIMM16,
OPENRISC_F_UIMM5,
OPENRISC_F_HI16,
OPENRISC_F_LO16,
OPENRISC_F_OP1,
OPENRISC_F_OP2,
OPENRISC_F_OP3,
OPENRISC_F_OP4,
OPENRISC_F_OP5,
OPENRISC_F_OP6,
OPENRISC_F_OP7,
OPENRISC_F_I16_1,
OPENRISC_F_I16_2,
OPENRISC_F_DISP26,
OPENRISC_F_ABS26,
OPENRISC_F_I16NC,
OPENRISC_F_F_15_8,
OPENRISC_F_F_10_3,
OPENRISC_F_F_4_1,
OPENRISC_F_F_7_3,
OPENRISC_F_F_10_7,
OPENRISC_F_F_10_11,
OPENRISC_F_MAX,
XSTORMY16_F_NIL,
XSTORMY16_F_ANYOF,
XSTORMY16_F_RD,
XSTORMY16_F_RDM,
XSTORMY16_F_RM,
XSTORMY16_F_RS,
XSTORMY16_F_RB,
XSTORMY16_F_RBJ,
XSTORMY16_F_OP1,
XSTORMY16_F_OP2,
XSTORMY16_F_OP2A,
XSTORMY16_F_OP2M,
XSTORMY16_F_OP3,
XSTORMY16_F_OP3A,
XSTORMY16_F_OP3B,
XSTORMY16_F_OP4,
XSTORMY16_F_OP4M,
XSTORMY16_F_OP4B,
XSTORMY16_F_OP5,
XSTORMY16_F_OP5A,
XSTORMY16_F_OP,
XSTORMY16_F_IMM2,
XSTORMY16_F_IMM3,
XSTORMY16_F_IMM3B,
XSTORMY16_F_IMM4,
XSTORMY16_F_IMM8,
XSTORMY16_F_IMM12,
XSTORMY16_F_IMM16,
XSTORMY16_F_LMEM8,
XSTORMY16_F_HMEM8,
XSTORMY16_F_REL8_2,
XSTORMY16_F_REL8_4,
XSTORMY16_F_REL12,
XSTORMY16_F_REL12A,
XSTORMY16_F_ABS24_1,
XSTORMY16_F_ABS24_2,
XSTORMY16_F_ABS24,
XSTORMY16_F_MAX
} |
| enum | cgen_hw_attr {
CGEN_HW_VIRTUAL,
CGEN_HW_CACHE_ADDR,
CGEN_HW_PC,
CGEN_HW_PROFILE,
CGEN_HW_END_BOOLS,
CGEN_HW_START_NBOOLS = 31,
CGEN_HW_MACH,
CGEN_HW_END_NBOOLS,
CGEN_HW_VIRTUAL,
CGEN_HW_CACHE_ADDR,
CGEN_HW_PC,
CGEN_HW_PROFILE,
CGEN_HW_END_BOOLS,
CGEN_HW_START_NBOOLS = 31,
CGEN_HW_MACH,
CGEN_HW_END_NBOOLS,
CGEN_HW_VIRTUAL,
CGEN_HW_CACHE_ADDR,
CGEN_HW_PC,
CGEN_HW_PROFILE,
CGEN_HW_END_BOOLS,
CGEN_HW_START_NBOOLS = 31,
CGEN_HW_MACH,
CGEN_HW_END_NBOOLS,
CGEN_HW_VIRTUAL,
CGEN_HW_CACHE_ADDR,
CGEN_HW_PC,
CGEN_HW_PROFILE,
CGEN_HW_END_BOOLS,
CGEN_HW_START_NBOOLS = 31,
CGEN_HW_MACH,
CGEN_HW_END_NBOOLS,
CGEN_HW_VIRTUAL,
CGEN_HW_CACHE_ADDR,
CGEN_HW_PC,
CGEN_HW_PROFILE,
CGEN_HW_END_BOOLS,
CGEN_HW_START_NBOOLS = 31,
CGEN_HW_MACH,
CGEN_HW_END_NBOOLS,
CGEN_HW_VIRTUAL,
CGEN_HW_CACHE_ADDR,
CGEN_HW_PC,
CGEN_HW_PROFILE,
CGEN_HW_END_BOOLS,
CGEN_HW_START_NBOOLS = 31,
CGEN_HW_MACH,
CGEN_HW_END_NBOOLS,
CGEN_HW_VIRTUAL,
CGEN_HW_CACHE_ADDR,
CGEN_HW_PC,
CGEN_HW_PROFILE,
CGEN_HW_END_BOOLS,
CGEN_HW_START_NBOOLS = 31,
CGEN_HW_MACH,
CGEN_HW_END_NBOOLS
} |
| enum | cgen_hw_type {
CGEN_HW_MAX,
HW_H_MEMORY,
HW_H_SINT,
HW_H_UINT,
HW_H_ADDR,
HW_H_IADDR,
HW_H_PC,
HW_H_GR,
HW_H_CR,
HW_H_DR,
HW_H_PS,
HW_H_R13,
HW_H_R14,
HW_H_R15,
HW_H_NBIT,
HW_H_ZBIT,
HW_H_VBIT,
HW_H_CBIT,
HW_H_IBIT,
HW_H_SBIT,
HW_H_TBIT,
HW_H_D0BIT,
HW_H_D1BIT,
HW_H_CCR,
HW_H_SCR,
HW_H_ILM,
HW_MAX,
HW_H_MEMORY,
HW_H_SINT,
HW_H_UINT,
HW_H_ADDR,
HW_H_IADDR,
HW_H_RELOC_ANN,
HW_H_PC,
HW_H_PSR_IMPLE,
HW_H_PSR_VER,
HW_H_PSR_ICE,
HW_H_PSR_NEM,
HW_H_PSR_CM,
HW_H_PSR_BE,
HW_H_PSR_ESR,
HW_H_PSR_EF,
HW_H_PSR_EM,
HW_H_PSR_PIL,
HW_H_PSR_PS,
HW_H_PSR_ET,
HW_H_PSR_S,
HW_H_TBR_TBA,
HW_H_TBR_TT,
HW_H_BPSR_BS,
HW_H_BPSR_BET,
HW_H_GR,
HW_H_GR_DOUBLE,
HW_H_GR_HI,
HW_H_GR_LO,
HW_H_FR,
HW_H_FR_DOUBLE,
HW_H_FR_INT,
HW_H_FR_HI,
HW_H_FR_LO,
HW_H_FR_0,
HW_H_FR_1,
HW_H_FR_2,
HW_H_FR_3,
HW_H_CPR,
HW_H_CPR_DOUBLE,
HW_H_SPR,
HW_H_ACCG,
HW_H_ACC40S,
HW_H_ACC40U,
HW_H_IACC0,
HW_H_ICCR,
HW_H_FCCR,
HW_H_CCCR,
HW_H_PACK,
HW_H_HINT_TAKEN,
HW_H_HINT_NOT_TAKEN,
HW_MAX,
HW_H_MEMORY,
HW_H_SINT,
HW_H_UINT,
HW_H_ADDR,
HW_H_IADDR,
HW_H_SPR,
HW_H_REGISTERS,
HW_H_STACK,
HW_H_PABITS,
HW_H_ZBIT,
HW_H_CBIT,
HW_H_DCBIT,
HW_H_PC,
HW_MAX,
HW_H_MEMORY,
HW_H_SINT,
HW_H_UINT,
HW_H_ADDR,
HW_H_IADDR,
HW_H_PC,
HW_H_GR,
HW_MAX,
HW_H_MEMORY,
HW_H_SINT,
HW_H_UINT,
HW_H_ADDR,
HW_H_IADDR,
HW_H_PC,
HW_H_HI16,
HW_H_SLO16,
HW_H_ULO16,
HW_H_GR,
HW_H_CR,
HW_H_ACCUM,
HW_H_ACCUMS,
HW_H_COND,
HW_H_PSW,
HW_H_BPSW,
HW_H_BBPSW,
HW_H_LOCK,
HW_MAX,
HW_H_MEMORY,
HW_H_SINT,
HW_H_UINT,
HW_H_ADDR,
HW_H_IADDR,
HW_H_PC,
HW_H_GR,
HW_H_SR,
HW_H_HI16,
HW_H_LO16,
HW_H_CBIT,
HW_H_DELAY_INSN,
HW_MAX,
HW_H_MEMORY,
HW_H_SINT,
HW_H_UINT,
HW_H_ADDR,
HW_H_IADDR,
HW_H_PC,
HW_H_GR,
HW_H_RB,
HW_H_RBJ,
HW_H_RPSW,
HW_H_Z8,
HW_H_Z16,
HW_H_CY,
HW_H_HC,
HW_H_OV,
HW_H_PT,
HW_H_S,
HW_H_BRANCHCOND,
HW_H_WORDSIZE,
HW_MAX
} |
| enum | cgen_operand_attr {
CGEN_OPERAND_VIRTUAL,
CGEN_OPERAND_PCREL_ADDR,
CGEN_OPERAND_ABS_ADDR,
CGEN_OPERAND_SIGN_OPT,
CGEN_OPERAND_SIGNED,
CGEN_OPERAND_NEGATIVE,
CGEN_OPERAND_RELAX,
CGEN_OPERAND_SEM_ONLY,
CGEN_OPERAND_HASH_PREFIX,
CGEN_OPERAND_END_BOOLS,
CGEN_OPERAND_START_NBOOLS = 31,
CGEN_OPERAND_MACH,
CGEN_OPERAND_END_NBOOLS,
CGEN_OPERAND_VIRTUAL,
CGEN_OPERAND_PCREL_ADDR,
CGEN_OPERAND_ABS_ADDR,
CGEN_OPERAND_SIGN_OPT,
CGEN_OPERAND_SIGNED,
CGEN_OPERAND_NEGATIVE,
CGEN_OPERAND_RELAX,
CGEN_OPERAND_SEM_ONLY,
CGEN_OPERAND_HASH_PREFIX,
CGEN_OPERAND_END_BOOLS,
CGEN_OPERAND_START_NBOOLS = 31,
CGEN_OPERAND_MACH,
CGEN_OPERAND_END_NBOOLS,
CGEN_OPERAND_VIRTUAL,
CGEN_OPERAND_PCREL_ADDR,
CGEN_OPERAND_ABS_ADDR,
CGEN_OPERAND_SIGN_OPT,
CGEN_OPERAND_SIGNED,
CGEN_OPERAND_NEGATIVE,
CGEN_OPERAND_RELAX,
CGEN_OPERAND_SEM_ONLY,
CGEN_OPERAND_END_BOOLS,
CGEN_OPERAND_START_NBOOLS = 31,
CGEN_OPERAND_MACH,
CGEN_OPERAND_END_NBOOLS,
CGEN_OPERAND_VIRTUAL,
CGEN_OPERAND_PCREL_ADDR,
CGEN_OPERAND_ABS_ADDR,
CGEN_OPERAND_SIGN_OPT,
CGEN_OPERAND_SIGNED,
CGEN_OPERAND_NEGATIVE,
CGEN_OPERAND_RELAX,
CGEN_OPERAND_SEM_ONLY,
CGEN_OPERAND_END_BOOLS,
CGEN_OPERAND_START_NBOOLS = 31,
CGEN_OPERAND_MACH,
CGEN_OPERAND_END_NBOOLS,
CGEN_OPERAND_VIRTUAL,
CGEN_OPERAND_PCREL_ADDR,
CGEN_OPERAND_ABS_ADDR,
CGEN_OPERAND_SIGN_OPT,
CGEN_OPERAND_SIGNED,
CGEN_OPERAND_NEGATIVE,
CGEN_OPERAND_RELAX,
CGEN_OPERAND_SEM_ONLY,
CGEN_OPERAND_RELOC,
CGEN_OPERAND_HASH_PREFIX,
CGEN_OPERAND_END_BOOLS,
CGEN_OPERAND_START_NBOOLS = 31,
CGEN_OPERAND_MACH,
CGEN_OPERAND_END_NBOOLS,
CGEN_OPERAND_VIRTUAL,
CGEN_OPERAND_PCREL_ADDR,
CGEN_OPERAND_ABS_ADDR,
CGEN_OPERAND_SIGN_OPT,
CGEN_OPERAND_SIGNED,
CGEN_OPERAND_NEGATIVE,
CGEN_OPERAND_RELAX,
CGEN_OPERAND_SEM_ONLY,
CGEN_OPERAND_END_BOOLS,
CGEN_OPERAND_START_NBOOLS = 31,
CGEN_OPERAND_MACH,
CGEN_OPERAND_END_NBOOLS,
CGEN_OPERAND_VIRTUAL,
CGEN_OPERAND_PCREL_ADDR,
CGEN_OPERAND_ABS_ADDR,
CGEN_OPERAND_SIGN_OPT,
CGEN_OPERAND_SIGNED,
CGEN_OPERAND_NEGATIVE,
CGEN_OPERAND_RELAX,
CGEN_OPERAND_SEM_ONLY,
CGEN_OPERAND_END_BOOLS,
CGEN_OPERAND_START_NBOOLS = 31,
CGEN_OPERAND_MACH,
CGEN_OPERAND_END_NBOOLS
} |
| enum | cgen_operand_type {
CGEN_OPERAND_MAX,
FR30_OPERAND_PC,
FR30_OPERAND_RI,
FR30_OPERAND_RJ,
FR30_OPERAND_RIC,
FR30_OPERAND_RJC,
FR30_OPERAND_CRI,
FR30_OPERAND_CRJ,
FR30_OPERAND_RS1,
FR30_OPERAND_RS2,
FR30_OPERAND_R13,
FR30_OPERAND_R14,
FR30_OPERAND_R15,
FR30_OPERAND_PS,
FR30_OPERAND_U4,
FR30_OPERAND_U4C,
FR30_OPERAND_U8,
FR30_OPERAND_I8,
FR30_OPERAND_UDISP6,
FR30_OPERAND_DISP8,
FR30_OPERAND_DISP9,
FR30_OPERAND_DISP10,
FR30_OPERAND_S10,
FR30_OPERAND_U10,
FR30_OPERAND_I32,
FR30_OPERAND_M4,
FR30_OPERAND_I20,
FR30_OPERAND_DIR8,
FR30_OPERAND_DIR9,
FR30_OPERAND_DIR10,
FR30_OPERAND_LABEL9,
FR30_OPERAND_LABEL12,
FR30_OPERAND_REGLIST_LOW_LD,
FR30_OPERAND_REGLIST_HI_LD,
FR30_OPERAND_REGLIST_LOW_ST,
FR30_OPERAND_REGLIST_HI_ST,
FR30_OPERAND_CC,
FR30_OPERAND_CCC,
FR30_OPERAND_NBIT,
FR30_OPERAND_VBIT,
FR30_OPERAND_ZBIT,
FR30_OPERAND_CBIT,
FR30_OPERAND_IBIT,
FR30_OPERAND_SBIT,
FR30_OPERAND_TBIT,
FR30_OPERAND_D0BIT,
FR30_OPERAND_D1BIT,
FR30_OPERAND_CCR,
FR30_OPERAND_SCR,
FR30_OPERAND_ILM,
FR30_OPERAND_MAX,
FRV_OPERAND_PC,
FRV_OPERAND_PACK,
FRV_OPERAND_GRI,
FRV_OPERAND_GRJ,
FRV_OPERAND_GRK,
FRV_OPERAND_GRKHI,
FRV_OPERAND_GRKLO,
FRV_OPERAND_GRDOUBLEK,
FRV_OPERAND_ACC40SI,
FRV_OPERAND_ACC40UI,
FRV_OPERAND_ACC40SK,
FRV_OPERAND_ACC40UK,
FRV_OPERAND_ACCGI,
FRV_OPERAND_ACCGK,
FRV_OPERAND_CPRI,
FRV_OPERAND_CPRJ,
FRV_OPERAND_CPRK,
FRV_OPERAND_CPRDOUBLEK,
FRV_OPERAND_FRINTI,
FRV_OPERAND_FRINTJ,
FRV_OPERAND_FRINTK,
FRV_OPERAND_FRI,
FRV_OPERAND_FRJ,
FRV_OPERAND_FRK,
FRV_OPERAND_FRKHI,
FRV_OPERAND_FRKLO,
FRV_OPERAND_FRDOUBLEI,
FRV_OPERAND_FRDOUBLEJ,
FRV_OPERAND_FRDOUBLEK,
FRV_OPERAND_CRI,
FRV_OPERAND_CRJ,
FRV_OPERAND_CRJ_INT,
FRV_OPERAND_CRJ_FLOAT,
FRV_OPERAND_CRK,
FRV_OPERAND_CCI,
FRV_OPERAND_ICCI_1,
FRV_OPERAND_ICCI_2,
FRV_OPERAND_ICCI_3,
FRV_OPERAND_FCCI_1,
FRV_OPERAND_FCCI_2,
FRV_OPERAND_FCCI_3,
FRV_OPERAND_FCCK,
FRV_OPERAND_EIR,
FRV_OPERAND_S10,
FRV_OPERAND_U16,
FRV_OPERAND_S16,
FRV_OPERAND_S6,
FRV_OPERAND_S6_1,
FRV_OPERAND_U6,
FRV_OPERAND_S5,
FRV_OPERAND_COND,
FRV_OPERAND_CCOND,
FRV_OPERAND_HINT,
FRV_OPERAND_HINT_TAKEN,
FRV_OPERAND_HINT_NOT_TAKEN,
FRV_OPERAND_LI,
FRV_OPERAND_LOCK,
FRV_OPERAND_DEBUG,
FRV_OPERAND_AE,
FRV_OPERAND_LABEL16,
FRV_OPERAND_LRAE,
FRV_OPERAND_LRAD,
FRV_OPERAND_LRAS,
FRV_OPERAND_TLBPROPX,
FRV_OPERAND_TLBPRL,
FRV_OPERAND_A0,
FRV_OPERAND_A1,
FRV_OPERAND_FRINTIEVEN,
FRV_OPERAND_FRINTJEVEN,
FRV_OPERAND_FRINTKEVEN,
FRV_OPERAND_D12,
FRV_OPERAND_S12,
FRV_OPERAND_U12,
FRV_OPERAND_SPR,
FRV_OPERAND_ULO16,
FRV_OPERAND_SLO16,
FRV_OPERAND_UHI16,
FRV_OPERAND_LABEL24,
FRV_OPERAND_PSR_ESR,
FRV_OPERAND_PSR_S,
FRV_OPERAND_PSR_PS,
FRV_OPERAND_PSR_ET,
FRV_OPERAND_BPSR_BS,
FRV_OPERAND_BPSR_BET,
FRV_OPERAND_TBR_TBA,
FRV_OPERAND_TBR_TT,
FRV_OPERAND_LDANN,
FRV_OPERAND_LDDANN,
FRV_OPERAND_CALLANN,
FRV_OPERAND_MAX,
IP2K_OPERAND_PC,
IP2K_OPERAND_ADDR16CJP,
IP2K_OPERAND_FR,
IP2K_OPERAND_LIT8,
IP2K_OPERAND_BITNO,
IP2K_OPERAND_ADDR16P,
IP2K_OPERAND_ADDR16H,
IP2K_OPERAND_ADDR16L,
IP2K_OPERAND_RETI3,
IP2K_OPERAND_PABITS,
IP2K_OPERAND_ZBIT,
IP2K_OPERAND_CBIT,
IP2K_OPERAND_DCBIT,
IP2K_OPERAND_MAX,
IQ2000_OPERAND_PC,
IQ2000_OPERAND_RS,
IQ2000_OPERAND_RT,
IQ2000_OPERAND_RD,
IQ2000_OPERAND_RD_RS,
IQ2000_OPERAND_RD_RT,
IQ2000_OPERAND_RT_RS,
IQ2000_OPERAND_SHAMT,
IQ2000_OPERAND_IMM,
IQ2000_OPERAND_OFFSET,
IQ2000_OPERAND_BASEOFF,
IQ2000_OPERAND_JMPTARG,
IQ2000_OPERAND_MASK,
IQ2000_OPERAND_MASKQ10,
IQ2000_OPERAND_MASKL,
IQ2000_OPERAND_COUNT,
IQ2000_OPERAND__INDEX,
IQ2000_OPERAND_EXECODE,
IQ2000_OPERAND_BYTECOUNT,
IQ2000_OPERAND_CAM_Y,
IQ2000_OPERAND_CAM_Z,
IQ2000_OPERAND_CM_3FUNC,
IQ2000_OPERAND_CM_4FUNC,
IQ2000_OPERAND_CM_3Z,
IQ2000_OPERAND_CM_4Z,
IQ2000_OPERAND_BASE,
IQ2000_OPERAND_MASKR,
IQ2000_OPERAND_BITNUM,
IQ2000_OPERAND_HI16,
IQ2000_OPERAND_LO16,
IQ2000_OPERAND_MLO16,
IQ2000_OPERAND_JMPTARGQ10,
IQ2000_OPERAND_MAX,
M32R_OPERAND_PC,
M32R_OPERAND_SR,
M32R_OPERAND_DR,
M32R_OPERAND_SRC1,
M32R_OPERAND_SRC2,
M32R_OPERAND_SCR,
M32R_OPERAND_DCR,
M32R_OPERAND_SIMM8,
M32R_OPERAND_SIMM16,
M32R_OPERAND_UIMM3,
M32R_OPERAND_UIMM4,
M32R_OPERAND_UIMM5,
M32R_OPERAND_UIMM8,
M32R_OPERAND_UIMM16,
M32R_OPERAND_IMM1,
M32R_OPERAND_ACCD,
M32R_OPERAND_ACCS,
M32R_OPERAND_ACC,
M32R_OPERAND_HASH,
M32R_OPERAND_HI16,
M32R_OPERAND_SLO16,
M32R_OPERAND_ULO16,
M32R_OPERAND_UIMM24,
M32R_OPERAND_DISP8,
M32R_OPERAND_DISP16,
M32R_OPERAND_DISP24,
M32R_OPERAND_CONDBIT,
M32R_OPERAND_ACCUM,
M32R_OPERAND_MAX,
OPENRISC_OPERAND_PC,
OPENRISC_OPERAND_SR,
OPENRISC_OPERAND_CBIT,
OPENRISC_OPERAND_SIMM_16,
OPENRISC_OPERAND_UIMM_16,
OPENRISC_OPERAND_DISP_26,
OPENRISC_OPERAND_ABS_26,
OPENRISC_OPERAND_UIMM_5,
OPENRISC_OPERAND_RD,
OPENRISC_OPERAND_RA,
OPENRISC_OPERAND_RB,
OPENRISC_OPERAND_OP_F_23,
OPENRISC_OPERAND_OP_F_3,
OPENRISC_OPERAND_HI16,
OPENRISC_OPERAND_LO16,
OPENRISC_OPERAND_UI16NC,
OPENRISC_OPERAND_MAX,
XSTORMY16_OPERAND_PC,
XSTORMY16_OPERAND_PSW_Z8,
XSTORMY16_OPERAND_PSW_Z16,
XSTORMY16_OPERAND_PSW_CY,
XSTORMY16_OPERAND_PSW_HC,
XSTORMY16_OPERAND_PSW_OV,
XSTORMY16_OPERAND_PSW_PT,
XSTORMY16_OPERAND_PSW_S,
XSTORMY16_OPERAND_RD,
XSTORMY16_OPERAND_RDM,
XSTORMY16_OPERAND_RM,
XSTORMY16_OPERAND_RS,
XSTORMY16_OPERAND_RB,
XSTORMY16_OPERAND_RBJ,
XSTORMY16_OPERAND_BCOND2,
XSTORMY16_OPERAND_WS2,
XSTORMY16_OPERAND_BCOND5,
XSTORMY16_OPERAND_IMM2,
XSTORMY16_OPERAND_IMM3,
XSTORMY16_OPERAND_IMM3B,
XSTORMY16_OPERAND_IMM4,
XSTORMY16_OPERAND_IMM8,
XSTORMY16_OPERAND_IMM8SMALL,
XSTORMY16_OPERAND_IMM12,
XSTORMY16_OPERAND_IMM16,
XSTORMY16_OPERAND_LMEM8,
XSTORMY16_OPERAND_HMEM8,
XSTORMY16_OPERAND_REL8_2,
XSTORMY16_OPERAND_REL8_4,
XSTORMY16_OPERAND_REL12,
XSTORMY16_OPERAND_REL12A,
XSTORMY16_OPERAND_ABS24,
XSTORMY16_OPERAND_PSW,
XSTORMY16_OPERAND_RPSW,
XSTORMY16_OPERAND_SP,
XSTORMY16_OPERAND_R0,
XSTORMY16_OPERAND_R1,
XSTORMY16_OPERAND_R2,
XSTORMY16_OPERAND_R8,
XSTORMY16_OPERAND_MAX
} |
| enum | cgen_insn_attr {
CGEN_INSN_ALIAS = 0,
CGEN_INSN_ALIAS,
CGEN_INSN_VIRTUAL,
CGEN_INSN_UNCOND_CTI,
CGEN_INSN_COND_CTI,
CGEN_INSN_SKIP_CTI,
CGEN_INSN_DELAY_SLOT,
CGEN_INSN_RELAXABLE,
CGEN_INSN_RELAXED,
CGEN_INSN_NO_DIS,
CGEN_INSN_PBB,
CGEN_INSN_NOT_IN_DELAY_SLOT,
CGEN_INSN_END_BOOLS,
CGEN_INSN_START_NBOOLS = 31,
CGEN_INSN_MACH,
CGEN_INSN_END_NBOOLS,
CGEN_INSN_ALIAS,
CGEN_INSN_VIRTUAL,
CGEN_INSN_UNCOND_CTI,
CGEN_INSN_COND_CTI,
CGEN_INSN_SKIP_CTI,
CGEN_INSN_DELAY_SLOT,
CGEN_INSN_RELAXABLE,
CGEN_INSN_RELAXED,
CGEN_INSN_NO_DIS,
CGEN_INSN_PBB,
CGEN_INSN_PRIVILEGED,
CGEN_INSN_NON_EXCEPTING,
CGEN_INSN_CONDITIONAL,
CGEN_INSN_FR_ACCESS,
CGEN_INSN_PRESERVE_OVF,
CGEN_INSN_AUDIO,
CGEN_INSN_END_BOOLS,
CGEN_INSN_START_NBOOLS = 31,
CGEN_INSN_MACH,
CGEN_INSN_UNIT,
CGEN_INSN_FR400_MAJOR,
CGEN_INSN_FR450_MAJOR,
CGEN_INSN_FR500_MAJOR,
CGEN_INSN_FR550_MAJOR,
CGEN_INSN_END_NBOOLS,
CGEN_INSN_ALIAS,
CGEN_INSN_VIRTUAL,
CGEN_INSN_UNCOND_CTI,
CGEN_INSN_COND_CTI,
CGEN_INSN_SKIP_CTI,
CGEN_INSN_DELAY_SLOT,
CGEN_INSN_RELAXABLE,
CGEN_INSN_RELAXED,
CGEN_INSN_NO_DIS,
CGEN_INSN_PBB,
CGEN_INSN_EXT_SKIP_INSN,
CGEN_INSN_SKIPA,
CGEN_INSN_END_BOOLS,
CGEN_INSN_START_NBOOLS = 31,
CGEN_INSN_MACH,
CGEN_INSN_END_NBOOLS,
CGEN_INSN_ALIAS,
CGEN_INSN_VIRTUAL,
CGEN_INSN_UNCOND_CTI,
CGEN_INSN_COND_CTI,
CGEN_INSN_SKIP_CTI,
CGEN_INSN_DELAY_SLOT,
CGEN_INSN_RELAXABLE,
CGEN_INSN_RELAXED,
CGEN_INSN_NO_DIS,
CGEN_INSN_PBB,
CGEN_INSN_YIELD_INSN,
CGEN_INSN_LOAD_DELAY,
CGEN_INSN_EVEN_REG_NUM,
CGEN_INSN_UNSUPPORTED,
CGEN_INSN_USES_RD,
CGEN_INSN_USES_RS,
CGEN_INSN_USES_RT,
CGEN_INSN_USES_R31,
CGEN_INSN_END_BOOLS,
CGEN_INSN_START_NBOOLS = 31,
CGEN_INSN_MACH,
CGEN_INSN_END_NBOOLS,
CGEN_INSN_ALIAS,
CGEN_INSN_VIRTUAL,
CGEN_INSN_UNCOND_CTI,
CGEN_INSN_COND_CTI,
CGEN_INSN_SKIP_CTI,
CGEN_INSN_DELAY_SLOT,
CGEN_INSN_RELAXABLE,
CGEN_INSN_RELAXED,
CGEN_INSN_NO_DIS,
CGEN_INSN_PBB,
CGEN_INSN_FILL_SLOT,
CGEN_INSN_SPECIAL,
CGEN_INSN_SPECIAL_M32R,
CGEN_INSN_SPECIAL_FLOAT,
CGEN_INSN_END_BOOLS,
CGEN_INSN_START_NBOOLS = 31,
CGEN_INSN_MACH,
CGEN_INSN_PIPE,
CGEN_INSN_END_NBOOLS,
CGEN_INSN_ALIAS,
CGEN_INSN_VIRTUAL,
CGEN_INSN_UNCOND_CTI,
CGEN_INSN_COND_CTI,
CGEN_INSN_SKIP_CTI,
CGEN_INSN_DELAY_SLOT,
CGEN_INSN_RELAXABLE,
CGEN_INSN_RELAXED,
CGEN_INSN_NO_DIS,
CGEN_INSN_PBB,
CGEN_INSN_NOT_IN_DELAY_SLOT,
CGEN_INSN_END_BOOLS,
CGEN_INSN_START_NBOOLS = 31,
CGEN_INSN_MACH,
CGEN_INSN_END_NBOOLS,
CGEN_INSN_ALIAS,
CGEN_INSN_VIRTUAL,
CGEN_INSN_UNCOND_CTI,
CGEN_INSN_COND_CTI,
CGEN_INSN_SKIP_CTI,
CGEN_INSN_DELAY_SLOT,
CGEN_INSN_RELAXABLE,
CGEN_INSN_RELAXED,
CGEN_INSN_NO_DIS,
CGEN_INSN_PBB,
CGEN_INSN_END_BOOLS,
CGEN_INSN_START_NBOOLS = 31,
CGEN_INSN_MACH,
CGEN_INSN_END_NBOOLS
} |
Variables |
| struct cgen_ifld | iq2000_cgen_ifld_table [] |
| const CGEN_ATTR_TABLE | iq2000_cgen_hardware_attr_table [] |
| const CGEN_ATTR_TABLE | iq2000_cgen_ifield_attr_table [] |
| const CGEN_ATTR_TABLE | iq2000_cgen_operand_attr_table [] |
| const CGEN_ATTR_TABLE | iq2000_cgen_insn_attr_table [] |
| CGEN_KEYWORD | iq2000_cgen_opval_gr_names |
| const CGEN_HW_ENTRY | iq2000_cgen_hw_table [] |
