Open64: osprey/common/com/x8664/config_targ

00001 /*
00002  * Copyright 2007. PathScale, LLC.  All Rights Reserved.
00003  */
00004 
00005 /*
00006  * Copyright 2004, 2005, 2006 PathScale, Inc.  All Rights Reserved.
00007  */
00008 
00009 /*
00010 
00011   Copyright (C) 2000, 2001 Silicon Graphics, Inc.  All Rights Reserved.
00012 
00013   This program is free software; you can redistribute it and/or modify it
00014   under the terms of version 2 of the GNU General Public License as
00015   published by the Free Software Foundation.
00016 
00017   This program is distributed in the hope that it would be useful, but
00018   WITHOUT ANY WARRANTY; without even the implied warranty of
00019   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  
00020 
00021   Further, this software is distributed without any warranty that it is
00022   free of the rightful claim of any third person regarding infringement 
00023   or the like.  Any license provided herein, whether implied or 
00024   otherwise, applies only to this software file.  Patent licenses, if 
00025   any, provided herein do not apply to combinations of this program with 
00026   other software, or any other product whatsoever.  
00027 
00028   You should have received a copy of the GNU General Public License along
00029   with this program; if not, write the Free Software Foundation, Inc., 59
00030   Temple Place - Suite 330, Boston MA 02111-1307, USA.
00031 
00032   Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pky,
00033   Mountain View, CA 94043, or:
00034 
00035   http://www.sgi.com
00036 
00037   For further information regarding this notice, see:
00038 
00039   http://oss.sgi.com/projects/GenInfo/NoticeExplan
00040 
00041 */
00042 
00043 
00044 /* ====================================================================
00045  * ====================================================================
00046  *
00047  * $Source: common/com/x8664/SCCS/s.config_targ_opt.cxx $
00048  *
00049  * Revision history:
00050  *  26-Feb-97 - Original Version, extracted from config.c.
00051  *
00052  * Description:
00053  *
00054  * Configure the -TARG group (included in config.c).
00055  * See config_targ_opt.h for usage conventions.
00056  * See config_targ.* for more general target configuration support.
00057  *
00058  * NOTE:  There is an approximate distinction between -TARG option
00059  * group flags and their configuration (in this file), and more generic
00060  * target configuration (in config_targ.c).  Note that the related
00061  * header file config_targ.h is included in config.h, and hence in most
00062  * source files, whereas config_targ_opt.h is only included directly, so
00063  * putting new -TARG option-related variables in here is to be
00064  * preferred to putting them in config_targ.[hc].
00065  *
00066  * ====================================================================
00067  * ====================================================================
00068  */
00069 
00070 /* This file is included in config.c, so it doesn't need its own set of
00071  * standard includes -- only the following:
00072  */
00073 #include "config_targ_opt.h"
00074 
00075 /* ====================================================================
00076  * List of global variables that are set by the -TARG option group
00077  * ====================================================================
00078  */
00079 
00080 /* General target control: */
00081 char *ABI_Name = NULL;    /* -TARG:abi=xxx */
00082 char *ISA_Name = NULL;    /* -TARG:isa=xxx */
00083 char *Processor_Name = NULL;  /* -TARG:processor=xxx */
00084 static char * Platform_Name = NULL;
00085 INT16 Target_FPRs = 0;    /* -TARG:fp_regs=nn */
00086 BOOL Pure_ABI = FALSE;    /* Avoid non-ABI constructs? */
00087 
00088 BOOL Target_MMX = TRUE;        /* -TARG:mmx=on/off */
00089 BOOL Target_MMX_Set = FALSE;
00090 
00091 BOOL Target_SSE = TRUE;        /* -TARG:sse=on/off */
00092 BOOL Target_SSE_Set = FALSE;
00093 
00094 BOOL Target_SSE2 = TRUE;        /* -TARG:sse2=on/off */
00095 BOOL Target_SSE2_Set = FALSE;
00096 
00097 BOOL Target_SSE3 = FALSE;       /* -TARG:sse3=on/off */
00098 BOOL Target_SSE3_Set = FALSE;
00099 
00100 // bug 4405
00101 BOOL Target_3DNow = FALSE;       // -TARG:3dnow=on/off
00102 BOOL Target_3DNow_Set = FALSE;
00103 
00104 BOOL Target_SSE4a = FALSE;       // -TARG:sse4a=on/off
00105 BOOL Target_SSE4a_Set = FALSE;
00106 
00107 // bug 4327
00108 int Target_x87_Precision = 80;  // -TARG:x87_precision=32/64/80
00109 
00110 /* Fault handling: */
00111 BOOL Force_FP_Precise_Mode = FALSE; /* Force precise FP traps? */
00112 BOOL Force_Memory_Dismiss = FALSE;  /* Force mem fault dismissal? */
00113 BOOL Force_Page_Zero = FALSE;   /* Force mapping page zero? */
00114 BOOL Force_SMM = FALSE;     /* Force sequential memory? */
00115 char *FP_Excp_Max = NULL;   /* Max FP trap enables */
00116 char *FP_Excp_Min = NULL;   /* Min FP trap enables */
00117 BOOL Flush_To_Zero = FALSE;   /* suppress fp underflow */
00118 
00119 /* Miscellaneous target instruction features: */
00120 BOOL Madd_Allowed = FALSE;    /* Generate madd instructions? */
00121 BOOL Force_Jalr = FALSE;  /* Force calls via address in register */
00122 static BOOL Slow_CVTDL_Set = FALSE;
00123 
00124 BOOL Itanium_a0_step = FALSE;
00125 BOOL SYNC_Allowed = TRUE;
00126 BOOL Slow_CVTDL = FALSE;
00127 
00128 /* Target machine specification options.  This group defines the target
00129  * ABI, ISA, processor, and FPR count.  It should also be the home for
00130  * options like specifying processor revisions.
00131  */
00132 static OPTION_DESC Options_TARG[] = {
00133   { OVK_NAME, OV_VISIBLE, FALSE, "abi",   "ab",
00134     0, 0, 0, &ABI_Name,   NULL,
00135     "Specify the ABI to follow" },
00136   { OVK_NAME, OV_VISIBLE, FALSE, "isa",   "is",
00137     0, 0, 0, &ISA_Name,   NULL,
00138     "Specify the instruction set architecture to use" },
00139   { OVK_BOOL, OV_VISIBLE, FALSE, "mmx",   "mmx",
00140     0, 0, 0,  &Target_MMX,  &Target_MMX_Set,
00141     "Enable MMX extensions" },
00142   { OVK_BOOL, OV_VISIBLE, FALSE, "sse",   "sse",
00143     0, 0, 0,  &Target_SSE,  &Target_SSE_Set,
00144     "Enable SSE extensions" },
00145   { OVK_BOOL, OV_VISIBLE, FALSE, "sse2",    "sse2",
00146     0, 0, 0,  &Target_SSE2, &Target_SSE2_Set,
00147     "Enable SSE2 extensions" },
00148   { OVK_BOOL, OV_VISIBLE, FALSE, "sse3",    "sse3",
00149     0, 0, 0,  &Target_SSE3, &Target_SSE3_Set,
00150     "Enable SSE3 extensions" },
00151   { OVK_BOOL, OV_VISIBLE, FALSE, "3dnow",   "3dnow",
00152     0, 0, 0,  &Target_3DNow,  &Target_3DNow_Set,
00153     "Enable 3DNow extensions" },
00154   { OVK_BOOL,   OV_VISIBLE,     FALSE, "sse4a",         "sse4a",
00155     0, 0, 0,    &Target_SSE4a,  &Target_SSE4a_Set,
00156     "Enable SSE4a extensions" },
00157 
00158   { OVK_INT32,  OV_VISIBLE, FALSE, "x87-precision", "x87-precision",
00159     80, 32, 80, &Target_x87_Precision,  NULL,
00160     "Specify the precision of x87 floating-point calculations (32, 64, or 80)"},
00161 #if 0
00162   { OVK_SELF, OV_SHY,   FALSE, "mips1", NULL,
00163     0, 0, 0, &ISA_Name,   NULL,
00164     "Use the MIPS-I instruction set architecture" },
00165   { OVK_SELF, OV_SHY,   FALSE, "mips2", NULL,
00166     0, 0, 0, &ISA_Name,   NULL,
00167     "Use the MIPS-II instruction set architecture" },
00168   { OVK_SELF, OV_SHY,   FALSE, "mips3", NULL,
00169     0, 0, 0, &ISA_Name,   NULL,
00170     "Use the MIPS-III instruction set architecture" },
00171   { OVK_SELF, OV_SHY,   FALSE, "mips4", NULL,
00172     0, 0, 0, &ISA_Name,   NULL,
00173     "Use the MIPS-IV instruction set architecture" },
00174   { OVK_SELF, OV_SHY,   FALSE, "mips5", NULL,
00175     0, 0, 0, &ISA_Name,   NULL,
00176     "Use the MIPS-V instruction set architecture" },
00177   { OVK_SELF, OV_SHY,   FALSE, "mips6", NULL,
00178     0, 0, 0, &ISA_Name,   NULL,
00179     "Use the MIPS-VI instruction set architecture" },
00180 #endif
00181   { OVK_NAME, OV_VISIBLE, FALSE, "platform",  "pl",
00182     0, 0, 0, &Platform_Name,  NULL,
00183     "Specify the target platform" },
00184   { OVK_NAME, OV_VISIBLE, FALSE, "processor", "pr",
00185     0, 0, 0, &Processor_Name, NULL,
00186     "Specify the target microprocessor" },
00187 
00188   /* Miscellaneous features: */
00189   { OVK_BOOL, OV_VISIBLE, FALSE, "dismiss_mem_faults",  "dis",
00190     0, 0, 0,  &Force_Memory_Dismiss, NULL,
00191     "Force kernel to ignore memory faults (SIGSEGV/SIGBUS)" },
00192   { OVK_NAME, OV_VISIBLE, FALSE, "exc_max", "exc_ma",
00193     0, 0, 0,  &FP_Excp_Max, NULL,
00194     "Specify the only floating point exceptions which may be trapped" },
00195   { OVK_NAME, OV_VISIBLE, FALSE, "exc_min", "exc_mi",
00196     0, 0, 0,  &FP_Excp_Min, NULL,
00197     "Specify any floating point exceptions which must be trapped" },
00198   { OVK_BOOL, OV_SHY,   FALSE, "force_jalr",  "",
00199     0, 0, 0,  &Force_Jalr,  NULL,
00200     "Force use of JALR instruction for all subprogram calls" },
00201   { OVK_BOOL, OV_VISIBLE, FALSE, "flush_to_zero", "",
00202     0, 0, 0,  &Flush_To_Zero, NULL,
00203     "Suppress floating point underflow exceptions" },
00204   { OVK_BOOL, OV_VISIBLE, FALSE, "fp_precise",  "fp_p",
00205     0, 0, 0,  &Force_FP_Precise_Mode, NULL,
00206     "Force the processor into precise floating point mode" },
00207   { OVK_INT32,  OV_INTERNAL,  FALSE, "fp_regs", "fp_r",
00208     32, 16, 32, &Target_FPRs, NULL,
00209     "Specify number of FP registers to use (16 or 32)" },
00210   { OVK_BOOL, OV_VISIBLE, FALSE, "madd",    "",
00211     0, 0, 0,  &Madd_Allowed,  NULL,
00212     "Specify whether to generate MADD instructions" },
00213   { OVK_BOOL, OV_SHY,   FALSE, "page_zero", "",
00214     0, 0, 0,  &Force_Page_Zero, NULL,
00215     "Force the kernel to map page zero into address space" },
00216   { OVK_BOOL, OV_INTERNAL,  FALSE, "slow_cvtdl", "",
00217     0, 0, 0,  &Slow_CVTDL,  &Slow_CVTDL_Set,
00218     "" },
00219   { OVK_BOOL, OV_SHY,   FALSE, "seq_memory",  "seq",
00220     0, 0, 0,  &Force_SMM, NULL,
00221     "Force the processor into sequential memory mode" },
00222   { OVK_BOOL, OV_VISIBLE, FALSE, "sync", "",
00223     0, 0, 0,  &SYNC_Allowed,  NULL,
00224     "Specify whether to generate SYNC instructions" },
00225   { OVK_BOOL, OV_INTERNAL,  FALSE, "pure",  "pu",
00226     0, 0, 0,  &Pure_ABI,  NULL,
00227     "Generate pure ABI-compliant code" },
00228 
00229   { OVK_BOOL,   OV_INTERNAL,    FALSE, "ma0_step", "",
00230     0, 0, 0,    &Itanium_a0_step, NULL,
00231     "" },
00232 
00233   /* Unimplemented options: */
00234   /* Obsolete options: */
00235 
00236   { OVK_COUNT }   /* List terminator -- must be last */
00237 };
00238 
00239 
00240 /* ====================================================================
00241  *
00242  * Configure_Source_TARG
00243  *
00244  * Same as Configure_Source except here we handle target specifics.
00245  *
00246  * ====================================================================
00247  */
00248 static void
00249 Configure_Source_TARG ( char *filename )
00251 {
00252 }
osprey/common/com/x8664/config_targ_opt.cxx
