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osprey/kg++fe/gnu/MIPS/insn-output.c

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00001 /* Generated automatically by the program `genoutput'
00002    from the machine description file `md'.  */
00003 
00004 #include "config.h"
00005 #include "system.h"
00006 #include "flags.h"
00007 #include "ggc.h"
00008 #include "rtl.h"
00009 #include "expr.h"
00010 #include "insn-codes.h"
00011 #include "tm_p.h"
00012 #include "function.h"
00013 #include "regs.h"
00014 #include "hard-reg-set.h"
00015 #include "real.h"
00016 #include "insn-config.h"
00017 
00018 #include "conditions.h"
00019 #include "insn-attr.h"
00020 #include "insn-flags.h"
00021 #include "recog.h"
00022 
00023 #include "toplev.h"
00024 #include "output.h"
00025 
00026 static const char *output_0 PARAMS ((rtx *, rtx));
00027 
00028 static const char *
00029 output_0 (operands, insn)
00030      rtx *operands ATTRIBUTE_UNUSED;
00031      rtx insn ATTRIBUTE_UNUSED;
00032 {
00033 
00034 {
00035   if (ISA_HAS_COND_TRAP)
00036     return "teq\t$0,$0";
00037   /* The IRIX 6 O32 assembler requires the first break operand.  */
00038   else if (TARGET_MIPS16 || ! TARGET_GAS)
00039     return "break 0";
00040   else
00041     return "break";
00042 }
00043 }
00044 
00045 static const char *output_7 PARAMS ((rtx *, rtx));
00046 
00047 static const char *
00048 output_7 (operands, insn)
00049      rtx *operands ATTRIBUTE_UNUSED;
00050      rtx insn ATTRIBUTE_UNUSED;
00051 {
00052 
00053 {
00054   if (REGNO (operands[0]) == REGNO (operands[1]))
00055     return "addu\t%0,%2";
00056   return "addu\t%0,%1,%2";
00057 }
00058 }
00059 
00060 static const char *output_8 PARAMS ((rtx *, rtx));
00061 
00062 static const char *
00063 output_8 (operands, insn)
00064      rtx *operands ATTRIBUTE_UNUSED;
00065      rtx insn ATTRIBUTE_UNUSED;
00066 {
00067 
00068 {
00069   return (REGNO (operands[0]) == REGNO (operands[1])
00070     && REGNO (operands[0]) == REGNO (operands[2]))
00071     ? "srl\t%3,%L0,31\n\tsll\t%M0,%M0,1\n\tsll\t%L0,%L1,1\n\taddu\t%M0,%M0,%3"
00072     : "addu\t%L0,%L1,%L2\n\tsltu\t%3,%L0,%L2\n\taddu\t%M0,%M1,%M2\n\taddu\t%M0,%M0,%3";
00073 }
00074 }
00075 
00076 static const char * const output_9[] = {
00077   "addu\t%L0,%L1,%2\n\tsltu\t%3,%L0,%2\n\taddu\t%M0,%M1,%3",
00078   "move\t%L0,%L1\n\tmove\t%M0,%M1",
00079   "subu\t%L0,%L1,%n2\n\tsltu\t%3,%L0,%2\n\tsubu\t%M0,%M1,1\n\taddu\t%M0,%M0,%3",
00080 };
00081 
00082 static const char *output_10 PARAMS ((rtx *, rtx));
00083 
00084 static const char *
00085 output_10 (operands, insn)
00086      rtx *operands ATTRIBUTE_UNUSED;
00087      rtx insn ATTRIBUTE_UNUSED;
00088 {
00089 
00090 {
00091   return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
00092     ? "dsubu\t%0,%z1,%n2"
00093     : "daddu\t%0,%z1,%2";
00094 }
00095 }
00096 
00097 static const char *output_13 PARAMS ((rtx *, rtx));
00098 
00099 static const char *
00100 output_13 (operands, insn)
00101      rtx *operands ATTRIBUTE_UNUSED;
00102      rtx insn ATTRIBUTE_UNUSED;
00103 {
00104 
00105 {
00106   if (REGNO (operands[0]) == REGNO (operands[1]))
00107     return "daddu\t%0,%2";
00108   return "daddu\t%0,%1,%2";
00109 }
00110 }
00111 
00112 static const char *output_14 PARAMS ((rtx *, rtx));
00113 
00114 static const char *
00115 output_14 (operands, insn)
00116      rtx *operands ATTRIBUTE_UNUSED;
00117      rtx insn ATTRIBUTE_UNUSED;
00118 {
00119 
00120 {
00121   return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
00122     ? "subu\t%0,%z1,%n2"
00123     : "addu\t%0,%z1,%2";
00124 }
00125 }
00126 
00127 static const char *output_15 PARAMS ((rtx *, rtx));
00128 
00129 static const char *
00130 output_15 (operands, insn)
00131      rtx *operands ATTRIBUTE_UNUSED;
00132      rtx insn ATTRIBUTE_UNUSED;
00133 {
00134 
00135 {
00136   if (REGNO (operands[0]) == REGNO (operands[1]))
00137     return "addu\t%0,%2";
00138   return "addu\t%0,%1,%2";
00139 }
00140 }
00141 
00142 static const char *output_21 PARAMS ((rtx *, rtx));
00143 
00144 static const char *
00145 output_21 (operands, insn)
00146      rtx *operands ATTRIBUTE_UNUSED;
00147      rtx insn ATTRIBUTE_UNUSED;
00148 {
00149 
00150 {
00151   if (REGNO (operands[0]) == REGNO (operands[1]))
00152     return "subu\t%0,%2";
00153   return "subu\t%0,%1,%2";
00154 }
00155 }
00156 
00157 static const char * const output_23[] = {
00158   "sltu\t%3,%L1,%2\n\tsubu\t%L0,%L1,%2\n\tsubu\t%M0,%M1,%3",
00159   "move\t%L0,%L1\n\tmove\t%M0,%M1",
00160   "sltu\t%3,%L1,%2\n\tsubu\t%L0,%L1,%2\n\tsubu\t%M0,%M1,1\n\tsubu\t%M0,%M0,%3",
00161 };
00162 
00163 static const char *output_24 PARAMS ((rtx *, rtx));
00164 
00165 static const char *
00166 output_24 (operands, insn)
00167      rtx *operands ATTRIBUTE_UNUSED;
00168      rtx insn ATTRIBUTE_UNUSED;
00169 {
00170 
00171 {
00172   return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
00173     ? "daddu\t%0,%z1,%n2"
00174     : "dsubu\t%0,%z1,%2";
00175 }
00176 }
00177 
00178 static const char *output_27 PARAMS ((rtx *, rtx));
00179 
00180 static const char *
00181 output_27 (operands, insn)
00182      rtx *operands ATTRIBUTE_UNUSED;
00183      rtx insn ATTRIBUTE_UNUSED;
00184 {
00185 
00186 {
00187   if (REGNO (operands[0]) == REGNO (operands[1]))
00188     return "dsubu\t%0,%2";
00189   return "dsubu\t%0,%1,%2";
00190 }
00191 }
00192 
00193 static const char *output_28 PARAMS ((rtx *, rtx));
00194 
00195 static const char *
00196 output_28 (operands, insn)
00197      rtx *operands ATTRIBUTE_UNUSED;
00198      rtx insn ATTRIBUTE_UNUSED;
00199 {
00200 
00201 {
00202   return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
00203     ? "addu\t%0,%z1,%n2"
00204     : "subu\t%0,%z1,%2";
00205 }
00206 }
00207 
00208 static const char *output_29 PARAMS ((rtx *, rtx));
00209 
00210 static const char *
00211 output_29 (operands, insn)
00212      rtx *operands ATTRIBUTE_UNUSED;
00213      rtx insn ATTRIBUTE_UNUSED;
00214 {
00215 
00216 {
00217   if (REGNO (operands[0]) == REGNO (operands[1]))
00218     return "subu\t%0,%2";
00219   return "subu\t%0,%1,%2";
00220 }
00221 }
00222 
00223 static const char *output_31 PARAMS ((rtx *, rtx));
00224 
00225 static const char *
00226 output_31 (operands, insn)
00227      rtx *operands ATTRIBUTE_UNUSED;
00228      rtx insn ATTRIBUTE_UNUSED;
00229 {
00230 
00231 {
00232   output_asm_insn ("mul.d\t%0,%1,%2", operands);
00233   if (TARGET_4300_MUL_FIX)
00234     output_asm_insn ("nop", operands);
00235   return "";
00236 }
00237 }
00238 
00239 static const char *output_33 PARAMS ((rtx *, rtx));
00240 
00241 static const char *
00242 output_33 (operands, insn)
00243      rtx *operands ATTRIBUTE_UNUSED;
00244      rtx insn ATTRIBUTE_UNUSED;
00245 {
00246 
00247 {
00248   output_asm_insn ("mul.s\t%0,%1,%2", operands);
00249   if (TARGET_4300_MUL_FIX)
00250     output_asm_insn ("nop", operands);
00251   return "";
00252 }
00253 }
00254 
00255 static const char *output_34 PARAMS ((rtx *, rtx));
00256 
00257 static const char *
00258 output_34 (operands, insn)
00259      rtx *operands ATTRIBUTE_UNUSED;
00260      rtx insn ATTRIBUTE_UNUSED;
00261 {
00262 
00263 {
00264   if (which_alternative == 1)
00265     return "mult\t%1,%2";
00266   if (TARGET_MAD
00267       || TARGET_MIPS5400
00268       || TARGET_MIPS5500
00269       || ISA_MIPS32
00270       || ISA_MIPS64)
00271     return "mul\t%0,%1,%2";
00272   return "mult\t%0,%1,%2";
00273 }
00274 }
00275 
00276 static const char *output_36 PARAMS ((rtx *, rtx));
00277 
00278 static const char *
00279 output_36 (operands, insn)
00280      rtx *operands ATTRIBUTE_UNUSED;
00281      rtx insn ATTRIBUTE_UNUSED;
00282 {
00283 
00284 {
00285   rtx xoperands[10];
00286 
00287   xoperands[0] = operands[0];
00288   xoperands[1] = gen_rtx_REG (SImode, LO_REGNUM);
00289 
00290   output_asm_insn ("mult\t%1,%2", operands);
00291   output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
00292   return "";
00293 }
00294 }
00295 
00296 static const char *output_37 PARAMS ((rtx *, rtx));
00297 
00298 static const char *
00299 output_37 (operands, insn)
00300      rtx *operands ATTRIBUTE_UNUSED;
00301      rtx insn ATTRIBUTE_UNUSED;
00302 {
00303 
00304 {
00305   static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
00306   static const char *const macc[] = { "macc\t$0,%1,%2", "macc\t%0,%1,%2" };
00307   if (which_alternative == 2)
00308     return "#";
00309   if (ISA_HAS_MADD_MSUB && which_alternative != 0)
00310     return "#";
00311 
00312   if (TARGET_MIPS5400)
00313     return macc[which_alternative];
00314 
00315   if (TARGET_MIPS5500)
00316     {
00317       if (which_alternative == 0)
00318         return madd[0];
00319       else
00320         return macc[which_alternative];
00321     }
00322 
00323   return madd[which_alternative];
00324 }
00325 }
00326 
00327 static const char *output_38 PARAMS ((rtx *, rtx));
00328 
00329 static const char *
00330 output_38 (operands, insn)
00331      rtx *operands ATTRIBUTE_UNUSED;
00332      rtx insn ATTRIBUTE_UNUSED;
00333 {
00334 
00335 {
00336   if (which_alternative != 0)
00337     return "#";
00338   return "msub\t%2,%3";
00339 }
00340 }
00341 
00342 static const char * const output_39[] = {
00343   "muls\t$0,%1,%2",
00344   "muls\t%0,%1,%2",
00345 };
00346 
00347 static const char * const output_40[] = {
00348   "msac\t$0,%2,%3",
00349   "msac\t%0,%2,%3",
00350   "#",
00351 };
00352 
00353 static const char *output_42 PARAMS ((rtx *, rtx));
00354 
00355 static const char *
00356 output_42 (operands, insn)
00357      rtx *operands ATTRIBUTE_UNUSED;
00358      rtx insn ATTRIBUTE_UNUSED;
00359 {
00360 
00361 {
00362   if (GENERATE_MULT3_DI)
00363     output_asm_insn ("dmult\t%0,%1,%2", operands);
00364   else
00365     {
00366       rtx xoperands[10];
00367 
00368       xoperands[0] = operands[0];
00369       xoperands[1] = gen_rtx_REG (DImode, LO_REGNUM);
00370 
00371       output_asm_insn ("dmult\t%1,%2", operands);
00372       output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
00373     }
00374   return "";
00375 }
00376 }
00377 
00378 static const char *output_43 PARAMS ((rtx *, rtx));
00379 
00380 static const char *
00381 output_43 (operands, insn)
00382      rtx *operands ATTRIBUTE_UNUSED;
00383      rtx insn ATTRIBUTE_UNUSED;
00384 {
00385 
00386 {
00387   if (GET_CODE (operands[3]) == SIGN_EXTEND)
00388     return "mult\t%1,%2";
00389   return "multu\t%1,%2";
00390 }
00391 }
00392 
00393 static const char *output_44 PARAMS ((rtx *, rtx));
00394 
00395 static const char *
00396 output_44 (operands, insn)
00397      rtx *operands ATTRIBUTE_UNUSED;
00398      rtx insn ATTRIBUTE_UNUSED;
00399 {
00400 
00401 {
00402   if (GET_CODE (operands[3]) == SIGN_EXTEND)
00403     return "mult\t%1,%2";
00404   return "multu\t%1,%2";
00405 }
00406 }
00407 
00408 static const char *output_45 PARAMS ((rtx *, rtx));
00409 
00410 static const char *
00411 output_45 (operands, insn)
00412      rtx *operands ATTRIBUTE_UNUSED;
00413      rtx insn ATTRIBUTE_UNUSED;
00414 {
00415 
00416 {
00417   if (GET_CODE (operands[3]) == SIGN_EXTEND)
00418     return "muls\t$0,%1,%2";
00419   else
00420     return "mulsu\t$0,%1,%2";
00421 }
00422 }
00423 
00424 static const char *output_46 PARAMS ((rtx *, rtx));
00425 
00426 static const char *
00427 output_46 (operands, insn)
00428      rtx *operands ATTRIBUTE_UNUSED;
00429      rtx insn ATTRIBUTE_UNUSED;
00430 {
00431 
00432 {
00433   if (GET_CODE (operands[4]) == SIGN_EXTEND)
00434      {
00435        if (TARGET_MIPS5500)
00436          return "msub\t%1,%2";
00437        else
00438     return "msac\t$0,%1,%2";
00439     }
00440   else
00441      {
00442        if (TARGET_MIPS5500)
00443          return "msubu\t%1,%2";
00444        else
00445     return "msacu\t$0,%1,%2";
00446     }
00447 }
00448 }
00449 
00450 static const char *output_47 PARAMS ((rtx *, rtx));
00451 
00452 static const char *
00453 output_47 (operands, insn)
00454      rtx *operands ATTRIBUTE_UNUSED;
00455      rtx insn ATTRIBUTE_UNUSED;
00456 {
00457 
00458 {
00459   if (GET_CODE (operands[3]) == SIGN_EXTEND)
00460     return "mult\t%1,%2";
00461   else
00462     return "multu\t%1,%2";
00463 }
00464 }
00465 
00466 static const char *output_48 PARAMS ((rtx *, rtx));
00467 
00468 static const char *
00469 output_48 (operands, insn)
00470      rtx *operands ATTRIBUTE_UNUSED;
00471      rtx insn ATTRIBUTE_UNUSED;
00472 {
00473 
00474 {
00475   static char const *const sign[] = { "mult\t%1,%2",  "mulhi\t%0,%1,%2"  };
00476   static char const *const zero[] = { "multu\t%1,%2", "mulhiu\t%0,%1,%2" };
00477   if (GET_CODE (operands[3]) == SIGN_EXTEND)
00478     return sign[which_alternative];
00479   else
00480     return zero[which_alternative];
00481 }
00482 }
00483 
00484 static const char *output_49 PARAMS ((rtx *, rtx));
00485 
00486 static const char *
00487 output_49 (operands, insn)
00488      rtx *operands ATTRIBUTE_UNUSED;
00489      rtx insn ATTRIBUTE_UNUSED;
00490 {
00491 
00492 {
00493   static char const *const sign[] = { "mulshi\t$0,%1,%2",  "mulshi\t%0,%1,%2"  };
00494   static char const *const zero[] = { "mulshiu\t$0,%1,%2", "mulshiu\t%0,%1,%2" };
00495   if (GET_CODE (operands[3]) == SIGN_EXTEND)
00496     return sign[which_alternative];
00497   else
00498     return zero[which_alternative];
00499 }
00500 }
00501 
00502 static const char *output_53 PARAMS ((rtx *, rtx));
00503 
00504 static const char *
00505 output_53 (operands, insn)
00506      rtx *operands ATTRIBUTE_UNUSED;
00507      rtx insn ATTRIBUTE_UNUSED;
00508 {
00509 
00510 {
00511   if (GET_CODE (operands[3]) == SIGN_EXTEND)
00512     return "mad\t%1,%2";
00513   else
00514     return "madu\t%1,%2";
00515 }
00516 }
00517 
00518 static const char *output_54 PARAMS ((rtx *, rtx));
00519 
00520 static const char *
00521 output_54 (operands, insn)
00522      rtx *operands ATTRIBUTE_UNUSED;
00523      rtx insn ATTRIBUTE_UNUSED;
00524 {
00525 
00526 {
00527   if (TARGET_MAD)
00528     {
00529       if (GET_CODE (operands[3]) == SIGN_EXTEND)
00530         return "mad\t%1,%2";
00531       else
00532         return "madu\t%1,%2";
00533     }
00534   else if (ISA_HAS_MACC)
00535     {
00536       if (GET_CODE (operands[3]) == SIGN_EXTEND)
00537         {
00538           if (TARGET_MIPS5500)
00539             return "madd\t%1,%2";
00540           else
00541         return "macc\t$0,%1,%2";
00542         }
00543       else
00544         {
00545           if (TARGET_MIPS5500)
00546             return "maddu\t%1,%2";
00547           else
00548         return "maccu\t$0,%1,%2";
00549         }
00550     }
00551   else
00552     abort ();
00553 
00554 }
00555 }
00556 
00557 static const char *output_71 PARAMS ((rtx *, rtx));
00558 
00559 static const char *
00560 output_71 (operands, insn)
00561      rtx *operands ATTRIBUTE_UNUSED;
00562      rtx insn ATTRIBUTE_UNUSED;
00563 {
00564 
00565 {
00566   rtx link;
00567   int have_dep_anti = 0;
00568 
00569   /* For divmod if one division is not needed then we don't need an extra
00570      divide by zero trap, which is anti dependent on previous trap */
00571   for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
00572 
00573     if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
00574         && GET_CODE (XEXP (link, 0)) == INSN
00575         && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
00576   && which_alternative == 1)
00577       have_dep_anti = 1;
00578   if (! have_dep_anti)
00579     {
00580       if (GENERATE_BRANCHLIKELY)
00581   {
00582           if (which_alternative == 1)
00583       return "%(beql\t%0,$0,1f\n\tbreak\t%2\n%~1:%)";
00584     else
00585       return "%(beql\t%0,%1,1f\n\tbreak\t%2\n%~1:%)";
00586   }
00587       else
00588   {
00589           if (which_alternative == 1)
00590       return "%(bne\t%0,$0,1f\n\tnop\n\tbreak\t%2\n%~1:%)";
00591     else
00592       return "%(bne\t%0,%1,1f\n\tnop\n\tbreak\t%2\n%~1:%)";
00593   }
00594     }
00595   return "";
00596 }
00597 }
00598 
00599 static const char *output_72 PARAMS ((rtx *, rtx));
00600 
00601 static const char *
00602 output_72 (operands, insn)
00603      rtx *operands ATTRIBUTE_UNUSED;
00604      rtx insn ATTRIBUTE_UNUSED;
00605 {
00606 
00607 {
00608   rtx link;
00609   int have_dep_anti = 0;
00610 
00611   /* For divmod if one division is not needed then we don't need an extra
00612      divide by zero trap, which is anti dependent on previous trap */
00613   for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
00614 
00615     if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
00616         && GET_CODE (XEXP (link, 0)) == INSN
00617         && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
00618   && which_alternative == 1)
00619       have_dep_anti = 1;
00620   if (! have_dep_anti)
00621     {
00622       /* No branch delay slots on mips16.  */
00623       if (which_alternative == 1)
00624         return "%(bnez\t%0,1f\n\tbreak\t%2\n%~1:%)";
00625       else
00626         return "%(bne\t%0,%1,1f\n\tbreak\t%2\n%~1:%)";
00627     }
00628   return "";
00629 }
00630 }
00631 
00632 static const char *output_85 PARAMS ((rtx *, rtx));
00633 
00634 static const char *
00635 output_85 (operands, insn)
00636      rtx *operands ATTRIBUTE_UNUSED;
00637      rtx insn ATTRIBUTE_UNUSED;
00638 {
00639 
00640 {
00641   dslots_jump_total++;
00642   dslots_jump_filled++;
00643   operands[2] = const0_rtx;
00644 
00645   if (REGNO (operands[0]) == REGNO (operands[1]))
00646     {
00647       if (GENERATE_BRANCHLIKELY)
00648   return "%(bltzl\t%1,1f\n\tsubu\t%0,%z2,%0\n%~1:%)";
00649       else
00650   return "bgez\t%1,1f%#\n\tsubu\t%0,%z2,%0\n%~1:";
00651     }
00652   else
00653     return "%(bgez\t%1,1f\n\tmove\t%0,%1\n\tsubu\t%0,%z2,%0\n%~1:%)";
00654 }
00655 }
00656 
00657 static const char *output_86 PARAMS ((rtx *, rtx));
00658 
00659 static const char *
00660 output_86 (operands, insn)
00661      rtx *operands ATTRIBUTE_UNUSED;
00662      rtx insn ATTRIBUTE_UNUSED;
00663 {
00664 
00665 {
00666   unsigned int regno1;
00667   dslots_jump_total++;
00668   dslots_jump_filled++;
00669   operands[2] = const0_rtx;
00670 
00671   if (GET_CODE (operands[1]) == REG)
00672     regno1 = REGNO (operands[1]);
00673   else
00674     regno1 = REGNO (XEXP (operands[1], 0));
00675 
00676   if (REGNO (operands[0]) == regno1)
00677     return "%(bltzl\t%1,1f\n\tdsubu\t%0,%z2,%0\n%~1:%)";
00678   else
00679     return "%(bgez\t%1,1f\n\tmove\t%0,%1\n\tdsubu\t%0,%z2,%0\n%~1:%)";
00680 }
00681 }
00682 
00683 static const char *output_89 PARAMS ((rtx *, rtx));
00684 
00685 static const char *
00686 output_89 (operands, insn)
00687      rtx *operands ATTRIBUTE_UNUSED;
00688      rtx insn ATTRIBUTE_UNUSED;
00689 {
00690 
00691 {
00692   dslots_jump_total += 2;
00693   dslots_jump_filled += 2;
00694   operands[4] = const0_rtx;
00695 
00696   if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
00697     return "%(\
00698 move\t%0,%z4\n\
00699 \tbeq\t%1,%z4,2f\n\
00700 %~1:\tand\t%2,%1,0x0001\n\
00701 \taddu\t%0,%0,1\n\
00702 \tbeq\t%2,%z4,1b\n\
00703 \tsrl\t%1,%1,1\n\
00704 %~2:%)";
00705 
00706   return "%(\
00707 move\t%0,%z4\n\
00708 \tmove\t%3,%1\n\
00709 \tbeq\t%3,%z4,2f\n\
00710 %~1:\tand\t%2,%3,0x0001\n\
00711 \taddu\t%0,%0,1\n\
00712 \tbeq\t%2,%z4,1b\n\
00713 \tsrl\t%3,%3,1\n\
00714 %~2:%)";
00715 }
00716 }
00717 
00718 static const char *output_90 PARAMS ((rtx *, rtx));
00719 
00720 static const char *
00721 output_90 (operands, insn)
00722      rtx *operands ATTRIBUTE_UNUSED;
00723      rtx insn ATTRIBUTE_UNUSED;
00724 {
00725 
00726 {
00727   dslots_jump_total += 2;
00728   dslots_jump_filled += 2;
00729   operands[4] = const0_rtx;
00730 
00731   if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
00732     return "%(\
00733 move\t%0,%z4\n\
00734 \tbeq\t%1,%z4,2f\n\
00735 %~1:\tand\t%2,%1,0x0001\n\
00736 \tdaddu\t%0,%0,1\n\
00737 \tbeq\t%2,%z4,1b\n\
00738 \tdsrl\t%1,%1,1\n\
00739 %~2:%)";
00740 
00741   return "%(\
00742 move\t%0,%z4\n\
00743 \tmove\t%3,%1\n\
00744 \tbeq\t%3,%z4,2f\n\
00745 %~1:\tand\t%2,%3,0x0001\n\
00746 \tdaddu\t%0,%0,1\n\
00747 \tbeq\t%2,%z4,1b\n\
00748 \tdsrl\t%3,%3,1\n\
00749 %~2:%)";
00750 }
00751 }
00752 
00753 static const char *output_91 PARAMS ((rtx *, rtx));
00754 
00755 static const char *
00756 output_91 (operands, insn)
00757      rtx *operands ATTRIBUTE_UNUSED;
00758      rtx insn ATTRIBUTE_UNUSED;
00759 {
00760 
00761 {
00762   if (TARGET_MIPS16)
00763     return "neg\t%0,%1";
00764   operands[2] = const0_rtx;
00765   return "subu\t%0,%z2,%1";
00766 }
00767 }
00768 
00769 static const char *output_92 PARAMS ((rtx *, rtx));
00770 
00771 static const char *
00772 output_92 (operands, insn)
00773      rtx *operands ATTRIBUTE_UNUSED;
00774      rtx insn ATTRIBUTE_UNUSED;
00775 {
00776 
00777 {
00778   operands[3] = const0_rtx;
00779   return "subu\t%L0,%z3,%L1\n\tsubu\t%M0,%z3,%M1\n\tsltu\t%2,%z3,%L0\n\tsubu\t%M0,%M0,%2";
00780 }
00781 }
00782 
00783 static const char *output_93 PARAMS ((rtx *, rtx));
00784 
00785 static const char *
00786 output_93 (operands, insn)
00787      rtx *operands ATTRIBUTE_UNUSED;
00788      rtx insn ATTRIBUTE_UNUSED;
00789 {
00790 
00791 {
00792   operands[2] = const0_rtx;
00793   return "dsubu\t%0,%z2,%1";
00794 }
00795 }
00796 
00797 static const char *output_96 PARAMS ((rtx *, rtx));
00798 
00799 static const char *
00800 output_96 (operands, insn)
00801      rtx *operands ATTRIBUTE_UNUSED;
00802      rtx insn ATTRIBUTE_UNUSED;
00803 {
00804 
00805 {
00806   if (TARGET_MIPS16)
00807     return "not\t%0,%1";
00808   operands[2] = const0_rtx;
00809   return "nor\t%0,%z2,%1";
00810 }
00811 }
00812 
00813 static const char *output_97 PARAMS ((rtx *, rtx));
00814 
00815 static const char *
00816 output_97 (operands, insn)
00817      rtx *operands ATTRIBUTE_UNUSED;
00818      rtx insn ATTRIBUTE_UNUSED;
00819 {
00820 
00821 {
00822   if (TARGET_MIPS16)
00823     {
00824       if (TARGET_64BIT)
00825   return "not\t%0,%1";
00826       return "not\t%M0,%M1\n\tnot\t%L0,%L1";
00827     }
00828   operands[2] = const0_rtx;
00829   if (TARGET_64BIT)
00830     return "nor\t%0,%z2,%1";
00831   return "nor\t%M0,%z2,%M1\n\tnor\t%L0,%z2,%L1";
00832 }
00833 }
00834 
00835 static const char * const output_98[] = {
00836   "and\t%0,%1,%2",
00837   "andi\t%0,%1,%x2",
00838 };
00839 
00840 static const char *output_100 PARAMS ((rtx *, rtx));
00841 
00842 static const char *
00843 output_100 (operands, insn)
00844      rtx *operands ATTRIBUTE_UNUSED;
00845      rtx insn ATTRIBUTE_UNUSED;
00846 {
00847 
00848 {
00849   if (TARGET_64BIT)
00850     return "and\t%0,%1,%2";
00851   return "and\t%M0,%M1,%M2\n\tand\t%L0,%L1,%L2";
00852 }
00853 }
00854 
00855 static const char *output_101 PARAMS ((rtx *, rtx));
00856 
00857 static const char *
00858 output_101 (operands, insn)
00859      rtx *operands ATTRIBUTE_UNUSED;
00860      rtx insn ATTRIBUTE_UNUSED;
00861 {
00862 
00863 {
00864   if (TARGET_64BIT)
00865     return "and\t%0,%2";
00866   return "and\t%M0,%M2\n\tand\t%L0,%L2";
00867 }
00868 }
00869 
00870 static const char * const output_102[] = {
00871   "and\t%0,%1,%2",
00872   "andi\t%0,%1,%x2",
00873 };
00874 
00875 static const char * const output_103[] = {
00876   "or\t%0,%1,%2",
00877   "ori\t%0,%1,%x2",
00878 };
00879 
00880 static const char *output_105 PARAMS ((rtx *, rtx));
00881 
00882 static const char *
00883 output_105 (operands, insn)
00884      rtx *operands ATTRIBUTE_UNUSED;
00885      rtx insn ATTRIBUTE_UNUSED;
00886 {
00887 
00888 {
00889   if (TARGET_64BIT)
00890     return "or\t%0,%1,%2";
00891   return "or\t%M0,%M1,%M2\n\tor\t%L0,%L1,%L2";
00892 }
00893 }
00894 
00895 static const char *output_106 PARAMS ((rtx *, rtx));
00896 
00897 static const char *
00898 output_106 (operands, insn)
00899      rtx *operands ATTRIBUTE_UNUSED;
00900      rtx insn ATTRIBUTE_UNUSED;
00901 {
00902 
00903 {
00904   if (TARGET_64BIT)
00905     return "or\t%0,%2";
00906   return "or\t%M0,%M2\n\tor\t%L0,%L2";
00907 }
00908 }
00909 
00910 static const char * const output_107[] = {
00911   "xor\t%0,%1,%2",
00912   "xori\t%0,%1,%x2",
00913 };
00914 
00915 static const char * const output_108[] = {
00916   "xor\t%0,%2",
00917   "cmpi\t%1,%2",
00918   "cmp\t%1,%2",
00919 };
00920 
00921 static const char *output_109 PARAMS ((rtx *, rtx));
00922 
00923 static const char *
00924 output_109 (operands, insn)
00925      rtx *operands ATTRIBUTE_UNUSED;
00926      rtx insn ATTRIBUTE_UNUSED;
00927 {
00928 
00929 {
00930   if (TARGET_64BIT)
00931     return "xor\t%0,%1,%2";
00932   return "xor\t%M0,%M1,%M2\n\txor\t%L0,%L1,%L2";
00933 }
00934 }
00935 
00936 static const char * const output_111[] = {
00937   "xor\t%0,%2",
00938   "cmpi\t%1,%2",
00939   "cmp\t%1,%2",
00940 };
00941 
00942 static const char *output_114 PARAMS ((rtx *, rtx));
00943 
00944 static const char *
00945 output_114 (operands, insn)
00946      rtx *operands ATTRIBUTE_UNUSED;
00947      rtx insn ATTRIBUTE_UNUSED;
00948 {
00949 
00950 {
00951   if (TARGET_64BIT)
00952     return "nor\t%0,%z1,%z2";
00953   return "nor\t%M0,%M1,%M2\n\tnor\t%L0,%L1,%L2";
00954 }
00955 }
00956 
00957 static const char *output_116 PARAMS ((rtx *, rtx));
00958 
00959 static const char *
00960 output_116 (operands, insn)
00961      rtx *operands ATTRIBUTE_UNUSED;
00962      rtx insn ATTRIBUTE_UNUSED;
00963 {
00964 
00965 {
00966   if (TARGET_MIPS16)
00967     return "dsll\t%0,%1,32\n\tdsra\t%0,32";
00968   return "dsll\t%0,%1,32\n\tdsra\t%0,%0,32";
00969 }
00970 }
00971 
00972 static const char *output_117 PARAMS ((rtx *, rtx));
00973 
00974 static const char *
00975 output_117 (operands, insn)
00976      rtx *operands ATTRIBUTE_UNUSED;
00977      rtx insn ATTRIBUTE_UNUSED;
00978 {
00979 
00980 {
00981   if (TARGET_MIPS16)
00982     return "dsll\t%0,%1,48\n\tdsra\t%0,48";
00983   return "andi\t%0,%1,0xffff";
00984 }
00985 }
00986 
00987 static const char *output_118 PARAMS ((rtx *, rtx));
00988 
00989 static const char *
00990 output_118 (operands, insn)
00991      rtx *operands ATTRIBUTE_UNUSED;
00992      rtx insn ATTRIBUTE_UNUSED;
00993 {
00994 
00995 {
00996   if (TARGET_MIPS16)
00997     return "dsll\t%0,%1,56\n\tdsra\t%0,56";
00998   return "andi\t%0,%1,0x00ff";
00999 }
01000 }
01001 
01002 static const char *output_119 PARAMS ((rtx *, rtx));
01003 
01004 static const char *
01005 output_119 (operands, insn)
01006      rtx *operands ATTRIBUTE_UNUSED;
01007      rtx insn ATTRIBUTE_UNUSED;
01008 {
01009 
01010 {
01011   int shift_amt = INTVAL (operands[2]) & 0x3f;
01012 
01013   if (shift_amt < 32)
01014     {
01015       operands[2] = GEN_INT (32 - shift_amt);
01016       return "dsll\t%0,%1,%2\n\tdsra\t%0,%0,32";
01017     }
01018   else
01019     {
01020       operands[2] = GEN_INT (shift_amt);
01021       return "dsra\t%0,%1,%2";
01022     }
01023 }
01024 }
01025 
01026 static const char *output_120 PARAMS ((rtx *, rtx));
01027 
01028 static const char *
01029 output_120 (operands, insn)
01030      rtx *operands ATTRIBUTE_UNUSED;
01031      rtx insn ATTRIBUTE_UNUSED;
01032 {
01033 
01034 {
01035   int shift_amt = INTVAL (operands[2]) & 0x3f;
01036 
01037   if (shift_amt < 32)
01038     {
01039       operands[2] = GEN_INT (32 - shift_amt);
01040       return "dsll\t%0,%1,%2\n\tdsra\t%0,%0,32";
01041     }
01042   else if (shift_amt == 32)
01043     return "dsra\t%0,%1,32";
01044   else
01045     {
01046       operands[2] = GEN_INT (shift_amt);
01047       return "dsrl\t%0,%1,%2";
01048     }
01049 }
01050 }
01051 
01052 static const char *output_121 PARAMS ((rtx *, rtx));
01053 
01054 static const char *
01055 output_121 (operands, insn)
01056      rtx *operands ATTRIBUTE_UNUSED;
01057      rtx insn ATTRIBUTE_UNUSED;
01058 {
01059 
01060 {
01061   int shift_amt = INTVAL (operands[2]) & 0x3f;
01062 
01063   if (shift_amt < 32)
01064     {
01065       operands[2] = GEN_INT (32 + shift_amt);
01066       if (TARGET_MIPS16)
01067   return "dsll\t%0,%1,%2\n\tdsra\t%0,32";
01068       return "dsll\t%0,%1,%2\n\tdsra\t%0,%0,32";
01069     }
01070   else
01071     return "move\t%0,%.";
01072 }
01073 }
01074 
01075 static const char *output_125 PARAMS ((rtx *, rtx));
01076 
01077 static const char *
01078 output_125 (operands, insn)
01079      rtx *operands ATTRIBUTE_UNUSED;
01080      rtx insn ATTRIBUTE_UNUSED;
01081 {
01082  return mips_move_1word (operands, insn, TRUE);
01083 }
01084 
01085 static const char *output_126 PARAMS ((rtx *, rtx));
01086 
01087 static const char *
01088 output_126 (operands, insn)
01089      rtx *operands ATTRIBUTE_UNUSED;
01090      rtx insn ATTRIBUTE_UNUSED;
01091 {
01092 
01093 {
01094   if (which_alternative == 0)
01095     return "andi\t%0,%1,0xffff";
01096   else
01097     return mips_move_1word (operands, insn, TRUE);
01098 }
01099 }
01100 
01101 static const char *output_127 PARAMS ((rtx *, rtx));
01102 
01103 static const char *
01104 output_127 (operands, insn)
01105      rtx *operands ATTRIBUTE_UNUSED;
01106      rtx insn ATTRIBUTE_UNUSED;
01107 {
01108  return mips_move_1word (operands, insn, TRUE);
01109 }
01110 
01111 static const char *output_128 PARAMS ((rtx *, rtx));
01112 
01113 static const char *
01114 output_128 (operands, insn)
01115      rtx *operands ATTRIBUTE_UNUSED;
01116      rtx insn ATTRIBUTE_UNUSED;
01117 {
01118 
01119 {
01120   if (which_alternative == 0)
01121     return "andi\t%0,%1,0xffff";
01122   else
01123     return mips_move_1word (operands, insn, TRUE);
01124 }
01125 }
01126 
01127 static const char *output_129 PARAMS ((rtx *, rtx));
01128 
01129 static const char *
01130 output_129 (operands, insn)
01131      rtx *operands ATTRIBUTE_UNUSED;
01132      rtx insn ATTRIBUTE_UNUSED;
01133 {
01134  return mips_move_1word (operands, insn, TRUE);
01135 }
01136 
01137 static const char *output_130 PARAMS ((rtx *, rtx));
01138 
01139 static const char *
01140 output_130 (operands, insn)
01141      rtx *operands ATTRIBUTE_UNUSED;
01142      rtx insn ATTRIBUTE_UNUSED;
01143 {
01144 
01145 {
01146   if (which_alternative == 0)
01147     return "andi\t%0,%1,0x00ff";
01148   else
01149     return mips_move_1word (operands, insn, TRUE);
01150 }
01151 }
01152 
01153 static const char *output_131 PARAMS ((rtx *, rtx));
01154 
01155 static const char *
01156 output_131 (operands, insn)
01157      rtx *operands ATTRIBUTE_UNUSED;
01158      rtx insn ATTRIBUTE_UNUSED;
01159 {
01160  return mips_move_1word (operands, insn, TRUE);
01161 }
01162 
01163 static const char *output_132 PARAMS ((rtx *, rtx));
01164 
01165 static const char *
01166 output_132 (operands, insn)
01167      rtx *operands ATTRIBUTE_UNUSED;
01168      rtx insn ATTRIBUTE_UNUSED;
01169 {
01170 
01171 {
01172   if (which_alternative == 0)
01173     return "andi\t%0,%1,0x00ff";
01174   else
01175     return mips_move_1word (operands, insn, TRUE);
01176 }
01177 }
01178 
01179 static const char *output_133 PARAMS ((rtx *, rtx));
01180 
01181 static const char *
01182 output_133 (operands, insn)
01183      rtx *operands ATTRIBUTE_UNUSED;
01184      rtx insn ATTRIBUTE_UNUSED;
01185 {
01186  return mips_move_1word (operands, insn, TRUE);
01187 }
01188 
01189 static const char *output_134 PARAMS ((rtx *, rtx));
01190 
01191 static const char *
01192 output_134 (operands, insn)
01193      rtx *operands ATTRIBUTE_UNUSED;
01194      rtx insn ATTRIBUTE_UNUSED;
01195 {
01196 
01197 {
01198   if (which_alternative == 0)
01199     return "andi\t%0,%1,0x00ff";
01200   else
01201     return mips_move_1word (operands, insn, TRUE);
01202 }
01203 }
01204 
01205 static const char *output_135 PARAMS ((rtx *, rtx));
01206 
01207 static const char *
01208 output_135 (operands, insn)
01209      rtx *operands ATTRIBUTE_UNUSED;
01210      rtx insn ATTRIBUTE_UNUSED;
01211 {
01212 
01213 {
01214   return mips_move_1word (operands, insn, TRUE);
01215 }
01216 }
01217 
01218 static const char *output_136 PARAMS ((rtx *, rtx));
01219 
01220 static const char *
01221 output_136 (operands, insn)
01222      rtx *operands ATTRIBUTE_UNUSED;
01223      rtx insn ATTRIBUTE_UNUSED;
01224 {
01225  return mips_move_1word (operands, insn, TRUE);
01226 }
01227 
01228 static const char *output_137 PARAMS ((rtx *, rtx));
01229 
01230 static const char *
01231 output_137 (operands, insn)
01232      rtx *operands ATTRIBUTE_UNUSED;
01233      rtx insn ATTRIBUTE_UNUSED;
01234 {
01235  return mips_move_1word (operands, insn, FALSE);
01236 }
01237 
01238 static const char *output_138 PARAMS ((rtx *, rtx));
01239 
01240 static const char *
01241 output_138 (operands, insn)
01242      rtx *operands ATTRIBUTE_UNUSED;
01243      rtx insn ATTRIBUTE_UNUSED;
01244 {
01245  return mips_move_1word (operands, insn, FALSE);
01246 }
01247 
01248 static const char *output_139 PARAMS ((rtx *, rtx));
01249 
01250 static const char *
01251 output_139 (operands, insn)
01252      rtx *operands ATTRIBUTE_UNUSED;
01253      rtx insn ATTRIBUTE_UNUSED;
01254 {
01255  return mips_move_1word (operands, insn, FALSE);
01256 }
01257 
01258 static const char *output_140 PARAMS ((rtx *, rtx));
01259 
01260 static const char *
01261 output_140 (operands, insn)
01262      rtx *operands ATTRIBUTE_UNUSED;
01263      rtx insn ATTRIBUTE_UNUSED;
01264 {
01265  return mips_move_1word (operands, insn, FALSE);
01266 }
01267 
01268 static const char *output_141 PARAMS ((rtx *, rtx));
01269 
01270 static const char *
01271 output_141 (operands, insn)
01272      rtx *operands ATTRIBUTE_UNUSED;
01273      rtx insn ATTRIBUTE_UNUSED;
01274 {
01275  return mips_move_1word (operands, insn, FALSE);
01276 }
01277 
01278 static const char *output_153 PARAMS ((rtx *, rtx));
01279 
01280 static const char *
01281 output_153 (operands, insn)
01282      rtx *operands ATTRIBUTE_UNUSED;
01283      rtx insn ATTRIBUTE_UNUSED;
01284 {
01285 
01286 {
01287   rtx offset = const0_rtx;
01288   rtx addr = XEXP (operands[1], 0);
01289   rtx mem_addr = eliminate_constant_term (addr, &offset);
01290   const char *ret;
01291 
01292   if (TARGET_STATS)
01293     mips_count_memory_refs (operands[1], 2);
01294 
01295   /* The stack/frame pointers are always aligned, so we can convert
01296      to the faster lw if we are referencing an aligned stack location.  */
01297 
01298   if ((INTVAL (offset) & 3) == 0
01299       && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
01300     ret = "lw\t%0,%1";
01301   else
01302     ret = "ulw\t%0,%1";
01303 
01304   return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
01305 }
01306 }
01307 
01308 static const char *output_154 PARAMS ((rtx *, rtx));
01309 
01310 static const char *
01311 output_154 (operands, insn)
01312      rtx *operands ATTRIBUTE_UNUSED;
01313      rtx insn ATTRIBUTE_UNUSED;
01314 {
01315 
01316 {
01317   rtx offset = const0_rtx;
01318   rtx addr = XEXP (operands[0], 0);
01319   rtx mem_addr = eliminate_constant_term (addr, &offset);
01320 
01321   if (TARGET_STATS)
01322     mips_count_memory_refs (operands[0], 2);
01323 
01324   /* The stack/frame pointers are always aligned, so we can convert
01325      to the faster sw if we are referencing an aligned stack location.  */
01326 
01327   if ((INTVAL (offset) & 3) == 0
01328       && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
01329     return "sw\t%z1,%0";
01330 
01331   return "usw\t%z1,%0";
01332 }
01333 }
01334 
01335 static const char *output_155 PARAMS ((rtx *, rtx));
01336 
01337 static const char *
01338 output_155 (operands, insn)
01339      rtx *operands ATTRIBUTE_UNUSED;
01340      rtx insn ATTRIBUTE_UNUSED;
01341 {
01342 
01343 {
01344   rtx offset = const0_rtx;
01345   rtx addr = XEXP (operands[1], 0);
01346   rtx mem_addr = eliminate_constant_term (addr, &offset);
01347   const char *ret;
01348 
01349   if (TARGET_STATS)
01350     mips_count_memory_refs (operands[1], 2);
01351 
01352   /* The stack/frame pointers are always aligned, so we can convert
01353      to the faster lw if we are referencing an aligned stack location.  */
01354 
01355   if ((INTVAL (offset) & 7) == 0
01356       && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
01357     ret = "ld\t%0,%1";
01358   else
01359     ret = "uld\t%0,%1";
01360 
01361   return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
01362 }
01363 }
01364 
01365 static const char *output_156 PARAMS ((rtx *, rtx));
01366 
01367 static const char *
01368 output_156 (operands, insn)
01369      rtx *operands ATTRIBUTE_UNUSED;
01370      rtx insn ATTRIBUTE_UNUSED;
01371 {
01372 
01373 {
01374   rtx offset = const0_rtx;
01375   rtx addr = XEXP (operands[0], 0);
01376   rtx mem_addr = eliminate_constant_term (addr, &offset);
01377 
01378   if (TARGET_STATS)
01379     mips_count_memory_refs (operands[0], 2);
01380 
01381   /* The stack/frame pointers are always aligned, so we can convert
01382      to the faster sw if we are referencing an aligned stack location.  */
01383 
01384   if ((INTVAL (offset) & 7) == 0
01385       && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
01386     return "sd\t%z1,%0";
01387 
01388   return "usd\t%z1,%0";
01389 }
01390 }
01391 
01392 static const char *output_159 PARAMS ((rtx *, rtx));
01393 
01394 static const char *
01395 output_159 (operands, insn)
01396      rtx *operands ATTRIBUTE_UNUSED;
01397      rtx insn ATTRIBUTE_UNUSED;
01398 {
01399 
01400 {
01401   operands[1] = gen_rtx (REG, DImode, 31);
01402   return mips_move_2words (operands, insn);
01403 }
01404 }
01405 
01406 static const char *output_160 PARAMS ((rtx *, rtx));
01407 
01408 static const char *
01409 output_160 (operands, insn)
01410      rtx *operands ATTRIBUTE_UNUSED;
01411      rtx insn ATTRIBUTE_UNUSED;
01412 {
01413  return mips_move_2words (operands, insn); 
01414 }
01415 
01416 static const char *output_161 PARAMS ((rtx *, rtx));
01417 
01418 static const char *
01419 output_161 (operands, insn)
01420      rtx *operands ATTRIBUTE_UNUSED;
01421      rtx insn ATTRIBUTE_UNUSED;
01422 {
01423  return mips_move_2words (operands, insn);
01424 }
01425 
01426 static const char *output_162 PARAMS ((rtx *, rtx));
01427 
01428 static const char *
01429 output_162 (operands, insn)
01430      rtx *operands ATTRIBUTE_UNUSED;
01431      rtx insn ATTRIBUTE_UNUSED;
01432 {
01433  return mips_move_2words (operands, insn); 
01434 }
01435 
01436 static const char *output_163 PARAMS ((rtx *, rtx));
01437 
01438 static const char *
01439 output_163 (operands, insn)
01440      rtx *operands ATTRIBUTE_UNUSED;
01441      rtx insn ATTRIBUTE_UNUSED;
01442 {
01443  return mips_sign_extend (insn, operands[0], operands[1]);
01444 }
01445 
01446 static const char *output_164 PARAMS ((rtx *, rtx));
01447 
01448 static const char *
01449 output_164 (operands, insn)
01450      rtx *operands ATTRIBUTE_UNUSED;
01451      rtx insn ATTRIBUTE_UNUSED;
01452 {
01453  return mips_move_2words (operands, insn);
01454 }
01455 
01456 static const char *output_166 PARAMS ((rtx *, rtx));
01457 
01458 static const char *
01459 output_166 (operands, insn)
01460      rtx *operands ATTRIBUTE_UNUSED;
01461      rtx insn ATTRIBUTE_UNUSED;
01462 {
01463  return mips_move_1word (operands, insn, FALSE);
01464 }
01465 
01466 static const char *output_167 PARAMS ((rtx *, rtx));
01467 
01468 static const char *
01469 output_167 (operands, insn)
01470      rtx *operands ATTRIBUTE_UNUSED;
01471      rtx insn ATTRIBUTE_UNUSED;
01472 {
01473  return mips_move_1word (operands, insn, FALSE);
01474 }
01475 
01476 static const char *output_169 PARAMS ((rtx *, rtx));
01477 
01478 static const char *
01479 output_169 (operands, insn)
01480      rtx *operands ATTRIBUTE_UNUSED;
01481      rtx insn ATTRIBUTE_UNUSED;
01482 {
01483  return mips_move_1word (operands, insn, FALSE);
01484 }
01485 
01486 static const char *output_178 PARAMS ((rtx *, rtx));
01487 
01488 static const char *
01489 output_178 (operands, insn)
01490      rtx *operands ATTRIBUTE_UNUSED;
01491      rtx insn ATTRIBUTE_UNUSED;
01492 {
01493  return mips_move_1word (operands, insn, TRUE);
01494 }
01495 
01496 static const char *output_179 PARAMS ((rtx *, rtx));
01497 
01498 static const char *
01499 output_179 (operands, insn)
01500      rtx *operands ATTRIBUTE_UNUSED;
01501      rtx insn ATTRIBUTE_UNUSED;
01502 {
01503  return mips_move_1word (operands, insn, TRUE);
01504 }
01505 
01506 static const char *output_180 PARAMS ((rtx *, rtx));
01507 
01508 static const char *
01509 output_180 (operands, insn)
01510      rtx *operands ATTRIBUTE_UNUSED;
01511      rtx insn ATTRIBUTE_UNUSED;
01512 {
01513  return mips_move_1word (operands, insn, TRUE);
01514 }
01515 
01516 static const char *output_181 PARAMS ((rtx *, rtx));
01517 
01518 static const char *
01519 output_181 (operands, insn)
01520      rtx *operands ATTRIBUTE_UNUSED;
01521      rtx insn ATTRIBUTE_UNUSED;
01522 {
01523  return mips_move_1word (operands, insn, TRUE);
01524 }
01525 
01526 static const char *output_182 PARAMS ((rtx *, rtx));
01527 
01528 static const char *
01529 output_182 (operands, insn)
01530      rtx *operands ATTRIBUTE_UNUSED;
01531      rtx insn ATTRIBUTE_UNUSED;
01532 {
01533  return mips_move_1word (operands, insn, FALSE);
01534 }
01535 
01536 static const char *output_183 PARAMS ((rtx *, rtx));
01537 
01538 static const char *
01539 output_183 (operands, insn)
01540      rtx *operands ATTRIBUTE_UNUSED;
01541      rtx insn ATTRIBUTE_UNUSED;
01542 {
01543  return mips_move_1word (operands, insn, FALSE);
01544 }
01545 
01546 static const char *output_184 PARAMS ((rtx *, rtx));
01547 
01548 static const char *
01549 output_184 (operands, insn)
01550      rtx *operands ATTRIBUTE_UNUSED;
01551      rtx insn ATTRIBUTE_UNUSED;
01552 {
01553  return mips_move_1word (operands, insn, FALSE);
01554 }
01555 
01556 static const char *output_185 PARAMS ((rtx *, rtx));
01557 
01558 static const char *
01559 output_185 (operands, insn)
01560      rtx *operands ATTRIBUTE_UNUSED;
01561      rtx insn ATTRIBUTE_UNUSED;
01562 {
01563  return mips_move_2words (operands, insn); 
01564 }
01565 
01566 static const char *output_186 PARAMS ((rtx *, rtx));
01567 
01568 static const char *
01569 output_186 (operands, insn)
01570      rtx *operands ATTRIBUTE_UNUSED;
01571      rtx insn ATTRIBUTE_UNUSED;
01572 {
01573  return mips_move_2words (operands, insn); 
01574 }
01575 
01576 static const char *output_187 PARAMS ((rtx *, rtx));
01577 
01578 static const char *
01579 output_187 (operands, insn)
01580      rtx *operands ATTRIBUTE_UNUSED;
01581      rtx insn ATTRIBUTE_UNUSED;
01582 {
01583  return mips_move_2words (operands, insn); 
01584 }
01585 
01586 static const char *output_188 PARAMS ((rtx *, rtx));
01587 
01588 static const char *
01589 output_188 (operands, insn)
01590      rtx *operands ATTRIBUTE_UNUSED;
01591      rtx insn ATTRIBUTE_UNUSED;
01592 {
01593  return mips_move_2words (operands, insn);
01594 }
01595 
01596 static const char *output_190 PARAMS ((rtx *, rtx));
01597 
01598 static const char *
01599 output_190 (operands, insn)
01600      rtx *operands ATTRIBUTE_UNUSED;
01601      rtx insn ATTRIBUTE_UNUSED;
01602 {
01603  return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);
01604 }
01605 
01606 static const char *output_191 PARAMS ((rtx *, rtx));
01607 
01608 static const char *
01609 output_191 (operands, insn)
01610      rtx *operands ATTRIBUTE_UNUSED;
01611      rtx insn ATTRIBUTE_UNUSED;
01612 {
01613  return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);
01614 }
01615 
01616 static const char *output_192 PARAMS ((rtx *, rtx));
01617 
01618 static const char *
01619 output_192 (operands, insn)
01620      rtx *operands ATTRIBUTE_UNUSED;
01621      rtx insn ATTRIBUTE_UNUSED;
01622 {
01623  return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);
01624 }
01625 
01626 static const char *output_193 PARAMS ((rtx *, rtx));
01627 
01628 static const char *
01629 output_193 (operands, insn)
01630      rtx *operands ATTRIBUTE_UNUSED;
01631      rtx insn ATTRIBUTE_UNUSED;
01632 {
01633  return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);
01634 }
01635 
01636 static const char *output_194 PARAMS ((rtx *, rtx));
01637 
01638 static const char *
01639 output_194 (operands, insn)
01640      rtx *operands ATTRIBUTE_UNUSED;
01641      rtx insn ATTRIBUTE_UNUSED;
01642 {
01643  return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);
01644 }
01645 
01646 static const char *output_195 PARAMS ((rtx *, rtx));
01647 
01648 static const char *
01649 output_195 (operands, insn)
01650      rtx *operands ATTRIBUTE_UNUSED;
01651      rtx insn ATTRIBUTE_UNUSED;
01652 {
01653 
01654 {
01655   if (GET_CODE (operands[2]) == CONST_INT)
01656     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01657 
01658   return "sll\t%0,%1,%2";
01659 }
01660 }
01661 
01662 static const char *output_196 PARAMS ((rtx *, rtx));
01663 
01664 static const char *
01665 output_196 (operands, insn)
01666      rtx *operands ATTRIBUTE_UNUSED;
01667      rtx insn ATTRIBUTE_UNUSED;
01668 {
01669 
01670 {
01671   if (which_alternative == 0)
01672     return "sll\t%0,%2";
01673 
01674   if (GET_CODE (operands[2]) == CONST_INT)
01675     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01676 
01677   return "sll\t%0,%1,%2";
01678 }
01679 }
01680 
01681 static const char *output_197 PARAMS ((rtx *, rtx));
01682 
01683 static const char *
01684 output_197 (operands, insn)
01685      rtx *operands ATTRIBUTE_UNUSED;
01686      rtx insn ATTRIBUTE_UNUSED;
01687 {
01688 
01689 {
01690   operands[4] = const0_rtx;
01691   dslots_jump_total += 3;
01692   dslots_jump_filled += 2;
01693 
01694   return "sll\t%3,%2,26\n\
01695 \tbgez\t%3,1f\n\
01696 \tsll\t%M0,%L1,%2\n\
01697 \t%(b\t3f\n\
01698 \tmove\t%L0,%z4%)\n\
01699 \n\
01700 %~1:\n\
01701 \t%(beq\t%3,%z4,2f\n\
01702 \tsll\t%M0,%M1,%2%)\n\
01703 \n\
01704 \tsubu\t%3,%z4,%2\n\
01705 \tsrl\t%3,%L1,%3\n\
01706 \tor\t%M0,%M0,%3\n\
01707 %~2:\n\
01708 \tsll\t%L0,%L1,%2\n\
01709 %~3:";
01710 }
01711 }
01712 
01713 static const char *output_198 PARAMS ((rtx *, rtx));
01714 
01715 static const char *
01716 output_198 (operands, insn)
01717      rtx *operands ATTRIBUTE_UNUSED;
01718      rtx insn ATTRIBUTE_UNUSED;
01719 {
01720 
01721 {
01722   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01723   operands[4] = const0_rtx;
01724   return "sll\t%M0,%L1,%2\n\tmove\t%L0,%z4";
01725 }
01726 }
01727 
01728 static const char *output_199 PARAMS ((rtx *, rtx));
01729 
01730 static const char *
01731 output_199 (operands, insn)
01732      rtx *operands ATTRIBUTE_UNUSED;
01733      rtx insn ATTRIBUTE_UNUSED;
01734 {
01735 
01736 {
01737   int amount = INTVAL (operands[2]);
01738 
01739   operands[2] = GEN_INT (amount & 31);
01740   operands[4] = const0_rtx;
01741   operands[5] = GEN_INT ((-amount) & 31);
01742 
01743   return "sll\t%M0,%M1,%2\n\tsrl\t%3,%L1,%5\n\tor\t%M0,%M0,%3\n\tsll\t%L0,%L1,%2";
01744 }
01745 }
01746 
01747 static const char *output_200 PARAMS ((rtx *, rtx));
01748 
01749 static const char *
01750 output_200 (operands, insn)
01751      rtx *operands ATTRIBUTE_UNUSED;
01752      rtx insn ATTRIBUTE_UNUSED;
01753 {
01754 
01755 {
01756   if (GET_CODE (operands[2]) == CONST_INT)
01757     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
01758 
01759   return "dsll\t%0,%1,%2";
01760 }
01761 }
01762 
01763 static const char *output_201 PARAMS ((rtx *, rtx));
01764 
01765 static const char *
01766 output_201 (operands, insn)
01767      rtx *operands ATTRIBUTE_UNUSED;
01768      rtx insn ATTRIBUTE_UNUSED;
01769 {
01770 
01771 {
01772   if (which_alternative == 0)
01773     return "dsll\t%0,%2";
01774 
01775   if (GET_CODE (operands[2]) == CONST_INT)
01776     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
01777 
01778   return "dsll\t%0,%1,%2";
01779 }
01780 }
01781 
01782 static const char *output_202 PARAMS ((rtx *, rtx));
01783 
01784 static const char *
01785 output_202 (operands, insn)
01786      rtx *operands ATTRIBUTE_UNUSED;
01787      rtx insn ATTRIBUTE_UNUSED;
01788 {
01789 
01790 {
01791   if (GET_CODE (operands[2]) == CONST_INT)
01792     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01793 
01794   return "sra\t%0,%1,%2";
01795 }
01796 }
01797 
01798 static const char *output_203 PARAMS ((rtx *, rtx));
01799 
01800 static const char *
01801 output_203 (operands, insn)
01802      rtx *operands ATTRIBUTE_UNUSED;
01803      rtx insn ATTRIBUTE_UNUSED;
01804 {
01805 
01806 {
01807   if (which_alternative == 0)
01808     return "sra\t%0,%2";
01809 
01810   if (GET_CODE (operands[2]) == CONST_INT)
01811     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01812 
01813   return "sra\t%0,%1,%2";
01814 }
01815 }
01816 
01817 static const char *output_204 PARAMS ((rtx *, rtx));
01818 
01819 static const char *
01820 output_204 (operands, insn)
01821      rtx *operands ATTRIBUTE_UNUSED;
01822      rtx insn ATTRIBUTE_UNUSED;
01823 {
01824 
01825 {
01826   operands[4] = const0_rtx;
01827   dslots_jump_total += 3;
01828   dslots_jump_filled += 2;
01829 
01830   return "sll\t%3,%2,26\n\
01831 \tbgez\t%3,1f\n\
01832 \tsra\t%L0,%M1,%2\n\
01833 \t%(b\t3f\n\
01834 \tsra\t%M0,%M1,31%)\n\
01835 \n\
01836 %~1:\n\
01837 \t%(beq\t%3,%z4,2f\n\
01838 \tsrl\t%L0,%L1,%2%)\n\
01839 \n\
01840 \tsubu\t%3,%z4,%2\n\
01841 \tsll\t%3,%M1,%3\n\
01842 \tor\t%L0,%L0,%3\n\
01843 %~2:\n\
01844 \tsra\t%M0,%M1,%2\n\
01845 %~3:";
01846 }
01847 }
01848 
01849 static const char *output_205 PARAMS ((rtx *, rtx));
01850 
01851 static const char *
01852 output_205 (operands, insn)
01853      rtx *operands ATTRIBUTE_UNUSED;
01854      rtx insn ATTRIBUTE_UNUSED;
01855 {
01856 
01857 {
01858   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01859   return "sra\t%L0,%M1,%2\n\tsra\t%M0,%M1,31";
01860 }
01861 }
01862 
01863 static const char *output_206 PARAMS ((rtx *, rtx));
01864 
01865 static const char *
01866 output_206 (operands, insn)
01867      rtx *operands ATTRIBUTE_UNUSED;
01868      rtx insn ATTRIBUTE_UNUSED;
01869 {
01870 
01871 {
01872   int amount = INTVAL (operands[2]);
01873 
01874   operands[2] = GEN_INT (amount & 31);
01875   operands[4] = GEN_INT ((-amount) & 31);
01876 
01877   return "srl\t%L0,%L1,%2\n\tsll\t%3,%M1,%4\n\tor\t%L0,%L0,%3\n\tsra\t%M0,%M1,%2";
01878 }
01879 }
01880 
01881 static const char *output_207 PARAMS ((rtx *, rtx));
01882 
01883 static const char *
01884 output_207 (operands, insn)
01885      rtx *operands ATTRIBUTE_UNUSED;
01886      rtx insn ATTRIBUTE_UNUSED;
01887 {
01888 
01889 {
01890   if (GET_CODE (operands[2]) == CONST_INT)
01891     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
01892 
01893   return "dsra\t%0,%1,%2";
01894 }
01895 }
01896 
01897 static const char *output_208 PARAMS ((rtx *, rtx));
01898 
01899 static const char *
01900 output_208 (operands, insn)
01901      rtx *operands ATTRIBUTE_UNUSED;
01902      rtx insn ATTRIBUTE_UNUSED;
01903 {
01904 
01905 {
01906   if (GET_CODE (operands[2]) == CONST_INT)
01907     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
01908 
01909   return "dsra\t%0,%2";
01910 }
01911 }
01912 
01913 static const char *output_209 PARAMS ((rtx *, rtx));
01914 
01915 static const char *
01916 output_209 (operands, insn)
01917      rtx *operands ATTRIBUTE_UNUSED;
01918      rtx insn ATTRIBUTE_UNUSED;
01919 {
01920 
01921 {
01922   if (GET_CODE (operands[2]) == CONST_INT)
01923     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01924 
01925   return "srl\t%0,%1,%2";
01926 }
01927 }
01928 
01929 static const char *output_210 PARAMS ((rtx *, rtx));
01930 
01931 static const char *
01932 output_210 (operands, insn)
01933      rtx *operands ATTRIBUTE_UNUSED;
01934      rtx insn ATTRIBUTE_UNUSED;
01935 {
01936 
01937 {
01938   if (which_alternative == 0)
01939     return "srl\t%0,%2";
01940 
01941   if (GET_CODE (operands[2]) == CONST_INT)
01942     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01943 
01944   return "srl\t%0,%1,%2";
01945 }
01946 }
01947 
01948 static const char *output_212 PARAMS ((rtx *, rtx));
01949 
01950 static const char *
01951 output_212 (operands, insn)
01952      rtx *operands ATTRIBUTE_UNUSED;
01953      rtx insn ATTRIBUTE_UNUSED;
01954 {
01955 
01956 {
01957   operands[4] = const0_rtx;
01958   dslots_jump_total += 3;
01959   dslots_jump_filled += 2;
01960 
01961   return "sll\t%3,%2,26\n\
01962 \tbgez\t%3,1f\n\
01963 \tsrl\t%L0,%M1,%2\n\
01964 \t%(b\t3f\n\
01965 \tmove\t%M0,%z4%)\n\
01966 \n\
01967 %~1:\n\
01968 \t%(beq\t%3,%z4,2f\n\
01969 \tsrl\t%L0,%L1,%2%)\n\
01970 \n\
01971 \tsubu\t%3,%z4,%2\n\
01972 \tsll\t%3,%M1,%3\n\
01973 \tor\t%L0,%L0,%3\n\
01974 %~2:\n\
01975 \tsrl\t%M0,%M1,%2\n\
01976 %~3:";
01977 }
01978 }
01979 
01980 static const char *output_213 PARAMS ((rtx *, rtx));
01981 
01982 static const char *
01983 output_213 (operands, insn)
01984      rtx *operands ATTRIBUTE_UNUSED;
01985      rtx insn ATTRIBUTE_UNUSED;
01986 {
01987 
01988 {
01989   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
01990   operands[4] = const0_rtx;
01991   return "srl\t%L0,%M1,%2\n\tmove\t%M0,%z4";
01992 }
01993 }
01994 
01995 static const char *output_214 PARAMS ((rtx *, rtx));
01996 
01997 static const char *
01998 output_214 (operands, insn)
01999      rtx *operands ATTRIBUTE_UNUSED;
02000      rtx insn ATTRIBUTE_UNUSED;
02001 {
02002 
02003 {
02004   int amount = INTVAL (operands[2]);
02005 
02006   operands[2] = GEN_INT (amount & 31);
02007   operands[4] = GEN_INT ((-amount) & 31);
02008 
02009   return "srl\t%L0,%L1,%2\n\tsll\t%3,%M1,%4\n\tor\t%L0,%L0,%3\n\tsrl\t%M0,%M1,%2";
02010 }
02011 }
02012 
02013 static const char *output_215 PARAMS ((rtx *, rtx));
02014 
02015 static const char *
02016 output_215 (operands, insn)
02017      rtx *operands ATTRIBUTE_UNUSED;
02018      rtx insn ATTRIBUTE_UNUSED;
02019 {
02020 
02021 {
02022   if (GET_CODE (operands[2]) == CONST_INT)
02023     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
02024 
02025   return "dsrl\t%0,%1,%2";
02026 }
02027 }
02028 
02029 static const char *output_216 PARAMS ((rtx *, rtx));
02030 
02031 static const char *
02032 output_216 (operands, insn)
02033      rtx *operands ATTRIBUTE_UNUSED;
02034      rtx insn ATTRIBUTE_UNUSED;
02035 {
02036 
02037 {
02038   if (GET_CODE (operands[2]) == CONST_INT)
02039     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
02040 
02041   return "dsrl\t%0,%2";
02042 }
02043 }
02044 
02045 static const char *output_217 PARAMS ((rtx *, rtx));
02046 
02047 static const char *
02048 output_217 (operands, insn)
02049      rtx *operands ATTRIBUTE_UNUSED;
02050      rtx insn ATTRIBUTE_UNUSED;
02051 {
02052 
02053 {
02054   if (TARGET_SR71K && GET_CODE (operands[2]) != CONST_INT)
02055     return "rorv\t%0,%1,%2";
02056 
02057   if ((GET_CODE (operands[2]) == CONST_INT)
02058       && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 32))
02059     abort ();
02060 
02061   return "ror\t%0,%1,%2";
02062 }
02063 }
02064 
02065 static const char *output_218 PARAMS ((rtx *, rtx));
02066 
02067 static const char *
02068 output_218 (operands, insn)
02069      rtx *operands ATTRIBUTE_UNUSED;
02070      rtx insn ATTRIBUTE_UNUSED;
02071 {
02072 
02073 {
02074    if (TARGET_SR71K)
02075     {
02076       if (GET_CODE (operands[2]) != CONST_INT)
02077         return "drorv\t%0,%1,%2";
02078 
02079       if (INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) <= 63)
02080         return "dror32\t%0,%1,%2";
02081     }
02082 
02083   if ((GET_CODE (operands[2]) == CONST_INT)
02084       && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 64))
02085     abort ();
02086 
02087   return "dror\t%0,%1,%2";
02088 }
02089 }
02090 
02091 static const char *output_219 PARAMS ((rtx *, rtx));
02092 
02093 static const char *
02094 output_219 (operands, insn)
02095      rtx *operands ATTRIBUTE_UNUSED;
02096      rtx insn ATTRIBUTE_UNUSED;
02097 {
02098 
02099 {
02100   return mips_output_conditional_branch (insn,
02101            operands,
02102            /*two_operands_p=*/0,
02103            /*float_p=*/1,
02104            /*inverted_p=*/0,
02105            get_attr_length (insn));
02106 }
02107 }
02108 
02109 static const char *output_220 PARAMS ((rtx *, rtx));
02110 
02111 static const char *
02112 output_220 (operands, insn)
02113      rtx *operands ATTRIBUTE_UNUSED;
02114      rtx insn ATTRIBUTE_UNUSED;
02115 {
02116 
02117 {
02118   return mips_output_conditional_branch (insn,
02119            operands,
02120            /*two_operands_p=*/0,
02121            /*float_p=*/1,
02122            /*inverted_p=*/1,
02123            get_attr_length (insn));
02124 }
02125 }
02126 
02127 static const char *output_221 PARAMS ((rtx *, rtx));
02128 
02129 static const char *
02130 output_221 (operands, insn)
02131      rtx *operands ATTRIBUTE_UNUSED;
02132      rtx insn ATTRIBUTE_UNUSED;
02133 {
02134 
02135 {
02136   return mips_output_conditional_branch (insn,
02137            operands,
02138            /*two_operands_p=*/0,
02139            /*float_p=*/0,
02140            /*inverted_p=*/0,
02141            get_attr_length (insn));
02142 }
02143 }
02144 
02145 static const char *output_222 PARAMS ((rtx *, rtx));
02146 
02147 static const char *
02148 output_222 (operands, insn)
02149      rtx *operands ATTRIBUTE_UNUSED;
02150      rtx insn ATTRIBUTE_UNUSED;
02151 {
02152 
02153 {
02154   return mips_output_conditional_branch (insn,
02155            operands,
02156            /*two_operands_p=*/0,
02157            /*float_p=*/0,
02158            /*inverted_p=*/1,
02159            get_attr_length (insn));
02160 }
02161 }
02162 
02163 static const char *output_223 PARAMS ((rtx *, rtx));
02164 
02165 static const char *
02166 output_223 (operands, insn)
02167      rtx *operands ATTRIBUTE_UNUSED;
02168      rtx insn ATTRIBUTE_UNUSED;
02169 {
02170 
02171 {
02172   return mips_output_conditional_branch (insn,
02173            operands,
02174            /*two_operands_p=*/0,
02175            /*float_p=*/0,
02176            /*inverted_p=*/0,
02177            get_attr_length (insn));
02178 }
02179 }
02180 
02181 static const char *output_224 PARAMS ((rtx *, rtx));
02182 
02183 static const char *
02184 output_224 (operands, insn)
02185      rtx *operands ATTRIBUTE_UNUSED;
02186      rtx insn ATTRIBUTE_UNUSED;
02187 {
02188 
02189 {
02190   return mips_output_conditional_branch (insn,
02191            operands,
02192            /*two_operands_p=*/0,
02193            /*float_p=*/0,
02194            /*inverted_p=*/1,
02195            get_attr_length (insn));
02196 }
02197 }
02198 
02199 static const char *output_225 PARAMS ((rtx *, rtx));
02200 
02201 static const char *
02202 output_225 (operands, insn)
02203      rtx *operands ATTRIBUTE_UNUSED;
02204      rtx insn ATTRIBUTE_UNUSED;
02205 {
02206 
02207 {
02208   return mips_output_conditional_branch (insn,
02209            operands,
02210            /*two_operands_p=*/1,
02211            /*float_p=*/0,
02212            /*inverted_p=*/0,
02213            get_attr_length (insn));
02214 }
02215 }
02216 
02217 static const char *output_226 PARAMS ((rtx *, rtx));
02218 
02219 static const char *
02220 output_226 (operands, insn)
02221      rtx *operands ATTRIBUTE_UNUSED;
02222      rtx insn ATTRIBUTE_UNUSED;
02223 {
02224 
02225 {
02226   return mips_output_conditional_branch (insn,
02227            operands,
02228            /*two_operands_p=*/1,
02229            /*float_p=*/0,
02230            /*inverted_p=*/0,
02231            get_attr_length (insn));
02232 }
02233 }
02234 
02235 static const char *output_227 PARAMS ((rtx *, rtx));
02236 
02237 static const char *
02238 output_227 (operands, insn)
02239      rtx *operands ATTRIBUTE_UNUSED;
02240      rtx insn ATTRIBUTE_UNUSED;
02241 {
02242 
02243 {
02244   return mips_output_conditional_branch (insn,
02245            operands,
02246            /*two_operands_p=*/1,
02247            /*float_p=*/0,
02248            /*inverted_p=*/1,
02249            get_attr_length (insn));
02250 }
02251 }
02252 
02253 static const char *output_228 PARAMS ((rtx *, rtx));
02254 
02255 static const char *
02256 output_228 (operands, insn)
02257      rtx *operands ATTRIBUTE_UNUSED;
02258      rtx insn ATTRIBUTE_UNUSED;
02259 {
02260 
02261 {
02262   return mips_output_conditional_branch (insn,
02263            operands,
02264            /*two_operands_p=*/1,
02265            /*float_p=*/0,
02266            /*inverted_p=*/1,
02267            get_attr_length (insn));
02268 }
02269 }
02270 
02271 static const char *output_229 PARAMS ((rtx *, rtx));
02272 
02273 static const char *
02274 output_229 (operands, insn)
02275      rtx *operands ATTRIBUTE_UNUSED;
02276      rtx insn ATTRIBUTE_UNUSED;
02277 {
02278 
02279 {
02280   if (operands[2] != pc_rtx)
02281     {
02282       if (which_alternative == 0)
02283   return "%*b%C0z\t%1,%2";
02284       else
02285   return "%*bt%C0z\t%2";
02286     }
02287   else
02288     {
02289       if (which_alternative == 0)
02290   return "%*b%N0z\t%1,%3";
02291       else
02292   return "%*bt%N0z\t%3";
02293     }
02294 }
02295 }
02296 
02297 static const char *output_230 PARAMS ((rtx *, rtx));
02298 
02299 static const char *
02300 output_230 (operands, insn)
02301      rtx *operands ATTRIBUTE_UNUSED;
02302      rtx insn ATTRIBUTE_UNUSED;
02303 {
02304 
02305 {
02306   if (operands[2] != pc_rtx)
02307     {
02308       if (which_alternative == 0)
02309   return "%*b%C0z\t%1,%2";
02310       else
02311   return "%*bt%C0z\t%2";
02312     }
02313   else
02314     {
02315       if (which_alternative == 0)
02316   return "%*b%N0z\t%1,%3";
02317       else
02318   return "%*bt%N0z\t%3";
02319     }
02320 }
02321 }
02322 
02323 static const char *output_245 PARAMS ((rtx *, rtx));
02324 
02325 static const char *
02326 output_245 (operands, insn)
02327      rtx *operands ATTRIBUTE_UNUSED;
02328      rtx insn ATTRIBUTE_UNUSED;
02329 {
02330 
02331 {
02332   operands[2] = GEN_INT (INTVAL (operands[2])+1);
02333   return "slt\t%0,%1,%2";
02334 }
02335 }
02336 
02337 static const char *output_246 PARAMS ((rtx *, rtx));
02338 
02339 static const char *
02340 output_246 (operands, insn)
02341      rtx *operands ATTRIBUTE_UNUSED;
02342      rtx insn ATTRIBUTE_UNUSED;
02343 {
02344 
02345 {
02346   operands[2] = GEN_INT (INTVAL (operands[2])+1);
02347   return "slt\t%1,%2";
02348 }
02349 }
02350 
02351 static const char *output_247 PARAMS ((rtx *, rtx));
02352 
02353 static const char *
02354 output_247 (operands, insn)
02355      rtx *operands ATTRIBUTE_UNUSED;
02356      rtx insn ATTRIBUTE_UNUSED;
02357 {
02358 
02359 {
02360   operands[2] = GEN_INT (INTVAL (operands[2])+1);
02361   return "slt\t%0,%1,%2";
02362 }
02363 }
02364 
02365 static const char *output_248 PARAMS ((rtx *, rtx));
02366 
02367 static const char *
02368 output_248 (operands, insn)
02369      rtx *operands ATTRIBUTE_UNUSED;
02370      rtx insn ATTRIBUTE_UNUSED;
02371 {
02372 
02373 {
02374   operands[2] = GEN_INT (INTVAL (operands[2])+1);
02375   return "slt\t%1,%2";
02376 }
02377 }
02378 
02379 static const char *output_257 PARAMS ((rtx *, rtx));
02380 
02381 static const char *
02382 output_257 (operands, insn)
02383      rtx *operands ATTRIBUTE_UNUSED;
02384      rtx insn ATTRIBUTE_UNUSED;
02385 {
02386 
02387 {
02388   operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
02389   return "sltu\t%0,%1,%2";
02390 }
02391 }
02392 
02393 static const char *output_258 PARAMS ((rtx *, rtx));
02394 
02395 static const char *
02396 output_258 (operands, insn)
02397      rtx *operands ATTRIBUTE_UNUSED;
02398      rtx insn ATTRIBUTE_UNUSED;
02399 {
02400 
02401 {
02402   operands[2] = GEN_INT (INTVAL (operands[2])+1);
02403   return "sltu\t%1,%2";
02404 }
02405 }
02406 
02407 static const char *output_259 PARAMS ((rtx *, rtx));
02408 
02409 static const char *
02410 output_259 (operands, insn)
02411      rtx *operands ATTRIBUTE_UNUSED;
02412      rtx insn ATTRIBUTE_UNUSED;
02413 {
02414 
02415 {
02416   operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
02417   return "sltu\t%0,%1,%2";
02418 }
02419 }
02420 
02421 static const char *output_260 PARAMS ((rtx *, rtx));
02422 
02423 static const char *
02424 output_260 (operands, insn)
02425      rtx *operands ATTRIBUTE_UNUSED;
02426      rtx insn ATTRIBUTE_UNUSED;
02427 {
02428 
02429 {
02430   operands[2] = GEN_INT (INTVAL (operands[2])+1);
02431   return "sltu\t%1,%2";
02432 }
02433 }
02434 
02435 static const char *output_261 PARAMS ((rtx *, rtx));
02436 
02437 static const char *
02438 output_261 (operands, insn)
02439      rtx *operands ATTRIBUTE_UNUSED;
02440      rtx insn ATTRIBUTE_UNUSED;
02441 {
02442 
02443 {
02444  return mips_fill_delay_slot ("c.un.d\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02445 }
02446 }
02447 
02448 static const char *output_262 PARAMS ((rtx *, rtx));
02449 
02450 static const char *
02451 output_262 (operands, insn)
02452      rtx *operands ATTRIBUTE_UNUSED;
02453      rtx insn ATTRIBUTE_UNUSED;
02454 {
02455 
02456 {
02457  return mips_fill_delay_slot ("c.ult.d\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02458 }
02459 }
02460 
02461 static const char *output_263 PARAMS ((rtx *, rtx));
02462 
02463 static const char *
02464 output_263 (operands, insn)
02465      rtx *operands ATTRIBUTE_UNUSED;
02466      rtx insn ATTRIBUTE_UNUSED;
02467 {
02468 
02469 {
02470  return mips_fill_delay_slot ("c.ueq.d\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02471 }
02472 }
02473 
02474 static const char *output_264 PARAMS ((rtx *, rtx));
02475 
02476 static const char *
02477 output_264 (operands, insn)
02478      rtx *operands ATTRIBUTE_UNUSED;
02479      rtx insn ATTRIBUTE_UNUSED;
02480 {
02481 
02482 {
02483  return mips_fill_delay_slot ("c.ule.d\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02484 }
02485 }
02486 
02487 static const char *output_265 PARAMS ((rtx *, rtx));
02488 
02489 static const char *
02490 output_265 (operands, insn)
02491      rtx *operands ATTRIBUTE_UNUSED;
02492      rtx insn ATTRIBUTE_UNUSED;
02493 {
02494 
02495 {
02496   return mips_fill_delay_slot ("c.eq.d\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02497 }
02498 }
02499 
02500 static const char *output_266 PARAMS ((rtx *, rtx));
02501 
02502 static const char *
02503 output_266 (operands, insn)
02504      rtx *operands ATTRIBUTE_UNUSED;
02505      rtx insn ATTRIBUTE_UNUSED;
02506 {
02507 
02508 {
02509   return mips_fill_delay_slot ("c.lt.d\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02510 }
02511 }
02512 
02513 static const char *output_267 PARAMS ((rtx *, rtx));
02514 
02515 static const char *
02516 output_267 (operands, insn)
02517      rtx *operands ATTRIBUTE_UNUSED;
02518      rtx insn ATTRIBUTE_UNUSED;
02519 {
02520 
02521 {
02522   return mips_fill_delay_slot ("c.le.d\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02523 }
02524 }
02525 
02526 static const char *output_268 PARAMS ((rtx *, rtx));
02527 
02528 static const char *
02529 output_268 (operands, insn)
02530      rtx *operands ATTRIBUTE_UNUSED;
02531      rtx insn ATTRIBUTE_UNUSED;
02532 {
02533 
02534 {
02535   return mips_fill_delay_slot ("c.lt.d\t%Z0%2,%1", DELAY_FCMP, operands, insn);
02536 }
02537 }
02538 
02539 static const char *output_269 PARAMS ((rtx *, rtx));
02540 
02541 static const char *
02542 output_269 (operands, insn)
02543      rtx *operands ATTRIBUTE_UNUSED;
02544      rtx insn ATTRIBUTE_UNUSED;
02545 {
02546 
02547 {
02548   return mips_fill_delay_slot ("c.le.d\t%Z0%2,%1", DELAY_FCMP, operands, insn);
02549 }
02550 }
02551 
02552 static const char *output_270 PARAMS ((rtx *, rtx));
02553 
02554 static const char *
02555 output_270 (operands, insn)
02556      rtx *operands ATTRIBUTE_UNUSED;
02557      rtx insn ATTRIBUTE_UNUSED;
02558 {
02559 
02560 {
02561  return mips_fill_delay_slot ("c.un.s\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02562 }
02563 }
02564 
02565 static const char *output_271 PARAMS ((rtx *, rtx));
02566 
02567 static const char *
02568 output_271 (operands, insn)
02569      rtx *operands ATTRIBUTE_UNUSED;
02570      rtx insn ATTRIBUTE_UNUSED;
02571 {
02572 
02573 {
02574  return mips_fill_delay_slot ("c.ult.s\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02575 }
02576 }
02577 
02578 static const char *output_272 PARAMS ((rtx *, rtx));
02579 
02580 static const char *
02581 output_272 (operands, insn)
02582      rtx *operands ATTRIBUTE_UNUSED;
02583      rtx insn ATTRIBUTE_UNUSED;
02584 {
02585 
02586 {
02587  return mips_fill_delay_slot ("c.ueq.s\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02588 }
02589 }
02590 
02591 static const char *output_273 PARAMS ((rtx *, rtx));
02592 
02593 static const char *
02594 output_273 (operands, insn)
02595      rtx *operands ATTRIBUTE_UNUSED;
02596      rtx insn ATTRIBUTE_UNUSED;
02597 {
02598 
02599 {
02600  return mips_fill_delay_slot ("c.ule.s\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02601 }
02602 }
02603 
02604 static const char *output_274 PARAMS ((rtx *, rtx));
02605 
02606 static const char *
02607 output_274 (operands, insn)
02608      rtx *operands ATTRIBUTE_UNUSED;
02609      rtx insn ATTRIBUTE_UNUSED;
02610 {
02611 
02612 {
02613   return mips_fill_delay_slot ("c.eq.s\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02614 }
02615 }
02616 
02617 static const char *output_275 PARAMS ((rtx *, rtx));
02618 
02619 static const char *
02620 output_275 (operands, insn)
02621      rtx *operands ATTRIBUTE_UNUSED;
02622      rtx insn ATTRIBUTE_UNUSED;
02623 {
02624 
02625 {
02626   return mips_fill_delay_slot ("c.lt.s\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02627 }
02628 }
02629 
02630 static const char *output_276 PARAMS ((rtx *, rtx));
02631 
02632 static const char *
02633 output_276 (operands, insn)
02634      rtx *operands ATTRIBUTE_UNUSED;
02635      rtx insn ATTRIBUTE_UNUSED;
02636 {
02637 
02638 {
02639   return mips_fill_delay_slot ("c.le.s\t%Z0%1,%2", DELAY_FCMP, operands, insn);
02640 }
02641 }
02642 
02643 static const char *output_277 PARAMS ((rtx *, rtx));
02644 
02645 static const char *
02646 output_277 (operands, insn)
02647      rtx *operands ATTRIBUTE_UNUSED;
02648      rtx insn ATTRIBUTE_UNUSED;
02649 {
02650 
02651 {
02652   return mips_fill_delay_slot ("c.lt.s\t%Z0%2,%1", DELAY_FCMP, operands, insn);
02653 }
02654 }
02655 
02656 static const char *output_278 PARAMS ((rtx *, rtx));
02657 
02658 static const char *
02659 output_278 (operands, insn)
02660      rtx *operands ATTRIBUTE_UNUSED;
02661      rtx insn ATTRIBUTE_UNUSED;
02662 {
02663 
02664 {
02665   return mips_fill_delay_slot ("c.le.s\t%Z0%2,%1", DELAY_FCMP, operands, insn);
02666 }
02667 }
02668 
02669 static const char *output_279 PARAMS ((rtx *, rtx));
02670 
02671 static const char *
02672 output_279 (operands, insn)
02673      rtx *operands ATTRIBUTE_UNUSED;
02674      rtx insn ATTRIBUTE_UNUSED;
02675 {
02676 
02677 {
02678   if (flag_pic && ! TARGET_EMBEDDED_PIC)
02679     {
02680       if (get_attr_length (insn) <= 8)
02681   return "%*b\t%l0";
02682       else if (Pmode == DImode)
02683   return "%[dla\t%@,%l0\n\t%*jr\t%@%]";
02684       else
02685   return "%[la\t%@,%l0\n\t%*jr\t%@%]";
02686     }
02687   else
02688     return "%*j\t%l0";
02689 }
02690 }
02691 
02692 static const char *output_285 PARAMS ((rtx *, rtx));
02693 
02694 static const char *
02695 output_285 (operands, insn)
02696      rtx *operands ATTRIBUTE_UNUSED;
02697      rtx insn ATTRIBUTE_UNUSED;
02698 {
02699 
02700 {
02701   /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic.  */
02702   if (mips_abi == ABI_32 || mips_abi == ABI_O64)
02703     output_asm_insn (".cpadd\t%0", operands);
02704   return "%*j\t%0";
02705 }
02706 }
02707 
02708 static const char *output_291 PARAMS ((rtx *, rtx));
02709 
02710 static const char *
02711 output_291 (operands, insn)
02712      rtx *operands ATTRIBUTE_UNUSED;
02713      rtx insn ATTRIBUTE_UNUSED;
02714 {
02715 
02716 {
02717   return "%*j\t%0";
02718 }
02719 }
02720 
02721 static const char *output_295 PARAMS ((rtx *, rtx));
02722 
02723 static const char *
02724 output_295 (operands, insn)
02725      rtx *operands ATTRIBUTE_UNUSED;
02726      rtx insn ATTRIBUTE_UNUSED;
02727 {
02728  return mips_restore_gp (operands, insn);
02729 }
02730 
02731 static const char *output_297 PARAMS ((rtx *, rtx));
02732 
02733 static const char *
02734 output_297 (operands, insn)
02735      rtx *operands ATTRIBUTE_UNUSED;
02736      rtx insn ATTRIBUTE_UNUSED;
02737 {
02738 
02739 {
02740   register rtx target = operands[0];
02741 
02742   if (GET_CODE (target) == CONST_INT)
02743     return "%[li\t%@,%0\n\t%*jal\t%2,%@%]";
02744   else if (CONSTANT_ADDRESS_P (target))
02745     return "%*jal\t%0";
02746   else
02747     return "%*jal\t%2,%0";
02748 }
02749 }
02750 
02751 static const char *output_298 PARAMS ((rtx *, rtx));
02752 
02753 static const char *
02754 output_298 (operands, insn)
02755      rtx *operands ATTRIBUTE_UNUSED;
02756      rtx insn ATTRIBUTE_UNUSED;
02757 {
02758 
02759 {
02760   register rtx target = operands[0];
02761 
02762   if (GET_CODE (target) == CONST_INT)
02763     return "li\t%^,%0\n\tjal\t%2,%^";
02764   else if (CONSTANT_ADDRESS_P (target))
02765     {
02766       if (GET_MODE (target) == SImode)
02767   return "la\t%^,%0\n\tjal\t%2,%^";
02768       else
02769   return "dla\t%^,%0\n\tjal\t%2,%^";
02770     }
02771   else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
02772     return "move\t%^,%0\n\tjal\t%2,%^";
02773   else
02774     return "jal\t%2,%0";
02775 }
02776 }
02777 
02778 static const char *output_302 PARAMS ((rtx *, rtx));
02779 
02780 static const char *
02781 output_302 (operands, insn)
02782      rtx *operands ATTRIBUTE_UNUSED;
02783      rtx insn ATTRIBUTE_UNUSED;
02784 {
02785 
02786 {
02787   if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
02788     return "move\t%^,%0\n\tjal\t%2,%^";
02789   else
02790     return "jal\t%2,%0";
02791 }
02792 }
02793 
02794 static const char *output_303 PARAMS ((rtx *, rtx));
02795 
02796 static const char *
02797 output_303 (operands, insn)
02798      rtx *operands ATTRIBUTE_UNUSED;
02799      rtx insn ATTRIBUTE_UNUSED;
02800 {
02801 
02802 {
02803   if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
02804     return "move\t%^,%0\n\tjal\t%2,%^";
02805   else
02806     return "jal\t%2,%0";
02807 }
02808 }
02809 
02810 static const char *output_305 PARAMS ((rtx *, rtx));
02811 
02812 static const char *
02813 output_305 (operands, insn)
02814      rtx *operands ATTRIBUTE_UNUSED;
02815      rtx insn ATTRIBUTE_UNUSED;
02816 {
02817 
02818 {
02819   register rtx target = operands[1];
02820 
02821   if (GET_CODE (target) == CONST_INT)
02822     return "%[li\t%@,%1\n\t%*jal\t%3,%@%]";
02823   else if (CONSTANT_ADDRESS_P (target))
02824     return "%*jal\t%1";
02825   else
02826     return "%*jal\t%3,%1";
02827 }
02828 }
02829 
02830 static const char *output_306 PARAMS ((rtx *, rtx));
02831 
02832 static const char *
02833 output_306 (operands, insn)
02834      rtx *operands ATTRIBUTE_UNUSED;
02835      rtx insn ATTRIBUTE_UNUSED;
02836 {
02837 
02838 {
02839   register rtx target = operands[1];
02840 
02841   if (GET_CODE (target) == CONST_INT)
02842     return "li\t%^,%1\n\tjal\t%3,%^";
02843   else if (CONSTANT_ADDRESS_P (target))
02844     {
02845       if (GET_MODE (target) == SImode)
02846   return "la\t%^,%1\n\tjal\t%3,%^";
02847       else
02848   return "dla\t%^,%1\n\tjal\t%3,%^";
02849     }
02850   else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
02851     return "move\t%^,%1\n\tjal\t%3,%^";
02852   else
02853     return "jal\t%3,%1";
02854 }
02855 }
02856 
02857 static const char *output_310 PARAMS ((rtx *, rtx));
02858 
02859 static const char *
02860 output_310 (operands, insn)
02861      rtx *operands ATTRIBUTE_UNUSED;
02862      rtx insn ATTRIBUTE_UNUSED;
02863 {
02864 
02865 {
02866   if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
02867     return "move\t%^,%1\n\tjal\t%3,%^";
02868   else
02869     return "jal\t%3,%1";
02870 }
02871 }
02872 
02873 static const char *output_311 PARAMS ((rtx *, rtx));
02874 
02875 static const char *
02876 output_311 (operands, insn)
02877      rtx *operands ATTRIBUTE_UNUSED;
02878      rtx insn ATTRIBUTE_UNUSED;
02879 {
02880 
02881 {
02882   if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
02883     return "move\t%^,%1\n\tjal\t%3,%^";
02884   else
02885     return "jal\t%3,%1";
02886 }
02887 }
02888 
02889 static const char *output_312 PARAMS ((rtx *, rtx));
02890 
02891 static const char *
02892 output_312 (operands, insn)
02893      rtx *operands ATTRIBUTE_UNUSED;
02894      rtx insn ATTRIBUTE_UNUSED;
02895 {
02896 
02897 {
02898   register rtx target = operands[1];
02899 
02900   if (GET_CODE (target) == CONST_INT)
02901     return "%[li\t%@,%1\n\t%*jal\t%4,%@%]";
02902   else if (CONSTANT_ADDRESS_P (target))
02903     return "%*jal\t%1";
02904   else
02905     return "%*jal\t%4,%1";
02906 }
02907 }
02908 
02909 static const char *output_313 PARAMS ((rtx *, rtx));
02910 
02911 static const char *
02912 output_313 (operands, insn)
02913      rtx *operands ATTRIBUTE_UNUSED;
02914      rtx insn ATTRIBUTE_UNUSED;
02915 {
02916 
02917 {
02918   register rtx target = operands[1];
02919 
02920   if (GET_CODE (target) == CONST_INT)
02921     return "li\t%^,%1\n\tjal\t%4,%^";
02922   else if (CONSTANT_ADDRESS_P (target))
02923     {
02924       if (GET_MODE (target) == SImode)
02925   return "la\t%^,%1\n\tjal\t%4,%^";
02926       else
02927   return "dla\t%^,%1\n\tjal\t%4,%^";
02928     }
02929   else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
02930     return "move\t%^,%1\n\tjal\t%4,%^";
02931   else
02932     return "jal\t%4,%1";
02933 }
02934 }
02935 
02936 static const char *output_314 PARAMS ((rtx *, rtx));
02937 
02938 static const char *
02939 output_314 (operands, insn)
02940      rtx *operands ATTRIBUTE_UNUSED;
02941      rtx insn ATTRIBUTE_UNUSED;
02942 {
02943  return mips_emit_prefetch (operands);
02944 }
02945 
02946 static const char *output_315 PARAMS ((rtx *, rtx));
02947 
02948 static const char *
02949 output_315 (operands, insn)
02950      rtx *operands ATTRIBUTE_UNUSED;
02951      rtx insn ATTRIBUTE_UNUSED;
02952 {
02953  return mips_emit_prefetch (operands);
02954 }
02955 
02956 static const char *output_316 PARAMS ((rtx *, rtx));
02957 
02958 static const char *
02959 output_316 (operands, insn)
02960      rtx *operands ATTRIBUTE_UNUSED;
02961      rtx insn ATTRIBUTE_UNUSED;
02962 {
02963  return mips_emit_prefetch (operands);
02964 }
02965 
02966 static const char *output_317 PARAMS ((rtx *, rtx));
02967 
02968 static const char *
02969 output_317 (operands, insn)
02970      rtx *operands ATTRIBUTE_UNUSED;
02971      rtx insn ATTRIBUTE_UNUSED;
02972 {
02973  return mips_emit_prefetch (operands);
02974 }
02975 
02976 static const char * const output_319[] = {
02977   "mov%B4\t%0,%z2,%1",
02978   "mov%b4\t%0,%z3,%1",
02979 };
02980 
02981 static const char * const output_320[] = {
02982   "mov%B4\t%0,%z2,%1",
02983   "mov%b4\t%0,%z3,%1",
02984 };
02985 
02986 static const char * const output_321[] = {
02987   "mov%T3\t%0,%z1,%4",
02988   "mov%t3\t%0,%z2,%4",
02989 };
02990 
02991 static const char * const output_322[] = {
02992   "mov%B4\t%0,%z2,%1",
02993   "mov%b4\t%0,%z3,%1",
02994 };
02995 
02996 static const char * const output_323[] = {
02997   "mov%B4\t%0,%z2,%1",
02998   "mov%b4\t%0,%z3,%1",
02999 };
03000 
03001 static const char * const output_324[] = {
03002   "mov%T3\t%0,%z1,%4",
03003   "mov%t3\t%0,%z2,%4",
03004 };
03005 
03006 static const char * const output_325[] = {
03007   "mov%B4.s\t%0,%2,%1",
03008   "mov%b4.s\t%0,%3,%1",
03009 };
03010 
03011 static const char * const output_326[] = {
03012   "mov%B4.s\t%0,%2,%1",
03013   "mov%b4.s\t%0,%3,%1",
03014 };
03015 
03016 static const char * const output_327[] = {
03017   "mov%T3.s\t%0,%1,%4",
03018   "mov%t3.s\t%0,%2,%4",
03019 };
03020 
03021 static const char * const output_328[] = {
03022   "mov%B4.d\t%0,%2,%1",
03023   "mov%b4.d\t%0,%3,%1",
03024 };
03025 
03026 static const char * const output_329[] = {
03027   "mov%B4.d\t%0,%2,%1",
03028   "mov%b4.d\t%0,%3,%1",
03029 };
03030 
03031 static const char * const output_330[] = {
03032   "mov%T3.d\t%0,%1,%4",
03033   "mov%t3.d\t%0,%2,%4",
03034 };
03035 
03036 static const char *output_331 PARAMS ((rtx *, rtx));
03037 
03038 static const char *
03039 output_331 (operands, insn)
03040      rtx *operands ATTRIBUTE_UNUSED;
03041      rtx insn ATTRIBUTE_UNUSED;
03042 {
03043 
03044 {
03045   assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
03046   return "";
03047 }
03048 }
03049 
03050 static const char *output_332 PARAMS ((rtx *, rtx));
03051 
03052 static const char *
03053 output_332 (operands, insn)
03054      rtx *operands ATTRIBUTE_UNUSED;
03055      rtx insn ATTRIBUTE_UNUSED;
03056 {
03057 
03058 {
03059   assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
03060   return "";
03061 }
03062 }
03063 
03064 static const char *output_333 PARAMS ((rtx *, rtx));
03065 
03066 static const char *
03067 output_333 (operands, insn)
03068      rtx *operands ATTRIBUTE_UNUSED;
03069      rtx insn ATTRIBUTE_UNUSED;
03070 {
03071 
03072 {
03073   assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
03074   return "";
03075 }
03076 }
03077 
03078 static const char *output_334 PARAMS ((rtx *, rtx));
03079 
03080 static const char *
03081 output_334 (operands, insn)
03082      rtx *operands ATTRIBUTE_UNUSED;
03083      rtx insn ATTRIBUTE_UNUSED;
03084 {
03085 
03086 {
03087   assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
03088   return "";
03089 }
03090 }
03091 
03092 static const char *output_335 PARAMS ((rtx *, rtx));
03093 
03094 static const char *
03095 output_335 (operands, insn)
03096      rtx *operands ATTRIBUTE_UNUSED;
03097      rtx insn ATTRIBUTE_UNUSED;
03098 {
03099 
03100 {
03101   REAL_VALUE_TYPE d;
03102 
03103   if (GET_CODE (operands[0]) != CONST_DOUBLE)
03104     abort ();
03105   REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
03106   assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
03107   return "";
03108 }
03109 }
03110 
03111 static const char *output_336 PARAMS ((rtx *, rtx));
03112 
03113 static const char *
03114 output_336 (operands, insn)
03115      rtx *operands ATTRIBUTE_UNUSED;
03116      rtx insn ATTRIBUTE_UNUSED;
03117 {
03118 
03119 {
03120   REAL_VALUE_TYPE d;
03121 
03122   if (GET_CODE (operands[0]) != CONST_DOUBLE)
03123     abort ();
03124   REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
03125   assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
03126   return "";
03127 }
03128 }
03129 
03130 static const char *output_529 PARAMS ((rtx *, rtx));
03131 
03132 static const char *
03133 output_529 (operands, insn)
03134      rtx *operands ATTRIBUTE_UNUSED;
03135      rtx insn ATTRIBUTE_UNUSED;
03136 {
03137 
03138 {
03139   if (operands[3] != pc_rtx)
03140     return "%*b%C2z\t%1,%3";
03141   else
03142     return "%*b%N2z\t%1,%4";
03143 }
03144 }
03145 
03146 static const char *output_530 PARAMS ((rtx *, rtx));
03147 
03148 static const char *
03149 output_530 (operands, insn)
03150      rtx *operands ATTRIBUTE_UNUSED;
03151      rtx insn ATTRIBUTE_UNUSED;
03152 {
03153 
03154 {
03155   if (operands[3] != pc_rtx)
03156     return "%*b%C2z\t%1,%3";
03157   else
03158     return "%*b%N2z\t%1,%4";
03159 }
03160 }
03161 
03162 static const char *output_531 PARAMS ((rtx *, rtx));
03163 
03164 static const char *
03165 output_531 (operands, insn)
03166      rtx *operands ATTRIBUTE_UNUSED;
03167      rtx insn ATTRIBUTE_UNUSED;
03168 {
03169 
03170 {
03171   if (operands[3] != pc_rtx)
03172     return "%*bt%C2z\t%3";
03173   else
03174     return "%*bt%N2z\t%4";
03175 }
03176 }
03177 
03178 static const char *output_532 PARAMS ((rtx *, rtx));
03179 
03180 static const char *
03181 output_532 (operands, insn)
03182      rtx *operands ATTRIBUTE_UNUSED;
03183      rtx insn ATTRIBUTE_UNUSED;
03184 {
03185 
03186 {
03187   if (operands[3] != pc_rtx)
03188     return "%*bt%C2z\t%3";
03189   else
03190     return "%*bt%N2z\t%4";
03191 }
03192 }
03193 
03194 
03195 extern int trap_cmp_op PARAMS ((rtx, enum machine_mode));
03196 extern int reg_or_0_operand PARAMS ((rtx, enum machine_mode));
03197 extern int nonmemory_operand PARAMS ((rtx, enum machine_mode));
03198 extern int register_operand PARAMS ((rtx, enum machine_mode));
03199 extern int arith_operand PARAMS ((rtx, enum machine_mode));
03200 extern int small_int PARAMS ((rtx, enum machine_mode));
03201 extern int se_reg_or_0_operand PARAMS ((rtx, enum machine_mode));
03202 extern int se_arith_operand PARAMS ((rtx, enum machine_mode));
03203 extern int scratch_operand PARAMS ((rtx, enum machine_mode));
03204 extern int se_register_operand PARAMS ((rtx, enum machine_mode));
03205 extern int extend_operator PARAMS ((rtx, enum machine_mode));
03206 extern int highpart_shift_operator PARAMS ((rtx, enum machine_mode));
03207 extern int const_float_1_operand PARAMS ((rtx, enum machine_mode));
03208 extern int true_reg_or_0_operand PARAMS ((rtx, enum machine_mode));
03209 extern int immediate_operand PARAMS ((rtx, enum machine_mode));
03210 extern int se_nonmemory_operand PARAMS ((rtx, enum machine_mode));
03211 extern int uns_arith_operand PARAMS ((rtx, enum machine_mode));
03212 extern int se_uns_arith_operand PARAMS ((rtx, enum machine_mode));
03213 extern int memory_operand PARAMS ((rtx, enum machine_mode));
03214 extern int nonimmediate_operand PARAMS ((rtx, enum machine_mode));
03215 extern int general_operand PARAMS ((rtx, enum machine_mode));
03216 extern int move_operand PARAMS ((rtx, enum machine_mode));
03217 extern int movdi_operand PARAMS ((rtx, enum machine_mode));
03218 extern int address_operand PARAMS ((rtx, enum machine_mode));
03219 extern int cmp_op PARAMS ((rtx, enum machine_mode));
03220 extern int equality_op PARAMS ((rtx, enum machine_mode));
03221 extern int pc_or_label_operand PARAMS ((rtx, enum machine_mode));
03222 extern int pmode_register_operand PARAMS ((rtx, enum machine_mode));
03223 extern int call_insn_operand PARAMS ((rtx, enum machine_mode));
03224 extern int const_int_operand PARAMS ((rtx, enum machine_mode));
03225 extern int consttable_operand PARAMS ((rtx, enum machine_mode));
03226 extern int large_int PARAMS ((rtx, enum machine_mode));
03227 extern int fcc_register_operand PARAMS ((rtx, enum machine_mode));
03228 extern int arith32_operand PARAMS ((rtx, enum machine_mode));
03229 extern int comparison_operator PARAMS ((rtx, enum machine_mode));
03230 
03231 
03232 
03233 static const struct insn_operand_data operand_data[] = 
03234 {
03235   {
03236     0,
03237     "",
03238     VOIDmode,
03239     0,
03240     0
03241   },
03242   {
03243     trap_cmp_op,
03244     "",
03245     VOIDmode,
03246     0,
03247     0
03248   },
03249   {
03250     reg_or_0_operand,
03251     "d",
03252     SImode,
03253     0,
03254     1
03255   },
03256   {
03257     nonmemory_operand,
03258     "dI",
03259     SImode,
03260     0,
03261     1
03262   },
03263   {
03264     register_operand,
03265     "=f",
03266     DFmode,
03267     0,
03268     1
03269   },
03270   {
03271     register_operand,
03272     "f",
03273     DFmode,
03274     0,
03275     1
03276   },
03277   {
03278     register_operand,
03279     "f",
03280     DFmode,
03281     0,
03282     1
03283   },
03284   {
03285     register_operand,
03286     "=f",
03287     SFmode,
03288     0,
03289     1
03290   },
03291   {
03292     register_operand,
03293     "f",
03294     SFmode,
03295     0,
03296     1
03297   },
03298   {
03299     register_operand,
03300     "f",
03301     SFmode,
03302     0,
03303     1
03304   },
03305   {
03306     register_operand,
03307     "=d",
03308     SImode,
03309     0,
03310     1
03311   },
03312   {
03313     reg_or_0_operand,
03314     "dJ",
03315     SImode,
03316     0,
03317     1
03318   },
03319   {
03320     arith_operand,
03321     "dI",
03322     SImode,
03323     0,
03324     1
03325   },
03326   {
03327     small_int,
03328     "I",
03329     SImode,
03330     0,
03331     1
03332   },
03333   {
03334     register_operand,
03335     "=d",
03336     SImode,
03337     0,
03338     1
03339   },
03340   {
03341     small_int,
03342     "I",
03343     SImode,
03344     0,
03345     1
03346   },
03347   {
03348     register_operand,
03349     "=d,d,d",
03350     SImode,
03351     0,
03352     1
03353   },
03354   {
03355     register_operand,
03356     "0,d,d",
03357     SImode,
03358     0,
03359     1
03360   },
03361   {
03362     arith_operand,
03363     "IQ,O,d",
03364     SImode,
03365     0,
03366     1
03367   },
03368   {
03369     register_operand,
03370     "=d,&d",
03371     DImode,
03372     0,
03373     1
03374   },
03375   {
03376     register_operand,
03377     "0,d",
03378     DImode,
03379     0,
03380     1
03381   },
03382   {
03383     register_operand,
03384     "d,d",
03385     DImode,
03386     0,
03387     1
03388   },
03389   {
03390     register_operand,
03391     "=d,d",
03392     SImode,
03393     0,
03394     1
03395   },
03396   {
03397     register_operand,
03398     "=d,d,d",
03399     DImode,
03400     0,
03401     1
03402   },
03403   {
03404     register_operand,
03405     "%d,%d,%d",
03406     DImode,
03407     0,
03408     1
03409   },
03410   {
03411     small_int,
03412     "P,J,N",
03413     DImode,
03414     0,
03415     1
03416   },
03417   {
03418     register_operand,
03419     "=d,d,d",
03420     SImode,
03421     0,
03422     1
03423   },
03424   {
03425     register_operand,
03426     "=d",
03427     DImode,
03428     0,
03429     1
03430   },
03431   {
03432     se_reg_or_0_operand,
03433     "dJ",
03434     DImode,
03435     0,
03436     1
03437   },
03438   {
03439     se_arith_operand,
03440     "dI",
03441     DImode,
03442     0,
03443     1
03444   },
03445   {
03446     small_int,
03447     "I",
03448     DImode,
03449     0,
03450     1
03451   },
03452   {
03453     register_operand,
03454     "=d",
03455     DImode,
03456     0,
03457     1
03458   },
03459   {
03460     small_int,
03461     "I",
03462     DImode,
03463     0,
03464     1
03465   },
03466   {
03467     register_operand,
03468     "=d,d,d",
03469     DImode,
03470     0,
03471     1
03472   },
03473   {
03474     register_operand,
03475     "0,d,d",
03476     DImode,
03477     0,
03478     1
03479   },
03480   {
03481     arith_operand,
03482     "IQ,O,d",
03483     DImode,
03484     0,
03485     1
03486   },
03487   {
03488     register_operand,
03489     "=d",
03490     DImode,
03491     0,
03492     1
03493   },
03494   {
03495     reg_or_0_operand,
03496     "dJ",
03497     SImode,
03498     0,
03499     1
03500   },
03501   {
03502     arith_operand,
03503     "dI",
03504     SImode,
03505     0,
03506     1
03507   },
03508   {
03509     register_operand,
03510     "=d,d,d",
03511     DImode,
03512     0,
03513     1
03514   },
03515   {
03516     register_operand,
03517     "0,d,d",
03518     SImode,
03519     0,
03520     1
03521   },
03522   {
03523     arith_operand,
03524     "I,O,d",
03525     SImode,
03526     0,
03527     1
03528   },
03529   {
03530     register_operand,
03531     "=d,d,d",
03532     SImode,
03533     0,
03534     1
03535   },
03536   {
03537     register_operand,
03538     "0,d,d",
03539     SImode,
03540     0,
03541     1
03542   },
03543   {
03544     arith_operand,
03545     "I,O,d",
03546     SImode,
03547     0,
03548     1
03549   },
03550   {
03551     register_operand,
03552     "=d",
03553     DImode,
03554     0,
03555     1
03556   },
03557   {
03558     register_operand,
03559     "d",
03560     DImode,
03561     0,
03562     1
03563   },
03564   {
03565     register_operand,
03566     "d",
03567     DImode,
03568     0,
03569     1
03570   },
03571   {
03572     register_operand,
03573     "=d",
03574     SImode,
03575     0,
03576     1
03577   },
03578   {
03579     register_operand,
03580     "=d,d,d",
03581     DImode,
03582     0,
03583     1
03584   },
03585   {
03586     register_operand,
03587     "d,d,d",
03588     DImode,
03589     0,
03590     1
03591   },
03592   {
03593     small_int,
03594     "P,J,N",
03595     DImode,
03596     0,
03597     1
03598   },
03599   {
03600     register_operand,
03601     "=d,d,d",
03602     SImode,
03603     0,
03604     1
03605   },
03606   {
03607     register_operand,
03608     "=d,d,d",
03609     DImode,
03610     0,
03611     1
03612   },
03613   {
03614     register_operand,
03615     "0,d,d",
03616     DImode,
03617     0,
03618     1
03619   },
03620   {
03621     arith_operand,
03622     "I,O,d",
03623     DImode,
03624     0,
03625     1
03626   },
03627   {
03628     register_operand,
03629     "=d,l",
03630     SImode,
03631     0,
03632     1
03633   },
03634   {
03635     register_operand,
03636     "d,d",
03637     SImode,
03638     0,
03639     1
03640   },
03641   {
03642     register_operand,
03643     "d,d",
03644     SImode,
03645     0,
03646     1
03647   },
03648   {
03649     scratch_operand,
03650     "=h,h",
03651     SImode,
03652     0,
03653     0
03654   },
03655   {
03656     scratch_operand,
03657     "=l,X",
03658     SImode,
03659     0,
03660     0
03661   },
03662   {
03663     scratch_operand,
03664     "=a,a",
03665     SImode,
03666     0,
03667     0
03668   },
03669   {
03670     register_operand,
03671     "=l",
03672     SImode,
03673     0,
03674     1
03675   },
03676   {
03677     register_operand,
03678     "d",
03679     SImode,
03680     0,
03681     1
03682   },
03683   {
03684     register_operand,
03685     "d",
03686     SImode,
03687     0,
03688     1
03689   },
03690   {
03691     scratch_operand,
03692     "=h",
03693     SImode,
03694     0,
03695     0
03696   },
03697   {
03698     scratch_operand,
03699     "=a",
03700     SImode,
03701     0,
03702     0
03703   },
03704   {
03705     register_operand,
03706     "=d",
03707     SImode,
03708     0,
03709     1
03710   },
03711   {
03712     register_operand,
03713     "d",
03714     SImode,
03715     0,
03716     1
03717   },
03718   {
03719     register_operand,
03720     "d",
03721     SImode,
03722     0,
03723     1
03724   },
03725   {
03726     scratch_operand,
03727     "=h",
03728     SImode,
03729     0,
03730     0
03731   },
03732   {
03733     scratch_operand,
03734     "=l",
03735     SImode,
03736     0,
03737     0
03738   },
03739   {
03740     scratch_operand,
03741     "=a",
03742     SImode,
03743     0,
03744     0
03745   },
03746   {
03747     register_operand,
03748     "=l,*d,*d",
03749     SImode,
03750     0,
03751     1
03752   },
03753   {
03754     register_operand,
03755     "d,d,d",
03756     SImode,
03757     0,
03758     1
03759   },
03760   {
03761     register_operand,
03762     "d,d,d",
03763     SImode,
03764     0,
03765     1
03766   },
03767   {
03768     register_operand,
03769     "0,l,*d",
03770     SImode,
03771     0,
03772     1
03773   },
03774   {
03775     scratch_operand,
03776     "=h,h,h",
03777     SImode,
03778     0,
03779     0
03780   },
03781   {
03782     scratch_operand,
03783     "=X,3,l",
03784     SImode,
03785     0,
03786     0
03787   },
03788   {
03789     scratch_operand,
03790     "=a,a,a",
03791     SImode,
03792     0,
03793     0
03794   },
03795   {
03796     scratch_operand,
03797     "=X,X,d",
03798     SImode,
03799     0,
03800     0
03801   },
03802   {
03803     register_operand,
03804     "=l,*d,*d",
03805     SImode,
03806     0,
03807     1
03808   },
03809   {
03810     register_operand,
03811     "0,l,*d",
03812     SImode,
03813     0,
03814     1
03815   },
03816   {
03817     register_operand,
03818     "d,d,d",
03819     SImode,
03820     0,
03821     1
03822   },
03823   {
03824     register_operand,
03825     "d,d,d",
03826     SImode,
03827     0,
03828     1
03829   },
03830   {
03831     scratch_operand,
03832     "=h,h,h",
03833     SImode,
03834     0,
03835     0
03836   },
03837   {
03838     scratch_operand,
03839     "=X,3,l",
03840     SImode,
03841     0,
03842     0
03843   },
03844   {
03845     scratch_operand,
03846     "=a,a,a",
03847     SImode,
03848     0,
03849     0
03850   },
03851   {
03852     scratch_operand,
03853     "=X,X,d",
03854     SImode,
03855     0,
03856     0
03857   },
03858   {
03859     register_operand,
03860     "=l,d",
03861     SImode,
03862     0,
03863     1
03864   },
03865   {
03866     register_operand,
03867     "d,d",
03868     SImode,
03869     0,
03870     1
03871   },
03872   {
03873     register_operand,
03874     "d,d",
03875     SImode,
03876     0,
03877     1
03878   },
03879   {
03880     scratch_operand,
03881     "=h,h",
03882     SImode,
03883     0,
03884     0
03885   },
03886   {
03887     scratch_operand,
03888     "=a,a",
03889     SImode,
03890     0,
03891     0
03892   },
03893   {
03894     scratch_operand,
03895     "=X,l",
03896     SImode,
03897     0,
03898     0
03899   },
03900   {
03901     register_operand,
03902     "=l,*d,*d",
03903     SImode,
03904     0,
03905     1
03906   },
03907   {
03908     register_operand,
03909     "0,l,*d",
03910     SImode,
03911     0,
03912     1
03913   },
03914   {
03915     register_operand,
03916     "d,d,d",
03917     SImode,
03918     0,
03919     1
03920   },
03921   {
03922     register_operand,
03923     "d,d,d",
03924     SImode,
03925     0,
03926     1
03927   },
03928   {
03929     scratch_operand,
03930     "=h,h,h",
03931     SImode,
03932     0,
03933     0
03934   },
03935   {
03936     scratch_operand,
03937     "=X,1,l",
03938     SImode,
03939     0,
03940     0
03941   },
03942   {
03943     scratch_operand,
03944     "=a,a,a",
03945     SImode,
03946     0,
03947     0
03948   },
03949   {
03950     scratch_operand,
03951     "=X,X,d",
03952     SImode,
03953     0,
03954     0
03955   },
03956   {
03957     register_operand,
03958     "=l",
03959     DImode,
03960     0,
03961     1
03962   },
03963   {
03964     se_register_operand,
03965     "d",
03966     DImode,
03967     0,
03968     1
03969   },
03970   {
03971     register_operand,
03972     "d",
03973     DImode,
03974     0,
03975     1
03976   },
03977   {
03978     scratch_operand,
03979     "=h",
03980     DImode,
03981     0,
03982     0
03983   },
03984   {
03985     scratch_operand,
03986     "=a",
03987     DImode,
03988     0,
03989     0
03990   },
03991   {
03992     register_operand,
03993     "=d",
03994     DImode,
03995     0,
03996     1
03997   },
03998   {
03999     se_register_operand,
04000     "d",
04001     DImode,
04002     0,
04003     1
04004   },
04005   {
04006     register_operand,
04007     "d",
04008     DImode,
04009     0,
04010     1
04011   },
04012   {
04013     scratch_operand,
04014     "=h",
04015     DImode,
04016     0,
04017     0
04018   },
04019   {
04020     scratch_operand,
04021     "=l",
04022     DImode,
04023     0,
04024     0
04025   },
04026   {
04027     scratch_operand,
04028     "=a",
04029     DImode,
04030     0,
04031     0
04032   },
04033   {
04034     register_operand,
04035     "=x",
04036     DImode,
04037     0,
04038     1
04039   },
04040   {
04041     register_operand,
04042     "d",
04043     SImode,
04044     0,
04045     1
04046   },
04047   {
04048     register_operand,
04049     "d",
04050     SImode,
04051     0,
04052     1
04053   },
04054   {
04055     extend_operator,
04056     "",
04057     DImode,
04058     0,
04059     0
04060   },
04061   {
04062     extend_operator,
04063     "",
04064     DImode,
04065     0,
04066     0
04067   },
04068   {
04069     scratch_operand,
04070     "=a",
04071     SImode,
04072     0,
04073     0
04074   },
04075   {
04076     register_operand,
04077     "=a",
04078     DImode,
04079     0,
04080     1
04081   },
04082   {
04083     register_operand,
04084     "d",
04085     SImode,
04086     0,
04087     1
04088   },
04089   {
04090     register_operand,
04091     "d",
04092     SImode,
04093     0,
04094     1
04095   },
04096   {
04097     extend_operator,
04098     "",
04099     DImode,
04100     0,
04101     0
04102   },
04103   {
04104     extend_operator,
04105     "",
04106     DImode,
04107     0,
04108     0
04109   },
04110   {
04111     scratch_operand,
04112     "=l",
04113     DImode,
04114     0,
04115     0
04116   },
04117   {
04118     scratch_operand,
04119     "=h",
04120     DImode,
04121     0,
04122     0
04123   },
04124   {
04125     register_operand,
04126     "=a",
04127     DImode,
04128     0,
04129     1
04130   },
04131   {
04132     register_operand,
04133     "d",
04134     SImode,
04135     0,
04136     1
04137   },
04138   {
04139     register_operand,
04140     "d",
04141     SImode,
04142     0,
04143     1
04144   },
04145   {
04146     extend_operator,
04147     "",
04148     DImode,
04149     0,
04150     0
04151   },
04152   {
04153     extend_operator,
04154     "",
04155     DImode,
04156     0,
04157     0
04158   },
04159   {
04160     scratch_operand,
04161     "=h",
04162     SImode,
04163     0,
04164     0
04165   },
04166   {
04167     scratch_operand,
04168     "=l",
04169     SImode,
04170     0,
04171     0
04172   },
04173   {
04174     register_operand,
04175     "=a",
04176     DImode,
04177     0,
04178     1
04179   },
04180   {
04181     register_operand,
04182     "d",
04183     SImode,
04184     0,
04185     1
04186   },
04187   {
04188     register_operand,
04189     "d",
04190     SImode,
04191     0,
04192     1
04193   },
04194   {
04195     register_operand,
04196     "0",
04197     DImode,
04198     0,
04199     1
04200   },
04201   {
04202     extend_operator,
04203     "",
04204     DImode,
04205     0,
04206     0
04207   },
04208   {
04209     extend_operator,
04210     "",
04211     DImode,
04212     0,
04213     0
04214   },
04215   {
04216     scratch_operand,
04217     "=h",
04218     SImode,
04219     0,
04220     0
04221   },
04222   {
04223     scratch_operand,
04224     "=l",
04225     SImode,
04226     0,
04227     0
04228   },
04229   {
04230     register_operand,
04231     "=h",
04232     SImode,
04233     0,
04234     1
04235   },
04236   {
04237     register_operand,
04238     "d",
04239     SImode,
04240     0,
04241     1
04242   },
04243   {
04244     register_operand,
04245     "d",
04246     SImode,
04247     0,
04248     1
04249   },
04250   {
04251     extend_operator,
04252     "",
04253     DImode,
04254     0,
04255     0
04256   },
04257   {
04258     extend_operator,
04259     "",
04260     DImode,
04261     0,
04262     0
04263   },
04264   {
04265     highpart_shift_operator,
04266     "",
04267     DImode,
04268     0,
04269     0
04270   },
04271   {
04272     scratch_operand,
04273     "=l",
04274     SImode,
04275     0,
04276     0
04277   },
04278   {
04279     scratch_operand,
04280     "=a",
04281     SImode,
04282     0,
04283     0
04284   },
04285   {
04286     register_operand,
04287     "=h,d",
04288     SImode,
04289     0,
04290     1
04291   },
04292   {
04293     register_operand,
04294     "d,d",
04295     SImode,
04296     0,
04297     1
04298   },
04299   {
04300     register_operand,
04301     "d,d",
04302     SImode,
04303     0,
04304     1
04305   },
04306   {
04307     extend_operator,
04308     "",
04309     DImode,
04310     0,
04311     0
04312   },
04313   {
04314     extend_operator,
04315     "",
04316     DImode,
04317     0,
04318     0
04319   },
04320   {
04321     highpart_shift_operator,
04322     "",
04323     DImode,
04324     0,
04325     0
04326   },
04327   {
04328     scratch_operand,
04329     "=l,l",
04330     SImode,
04331     0,
04332     0
04333   },
04334   {
04335     scratch_operand,
04336     "=a,a",
04337     SImode,
04338     0,
04339     0
04340   },
04341   {
04342     scratch_operand,
04343     "=X,h",
04344     SImode,
04345     0,
04346     0
04347   },
04348   {
04349     register_operand,
04350     "=h",
04351     DImode,
04352     0,
04353     1
04354   },
04355   {
04356     se_register_operand,
04357     "d",
04358     DImode,
04359     0,
04360     1
04361   },
04362   {
04363     se_register_operand,
04364     "d",
04365     DImode,
04366     0,
04367     1
04368   },
04369   {
04370     scratch_operand,
04371     "=l",
04372     DImode,
04373     0,
04374     0
04375   },
04376   {
04377     scratch_operand,
04378     "=a",
04379     DImode,
04380     0,
04381     0
04382   },
04383   {
04384     register_operand,
04385     "+l",
04386     SImode,
04387     0,
04388     1
04389   },
04390   {
04391     register_operand,
04392     "d",
04393     SImode,
04394     0,
04395     1
04396   },
04397   {
04398     register_operand,
04399     "d",
04400     SImode,
04401     0,
04402     1
04403   },
04404   {
04405     scratch_operand,
04406     "=h",
04407     SImode,
04408     0,
04409     0
04410   },
04411   {
04412     scratch_operand,
04413     "=a",
04414     SImode,
04415     0,
04416     0
04417   },
04418   {
04419     register_operand,
04420     "+x",
04421     DImode,
04422     0,
04423     1
04424   },
04425   {
04426     register_operand,
04427     "d",
04428     SImode,
04429     0,
04430     1
04431   },
04432   {
04433     register_operand,
04434     "d",
04435     SImode,
04436     0,
04437     1
04438   },
04439   {
04440     extend_operator,
04441     "",
04442     DImode,
04443     0,
04444     0
04445   },
04446   {
04447     extend_operator,
04448     "",
04449     DImode,
04450     0,
04451     0
04452   },
04453   {
04454     scratch_operand,
04455     "=a",
04456     SImode,
04457     0,
04458     0
04459   },
04460   {
04461     register_operand,
04462     "+a",
04463     DImode,
04464     0,
04465     1
04466   },
04467   {
04468     register_operand,
04469     "d",
04470     SImode,
04471     0,
04472     1
04473   },
04474   {
04475     register_operand,
04476     "d",
04477     SImode,
04478     0,
04479     1
04480   },
04481   {
04482     extend_operator,
04483     "",
04484     DImode,
04485     0,
04486     0
04487   },
04488   {
04489     extend_operator,
04490     "",
04491     DImode,
04492     0,
04493     0
04494   },
04495   {
04496     scratch_operand,
04497     "=h",
04498     SImode,
04499     0,
04500     0
04501   },
04502   {
04503     scratch_operand,
04504     "=l",
04505     SImode,
04506     0,
04507     0
04508   },
04509   {
04510     register_operand,
04511     "=f",
04512     DFmode,
04513     0,
04514     1
04515   },
04516   {
04517     register_operand,
04518     "f",
04519     DFmode,
04520     0,
04521     1
04522   },
04523   {
04524     register_operand,
04525     "f",
04526     DFmode,
04527     0,
04528     1
04529   },
04530   {
04531     register_operand,
04532     "f",
04533     DFmode,
04534     0,
04535     1
04536   },
04537   {
04538     register_operand,
04539     "=f",
04540     SFmode,
04541     0,
04542     1
04543   },
04544   {
04545     register_operand,
04546     "f",
04547     SFmode,
04548     0,
04549     1
04550   },
04551   {
04552     register_operand,
04553     "f",
04554     SFmode,
04555     0,
04556     1
04557   },
04558   {
04559     register_operand,
04560     "f",
04561     SFmode,
04562     0,
04563     1
04564   },
04565   {
04566     register_operand,
04567     "=f",
04568     DFmode,
04569     0,
04570     1
04571   },
04572   {
04573     const_float_1_operand,
04574     "",
04575     DFmode,
04576     0,
04577     1
04578   },
04579   {
04580     register_operand,
04581     "f",
04582     DFmode,
04583     0,
04584     1
04585   },
04586   {
04587     register_operand,
04588     "=f",
04589     SFmode,
04590     0,
04591     1
04592   },
04593   {
04594     const_float_1_operand,
04595     "",
04596     SFmode,
04597     0,
04598     1
04599   },
04600   {
04601     register_operand,
04602     "f",
04603     SFmode,
04604     0,
04605     1
04606   },
04607   {
04608     register_operand,
04609     "=l",
04610     SImode,
04611     0,
04612     1
04613   },
04614   {
04615     register_operand,
04616     "d",
04617     SImode,
04618     0,
04619     1
04620   },
04621   {
04622     register_operand,
04623     "d",
04624     SImode,
04625     0,
04626     1
04627   },
04628   {
04629     register_operand,
04630     "=h",
04631     SImode,
04632     0,
04633     1
04634   },
04635   {
04636     scratch_operand,
04637     "=a",
04638     SImode,
04639     0,
04640     0
04641   },
04642   {
04643     register_operand,
04644     "=l",
04645     DImode,
04646     0,
04647     1
04648   },
04649   {
04650     se_register_operand,
04651     "d",
04652     DImode,
04653     0,
04654     1
04655   },
04656   {
04657     se_register_operand,
04658     "d",
04659     DImode,
04660     0,
04661     1
04662   },
04663   {
04664     register_operand,
04665     "=h",
04666     DImode,
04667     0,
04668     1
04669   },
04670   {
04671     scratch_operand,
04672     "=a",
04673     DImode,
04674     0,
04675     0
04676   },
04677   {
04678     register_operand,
04679     "d,d",
04680     VOIDmode,
04681     0,
04682     1
04683   },
04684   {
04685     true_reg_or_0_operand,
04686     "d,J",
04687     VOIDmode,
04688     0,
04689     1
04690   },
04691   {
04692     immediate_operand,
04693     "",
04694     VOIDmode,
04695     0,
04696     1
04697   },
04698   {
04699     register_operand,
04700     "=l",
04701     SImode,
04702     0,
04703     1
04704   },
04705   {
04706     register_operand,
04707     "d",
04708     SImode,
04709     0,
04710     1
04711   },
04712   {
04713     nonmemory_operand,
04714     "di",
04715     SImode,
04716     0,
04717     1
04718   },
04719   {
04720     scratch_operand,
04721     "=h",
04722     SImode,
04723     0,
04724     0
04725   },
04726   {
04727     scratch_operand,
04728     "=a",
04729     SImode,
04730     0,
04731     0
04732   },
04733   {
04734     register_operand,
04735     "=l",
04736     DImode,
04737     0,
04738     1
04739   },
04740   {
04741     se_register_operand,
04742     "d",
04743     DImode,
04744     0,
04745     1
04746   },
04747   {
04748     se_nonmemory_operand,
04749     "di",
04750     DImode,
04751     0,
04752     1
04753   },
04754   {
04755     scratch_operand,
04756     "=h",
04757     SImode,
04758     0,
04759     0
04760   },
04761   {
04762     scratch_operand,
04763     "=a",
04764     SImode,
04765     0,
04766     0
04767   },
04768   {
04769     register_operand,
04770     "=h",
04771     SImode,
04772     0,
04773     1
04774   },
04775   {
04776     register_operand,
04777     "d",
04778     SImode,
04779     0,
04780     1
04781   },
04782   {
04783     nonmemory_operand,
04784     "di",
04785     SImode,
04786     0,
04787     1
04788   },
04789   {
04790     scratch_operand,
04791     "=l",
04792     SImode,
04793     0,
04794     0
04795   },
04796   {
04797     scratch_operand,
04798     "=a",
04799     SImode,
04800     0,
04801     0
04802   },
04803   {
04804     register_operand,
04805     "=h",
04806     DImode,
04807     0,
04808     1
04809   },
04810   {
04811     se_register_operand,
04812     "d",
04813     DImode,
04814     0,
04815     1
04816   },
04817   {
04818     se_nonmemory_operand,
04819     "di",
04820     DImode,
04821     0,
04822     1
04823   },
04824   {
04825     scratch_operand,
04826     "=l",
04827     SImode,
04828     0,
04829     0
04830   },
04831   {
04832     scratch_operand,
04833     "=a",
04834     SImode,
04835     0,
04836     0
04837   },
04838   {
04839     register_operand,
04840     "=&d",
04841     SImode,
04842     0,
04843     1
04844   },
04845   {
04846     register_operand,
04847     "d",
04848     SImode,
04849     0,
04850     1
04851   },
04852   {
04853     scratch_operand,
04854     "=&d",
04855     SImode,
04856     0,
04857     0
04858   },
04859   {
04860     scratch_operand,
04861     "=&d",
04862     SImode,
04863     0,
04864     0
04865   },
04866   {
04867     register_operand,
04868     "=&d",
04869     DImode,
04870     0,
04871     1
04872   },
04873   {
04874     se_register_operand,
04875     "d",
04876     DImode,
04877     0,
04878     1
04879   },
04880   {
04881     scratch_operand,
04882     "=&d",
04883     DImode,
04884     0,
04885     0
04886   },
04887   {
04888     scratch_operand,
04889     "=&d",
04890     DImode,
04891     0,
04892     0
04893   },
04894   {
04895     register_operand,
04896     "=d",
04897     DImode,
04898     0,
04899     1
04900   },
04901   {
04902     register_operand,
04903     "d",
04904     DImode,
04905     0,
04906     1
04907   },
04908   {
04909     register_operand,
04910     "=d",
04911     SImode,
04912     0,
04913     1
04914   },
04915   {
04916     register_operand,
04917     "=d,d",
04918     SImode,
04919     0,
04920     1
04921   },
04922   {
04923     uns_arith_operand,
04924     "%d,d",
04925     SImode,
04926     0,
04927     1
04928   },
04929   {
04930     uns_arith_operand,
04931     "d,K",
04932     SImode,
04933     0,
04934     1
04935   },
04936   {
04937     register_operand,
04938     "=d",
04939     SImode,
04940     0,
04941     1
04942   },
04943   {
04944     register_operand,
04945     "%0",
04946     SImode,
04947     0,
04948     1
04949   },
04950   {
04951     register_operand,
04952     "d",
04953     SImode,
04954     0,
04955     1
04956   },
04957   {
04958     register_operand,
04959     "=d",
04960     DImode,
04961     0,
04962     1
04963   },
04964   {
04965     se_register_operand,
04966     "d",
04967     DImode,
04968     0,
04969     1
04970   },
04971   {
04972     se_register_operand,
04973     "d",
04974     DImode,
04975     0,
04976     1
04977   },
04978   {
04979     register_operand,
04980     "=d",
04981     DImode,
04982     0,
04983     1
04984   },
04985   {
04986     se_register_operand,
04987     "0",
04988     DImode,
04989     0,
04990     1
04991   },
04992   {
04993     se_register_operand,
04994     "d",
04995     DImode,
04996     0,
04997     1
04998   },
04999   {
05000     register_operand,
05001     "=d,d",
05002     DImode,
05003     0,
05004     1
05005   },
05006   {
05007     se_register_operand,
05008     "%d,d",
05009     DImode,
05010     0,
05011     1
05012   },
05013   {
05014     se_uns_arith_operand,
05015     "d,K",
05016     DImode,
05017     0,
05018     1
05019   },
05020   {
05021     register_operand,
05022     "=d,t,t",
05023     SImode,
05024     0,
05025     1
05026   },
05027   {
05028     uns_arith_operand,
05029     "%0,d,d",
05030     SImode,
05031     0,
05032     1
05033   },
05034   {
05035     uns_arith_operand,
05036     "d,K,d",
05037     SImode,
05038     0,
05039     1
05040   },
05041   {
05042     register_operand,
05043     "=d,t,t",
05044     DImode,
05045     0,
05046     1
05047   },
05048   {
05049     se_register_operand,
05050     "%0,d,d",
05051     DImode,
05052     0,
05053     1
05054   },
05055   {
05056     se_uns_arith_operand,
05057     "d,K,d",
05058     DImode,
05059     0,
05060     1
05061   },
05062   {
05063     register_operand,
05064     "=d",
05065     DImode,
05066     0,
05067     1
05068   },
05069   {
05070     se_register_operand,
05071     "d",
05072     DImode,
05073     0,
05074     1
05075   },
05076   {
05077     se_uns_arith_operand,
05078     "K",
05079     DImode,
05080     0,
05081     1
05082   },
05083   {
05084     register_operand,
05085     "=f",
05086     SFmode,
05087     0,
05088     1
05089   },
05090   {
05091     register_operand,
05092     "f",
05093     DFmode,
05094     0,
05095     1
05096   },
05097   {
05098     register_operand,
05099     "=d",
05100     SImode,
05101     0,
05102     1
05103   },
05104   {
05105     se_register_operand,
05106     "d",
05107     DImode,
05108     0,
05109     1
05110   },
05111   {
05112     register_operand,
05113     "=d",
05114     HImode,
05115     0,
05116     1
05117   },
05118   {
05119     se_register_operand,
05120     "d",
05121     DImode,
05122     0,
05123     1
05124   },
05125   {
05126     register_operand,
05127     "=d",
05128     QImode,
05129     0,
05130     1
05131   },
05132   {
05133     se_register_operand,
05134     "d",
05135     DImode,
05136     0,
05137     1
05138   },
05139   {
05140     register_operand,
05141     "=d",
05142     SImode,
05143     0,
05144     1
05145   },
05146   {
05147     se_register_operand,
05148     "d",
05149     DImode,
05150     0,
05151     1
05152   },
05153   {
05154     small_int,
05155     "I",
05156     DImode,
05157     0,
05158     1
05159   },
05160   {
05161     register_operand,
05162     "=d,d",
05163     DImode,
05164     0,
05165     1
05166   },
05167   {
05168     memory_operand,
05169     "R,m",
05170     SImode,
05171     0,
05172     1
05173   },
05174   {
05175     register_operand,
05176     "=d,d,d",
05177     SImode,
05178     0,
05179     1
05180   },
05181   {
05182     nonimmediate_operand,
05183     "d,R,m",
05184     HImode,
05185     0,
05186     1
05187   },
05188   {
05189     register_operand,
05190     "=d,d",
05191     SImode,
05192     0,
05193     1
05194   },
05195   {
05196     memory_operand,
05197     "R,m",
05198     HImode,
05199     0,
05200     1
05201   },
05202   {
05203     register_operand,
05204     "=d,d,d",
05205     DImode,
05206     0,
05207     1
05208   },
05209   {
05210     nonimmediate_operand,
05211     "d,R,m",
05212     HImode,
05213     0,
05214     1
05215   },
05216   {
05217     register_operand,
05218     "=d,d",
05219     DImode,
05220     0,
05221     1
05222   },
05223   {
05224     memory_operand,
05225     "R,m",
05226     HImode,
05227     0,
05228     1
05229   },
05230   {
05231     register_operand,
05232     "=d,d,d",
05233     HImode,
05234     0,
05235     1
05236   },
05237   {
05238     nonimmediate_operand,
05239     "d,R,m",
05240     QImode,
05241     0,
05242     1
05243   },
05244   {
05245     register_operand,
05246     "=d,d",
05247     HImode,
05248     0,
05249     1
05250   },
05251   {
05252     memory_operand,
05253     "R,m",
05254     QImode,
05255     0,
05256     1
05257   },
05258   {
05259     register_operand,
05260     "=d,d,d",
05261     SImode,
05262     0,
05263     1
05264   },
05265   {
05266     nonimmediate_operand,
05267     "d,R,m",
05268     QImode,
05269     0,
05270     1
05271   },
05272   {
05273     register_operand,
05274     "=d,d",
05275     SImode,
05276     0,
05277     1
05278   },
05279   {
05280     memory_operand,
05281     "R,m",
05282     QImode,
05283     0,
05284     1
05285   },
05286   {
05287     register_operand,
05288     "=d,d,d",
05289     DImode,
05290     0,
05291     1
05292   },
05293   {
05294     nonimmediate_operand,
05295     "d,R,m",
05296     QImode,
05297     0,
05298     1
05299   },
05300   {
05301     register_operand,
05302     "=d,d",
05303     DImode,
05304     0,
05305     1
05306   },
05307   {
05308     memory_operand,
05309     "R,m",
05310     QImode,
05311     0,
05312     1
05313   },
05314   {
05315     register_operand,
05316     "=f",
05317     DFmode,
05318     0,
05319     1
05320   },
05321   {
05322     register_operand,
05323     "f",
05324     SFmode,
05325     0,
05326     1
05327   },
05328   {
05329     register_operand,
05330     "=f",
05331     SImode,
05332     0,
05333     1
05334   },
05335   {
05336     register_operand,
05337     "f",
05338     DFmode,
05339     0,
05340     1
05341   },
05342   {
05343     scratch_operand,
05344     "=d",
05345     DFmode,
05346     0,
05347     0
05348   },
05349   {
05350     register_operand,
05351     "=f",
05352     SImode,
05353     0,
05354     1
05355   },
05356   {
05357     register_operand,
05358     "f",
05359     SFmode,
05360     0,
05361     1
05362   },
05363   {
05364     scratch_operand,
05365     "=d",
05366     SFmode,
05367     0,
05368     0
05369   },
05370   {
05371     register_operand,
05372     "=f",
05373     DImode,
05374     0,
05375     1
05376   },
05377   {
05378     register_operand,
05379     "f",
05380     DFmode,
05381     0,
05382     1
05383   },
05384   {
05385     register_operand,
05386     "=f",
05387     DImode,
05388     0,
05389     1
05390   },
05391   {
05392     register_operand,
05393     "f",
05394     SFmode,
05395     0,
05396     1
05397   },
05398   {
05399     register_operand,
05400     "=f",
05401     DFmode,
05402     0,
05403     1
05404   },
05405   {
05406     register_operand,
05407     "f",
05408     SImode,
05409     0,
05410     1
05411   },
05412   {
05413     register_operand,
05414     "=f",
05415     DFmode,
05416     0,
05417     1
05418   },
05419   {
05420     register_operand,
05421     "f",
05422     DImode,
05423     0,
05424     1
05425   },
05426   {
05427     register_operand,
05428     "=f",
05429     SFmode,
05430     0,
05431     1
05432   },
05433   {
05434     register_operand,
05435     "f",
05436     SImode,
05437     0,
05438     1
05439   },
05440   {
05441     register_operand,
05442     "=f",
05443     SFmode,
05444     0,
05445     1
05446   },
05447   {
05448     register_operand,
05449     "f",
05450     DImode,
05451     0,
05452     1
05453   },
05454   {
05455     register_operand,
05456     "=&d,&d",
05457     SImode,
05458     0,
05459     1
05460   },
05461   {
05462     general_operand,
05463     "R,o",
05464     BLKmode,
05465     0,
05466     1
05467   },
05468   {
05469     memory_operand,
05470     "=R,o",
05471     BLKmode,
05472     0,
05473     1
05474   },
05475   {
05476     reg_or_0_operand,
05477     "dJ,dJ",
05478     SImode,
05479     0,
05480     1
05481   },
05482   {
05483     register_operand,
05484     "=&d,&d",
05485     DImode,
05486     0,
05487     1
05488   },
05489   {
05490     general_operand,
05491     "R,o",
05492     BLKmode,
05493     0,
05494     1
05495   },
05496   {
05497     memory_operand,
05498     "=R,o",
05499     BLKmode,
05500     0,
05501     1
05502   },
05503   {
05504     reg_or_0_operand,
05505     "dJ,dJ",
05506     DImode,
05507     0,
05508     1
05509   },
05510   {
05511     register_operand,
05512     "=r",
05513     SImode,
05514     0,
05515     1
05516   },
05517   {
05518     immediate_operand,
05519     "",
05520     SImode,
05521     0,
05522     1
05523   },
05524   {
05525     register_operand,
05526     "=r",
05527     SImode,
05528     0,
05529     1
05530   },
05531   {
05532     register_operand,
05533     "r",
05534     SImode,
05535     0,
05536     1
05537   },
05538   {
05539     immediate_operand,
05540     "",
05541     SImode,
05542     0,
05543     1
05544   },
05545   {
05546     memory_operand,
05547     "=R,m",
05548     DImode,
05549     0,
05550     1
05551   },
05552   {
05553     nonimmediate_operand,
05554     "=d,d,d,d,R,o,*x,*d,*x,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R",
05555     DImode,
05556     0,
05557     1
05558   },
05559   {
05560     general_operand,
05561     "d,iF,R,o,d,d,J,*x,*d,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D",
05562     DImode,
05563     0,
05564     1
05565   },
05566   {
05567     nonimmediate_operand,
05568     "=d,y,d,d,d,d,d,R,To,*d",
05569     DImode,
05570     0,
05571     1
05572   },
05573   {
05574     general_operand,
05575     "d,d,y,K,N,R,To,d,d,*x",
05576     DImode,
05577     0,
05578     1
05579   },
05580   {
05581     nonimmediate_operand,
05582     "=d,d,d,d,d,R,m,*f,*f,*f,*f,*d,*R,*m,*x,*d,*x,*a,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R",
05583     DImode,
05584     0,
05585     1
05586   },
05587   {
05588     move_operand,
05589     "d,IKL,Mnis,R,m,dJ,dJ,*f,*d*J,*R,*m,*f,*f,*f,*J,*x,*d,*J,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D",
05590     DImode,
05591     0,
05592     1
05593   },
05594   {
05595     nonimmediate_operand,
05596     "=d,d,d,d,d,R,m,*d,*f,*x,*d,*x,*a,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R",
05597     DImode,
05598     0,
05599     1
05600   },
05601   {
05602     move_operand,
05603     "d,IKL,Mnis,R,m,dJ,dJ,*f,*d*J,*J,*x,*d,*J,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D",
05604     SImode,
05605     0,
05606     1
05607   },
05608   {
05609     nonimmediate_operand,
05610     "=d,y,d,d,d,d,d,d,R,m,*d",
05611     DImode,
05612     0,
05613     1
05614   },
05615   {
05616     movdi_operand,
05617     "d,d,y,K,N,s,R,m,d,d,*x",
05618     DImode,
05619     0,
05620     1
05621   },
05622   {
05623     small_int,
05624     "n",
05625     SImode,
05626     0,
05627     1
05628   },
05629   {
05630     nonimmediate_operand,
05631     "=d,d,d,d,d,R,m,*f,*f,*f,?*f,*d,*R,*m,*d,*z,*x,*d,*x,*d,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R",
05632     SImode,
05633     0,
05634     1
05635   },
05636   {
05637     move_operand,
05638     "d,IKL,Mnis,R,m,dJ,dJ,*f,*d*J,*R,*m,*f,*f,*f,*z,*d,J,*x,*d,*a,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D",
05639     SImode,
05640     0,
05641     1
05642   },
05643   {
05644     nonimmediate_operand,
05645     "=d,y,d,d,d,d,d,d,R,m,*d,*d",
05646     SImode,
05647     0,
05648     1
05649   },
05650   {
05651     move_operand,
05652     "d,d,y,K,N,s,R,m,d,d,*x,*a",
05653     SImode,
05654     0,
05655     1
05656   },
05657   {
05658     register_operand,
05659     "=b",
05660     VOIDmode,
05661     0,
05662     1
05663   },
05664   {
05665     nonimmediate_operand,
05666     "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m",
05667     CCmode,
05668     0,
05669     1
05670   },
05671   {
05672     general_operand,
05673     "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f",
05674     CCmode,
05675     0,
05676     1
05677   },
05678   {
05679     register_operand,
05680     "=f",
05681     SFmode,
05682     0,
05683     1
05684   },
05685   {
05686     register_operand,
05687     "d",
05688     SImode,
05689     0,
05690     1
05691   },
05692   {
05693     register_operand,
05694     "d",
05695     SImode,
05696     0,
05697     1
05698   },
05699   {
05700     register_operand,
05701     "=f",
05702     SFmode,
05703     0,
05704     1
05705   },
05706   {
05707     se_register_operand,
05708     "d",
05709     DImode,
05710     0,
05711     1
05712   },
05713   {
05714     se_register_operand,
05715     "d",
05716     DImode,
05717     0,
05718     1
05719   },
05720   {
05721     register_operand,
05722     "=f",
05723     DFmode,
05724     0,
05725     1
05726   },
05727   {
05728     register_operand,
05729     "d",
05730     SImode,
05731     0,
05732     1
05733   },
05734   {
05735     register_operand,
05736     "d",
05737     SImode,
05738     0,
05739     1
05740   },
05741   {
05742     register_operand,
05743     "=f",
05744     DFmode,
05745     0,
05746     1
05747   },
05748   {
05749     se_register_operand,
05750     "d",
05751     DImode,
05752     0,
05753     1
05754   },
05755   {
05756     se_register_operand,
05757     "d",
05758     DImode,
05759     0,
05760     1
05761   },
05762   {
05763     register_operand,
05764     "f",
05765     SFmode,
05766     0,
05767     1
05768   },
05769   {
05770     register_operand,
05771     "d",
05772     SImode,
05773     0,
05774     1
05775   },
05776   {
05777     register_operand,
05778     "d",
05779     SImode,
05780     0,
05781     1
05782   },
05783   {
05784     register_operand,
05785     "f",
05786     SFmode,
05787     0,
05788     1
05789   },
05790   {
05791     se_register_operand,
05792     "d",
05793     DImode,
05794     0,
05795     1
05796   },
05797   {
05798     se_register_operand,
05799     "d",
05800     DImode,
05801     0,
05802     1
05803   },
05804   {
05805     register_operand,
05806     "f",
05807     DFmode,
05808     0,
05809     1
05810   },
05811   {
05812     register_operand,
05813     "d",
05814     SImode,
05815     0,
05816     1
05817   },
05818   {
05819     register_operand,
05820     "d",
05821     SImode,
05822     0,
05823     1
05824   },
05825   {
05826     register_operand,
05827     "f",
05828     DFmode,
05829     0,
05830     1
05831   },
05832   {
05833     se_register_operand,
05834     "d",
05835     DImode,
05836     0,
05837     1
05838   },
05839   {
05840     se_register_operand,
05841     "d",
05842     DImode,
05843     0,
05844     1
05845   },
05846   {
05847     nonimmediate_operand,
05848     "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d",
05849     HImode,
05850     0,
05851     1
05852   },
05853   {
05854     general_operand,
05855     "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x",
05856     HImode,
05857     0,
05858     1
05859   },
05860   {
05861     nonimmediate_operand,
05862     "=d,y,d,d,d,d,d,R,m,*d",
05863     HImode,
05864     0,
05865     1
05866   },
05867   {
05868     general_operand,
05869     "d,d,y,K,N,R,m,d,d,*x",
05870     HImode,
05871     0,
05872     1
05873   },
05874   {
05875     nonimmediate_operand,
05876     "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d",
05877     QImode,
05878     0,
05879     1
05880   },
05881   {
05882     general_operand,
05883     "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x",
05884     QImode,
05885     0,
05886     1
05887   },
05888   {
05889     nonimmediate_operand,
05890     "=d,y,d,d,d,d,d,R,m,*d",
05891     QImode,
05892     0,
05893     1
05894   },
05895   {
05896     general_operand,
05897     "d,d,y,K,N,R,m,d,d,*x",
05898     QImode,
05899     0,
05900     1
05901   },
05902   {
05903     nonimmediate_operand,
05904     "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m",
05905     SFmode,
05906     0,
05907     1
05908   },
05909   {
05910     general_operand,
05911     "f,G,R,m,fG,fG,*d,*f,*G*d,*R,*m,*d,*d",
05912     SFmode,
05913     0,
05914     1
05915   },
05916   {
05917     nonimmediate_operand,
05918     "=d,d,d,R,m",
05919     SFmode,
05920     0,
05921     1
05922   },
05923   {
05924     general_operand,
05925     "Gd,R,m,d,d",
05926     SFmode,
05927     0,
05928     1
05929   },
05930   {
05931     nonimmediate_operand,
05932     "=d,y,d,d,d,R,m",
05933     SFmode,
05934     0,
05935     1
05936   },
05937   {
05938     nonimmediate_operand,
05939     "d,d,y,R,m,d,d",
05940     SFmode,
05941     0,
05942     1
05943   },
05944   {
05945     nonimmediate_operand,
05946     "=f,f,f,f,R,To,*f,*d,*d,*d,*d,*R,*T",
05947     DFmode,
05948     0,
05949     1
05950   },
05951   {
05952     general_operand,
05953     "f,G,R,To,fG,fG,*d,*f,*d*G,*R,*T,*d,*d",
05954     DFmode,
05955     0,
05956     1
05957   },
05958   {
05959     nonimmediate_operand,
05960     "=f,f,R,R,To,To,*d,*d,*To,*R,*d",
05961     DFmode,
05962     0,
05963     1
05964   },
05965   {
05966     general_operand,
05967     "f,To,f,G,f,G,*To,*R,*d,*d,*d",
05968     DFmode,
05969     0,
05970     1
05971   },
05972   {
05973     nonimmediate_operand,
05974     "=d,d,d,R,To,d,f,f",
05975     DFmode,
05976     0,
05977     1
05978   },
05979   {
05980     general_operand,
05981     "dG,R,To,d,d,f,d,f",
05982     DFmode,
05983     0,
05984     1
05985   },
05986   {
05987     nonimmediate_operand,
05988     "=d,y,d,d,d,R,To",
05989     DFmode,
05990     0,
05991     1
05992   },
05993   {
05994     nonimmediate_operand,
05995     "d,d,y,R,To,d,d",
05996     DFmode,
05997     0,
05998     1
05999   },
06000   {
06001     address_operand,
06002     "",
06003     DImode,
06004     0,
06005     1
06006   },
06007   {
06008     register_operand,
06009     "",
06010     DImode,
06011     0,
06012     1
06013   },
06014   {
06015     memory_operand,
06016     "=o",
06017     BLKmode,
06018     0,
06019     1
06020   },
06021   {
06022     memory_operand,
06023     "o",
06024     BLKmode,
06025     0,
06026     1
06027   },
06028   {
06029     small_int,
06030     "I",
06031     SImode,
06032     0,
06033     1
06034   },
06035   {
06036     small_int,
06037     "I",
06038     SImode,
06039     0,
06040     1
06041   },
06042   {
06043     scratch_operand,
06044     "=&d",
06045     SImode,
06046     0,
06047     0
06048   },
06049   {
06050     scratch_operand,
06051     "=&d",
06052     SImode,
06053     0,
06054     0
06055   },
06056   {
06057     scratch_operand,
06058     "=&d",
06059     SImode,
06060     0,
06061     0
06062   },
06063   {
06064     scratch_operand,
06065     "=&d",
06066     SImode,
06067     0,
06068     0
06069   },
06070   {
06071     memory_operand,
06072     "=Ro",
06073     BLKmode,
06074     0,
06075     1
06076   },
06077   {
06078     memory_operand,
06079     "Ro",
06080     BLKmode,
06081     0,
06082     1
06083   },
06084   {
06085     small_int,
06086     "I",
06087     SImode,
06088     0,
06089     1
06090   },
06091   {
06092     small_int,
06093     "I",
06094     SImode,
06095     0,
06096     1
06097   },
06098   {
06099     scratch_operand,
06100     "=&d",
06101     SImode,
06102     0,
06103     0
06104   },
06105   {
06106     scratch_operand,
06107     "=&d",
06108     SImode,
06109     0,
06110     0
06111   },
06112   {
06113     scratch_operand,
06114     "=&d",
06115     SImode,
06116     0,
06117     0
06118   },
06119   {
06120     scratch_operand,
06121     "=&d",
06122     SImode,
06123     0,
06124     0
06125   },
06126   {
06127     register_operand,
06128     "=d",
06129     SImode,
06130     0,
06131     1
06132   },
06133   {
06134     register_operand,
06135     "d",
06136     SImode,
06137     0,
06138     1
06139   },
06140   {
06141     arith_operand,
06142     "dI",
06143     SImode,
06144     0,
06145     1
06146   },
06147   {
06148     register_operand,
06149     "=d,d",
06150     SImode,
06151     0,
06152     1
06153   },
06154   {
06155     register_operand,
06156     "0,d",
06157     SImode,
06158     0,
06159     1
06160   },
06161   {
06162     arith_operand,
06163     "d,I",
06164     SImode,
06165     0,
06166     1
06167   },
06168   {
06169     register_operand,
06170     "=&d",
06171     DImode,
06172     0,
06173     1
06174   },
06175   {
06176     register_operand,
06177     "d",
06178     DImode,
06179     0,
06180     1
06181   },
06182   {
06183     register_operand,
06184     "d",
06185     SImode,
06186     0,
06187     1
06188   },
06189   {
06190     register_operand,
06191     "=d",
06192     SImode,
06193     0,
06194     1
06195   },
06196   {
06197     register_operand,
06198     "=d",
06199     DImode,
06200     0,
06201     1
06202   },
06203   {
06204     register_operand,
06205     "d",
06206     DImode,
06207     0,
06208     1
06209   },
06210   {
06211     small_int,
06212     "IJK",
06213     SImode,
06214     0,
06215     1
06216   },
06217   {
06218     register_operand,
06219     "=d",
06220     SImode,
06221     0,
06222     1
06223   },
06224   {
06225     register_operand,
06226     "=d",
06227     DImode,
06228     0,
06229     1
06230   },
06231   {
06232     se_register_operand,
06233     "d",
06234     DImode,
06235     0,
06236     1
06237   },
06238   {
06239     arith_operand,
06240     "dI",
06241     SImode,
06242     0,
06243     1
06244   },
06245   {
06246     register_operand,
06247     "=d,d",
06248     DImode,
06249     0,
06250     1
06251   },
06252   {
06253     se_register_operand,
06254     "0,d",
06255     DImode,
06256     0,
06257     1
06258   },
06259   {
06260     arith_operand,
06261     "d,I",
06262     SImode,
06263     0,
06264     1
06265   },
06266   {
06267     register_operand,
06268     "=d,d",
06269     DImode,
06270     0,
06271     1
06272   },
06273   {
06274     se_register_operand,
06275     "0,0",
06276     DImode,
06277     0,
06278     1
06279   },
06280   {
06281     arith_operand,
06282     "d,I",
06283     SImode,
06284     0,
06285     1
06286   },
06287   {
06288     register_operand,
06289     "=d,d",
06290     SImode,
06291     0,
06292     1
06293   },
06294   {
06295     memory_operand,
06296     "R,m",
06297     SImode,
06298     0,
06299     1
06300   },
06301   {
06302     immediate_operand,
06303     "I,I",
06304     SImode,
06305     0,
06306     1
06307   },
06308   {
06309     register_operand,
06310     "=d",
06311     SImode,
06312     0,
06313     1
06314   },
06315   {
06316     register_operand,
06317     "d",
06318     SImode,
06319     0,
06320     1
06321   },
06322   {
06323     arith_operand,
06324     "dn",
06325     SImode,
06326     0,
06327     1
06328   },
06329   {
06330     register_operand,
06331     "=d",
06332     DImode,
06333     0,
06334     1
06335   },
06336   {
06337     register_operand,
06338     "d",
06339     DImode,
06340     0,
06341     1
06342   },
06343   {
06344     arith_operand,
06345     "dn",
06346     DImode,
06347     0,
06348     1
06349   },
06350   {
06351     cmp_op,
06352     "",
06353     CCmode,
06354     0,
06355     0
06356   },
06357   {
06358     0,
06359     "",
06360     VOIDmode,
06361     0,
06362     1
06363   },
06364   {
06365     register_operand,
06366     "z",
06367     CCmode,
06368     0,
06369     1
06370   },
06371   {
06372     cmp_op,
06373     "",
06374     SImode,
06375     0,
06376     0
06377   },
06378   {
06379     0,
06380     "",
06381     VOIDmode,
06382     0,
06383     1
06384   },
06385   {
06386     register_operand,
06387     "d",
06388     SImode,
06389     0,
06390     1
06391   },
06392   {
06393     cmp_op,
06394     "",
06395     DImode,
06396     0,
06397     0
06398   },
06399   {
06400     0,
06401     "",
06402     VOIDmode,
06403     0,
06404     1
06405   },
06406   {
06407     se_register_operand,
06408     "d",
06409     DImode,
06410     0,
06411     1
06412   },
06413   {
06414     equality_op,
06415     "",
06416     SImode,
06417     0,
06418     0
06419   },
06420   {
06421     0,
06422     "",
06423     VOIDmode,
06424     0,
06425     1
06426   },
06427   {
06428     register_operand,
06429     "d",
06430     SImode,
06431     0,
06432     1
06433   },
06434   {
06435     register_operand,
06436     "d",
06437     SImode,
06438     0,
06439     1
06440   },
06441   {
06442     equality_op,
06443     "",
06444     DImode,
06445     0,
06446     0
06447   },
06448   {
06449     0,
06450     "",
06451     VOIDmode,
06452     0,
06453     1
06454   },
06455   {
06456     se_register_operand,
06457     "d",
06458     DImode,
06459     0,
06460     1
06461   },
06462   {
06463     se_register_operand,
06464     "d",
06465     DImode,
06466     0,
06467     1
06468   },
06469   {
06470     equality_op,
06471     "",
06472     SImode,
06473     0,
06474     0
06475   },
06476   {
06477     register_operand,
06478     "d,t",
06479     SImode,
06480     0,
06481     1
06482   },
06483   {
06484     pc_or_label_operand,
06485     "",
06486     VOIDmode,
06487     0,
06488     1
06489   },
06490   {
06491     pc_or_label_operand,
06492     "",
06493     VOIDmode,
06494     0,
06495     1
06496   },
06497   {
06498     equality_op,
06499     "",
06500     DImode,
06501     0,
06502     0
06503   },
06504   {
06505     se_register_operand,
06506     "d,t",
06507     DImode,
06508     0,
06509     1
06510   },
06511   {
06512     pc_or_label_operand,
06513     "",
06514     VOIDmode,
06515     0,
06516     1
06517   },
06518   {
06519     pc_or_label_operand,
06520     "",
06521     VOIDmode,
06522     0,
06523     1
06524   },
06525   {
06526     register_operand,
06527     "=t",
06528     SImode,
06529     0,
06530     1
06531   },
06532   {
06533     register_operand,
06534     "d",
06535     SImode,
06536     0,
06537     1
06538   },
06539   {
06540     register_operand,
06541     "=t",
06542     DImode,
06543     0,
06544     1
06545   },
06546   {
06547     se_register_operand,
06548     "d",
06549     DImode,
06550     0,
06551     1
06552   },
06553   {
06554     register_operand,
06555     "=d",
06556     SImode,
06557     0,
06558     1
06559   },
06560   {
06561     register_operand,
06562     "d",
06563     SImode,
06564     0,
06565     1
06566   },
06567   {
06568     reg_or_0_operand,
06569     "dJ",
06570     SImode,
06571     0,
06572     1
06573   },
06574   {
06575     register_operand,
06576     "=t",
06577     SImode,
06578     0,
06579     1
06580   },
06581   {
06582     register_operand,
06583     "d",
06584     SImode,
06585     0,
06586     1
06587   },
06588   {
06589     register_operand,
06590     "d",
06591     SImode,
06592     0,
06593     1
06594   },
06595   {
06596     register_operand,
06597     "=d",
06598     DImode,
06599     0,
06600     1
06601   },
06602   {
06603     se_register_operand,
06604     "d",
06605     DImode,
06606     0,
06607     1
06608   },
06609   {
06610     se_reg_or_0_operand,
06611     "dJ",
06612     DImode,
06613     0,
06614     1
06615   },
06616   {
06617     register_operand,
06618     "=t,t",
06619     SImode,
06620     0,
06621     1
06622   },
06623   {
06624     register_operand,
06625     "d,d",
06626     SImode,
06627     0,
06628     1
06629   },
06630   {
06631     arith_operand,
06632     "d,I",
06633     SImode,
06634     0,
06635     1
06636   },
06637   {
06638     register_operand,
06639     "=d",
06640     DImode,
06641     0,
06642     1
06643   },
06644   {
06645     se_register_operand,
06646     "d",
06647     DImode,
06648     0,
06649     1
06650   },
06651   {
06652     se_arith_operand,
06653     "dI",
06654     DImode,
06655     0,
06656     1
06657   },
06658   {
06659     register_operand,
06660     "=t,t",
06661     DImode,
06662     0,
06663     1
06664   },
06665   {
06666     se_register_operand,
06667     "d,d",
06668     DImode,
06669     0,
06670     1
06671   },
06672   {
06673     se_arith_operand,
06674     "d,I",
06675     DImode,
06676     0,
06677     1
06678   },
06679   {
06680     register_operand,
06681     "=d",
06682     SImode,
06683     0,
06684     1
06685   },
06686   {
06687     register_operand,
06688     "d",
06689     SImode,
06690     0,
06691     1
06692   },
06693   {
06694     small_int,
06695     "I",
06696     SImode,
06697     0,
06698     1
06699   },
06700   {
06701     register_operand,
06702     "=t",
06703     SImode,
06704     0,
06705     1
06706   },
06707   {
06708     register_operand,
06709     "d",
06710     SImode,
06711     0,
06712     1
06713   },
06714   {
06715     small_int,
06716     "I",
06717     SImode,
06718     0,
06719     1
06720   },
06721   {
06722     register_operand,
06723     "=d",
06724     DImode,
06725     0,
06726     1
06727   },
06728   {
06729     se_register_operand,
06730     "d",
06731     DImode,
06732     0,
06733     1
06734   },
06735   {
06736     small_int,
06737     "I",
06738     DImode,
06739     0,
06740     1
06741   },
06742   {
06743     register_operand,
06744     "=t",
06745     DImode,
06746     0,
06747     1
06748   },
06749   {
06750     se_register_operand,
06751     "d",
06752     DImode,
06753     0,
06754     1
06755   },
06756   {
06757     small_int,
06758     "I",
06759     DImode,
06760     0,
06761     1
06762   },
06763   {
06764     register_operand,
06765     "=t",
06766     DImode,
06767     0,
06768     1
06769   },
06770   {
06771     se_register_operand,
06772     "d",
06773     DImode,
06774     0,
06775     1
06776   },
06777   {
06778     se_register_operand,
06779     "d",
06780     DImode,
06781     0,
06782     1
06783   },
06784   {
06785     register_operand,
06786     "=z",
06787     CCmode,
06788     0,
06789     1
06790   },
06791   {
06792     register_operand,
06793     "f",
06794     DFmode,
06795     0,
06796     1
06797   },
06798   {
06799     register_operand,
06800     "f",
06801     DFmode,
06802     0,
06803     1
06804   },
06805   {
06806     register_operand,
06807     "=z",
06808     CCmode,
06809     0,
06810     1
06811   },
06812   {
06813     register_operand,
06814     "f",
06815     SFmode,
06816     0,
06817     1
06818   },
06819   {
06820     register_operand,
06821     "f",
06822     SFmode,
06823     0,
06824     1
06825   },
06826   {
06827     register_operand,
06828     "d",
06829     SImode,
06830     0,
06831     1
06832   },
06833   {
06834     0,
06835     "",
06836     VOIDmode,
06837     0,
06838     1
06839   },
06840   {
06841     se_register_operand,
06842     "d",
06843     DImode,
06844     0,
06845     1
06846   },
06847   {
06848     0,
06849     "",
06850     VOIDmode,
06851     0,
06852     1
06853   },
06854   {
06855     register_operand,
06856     "d",
06857     SImode,
06858     0,
06859     1
06860   },
06861   {
06862     0,
06863     "",
06864     VOIDmode,
06865     0,
06866     1
06867   },
06868   {
06869     register_operand,
06870     "=d",
06871     SImode,
06872     0,
06873     1
06874   },
06875   {
06876     register_operand,
06877     "d",
06878     SImode,
06879     0,
06880     1
06881   },
06882   {
06883     0,
06884     "",
06885     VOIDmode,
06886     0,
06887     1
06888   },
06889   {
06890     register_operand,
06891     "=d",
06892     DImode,
06893     0,
06894     1
06895   },
06896   {
06897     pmode_register_operand,
06898     "",
06899     VOIDmode,
06900     0,
06901     1
06902   },
06903   {
06904     register_operand,
06905     "=d",
06906     VOIDmode,
06907     0,
06908     1
06909   },
06910   {
06911     0,
06912     "",
06913     VOIDmode,
06914     0,
06915     1
06916   },
06917   {
06918     register_operand,
06919     "d",
06920     DImode,
06921     0,
06922     1
06923   },
06924   {
06925     scratch_operand,
06926     "=&d",
06927     DImode,
06928     0,
06929     0
06930   },
06931   {
06932     call_insn_operand,
06933     "ei",
06934     VOIDmode,
06935     0,
06936     1
06937   },
06938   {
06939     0,
06940     "i",
06941     VOIDmode,
06942     0,
06943     1
06944   },
06945   {
06946     register_operand,
06947     "=y",
06948     SImode,
06949     0,
06950     1
06951   },
06952   {
06953     call_insn_operand,
06954     "ri",
06955     VOIDmode,
06956     0,
06957     1
06958   },
06959   {
06960     0,
06961     "i",
06962     VOIDmode,
06963     0,
06964     1
06965   },
06966   {
06967     register_operand,
06968     "=d",
06969     SImode,
06970     0,
06971     1
06972   },
06973   {
06974     register_operand,
06975     "r",
06976     SImode,
06977     0,
06978     1
06979   },
06980   {
06981     0,
06982     "i",
06983     VOIDmode,
06984     0,
06985     1
06986   },
06987   {
06988     register_operand,
06989     "=d",
06990     SImode,
06991     0,
06992     1
06993   },
06994   {
06995     se_register_operand,
06996     "r",
06997     DImode,
06998     0,
06999     1
07000   },
07001   {
07002     0,
07003     "i",
07004     VOIDmode,
07005     0,
07006     1
07007   },
07008   {
07009     register_operand,
07010     "=d",
07011     SImode,
07012     0,
07013     1
07014   },
07015   {
07016     register_operand,
07017     "e",
07018     SImode,
07019     0,
07020     1
07021   },
07022   {
07023     0,
07024     "i",
07025     VOIDmode,
07026     0,
07027     1
07028   },
07029   {
07030     register_operand,
07031     "=y",
07032     SImode,
07033     0,
07034     1
07035   },
07036   {
07037     register_operand,
07038     "=d",
07039     VOIDmode,
07040     0,
07041     1
07042   },
07043   {
07044     call_insn_operand,
07045     "ei",
07046     VOIDmode,
07047     0,
07048     1
07049   },
07050   {
07051     0,
07052     "i",
07053     VOIDmode,
07054     0,
07055     1
07056   },
07057   {
07058     register_operand,
07059     "=y",
07060     SImode,
07061     0,
07062     1
07063   },
07064   {
07065     register_operand,
07066     "=df",
07067     VOIDmode,
07068     0,
07069     1
07070   },
07071   {
07072     call_insn_operand,
07073     "ri",
07074     VOIDmode,
07075     0,
07076     1
07077   },
07078   {
07079     0,
07080     "i",
07081     VOIDmode,
07082     0,
07083     1
07084   },
07085   {
07086     register_operand,
07087     "=d",
07088     SImode,
07089     0,
07090     1
07091   },
07092   {
07093     register_operand,
07094     "=df",
07095     VOIDmode,
07096     0,
07097     1
07098   },
07099   {
07100     register_operand,
07101     "r",
07102     SImode,
07103     0,
07104     1
07105   },
07106   {
07107     0,
07108     "i",
07109     VOIDmode,
07110     0,
07111     1
07112   },
07113   {
07114     register_operand,
07115     "=d",
07116     SImode,
07117     0,
07118     1
07119   },
07120   {
07121     register_operand,
07122     "=df",
07123     VOIDmode,
07124     0,
07125     1
07126   },
07127   {
07128     se_register_operand,
07129     "r",
07130     DImode,
07131     0,
07132     1
07133   },
07134   {
07135     0,
07136     "i",
07137     VOIDmode,
07138     0,
07139     1
07140   },
07141   {
07142     register_operand,
07143     "=d",
07144     SImode,
07145     0,
07146     1
07147   },
07148   {
07149     register_operand,
07150     "=df",
07151     VOIDmode,
07152     0,
07153     1
07154   },
07155   {
07156     register_operand,
07157     "e",
07158     SImode,
07159     0,
07160     1
07161   },
07162   {
07163     0,
07164     "i",
07165     VOIDmode,
07166     0,
07167     1
07168   },
07169   {
07170     register_operand,
07171     "=y",
07172     SImode,
07173     0,
07174     1
07175   },
07176   {
07177     register_operand,
07178     "=df",
07179     VOIDmode,
07180     0,
07181     1
07182   },
07183   {
07184     call_insn_operand,
07185     "ri",
07186     VOIDmode,
07187     0,
07188     1
07189   },
07190   {
07191     0,
07192     "i",
07193     VOIDmode,
07194     0,
07195     1
07196   },
07197   {
07198     register_operand,
07199     "=df",
07200     VOIDmode,
07201     0,
07202     1
07203   },
07204   {
07205     register_operand,
07206     "=d",
07207     SImode,
07208     0,
07209     1
07210   },
07211   {
07212     register_operand,
07213     "r",
07214     SImode,
07215     0,
07216     1
07217   },
07218   {
07219     const_int_operand,
07220     "n",
07221     SImode,
07222     0,
07223     1
07224   },
07225   {
07226     const_int_operand,
07227     "n",
07228     SImode,
07229     0,
07230     1
07231   },
07232   {
07233     const_int_operand,
07234     "i",
07235     SImode,
07236     0,
07237     1
07238   },
07239   {
07240     se_register_operand,
07241     "r",
07242     DImode,
07243     0,
07244     1
07245   },
07246   {
07247     const_int_operand,
07248     "n",
07249     DImode,
07250     0,
07251     1
07252   },
07253   {
07254     const_int_operand,
07255     "n",
07256     DImode,
07257     0,
07258     1
07259   },
07260   {
07261     const_int_operand,
07262     "i",
07263     DImode,
07264     0,
07265     1
07266   },
07267   {
07268     register_operand,
07269     "=d,d",
07270     SImode,
07271     0,
07272     1
07273   },
07274   {
07275     register_operand,
07276     "d,d",
07277     SImode,
07278     0,
07279     1
07280   },
07281   {
07282     reg_or_0_operand,
07283     "dJ,0",
07284     SImode,
07285     0,
07286     1
07287   },
07288   {
07289     reg_or_0_operand,
07290     "0,dJ",
07291     SImode,
07292     0,
07293     1
07294   },
07295   {
07296     equality_op,
07297     "",
07298     VOIDmode,
07299     0,
07300     0
07301   },
07302   {
07303     register_operand,
07304     "=d,d",
07305     SImode,
07306     0,
07307     1
07308   },
07309   {
07310     se_register_operand,
07311     "d,d",
07312     DImode,
07313     0,
07314     1
07315   },
07316   {
07317     reg_or_0_operand,
07318     "dJ,0",
07319     SImode,
07320     0,
07321     1
07322   },
07323   {
07324     reg_or_0_operand,
07325     "0,dJ",
07326     SImode,
07327     0,
07328     1
07329   },
07330   {
07331     equality_op,
07332     "",
07333     VOIDmode,
07334     0,
07335     0
07336   },
07337   {
07338     register_operand,
07339     "=d,d",
07340     SImode,
07341     0,
07342     1
07343   },
07344   {
07345     reg_or_0_operand,
07346     "dJ,0",
07347     SImode,
07348     0,
07349     1
07350   },
07351   {
07352     reg_or_0_operand,
07353     "0,dJ",
07354     SImode,
07355     0,
07356     1
07357   },
07358   {
07359     equality_op,
07360     "",
07361     VOIDmode,
07362     0,
07363     0
07364   },
07365   {
07366     register_operand,
07367     "z,z",
07368     CCmode,
07369     0,
07370     1
07371   },
07372   {
07373     register_operand,
07374     "=d,d",
07375     DImode,
07376     0,
07377     1
07378   },
07379   {
07380     register_operand,
07381     "d,d",
07382     SImode,
07383     0,
07384     1
07385   },
07386   {
07387     se_reg_or_0_operand,
07388     "dJ,0",
07389     DImode,
07390     0,
07391     1
07392   },
07393   {
07394     se_reg_or_0_operand,
07395     "0,dJ",
07396     DImode,
07397     0,
07398     1
07399   },
07400   {
07401     equality_op,
07402     "",
07403     VOIDmode,
07404     0,
07405     0
07406   },
07407   {
07408     register_operand,
07409     "=d,d",
07410     DImode,
07411     0,
07412     1
07413   },
07414   {
07415     se_register_operand,
07416     "d,d",
07417     DImode,
07418     0,
07419     1
07420   },
07421   {
07422     se_reg_or_0_operand,
07423     "dJ,0",
07424     DImode,
07425     0,
07426     1
07427   },
07428   {
07429     se_reg_or_0_operand,
07430     "0,dJ",
07431     DImode,
07432     0,
07433     1
07434   },
07435   {
07436     equality_op,
07437     "",
07438     VOIDmode,
07439     0,
07440     0
07441   },
07442   {
07443     register_operand,
07444     "=d,d",
07445     DImode,
07446     0,
07447     1
07448   },
07449   {
07450     se_reg_or_0_operand,
07451     "dJ,0",
07452     DImode,
07453     0,
07454     1
07455   },
07456   {
07457     se_reg_or_0_operand,
07458     "0,dJ",
07459     DImode,
07460     0,
07461     1
07462   },
07463   {
07464     equality_op,
07465     "",
07466     VOIDmode,
07467     0,
07468     0
07469   },
07470   {
07471     register_operand,
07472     "z,z",
07473     CCmode,
07474     0,
07475     1
07476   },
07477   {
07478     register_operand,
07479     "=f,f",
07480     SFmode,
07481     0,
07482     1
07483   },
07484   {
07485     register_operand,
07486     "d,d",
07487     SImode,
07488     0,
07489     1
07490   },
07491   {
07492     register_operand,
07493     "f,0",
07494     SFmode,
07495     0,
07496     1
07497   },
07498   {
07499     register_operand,
07500     "0,f",
07501     SFmode,
07502     0,
07503     1
07504   },
07505   {
07506     equality_op,
07507     "",
07508     VOIDmode,
07509     0,
07510     0
07511   },
07512   {
07513     register_operand,
07514     "=f,f",
07515     SFmode,
07516     0,
07517     1
07518   },
07519   {
07520     se_register_operand,
07521     "d,d",
07522     DImode,
07523     0,
07524     1
07525   },
07526   {
07527     register_operand,
07528     "f,0",
07529     SFmode,
07530     0,
07531     1
07532   },
07533   {
07534     register_operand,
07535     "0,f",
07536     SFmode,
07537     0,
07538     1
07539   },
07540   {
07541     equality_op,
07542     "",
07543     VOIDmode,
07544     0,
07545     0
07546   },
07547   {
07548     register_operand,
07549     "=f,f",
07550     SFmode,
07551     0,
07552     1
07553   },
07554   {
07555     register_operand,
07556     "f,0",
07557     SFmode,
07558     0,
07559     1
07560   },
07561   {
07562     register_operand,
07563     "0,f",
07564     SFmode,
07565     0,
07566     1
07567   },
07568   {
07569     equality_op,
07570     "",
07571     VOIDmode,
07572     0,
07573     0
07574   },
07575   {
07576     register_operand,
07577     "z,z",
07578     CCmode,
07579     0,
07580     1
07581   },
07582   {
07583     register_operand,
07584     "=f,f",
07585     DFmode,
07586     0,
07587     1
07588   },
07589   {
07590     register_operand,
07591     "d,d",
07592     SImode,
07593     0,
07594     1
07595   },
07596   {
07597     register_operand,
07598     "f,0",
07599     DFmode,
07600     0,
07601     1
07602   },
07603   {
07604     register_operand,
07605     "0,f",
07606     DFmode,
07607     0,
07608     1
07609   },
07610   {
07611     equality_op,
07612     "",
07613     VOIDmode,
07614     0,
07615     0
07616   },
07617   {
07618     register_operand,
07619     "=f,f",
07620     DFmode,
07621     0,
07622     1
07623   },
07624   {
07625     se_register_operand,
07626     "d,d",
07627     DImode,
07628     0,
07629     1
07630   },
07631   {
07632     register_operand,
07633     "f,0",
07634     DFmode,
07635     0,
07636     1
07637   },
07638   {
07639     register_operand,
07640     "0,f",
07641     DFmode,
07642     0,
07643     1
07644   },
07645   {
07646     equality_op,
07647     "",
07648     VOIDmode,
07649     0,
07650     0
07651   },
07652   {
07653     register_operand,
07654     "=f,f",
07655     DFmode,
07656     0,
07657     1
07658   },
07659   {
07660     register_operand,
07661     "f,0",
07662     DFmode,
07663     0,
07664     1
07665   },
07666   {
07667     register_operand,
07668     "0,f",
07669     DFmode,
07670     0,
07671     1
07672   },
07673   {
07674     equality_op,
07675     "",
07676     VOIDmode,
07677     0,
07678     0
07679   },
07680   {
07681     register_operand,
07682     "z,z",
07683     CCmode,
07684     0,
07685     1
07686   },
07687   {
07688     consttable_operand,
07689     "=g",
07690     QImode,
07691     0,
07692     1
07693   },
07694   {
07695     consttable_operand,
07696     "=g",
07697     HImode,
07698     0,
07699     1
07700   },
07701   {
07702     consttable_operand,
07703     "=g",
07704     SImode,
07705     0,
07706     1
07707   },
07708   {
07709     consttable_operand,
07710     "=g",
07711     DImode,
07712     0,
07713     1
07714   },
07715   {
07716     consttable_operand,
07717     "=g",
07718     SFmode,
07719     0,
07720     1
07721   },
07722   {
07723     consttable_operand,
07724     "=g",
07725     DFmode,
07726     0,
07727     1
07728   },
07729   {
07730     register_operand,
07731     "=d",
07732     SImode,
07733     0,
07734     1
07735   },
07736   {
07737     address_operand,
07738     "p",
07739     SImode,
07740     0,
07741     1
07742   },
07743   {
07744     register_operand,
07745     "=d",
07746     DImode,
07747     0,
07748     1
07749   },
07750   {
07751     address_operand,
07752     "p",
07753     DImode,
07754     0,
07755     1
07756   },
07757   {
07758     cmp_op,
07759     "",
07760     VOIDmode,
07761     0,
07762     0
07763   },
07764   {
07765     const_int_operand,
07766     "",
07767     VOIDmode,
07768     0,
07769     1
07770   },
07771   {
07772     register_operand,
07773     "",
07774     SImode,
07775     0,
07776     1
07777   },
07778   {
07779     const_int_operand,
07780     "",
07781     SImode,
07782     0,
07783     1
07784   },
07785   {
07786     register_operand,
07787     "",
07788     SImode,
07789     0,
07790     1
07791   },
07792   {
07793     register_operand,
07794     "",
07795     SImode,
07796     0,
07797     1
07798   },
07799   {
07800     const_int_operand,
07801     "",
07802     SImode,
07803     0,
07804     1
07805   },
07806   {
07807     register_operand,
07808     "",
07809     DImode,
07810     0,
07811     1
07812   },
07813   {
07814     se_register_operand,
07815     "",
07816     DImode,
07817     0,
07818     1
07819   },
07820   {
07821     se_arith_operand,
07822     "",
07823     DImode,
07824     0,
07825     1
07826   },
07827   {
07828     register_operand,
07829     "",
07830     DImode,
07831     0,
07832     1
07833   },
07834   {
07835     register_operand,
07836     "",
07837     DImode,
07838     0,
07839     1
07840   },
07841   {
07842     register_operand,
07843     "",
07844     DImode,
07845     0,
07846     1
07847   },
07848   {
07849     register_operand,
07850     "",
07851     SImode,
07852     0,
07853     1
07854   },
07855   {
07856     register_operand,
07857     "",
07858     DImode,
07859     0,
07860     1
07861   },
07862   {
07863     register_operand,
07864     "",
07865     DImode,
07866     0,
07867     1
07868   },
07869   {
07870     small_int,
07871     "",
07872     DImode,
07873     0,
07874     1
07875   },
07876   {
07877     register_operand,
07878     "",
07879     SImode,
07880     0,
07881     1
07882   },
07883   {
07884     register_operand,
07885     "",
07886     DImode,
07887     0,
07888     1
07889   },
07890   {
07891     const_int_operand,
07892     "",
07893     DImode,
07894     0,
07895     1
07896   },
07897   {
07898     register_operand,
07899     "",
07900     DImode,
07901     0,
07902     1
07903   },
07904   {
07905     register_operand,
07906     "",
07907     DImode,
07908     0,
07909     1
07910   },
07911   {
07912     const_int_operand,
07913     "",
07914     DImode,
07915     0,
07916     1
07917   },
07918   {
07919     register_operand,
07920     "",
07921     SImode,
07922     0,
07923     1
07924   },
07925   {
07926     register_operand,
07927     "",
07928     SImode,
07929     0,
07930     1
07931   },
07932   {
07933     register_operand,
07934     "",
07935     SImode,
07936     0,
07937     1
07938   },
07939   {
07940     register_operand,
07941     "",
07942     SImode,
07943     0,
07944     1
07945   },
07946   {
07947     scratch_operand,
07948     "",
07949     SImode,
07950     0,
07951     0
07952   },
07953   {
07954     scratch_operand,
07955     "",
07956     SImode,
07957     0,
07958     0
07959   },
07960   {
07961     scratch_operand,
07962     "",
07963     SImode,
07964     0,
07965     0
07966   },
07967   {
07968     scratch_operand,
07969     "",
07970     SImode,
07971     0,
07972     0
07973   },
07974   {
07975     register_operand,
07976     "=d",
07977     SImode,
07978     0,
07979     1
07980   },
07981   {
07982     register_operand,
07983     "d",
07984     SImode,
07985     0,
07986     1
07987   },
07988   {
07989     register_operand,
07990     "d",
07991     SImode,
07992     0,
07993     1
07994   },
07995   {
07996     register_operand,
07997     "=d",
07998     SImode,
07999     0,
08000     1
08001   },
08002   {
08003     scratch_operand,
08004     "=l",
08005     SImode,
08006     0,
08007     0
08008   },
08009   {
08010     scratch_operand,
08011     "=h",
08012     SImode,
08013     0,
08014     0
08015   },
08016   {
08017     scratch_operand,
08018     "=a",
08019     SImode,
08020     0,
08021     0
08022   },
08023   {
08024     register_operand,
08025     "=d",
08026     DImode,
08027     0,
08028     1
08029   },
08030   {
08031     se_register_operand,
08032     "d",
08033     DImode,
08034     0,
08035     1
08036   },
08037   {
08038     se_register_operand,
08039     "d",
08040     DImode,
08041     0,
08042     1
08043   },
08044   {
08045     register_operand,
08046     "=d",
08047     DImode,
08048     0,
08049     1
08050   },
08051   {
08052     scratch_operand,
08053     "=l",
08054     DImode,
08055     0,
08056     0
08057   },
08058   {
08059     scratch_operand,
08060     "=h",
08061     DImode,
08062     0,
08063     0
08064   },
08065   {
08066     scratch_operand,
08067     "=a",
08068     DImode,
08069     0,
08070     0
08071   },
08072   {
08073     register_operand,
08074     "d",
08075     VOIDmode,
08076     0,
08077     1
08078   },
08079   {
08080     true_reg_or_0_operand,
08081     "dJ",
08082     VOIDmode,
08083     0,
08084     1
08085   },
08086   {
08087     immediate_operand,
08088     "",
08089     VOIDmode,
08090     0,
08091     1
08092   },
08093   {
08094     register_operand,
08095     "=l",
08096     DImode,
08097     0,
08098     1
08099   },
08100   {
08101     se_register_operand,
08102     "d",
08103     DImode,
08104     0,
08105     1
08106   },
08107   {
08108     se_register_operand,
08109     "d",
08110     DImode,
08111     0,
08112     1
08113   },
08114   {
08115     scratch_operand,
08116     "=h",
08117     DImode,
08118     0,
08119     0
08120   },
08121   {
08122     scratch_operand,
08123     "=a",
08124     DImode,
08125     0,
08126     0
08127   },
08128   {
08129     register_operand,
08130     "=h",
08131     SImode,
08132     0,
08133     1
08134   },
08135   {
08136     register_operand,
08137     "d",
08138     SImode,
08139     0,
08140     1
08141   },
08142   {
08143     register_operand,
08144     "d",
08145     SImode,
08146     0,
08147     1
08148   },
08149   {
08150     scratch_operand,
08151     "=l",
08152     SImode,
08153     0,
08154     0
08155   },
08156   {
08157     scratch_operand,
08158     "=a",
08159     SImode,
08160     0,
08161     0
08162   },
08163   {
08164     register_operand,
08165     "=l",
08166     DImode,
08167     0,
08168     1
08169   },
08170   {
08171     se_register_operand,
08172     "d",
08173     DImode,
08174     0,
08175     1
08176   },
08177   {
08178     se_register_operand,
08179     "di",
08180     DImode,
08181     0,
08182     1
08183   },
08184   {
08185     scratch_operand,
08186     "=h",
08187     DImode,
08188     0,
08189     0
08190   },
08191   {
08192     scratch_operand,
08193     "=a",
08194     DImode,
08195     0,
08196     0
08197   },
08198   {
08199     register_operand,
08200     "=h",
08201     DImode,
08202     0,
08203     1
08204   },
08205   {
08206     se_register_operand,
08207     "d",
08208     DImode,
08209     0,
08210     1
08211   },
08212   {
08213     se_register_operand,
08214     "di",
08215     DImode,
08216     0,
08217     1
08218   },
08219   {
08220     scratch_operand,
08221     "=l",
08222     DImode,
08223     0,
08224     0
08225   },
08226   {
08227     scratch_operand,
08228     "=a",
08229     DImode,
08230     0,
08231     0
08232   },
08233   {
08234     register_operand,
08235     "",
08236     DImode,
08237     0,
08238     1
08239   },
08240   {
08241     nonimmediate_operand,
08242     "",
08243     SImode,
08244     0,
08245     1
08246   },
08247   {
08248     register_operand,
08249     "",
08250     SImode,
08251     0,
08252     1
08253   },
08254   {
08255     nonimmediate_operand,
08256     "",
08257     HImode,
08258     0,
08259     1
08260   },
08261   {
08262     register_operand,
08263     "",
08264     DImode,
08265     0,
08266     1
08267   },
08268   {
08269     nonimmediate_operand,
08270     "",
08271     HImode,
08272     0,
08273     1
08274   },
08275   {
08276     register_operand,
08277     "",
08278     HImode,
08279     0,
08280     1
08281   },
08282   {
08283     nonimmediate_operand,
08284     "",
08285     QImode,
08286     0,
08287     1
08288   },
08289   {
08290     register_operand,
08291     "",
08292     SImode,
08293     0,
08294     1
08295   },
08296   {
08297     nonimmediate_operand,
08298     "",
08299     QImode,
08300     0,
08301     1
08302   },
08303   {
08304     register_operand,
08305     "",
08306     DImode,
08307     0,
08308     1
08309   },
08310   {
08311     nonimmediate_operand,
08312     "",
08313     QImode,
08314     0,
08315     1
08316   },
08317   {
08318     register_operand,
08319     "",
08320     SImode,
08321     0,
08322     1
08323   },
08324   {
08325     register_operand,
08326     "",
08327     DFmode,
08328     0,
08329     1
08330   },
08331   {
08332     register_operand,
08333     "",
08334     DImode,
08335     0,
08336     1
08337   },
08338   {
08339     register_operand,
08340     "",
08341     DFmode,
08342     0,
08343     1
08344   },
08345   {
08346     register_operand,
08347     "",
08348     SImode,
08349     0,
08350     1
08351   },
08352   {
08353     register_operand,
08354     "",
08355     SFmode,
08356     0,
08357     1
08358   },
08359   {
08360     register_operand,
08361     "",
08362     DImode,
08363     0,
08364     1
08365   },
08366   {
08367     register_operand,
08368     "",
08369     SFmode,
08370     0,
08371     1
08372   },
08373   {
08374     register_operand,
08375     "",
08376     VOIDmode,
08377     0,
08378     1
08379   },
08380   {
08381     memory_operand,
08382     "",
08383     QImode,
08384     0,
08385     1
08386   },
08387   {
08388     immediate_operand,
08389     "",
08390     VOIDmode,
08391     0,
08392     1
08393   },
08394   {
08395     immediate_operand,
08396     "",
08397     VOIDmode,
08398     0,
08399     1
08400   },
08401   {
08402     register_operand,
08403     "",
08404     VOIDmode,
08405     0,
08406     1
08407   },
08408   {
08409     nonimmediate_operand,
08410     "",
08411     DImode,
08412     0,
08413     1
08414   },
08415   {
08416     general_operand,
08417     "",
08418     DImode,
08419     0,
08420     1
08421   },
08422   {
08423     register_operand,
08424     "=b",
08425     DImode,
08426     0,
08427     1
08428   },
08429   {
08430     0,
08431     "b",
08432     DImode,
08433     0,
08434     1
08435   },
08436   {
08437     register_operand,
08438     "=&d",
08439     TImode,
08440     0,
08441     1
08442   },
08443   {
08444     general_operand,
08445     "=b",
08446     DImode,
08447     0,
08448     1
08449   },
08450   {
08451     se_register_operand,
08452     "b",
08453     DImode,
08454     0,
08455     1
08456   },
08457   {
08458     register_operand,
08459     "=&d",
08460     TImode,
08461     0,
08462     1
08463   },
08464   {
08465     register_operand,
08466     "",
08467     SImode,
08468     0,
08469     1
08470   },
08471   {
08472     large_int,
08473     "",
08474     SImode,
08475     0,
08476     1
08477   },
08478   {
08479     nonimmediate_operand,
08480     "",
08481     SImode,
08482     0,
08483     1
08484   },
08485   {
08486     general_operand,
08487     "",
08488     SImode,
08489     0,
08490     1
08491   },
08492   {
08493     general_operand,
08494     "=b",
08495     SImode,
08496     0,
08497     1
08498   },
08499   {
08500     register_operand,
08501     "b",
08502     SImode,
08503     0,
08504     1
08505   },
08506   {
08507     register_operand,
08508     "=&d",
08509     SImode,
08510     0,
08511     1
08512   },
08513   {
08514     register_operand,
08515     "=b",
08516     SImode,
08517     0,
08518     1
08519   },
08520   {
08521     0,
08522     "b",
08523     SImode,
08524     0,
08525     1
08526   },
08527   {
08528     register_operand,
08529     "=&d",
08530     SImode,
08531     0,
08532     1
08533   },
08534   {
08535     fcc_register_operand,
08536     "=z",
08537     CCmode,
08538     0,
08539     1
08540   },
08541   {
08542     general_operand,
08543     "",
08544     CCmode,
08545     0,
08546     1
08547   },
08548   {
08549     register_operand,
08550     "=&f",
08551     TFmode,
08552     0,
08553     1
08554   },
08555   {
08556     fcc_register_operand,
08557     "=z",
08558     CCmode,
08559     0,
08560     1
08561   },
08562   {
08563     register_operand,
08564     "",
08565     CCmode,
08566     0,
08567     1
08568   },
08569   {
08570     register_operand,
08571     "=&f",
08572     TFmode,
08573     0,
08574     1
08575   },
08576   {
08577     nonimmediate_operand,
08578     "",
08579     HImode,
08580     0,
08581     1
08582   },
08583   {
08584     general_operand,
08585     "",
08586     HImode,
08587     0,
08588     1
08589   },
08590   {
08591     register_operand,
08592     "",
08593     HImode,
08594     0,
08595     1
08596   },
08597   {
08598     const_int_operand,
08599     "",
08600     SImode,
08601     0,
08602     1
08603   },
08604   {
08605     nonimmediate_operand,
08606     "",
08607     QImode,
08608     0,
08609     1
08610   },
08611   {
08612     general_operand,
08613     "",
08614     QImode,
08615     0,
08616     1
08617   },
08618   {
08619     register_operand,
08620     "",
08621     QImode,
08622     0,
08623     1
08624   },
08625   {
08626     const_int_operand,
08627     "",
08628     SImode,
08629     0,
08630     1
08631   },
08632   {
08633     nonimmediate_operand,
08634     "",
08635     SFmode,
08636     0,
08637     1
08638   },
08639   {
08640     general_operand,
08641     "",
08642     SFmode,
08643     0,
08644     1
08645   },
08646   {
08647     nonimmediate_operand,
08648     "",
08649     DFmode,
08650     0,
08651     1
08652   },
08653   {
08654     general_operand,
08655     "",
08656     DFmode,
08657     0,
08658     1
08659   },
08660   {
08661     register_operand,
08662     "",
08663     DFmode,
08664     0,
08665     1
08666   },
08667   {
08668     register_operand,
08669     "",
08670     DFmode,
08671     0,
08672     1
08673   },
08674   {
08675     general_operand,
08676     "",
08677     BLKmode,
08678     0,
08679     1
08680   },
08681   {
08682     general_operand,
08683     "",
08684     BLKmode,
08685     0,
08686     1
08687   },
08688   {
08689     arith32_operand,
08690     "",
08691     SImode,
08692     0,
08693     1
08694   },
08695   {
08696     immediate_operand,
08697     "",
08698     SImode,
08699     0,
08700     1
08701   },
08702   {
08703     register_operand,
08704     "",
08705     DImode,
08706     0,
08707     1
08708   },
08709   {
08710     se_register_operand,
08711     "",
08712     DImode,
08713     0,
08714     1
08715   },
08716   {
08717     arith_operand,
08718     "",
08719     SImode,
08720     0,
08721     1
08722   },
08723   {
08724     register_operand,
08725     "",
08726     DImode,
08727     0,
08728     1
08729   },
08730   {
08731     register_operand,
08732     "",
08733     DImode,
08734     0,
08735     1
08736   },
08737   {
08738     small_int,
08739     "",
08740     SImode,
08741     0,
08742     1
08743   },
08744   {
08745     register_operand,
08746     "",
08747     SImode,
08748     0,
08749     1
08750   },
08751   {
08752     register_operand,
08753     "",
08754     DImode,
08755     0,
08756     1
08757   },
08758   {
08759     register_operand,
08760     "",
08761     DImode,
08762     0,
08763     1
08764   },
08765   {
08766     const_int_operand,
08767     "",
08768     SImode,
08769     0,
08770     1
08771   },
08772   {
08773     register_operand,
08774     "",
08775     SImode,
08776     0,
08777     1
08778   },
08779   {
08780     memory_operand,
08781     "",
08782     SImode,
08783     0,
08784     1
08785   },
08786   {
08787     immediate_operand,
08788     "",
08789     SImode,
08790     0,
08791     1
08792   },
08793   {
08794     register_operand,
08795     "",
08796     SImode,
08797     0,
08798     1
08799   },
08800   {
08801     arith_operand,
08802     "",
08803     SImode,
08804     0,
08805     1
08806   },
08807   {
08808     register_operand,
08809     "",
08810     SFmode,
08811     0,
08812     1
08813   },
08814   {
08815     register_operand,
08816     "",
08817     SFmode,
08818     0,
08819     1
08820   },
08821   {
08822     register_operand,
08823     "d",
08824     VOIDmode,
08825     0,
08826     1
08827   },
08828   {
08829     0,
08830     "",
08831     VOIDmode,
08832     0,
08833     1
08834   },
08835   {
08836     register_operand,
08837     "d",
08838     HImode,
08839     0,
08840     1
08841   },
08842   {
08843     0,
08844     "",
08845     VOIDmode,
08846     0,
08847     1
08848   },
08849   {
08850     register_operand,
08851     "d",
08852     SImode,
08853     0,
08854     1
08855   },
08856   {
08857     arith_operand,
08858     "dI",
08859     SImode,
08860     0,
08861     1
08862   },
08863   {
08864     arith_operand,
08865     "",
08866     SImode,
08867     0,
08868     1
08869   },
08870   {
08871     0,
08872     "",
08873     VOIDmode,
08874     0,
08875     1
08876   },
08877   {
08878     0,
08879     "",
08880     VOIDmode,
08881     0,
08882     1
08883   },
08884   {
08885     0,
08886     "",
08887     VOIDmode,
08888     0,
08889     0
08890   },
08891   {
08892     scratch_operand,
08893     "",
08894     SImode,
08895     0,
08896     0
08897   },
08898   {
08899     register_operand,
08900     "r",
08901     VOIDmode,
08902     0,
08903     1
08904   },
08905   {
08906     register_operand,
08907     "r",
08908     DImode,
08909     0,
08910     1
08911   },
08912   {
08913     general_operand,
08914     "",
08915     VOIDmode,
08916     0,
08917     1
08918   },
08919   {
08920     register_operand,
08921     "",
08922     VOIDmode,
08923     0,
08924     1
08925   },
08926   {
08927     scratch_operand,
08928     "",
08929     VOIDmode,
08930     0,
08931     0
08932   },
08933   {
08934     memory_operand,
08935     "m",
08936     VOIDmode,
08937     0,
08938     1
08939   },
08940   {
08941     0,
08942     "i",
08943     VOIDmode,
08944     0,
08945     1
08946   },
08947   {
08948     0,
08949     "",
08950     VOIDmode,
08951     0,
08952     1
08953   },
08954   {
08955     0,
08956     "",
08957     VOIDmode,
08958     0,
08959     1
08960   },
08961   {
08962     0,
08963     "",
08964     SImode,
08965     0,
08966     1
08967   },
08968   {
08969     register_operand,
08970     "=df",
08971     VOIDmode,
08972     0,
08973     1
08974   },
08975   {
08976     memory_operand,
08977     "m",
08978     VOIDmode,
08979     0,
08980     1
08981   },
08982   {
08983     0,
08984     "i",
08985     VOIDmode,
08986     0,
08987     1
08988   },
08989   {
08990     0,
08991     "",
08992     VOIDmode,
08993     0,
08994     1
08995   },
08996   {
08997     0,
08998     "",
08999     VOIDmode,
09000     0,
09001     1
09002   },
09003   {
09004     0,
09005     "",
09006     VOIDmode,
09007     0,
09008     1
09009   },
09010   {
09011     0,
09012     "",
09013     SImode,
09014     0,
09015     1
09016   },
09017   {
09018     0,
09019     "",
09020     VOIDmode,
09021     0,
09022     1
09023   },
09024   {
09025     0,
09026     "",
09027     VOIDmode,
09028     0,
09029     1
09030   },
09031   {
09032     0,
09033     "",
09034     VOIDmode,
09035     0,
09036     1
09037   },
09038   {
09039     0,
09040     "",
09041     VOIDmode,
09042     0,
09043     1
09044   },
09045   {
09046     0,
09047     "",
09048     SImode,
09049     0,
09050     1
09051   },
09052   {
09053     address_operand,
09054     "",
09055     VOIDmode,
09056     0,
09057     1
09058   },
09059   {
09060     const_int_operand,
09061     "",
09062     VOIDmode,
09063     0,
09064     1
09065   },
09066   {
09067     const_int_operand,
09068     "",
09069     VOIDmode,
09070     0,
09071     1
09072   },
09073   {
09074     register_operand,
09075     "",
09076     SImode,
09077     0,
09078     1
09079   },
09080   {
09081     comparison_operator,
09082     "",
09083     VOIDmode,
09084     0,
09085     1
09086   },
09087   {
09088     reg_or_0_operand,
09089     "",
09090     SImode,
09091     0,
09092     1
09093   },
09094   {
09095     reg_or_0_operand,
09096     "",
09097     SImode,
09098     0,
09099     1
09100   },
09101   {
09102     register_operand,
09103     "",
09104     DImode,
09105     0,
09106     1
09107   },
09108   {
09109     comparison_operator,
09110     "",
09111     VOIDmode,
09112     0,
09113     1
09114   },
09115   {
09116     se_reg_or_0_operand,
09117     "",
09118     DImode,
09119     0,
09120     1
09121   },
09122   {
09123     se_reg_or_0_operand,
09124     "",
09125     DImode,
09126     0,
09127     1
09128   },
09129   {
09130     register_operand,
09131     "",
09132     SFmode,
09133     0,
09134     1
09135   },
09136   {
09137     comparison_operator,
09138     "",
09139     VOIDmode,
09140     0,
09141     1
09142   },
09143   {
09144     register_operand,
09145     "",
09146     SFmode,
09147     0,
09148     1
09149   },
09150   {
09151     register_operand,
09152     "",
09153     SFmode,
09154     0,
09155     1
09156   },
09157   {
09158     register_operand,
09159     "",
09160     DFmode,
09161     0,
09162     1
09163   },
09164   {
09165     comparison_operator,
09166     "",
09167     VOIDmode,
09168     0,
09169     1
09170   },
09171   {
09172     register_operand,
09173     "",
09174     DFmode,
09175     0,
09176     1
09177   },
09178   {
09179     register_operand,
09180     "",
09181     DFmode,
09182     0,
09183     1
09184   },
09185   {
09186     register_operand,
09187     "=t",
09188     SImode,
09189     0,
09190     1
09191   },
09192   {
09193     register_operand,
09194     "d",
09195     SImode,
09196     0,
09197     1
09198   },
09199   {
09200     equality_op,
09201     "",
09202     SImode,
09203     0,
09204     0
09205   },
09206   {
09207     pc_or_label_operand,
09208     "",
09209     VOIDmode,
09210     0,
09211     1
09212   },
09213   {
09214     pc_or_label_operand,
09215     "",
09216     VOIDmode,
09217     0,
09218     1
09219   },
09220   {
09221     register_operand,
09222     "=t",
09223     DImode,
09224     0,
09225     1
09226   },
09227   {
09228     register_operand,
09229     "d",
09230     DImode,
09231     0,
09232     1
09233   },
09234   {
09235     equality_op,
09236     "",
09237     DImode,
09238     0,
09239     0
09240   },
09241   {
09242     pc_or_label_operand,
09243     "",
09244     VOIDmode,
09245     0,
09246     1
09247   },
09248   {
09249     pc_or_label_operand,
09250     "",
09251     VOIDmode,
09252     0,
09253     1
09254   },
09255   {
09256     register_operand,
09257     "=d",
09258     SImode,
09259     0,
09260     1
09261   },
09262   {
09263     register_operand,
09264     "t",
09265     SImode,
09266     0,
09267     1
09268   },
09269   {
09270     equality_op,
09271     "",
09272     SImode,
09273     0,
09274     0
09275   },
09276   {
09277     pc_or_label_operand,
09278     "",
09279     VOIDmode,
09280     0,
09281     1
09282   },
09283   {
09284     pc_or_label_operand,
09285     "",
09286     VOIDmode,
09287     0,
09288     1
09289   },
09290   {
09291     register_operand,
09292     "=d",
09293     DImode,
09294     0,
09295     1
09296   },
09297   {
09298     register_operand,
09299     "t",
09300     DImode,
09301     0,
09302     1
09303   },
09304   {
09305     equality_op,
09306     "",
09307     DImode,
09308     0,
09309     0
09310   },
09311   {
09312     pc_or_label_operand,
09313     "",
09314     VOIDmode,
09315     0,
09316     1
09317   },
09318   {
09319     pc_or_label_operand,
09320     "",
09321     VOIDmode,
09322     0,
09323     1
09324   },
09325 };
09326 
09327 
09328 
09329 const struct insn_data insn_data[] = 
09330 {
09331   {
09332     "trap",
09333     (const PTR) output_0,
09334     (insn_gen_fn) gen_trap,
09335     &operand_data[0],
09336     0,
09337     0,
09338     0,
09339     3
09340   },
09341   {
09342     "*mips.md:584",
09343     "t%C0\t%z1,%z2",
09344     0,
09345     &operand_data[1],
09346     3,
09347     0,
09348     1,
09349     1
09350   },
09351   {
09352     "adddf3",
09353     "add.d\t%0,%1,%2",
09354     (insn_gen_fn) gen_adddf3,
09355     &operand_data[4],
09356     3,
09357     0,
09358     1,
09359     1
09360   },
09361   {
09362     "addsf3",
09363     "add.s\t%0,%1,%2",
09364     (insn_gen_fn) gen_addsf3,
09365     &operand_data[7],
09366     3,
09367     0,
09368     1,
09369     1
09370   },
09371   {
09372     "addsi3_internal",
09373     "addu\t%0,%z1,%2",
09374     (insn_gen_fn) gen_addsi3_internal,
09375     &operand_data[10],
09376     3,
09377     0,
09378     1,
09379     1
09380   },
09381   {
09382     "*mips.md:672",
09383     "addu\t%$,%$,%0",
09384     0,
09385     &operand_data[13],
09386     1,
09387     0,
09388     1,
09389     1
09390   },
09391   {
09392     "*mips.md:684",
09393     "addu\t%0,%$,%1",
09394     0,
09395     &operand_data[14],
09396     2,
09397     0,
09398     1,
09399     1
09400   },
09401   {
09402     "*mips.md:696",
09403     (const PTR) output_7,
09404     0,
09405     &operand_data[16],
09406     3,
09407     0,
09408     3,
09409     3
09410   },
09411   {
09412     "adddi3_internal_1",
09413     (const PTR) output_8,
09414     (insn_gen_fn) gen_adddi3_internal_1,
09415     &operand_data[19],
09416     4,
09417     0,
09418     2,
09419     3
09420   },
09421   {
09422     "adddi3_internal_2",
09423     (const PTR) output_9,
09424     (insn_gen_fn) gen_adddi3_internal_2,
09425     &operand_data[23],
09426     4,
09427     0,
09428     3,
09429     2
09430   },
09431   {
09432     "adddi3_internal_3",
09433     (const PTR) output_10,
09434     (insn_gen_fn) gen_adddi3_internal_3,
09435     &operand_data[27],
09436     3,
09437     0,
09438     1,
09439     3
09440   },
09441   {
09442     "*mips.md:1012",
09443     "daddu\t%$,%$,%0",
09444     0,
09445     &operand_data[30],
09446     1,
09447     0,
09448     1,
09449     1
09450   },
09451   {
09452     "*mips.md:1024",
09453     "daddu\t%0,%$,%1",
09454     0,
09455     &operand_data[31],
09456     2,
09457     0,
09458     1,
09459     1
09460   },
09461   {
09462     "*mips.md:1036",
09463     (const PTR) output_13,
09464     0,
09465     &operand_data[33],
09466     3,
09467     0,
09468     3,
09469     3
09470   },
09471   {
09472     "addsi3_internal_2",
09473     (const PTR) output_14,
09474     (insn_gen_fn) gen_addsi3_internal_2,
09475     &operand_data[36],
09476     3,
09477     0,
09478     1,
09479     3
09480   },
09481   {
09482     "*mips.md:1158",
09483     (const PTR) output_15,
09484     0,
09485     &operand_data[39],
09486     3,
09487     0,
09488     3,
09489     3
09490   },
09491   {
09492     "subdf3",
09493     "sub.d\t%0,%1,%2",
09494     (insn_gen_fn) gen_subdf3,
09495     &operand_data[4],
09496     3,
09497     0,
09498     1,
09499     1
09500   },
09501   {
09502     "subsf3",
09503     "sub.s\t%0,%1,%2",
09504     (insn_gen_fn) gen_subsf3,
09505     &operand_data[7],
09506     3,
09507     0,
09508     1,
09509     1
09510   },
09511   {
09512     "subsi3_internal",
09513     "subu\t%0,%z1,%2",
09514     (insn_gen_fn) gen_subsi3_internal,
09515     &operand_data[10],
09516     3,
09517     0,
09518     1,
09519     1
09520   },
09521   {
09522     "*mips.md:1235",
09523     "addu\t%$,%$,%n0",
09524     0,
09525     &operand_data[13],
09526     1,
09527     0,
09528     1,
09529     1
09530   },
09531   {
09532     "*mips.md:1248",
09533     "addu\t%0,%$,%n1",
09534     0,
09535     &operand_data[14],
09536     2,
09537     0,
09538     1,
09539     1
09540   },
09541   {
09542     "*mips.md:1262",
09543     (const PTR) output_21,
09544     0,
09545     &operand_data[42],
09546     3,
09547     0,
09548     3,
09549     3
09550   },
09551   {
09552     "subdi3_internal",
09553     "sltu\t%3,%L1,%L2\n\tsubu\t%L0,%L1,%L2\n\tsubu\t%M0,%M1,%M2\n\tsubu\t%M0,%M0,%3",
09554     (insn_gen_fn) gen_subdi3_internal,
09555     &operand_data[45],
09556     4,
09557     0,
09558     1,
09559     1
09560   },
09561   {
09562     "subdi3_internal_2",
09563     (const PTR) output_23,
09564     (insn_gen_fn) gen_subdi3_internal_2,
09565     &operand_data[49],
09566     4,
09567     0,
09568     3,
09569     2
09570   },
09571   {
09572     "subdi3_internal_3",
09573     (const PTR) output_24,
09574     (insn_gen_fn) gen_subdi3_internal_3,
09575     &operand_data[27],
09576     3,
09577     0,
09578     1,
09579     3
09580   },
09581   {
09582     "*mips.md:1522",
09583     "daddu\t%$,%$,%n0",
09584     0,
09585     &operand_data[30],
09586     1,
09587     0,
09588     1,
09589     1
09590   },
09591   {
09592     "*mips.md:1535",
09593     "daddu\t%0,%$,%n1",
09594     0,
09595     &operand_data[31],
09596     2,
09597     0,
09598     1,
09599     1
09600   },
09601   {
09602     "*mips.md:1548",
09603     (const PTR) output_27,
09604     0,
09605     &operand_data[53],
09606     3,
09607     0,
09608     3,
09609     3
09610   },
09611   {
09612     "subsi3_internal_2",
09613     (const PTR) output_28,
09614     (insn_gen_fn) gen_subsi3_internal_2,
09615     &operand_data[36],
09616     3,
09617     0,
09618     1,
09619     3
09620   },
09621   {
09622     "*mips.md:1656",
09623     (const PTR) output_29,
09624     0,
09625     &operand_data[39],
09626     3,
09627     0,
09628     3,
09629     3
09630   },
09631   {
09632     "muldf3_internal",
09633     "mul.d\t%0,%1,%2",
09634     (insn_gen_fn) gen_muldf3_internal,
09635     &operand_data[4],
09636     3,
09637     0,
09638     1,
09639     1
09640   },
09641   {
09642     "muldf3_r4300",
09643     (const PTR) output_31,
09644     (insn_gen_fn) gen_muldf3_r4300,
09645     &operand_data[4],
09646     3,
09647     0,
09648     1,
09649     3
09650   },
09651   {
09652     "mulsf3_internal",
09653     "mul.s\t%0,%1,%2",
09654     (insn_gen_fn) gen_mulsf3_internal,
09655     &operand_data[7],
09656     3,
09657     0,
09658     1,
09659     1
09660   },
09661   {
09662     "mulsf3_r4300",
09663     (const PTR) output_33,
09664     (insn_gen_fn) gen_mulsf3_r4300,
09665     &operand_data[7],
09666     3,
09667     0,
09668     1,
09669     3
09670   },
09671   {
09672     "mulsi3_mult3",
09673     (const PTR) output_34,
09674     (insn_gen_fn) gen_mulsi3_mult3,
09675     &operand_data[56],
09676     6,
09677     0,
09678     2,
09679     3
09680   },
09681   {
09682     "mulsi3_internal",
09683     "mult\t%1,%2",
09684     (insn_gen_fn) gen_mulsi3_internal,
09685     &operand_data[62],
09686     5,
09687     0,
09688     1,
09689     1
09690   },
09691   {
09692     "mulsi3_r4000",
09693     (const PTR) output_36,
09694     (insn_gen_fn) gen_mulsi3_r4000,
09695     &operand_data[67],
09696     6,
09697     0,
09698     1,
09699     3
09700   },
09701   {
09702     "*mul_acc_si",
09703     (const PTR) output_37,
09704     0,
09705     &operand_data[73],
09706     8,
09707     0,
09708     3,
09709     3
09710   },
09711   {
09712     "*mul_sub_si",
09713     (const PTR) output_38,
09714     0,
09715     &operand_data[81],
09716     8,
09717     0,
09718     3,
09719     3
09720   },
09721   {
09722     "*muls",
09723     (const PTR) output_39,
09724     0,
09725     &operand_data[89],
09726     6,
09727     0,
09728     2,
09729     2
09730   },
09731   {
09732     "*msac",
09733     (const PTR) output_40,
09734     0,
09735     &operand_data[95],
09736     8,
09737     0,
09738     3,
09739     2
09740   },
09741   {
09742     "muldi3_internal",
09743     "dmult\t%1,%2",
09744     (insn_gen_fn) gen_muldi3_internal,
09745     &operand_data[103],
09746     5,
09747     0,
09748     1,
09749     1
09750   },
09751   {
09752     "muldi3_internal2",
09753     (const PTR) output_42,
09754     (insn_gen_fn) gen_muldi3_internal2,
09755     &operand_data[108],
09756     6,
09757     0,
09758     1,
09759     3
09760   },
09761   {
09762     "mulsidi3_internal",
09763     (const PTR) output_43,
09764     (insn_gen_fn) gen_mulsidi3_internal,
09765     &operand_data[114],
09766     6,
09767     0,
09768     1,
09769     3
09770   },
09771   {
09772     "mulsidi3_64bit",
09773     (const PTR) output_44,
09774     (insn_gen_fn) gen_mulsidi3_64bit,
09775     &operand_data[120],
09776     7,
09777     0,
09778     1,
09779     3
09780   },
09781   {
09782     "*muls_di",
09783     (const PTR) output_45,
09784     0,
09785     &operand_data[127],
09786     7,
09787     0,
09788     1,
09789     3
09790   },
09791   {
09792     "*msac_di",
09793     (const PTR) output_46,
09794     0,
09795     &operand_data[134],
09796     8,
09797     0,
09798     1,
09799     3
09800   },
09801   {
09802     "xmulsi3_highpart_internal",
09803     (const PTR) output_47,
09804     (insn_gen_fn) gen_xmulsi3_highpart_internal,
09805     &operand_data[142],
09806     8,
09807     0,
09808     1,
09809     3
09810   },
09811   {
09812     "xmulsi3_highpart_mulhi",
09813     (const PTR) output_48,
09814     (insn_gen_fn) gen_xmulsi3_highpart_mulhi,
09815     &operand_data[150],
09816     9,
09817     0,
09818     2,
09819     3
09820   },
09821   {
09822     "*xmulsi3_neg_highpart_mulhi",
09823     (const PTR) output_49,
09824     0,
09825     &operand_data[150],
09826     9,
09827     0,
09828     2,
09829     3
09830   },
09831   {
09832     "smuldi3_highpart",
09833     "dmult\t%1,%2",
09834     (insn_gen_fn) gen_smuldi3_highpart,
09835     &operand_data[159],
09836     5,
09837     0,
09838     1,
09839     1
09840   },
09841   {
09842     "umuldi3_highpart",
09843     "dmultu\t%1,%2",
09844     (insn_gen_fn) gen_umuldi3_highpart,
09845     &operand_data[159],
09846     5,
09847     0,
09848     1,
09849     1
09850   },
09851   {
09852     "madsi",
09853     "mad\t%1,%2",
09854     (insn_gen_fn) gen_madsi,
09855     &operand_data[164],
09856     5,
09857     1,
09858     1,
09859     1
09860   },
09861   {
09862     "*mul_acc_di",
09863     (const PTR) output_53,
09864     0,
09865     &operand_data[169],
09866     6,
09867     1,
09868     1,
09869     3
09870   },
09871   {
09872     "*mul_acc_64bit_di",
09873     (const PTR) output_54,
09874     0,
09875     &operand_data[175],
09876     7,
09877     1,
09878     1,
09879     3
09880   },
09881   {
09882     "*mips.md:2502",
09883     "madd.d\t%0,%3,%1,%2",
09884     0,
09885     &operand_data[182],
09886     4,
09887     0,
09888     1,
09889     1
09890   },
09891   {
09892     "*mips.md:2512",
09893     "madd.s\t%0,%3,%1,%2",
09894     0,
09895     &operand_data[186],
09896     4,
09897     0,
09898     1,
09899     1
09900   },
09901   {
09902     "*mips.md:2522",
09903     "msub.d\t%0,%3,%1,%2",
09904     0,
09905     &operand_data[182],
09906     4,
09907     0,
09908     1,
09909     1
09910   },
09911   {
09912     "*mips.md:2532",
09913     "msub.s\t%0,%3,%1,%2",
09914     0,
09915     &operand_data[186],
09916     4,
09917     0,
09918     1,
09919     1
09920   },
09921   {
09922     "*mips.md:2543",
09923     "nmadd.d\t%0,%3,%1,%2",
09924     0,
09925     &operand_data[182],
09926     4,
09927     0,
09928     1,
09929     1
09930   },
09931   {
09932     "*mips.md:2553",
09933     "nmadd.s\t%0,%3,%1,%2",
09934     0,
09935     &operand_data[186],
09936     4,
09937     0,
09938     1,
09939     1
09940   },
09941   {
09942     "*mips.md:2563",
09943     "nmsub.d\t%0,%1,%2,%3",
09944     0,
09945     &operand_data[182],
09946     4,
09947     0,
09948     1,
09949     1
09950   },
09951   {
09952     "*mips.md:2573",
09953     "nmsub.s\t%0,%1,%2,%3",
09954     0,
09955     &operand_data[186],
09956     4,
09957     0,
09958     1,
09959     1
09960   },
09961   {
09962     "divdf3",
09963     "div.d\t%0,%1,%2",
09964     (insn_gen_fn) gen_divdf3,
09965     &operand_data[4],
09966     3,
09967     0,
09968     1,
09969     1
09970   },
09971   {
09972     "divsf3",
09973     "div.s\t%0,%1,%2",
09974     (insn_gen_fn) gen_divsf3,
09975     &operand_data[7],
09976     3,
09977     0,
09978     1,
09979     1
09980   },
09981   {
09982     "*mips.md:2609",
09983     "recip.d\t%0,%2",
09984     0,
09985     &operand_data[190],
09986     3,
09987     0,
09988     1,
09989     1
09990   },
09991   {
09992     "*mips.md:2618",
09993     "recip.s\t%0,%2",
09994     0,
09995     &operand_data[193],
09996     3,
09997     0,
09998     1,
09999     1
10000   },
10001   {
10002     "divmodsi4_internal",
10003     "div\t$0,%1,%2",
10004     (insn_gen_fn) gen_divmodsi4_internal,
10005     &operand_data[196],
10006     5,
10007     2,
10008     1,
10009     1
10010   },
10011   {
10012     "divmoddi4_internal",
10013     "ddiv\t$0,%1,%2",
10014     (insn_gen_fn) gen_divmoddi4_internal,
10015     &operand_data[201],
10016     5,
10017     2,
10018     1,
10019     1
10020   },
10021   {
10022     "udivmodsi4_internal",
10023     "divu\t$0,%1,%2",
10024     (insn_gen_fn) gen_udivmodsi4_internal,
10025     &operand_data[196],
10026     5,
10027     2,
10028     1,
10029     1
10030   },
10031   {
10032     "udivmoddi4_internal",
10033     "ddivu\t$0,%1,%2",
10034     (insn_gen_fn) gen_udivmoddi4_internal,
10035     &operand_data[201],
10036     5,
10037     2,
10038     1,
10039     1
10040   },
10041   {
10042     "div_trap_normal",
10043     (const PTR) output_71,
10044     (insn_gen_fn) gen_div_trap_normal,
10045     &operand_data[206],
10046     3,
10047     0,
10048     2,
10049     3
10050   },
10051   {
10052     "div_trap_mips16",
10053     (const PTR) output_72,
10054     (insn_gen_fn) gen_div_trap_mips16,
10055     &operand_data[206],
10056     3,
10057     0,
10058     2,
10059     3
10060   },
10061   {
10062     "divsi3_internal",
10063     "div\t$0,%1,%2",
10064     (insn_gen_fn) gen_divsi3_internal,
10065     &operand_data[209],
10066     5,
10067     0,
10068     1,
10069     1
10070   },
10071   {
10072     "divdi3_internal",
10073     "ddiv\t$0,%1,%2",
10074     (insn_gen_fn) gen_divdi3_internal,
10075     &operand_data[214],
10076     5,
10077     0,
10078     1,
10079     1
10080   },
10081   {
10082     "modsi3_internal",
10083     "div\t$0,%1,%2",
10084     (insn_gen_fn) gen_modsi3_internal,
10085     &operand_data[219],
10086     5,
10087     0,
10088     1,
10089     1
10090   },
10091   {
10092     "moddi3_internal",
10093     "ddiv\t$0,%1,%2",
10094     (insn_gen_fn) gen_moddi3_internal,
10095     &operand_data[224],
10096     5,
10097     0,
10098     1,
10099     1
10100   },
10101   {
10102     "udivsi3_internal",
10103     "divu\t$0,%1,%2",
10104     (insn_gen_fn) gen_udivsi3_internal,
10105     &operand_data[209],
10106     5,
10107     0,
10108     1,
10109     1
10110   },
10111   {
10112     "udivdi3_internal",
10113     "ddivu\t$0,%1,%2",
10114     (insn_gen_fn) gen_udivdi3_internal,
10115     &operand_data[214],
10116     5,
10117     0,
10118     1,
10119     1
10120   },
10121   {
10122     "umodsi3_internal",
10123     "divu\t$0,%1,%2",
10124     (insn_gen_fn) gen_umodsi3_internal,
10125     &operand_data[219],
10126     5,
10127     0,
10128     1,
10129     1
10130   },
10131   {
10132     "umoddi3_internal",
10133     "ddivu\t$0,%1,%2",
10134     (insn_gen_fn) gen_umoddi3_internal,
10135     &operand_data[224],
10136     5,
10137     0,
10138     1,
10139     1
10140   },
10141   {
10142     "sqrtdf2",
10143     "sqrt.d\t%0,%1",
10144     (insn_gen_fn) gen_sqrtdf2,
10145     &operand_data[4],
10146     2,
10147     0,
10148     1,
10149     1
10150   },
10151   {
10152     "sqrtsf2",
10153     "sqrt.s\t%0,%1",
10154     (insn_gen_fn) gen_sqrtsf2,
10155     &operand_data[7],
10156     2,
10157     0,
10158     1,
10159     1
10160   },
10161   {
10162     "*mips.md:3222",
10163     "rsqrt.d\t%0,%2",
10164     0,
10165     &operand_data[190],
10166     3,
10167     0,
10168     1,
10169     1
10170   },
10171   {
10172     "*mips.md:3231",
10173     "rsqrt.s\t%0,%2",
10174     0,
10175     &operand_data[193],
10176     3,
10177     0,
10178     1,
10179     1
10180   },
10181   {
10182     "abssi2",
10183     (const PTR) output_85,
10184     (insn_gen_fn) gen_abssi2,
10185     &operand_data[67],
10186     2,
10187     0,
10188     1,
10189     3
10190   },
10191   {
10192     "absdi2",
10193     (const PTR) output_86,
10194     (insn_gen_fn) gen_absdi2,
10195     &operand_data[108],
10196     2,
10197     0,
10198     1,
10199     3
10200   },
10201   {
10202     "absdf2",
10203     "abs.d\t%0,%1",
10204     (insn_gen_fn) gen_absdf2,
10205     &operand_data[4],
10206     2,
10207     0,
10208     1,
10209     1
10210   },
10211   {
10212     "abssf2",
10213     "abs.s\t%0,%1",
10214     (insn_gen_fn) gen_abssf2,
10215     &operand_data[7],
10216     2,
10217     0,
10218     1,
10219     1
10220   },
10221   {
10222     "ffssi2",
10223     (const PTR) output_89,
10224     (insn_gen_fn) gen_ffssi2,
10225     &operand_data[229],
10226     4,
10227     0,
10228     1,
10229     3
10230   },
10231   {
10232     "ffsdi2",
10233     (const PTR) output_90,
10234     (insn_gen_fn) gen_ffsdi2,
10235     &operand_data[233],
10236     4,
10237     0,
10238     1,
10239     3
10240   },
10241   {
10242     "negsi2",
10243     (const PTR) output_91,
10244     (insn_gen_fn) gen_negsi2,
10245     &operand_data[67],
10246     2,
10247     0,
10248     1,
10249     3
10250   },
10251   {
10252     "negdi2_internal",
10253     (const PTR) output_92,
10254     (insn_gen_fn) gen_negdi2_internal,
10255     &operand_data[237],
10256     3,
10257     0,
10258     1,
10259     3
10260   },
10261   {
10262     "negdi2_internal_2",
10263     (const PTR) output_93,
10264     (insn_gen_fn) gen_negdi2_internal_2,
10265     &operand_data[108],
10266     2,
10267     0,
10268     1,
10269     3
10270   },
10271   {
10272     "negdf2",
10273     "neg.d\t%0,%1",
10274     (insn_gen_fn) gen_negdf2,
10275     &operand_data[4],
10276     2,
10277     0,
10278     1,
10279     1
10280   },
10281   {
10282     "negsf2",
10283     "neg.s\t%0,%1",
10284     (insn_gen_fn) gen_negsf2,
10285     &operand_data[7],
10286     2,
10287     0,
10288     1,
10289     1
10290   },
10291   {
10292     "one_cmplsi2",
10293     (const PTR) output_96,
10294     (insn_gen_fn) gen_one_cmplsi2,
10295     &operand_data[67],
10296     2,
10297     0,
10298     1,
10299     3
10300   },
10301   {
10302     "one_cmpldi2",
10303     (const PTR) output_97,
10304     (insn_gen_fn) gen_one_cmpldi2,
10305     &operand_data[108],
10306     2,
10307     0,
10308     1,
10309     3
10310   },
10311   {
10312     "*mips.md:3553",
10313     (const PTR) output_98,
10314     0,
10315     &operand_data[240],
10316     3,
10317     0,
10318     2,
10319     2
10320   },
10321   {
10322     "*mips.md:3564",
10323     "and\t%0,%2",
10324     0,
10325     &operand_data[243],
10326     3,
10327     0,
10328     1,
10329     1
10330   },
10331   {
10332     "*mips.md:3587",
10333     (const PTR) output_100,
10334     0,
10335     &operand_data[246],
10336     3,
10337     0,
10338     1,
10339     3
10340   },
10341   {
10342     "*mips.md:3605",
10343     (const PTR) output_101,
10344     0,
10345     &operand_data[249],
10346     3,
10347     0,
10348     1,
10349     3
10350   },
10351   {
10352     "anddi3_internal1",
10353     (const PTR) output_102,
10354     (insn_gen_fn) gen_anddi3_internal1,
10355     &operand_data[252],
10356     3,
10357     0,
10358     2,
10359     2
10360   },
10361   {
10362     "*mips.md:3662",
10363     (const PTR) output_103,
10364     0,
10365     &operand_data[240],
10366     3,
10367     0,
10368     2,
10369     2
10370   },
10371   {
10372     "*mips.md:3673",
10373     "or\t%0,%2",
10374     0,
10375     &operand_data[243],
10376     3,
10377     0,
10378     1,
10379     1
10380   },
10381   {
10382     "*mips.md:3692",
10383     (const PTR) output_105,
10384     0,
10385     &operand_data[246],
10386     3,
10387     0,
10388     1,
10389     3
10390   },
10391   {
10392     "*mips.md:3710",
10393     (const PTR) output_106,
10394     0,
10395     &operand_data[249],
10396     3,
10397     0,
10398     1,
10399     3
10400   },
10401   {
10402     "*mips.md:3749",
10403     (const PTR) output_107,
10404     0,
10405     &operand_data[240],
10406     3,
10407     0,
10408     2,
10409     2
10410   },
10411   {
10412     "*mips.md:3760",
10413     (const PTR) output_108,
10414     0,
10415     &operand_data[255],
10416     3,
10417     0,
10418     3,
10419     2
10420   },
10421   {
10422     "*mips.md:3787",
10423     (const PTR) output_109,
10424     0,
10425     &operand_data[246],
10426     3,
10427     0,
10428     1,
10429     3
10430   },
10431   {
10432     "*mips.md:3805",
10433     "xor\t%M0,%M2\n\txor\t%L0,%L2",
10434     0,
10435     &operand_data[249],
10436     3,
10437     0,
10438     1,
10439     1
10440   },
10441   {
10442     "*mips.md:3815",
10443     (const PTR) output_111,
10444     0,
10445     &operand_data[258],
10446     3,
10447     0,
10448     3,
10449     2
10450   },
10451   {
10452     "xordi3_immed",
10453     "xori\t%0,%1,%x2",
10454     (insn_gen_fn) gen_xordi3_immed,
10455     &operand_data[261],
10456     3,
10457     0,
10458     1,
10459     1
10460   },
10461   {
10462     "*norsi3",
10463     "nor\t%0,%z1,%z2",
10464     0,
10465     &operand_data[67],
10466     3,
10467     0,
10468     1,
10469     1
10470   },
10471   {
10472     "*nordi3",
10473     (const PTR) output_114,
10474     0,
10475     &operand_data[246],
10476     3,
10477     0,
10478     1,
10479     3
10480   },
10481   {
10482     "truncdfsf2",
10483     "cvt.s.d\t%0,%1",
10484     (insn_gen_fn) gen_truncdfsf2,
10485     &operand_data[264],
10486     2,
10487     0,
10488     1,
10489     1
10490   },
10491   {
10492     "truncdisi2",
10493     (const PTR) output_116,
10494     (insn_gen_fn) gen_truncdisi2,
10495     &operand_data[266],
10496     2,
10497     0,
10498     1,
10499     3
10500   },
10501   {
10502     "truncdihi2",
10503     (const PTR) output_117,
10504     (insn_gen_fn) gen_truncdihi2,
10505     &operand_data[268],
10506     2,
10507     0,
10508     1,
10509     3
10510   },
10511   {
10512     "truncdiqi2",
10513     (const PTR) output_118,
10514     (insn_gen_fn) gen_truncdiqi2,
10515     &operand_data[270],
10516     2,
10517     0,
10518     1,
10519     3
10520   },
10521   {
10522     "*mips.md:3960",
10523     (const PTR) output_119,
10524     0,
10525     &operand_data[272],
10526     3,
10527     0,
10528     1,
10529     3
10530   },
10531   {
10532     "*mips.md:3984",
10533     (const PTR) output_120,
10534     0,
10535     &operand_data[272],
10536     3,
10537     0,
10538     1,
10539     3
10540   },
10541   {
10542     "*mips.md:4010",
10543     (const PTR) output_121,
10544     0,
10545     &operand_data[272],
10546     3,
10547     0,
10548     1,
10549     3
10550   },
10551   {
10552     "*mips.md:4035",
10553     "andi\t%0,%1,0xffff",
10554     0,
10555     &operand_data[266],
10556     2,
10557     0,
10558     1,
10559     1
10560   },
10561   {
10562     "*mips.md:4044",
10563     "andi\t%0,%1,0xff",
10564     0,
10565     &operand_data[266],
10566     2,
10567     0,
10568     1,
10569     1
10570   },
10571   {
10572     "*mips.md:4053",
10573     "andi\t%0,%1,0xff",
10574     0,
10575     &operand_data[268],
10576     2,
10577     0,
10578     1,
10579     1
10580   },
10581   {
10582     "zero_extendsidi2_internal",
10583     (const PTR) output_125,
10584     (insn_gen_fn) gen_zero_extendsidi2_internal,
10585     &operand_data[275],
10586     2,
10587     0,
10588     2,
10589     3
10590   },
10591   {
10592     "*mips.md:4118",
10593     (const PTR) output_126,
10594     0,
10595     &operand_data[277],
10596     2,
10597     0,
10598     3,
10599     3
10600   },
10601   {
10602     "*mips.md:4133",
10603     (const PTR) output_127,
10604     0,
10605     &operand_data[279],
10606     2,
10607     0,
10608     2,
10609     3
10610   },
10611   {
10612     "*mips.md:4158",
10613     (const PTR) output_128,
10614     0,
10615     &operand_data[281],
10616     2,
10617     0,
10618     3,
10619     3
10620   },
10621   {
10622     "*mips.md:4173",
10623     (const PTR) output_129,
10624     0,
10625     &operand_data[283],
10626     2,
10627     0,
10628     2,
10629     3
10630   },
10631   {
10632     "*mips.md:4199",
10633     (const PTR) output_130,
10634     0,
10635     &operand_data[285],
10636     2,
10637     0,
10638     3,
10639     3
10640   },
10641   {
10642     "*mips.md:4214",
10643     (const PTR) output_131,
10644     0,
10645     &operand_data[287],
10646     2,
10647     0,
10648     2,
10649     3
10650   },
10651   {
10652     "*mips.md:4239",
10653     (const PTR) output_132,
10654     0,
10655     &operand_data[289],
10656     2,
10657     0,
10658     3,
10659     3
10660   },
10661   {
10662     "*mips.md:4254",
10663     (const PTR) output_133,
10664     0,
10665     &operand_data[291],
10666     2,
10667     0,
10668     2,
10669     3
10670   },
10671   {
10672     "*mips.md:4279",
10673     (const PTR) output_134,
10674     0,
10675     &operand_data[293],
10676     2,
10677     0,
10678     3,
10679     3
10680   },
10681   {
10682     "*paradoxical_extendhidi2",
10683     (const PTR) output_135,
10684     0,
10685     &operand_data[283],
10686     2,
10687     0,
10688     2,
10689     3
10690   },
10691   {
10692     "*mips.md:4312",
10693     (const PTR) output_136,
10694     0,
10695     &operand_data[295],
10696     2,
10697     0,
10698     2,
10699     3
10700   },
10701   {
10702     "extendhidi2_internal",
10703     (const PTR) output_137,
10704     (insn_gen_fn) gen_extendhidi2_internal,
10705     &operand_data[283],
10706     2,
10707     0,
10708     2,
10709     3
10710   },
10711   {
10712     "extendhisi2_internal",
10713     (const PTR) output_138,
10714     (insn_gen_fn) gen_extendhisi2_internal,
10715     &operand_data[279],
10716     2,
10717     0,
10718     2,
10719     3
10720   },
10721   {
10722     "extendqihi2_internal",
10723     (const PTR) output_139,
10724     (insn_gen_fn) gen_extendqihi2_internal,
10725     &operand_data[287],
10726     2,
10727     0,
10728     2,
10729     3
10730   },
10731   {
10732     "extendqisi2_insn",
10733     (const PTR) output_140,
10734     (insn_gen_fn) gen_extendqisi2_insn,
10735     &operand_data[291],
10736     2,
10737     0,
10738     2,
10739     3
10740   },
10741   {
10742     "extendqidi2_insn",
10743     (const PTR) output_141,
10744     (insn_gen_fn) gen_extendqidi2_insn,
10745     &operand_data[295],
10746     2,
10747     0,
10748     2,
10749     3
10750   },
10751   {
10752     "extendsfdf2",
10753     "cvt.d.s\t%0,%1",
10754     (insn_gen_fn) gen_extendsfdf2,
10755     &operand_data[297],
10756     2,
10757     0,
10758     1,
10759     1
10760   },
10761   {
10762     "fix_truncdfsi2_insn",
10763     "trunc.w.d %0,%1",
10764     (insn_gen_fn) gen_fix_truncdfsi2_insn,
10765     &operand_data[299],
10766     2,
10767     0,
10768     1,
10769     1
10770   },
10771   {
10772     "fix_truncdfsi2_macro",
10773     "trunc.w.d %0,%1,%2",
10774     (insn_gen_fn) gen_fix_truncdfsi2_macro,
10775     &operand_data[299],
10776     3,
10777     0,
10778     1,
10779     1
10780   },
10781   {
10782     "fix_truncsfsi2_insn",
10783     "trunc.w.s %0,%1",
10784     (insn_gen_fn) gen_fix_truncsfsi2_insn,
10785     &operand_data[302],
10786     2,
10787     0,
10788     1,
10789     1
10790   },
10791   {
10792     "fix_truncsfsi2_macro",
10793     "trunc.w.s %0,%1,%2",
10794     (insn_gen_fn) gen_fix_truncsfsi2_macro,
10795     &operand_data[302],
10796     3,
10797     0,
10798     1,
10799     1
10800   },
10801   {
10802     "fix_truncdfdi2",
10803     "trunc.l.d %0,%1",
10804     (insn_gen_fn) gen_fix_truncdfdi2,
10805     &operand_data[305],
10806     2,
10807     0,
10808     1,
10809     1
10810   },
10811   {
10812     "fix_truncsfdi2",
10813     "trunc.l.s %0,%1",
10814     (insn_gen_fn) gen_fix_truncsfdi2,
10815     &operand_data[307],
10816     2,
10817     0,
10818     1,
10819     1
10820   },
10821   {
10822     "floatsidf2",
10823     "cvt.d.w\t%0,%1",
10824     (insn_gen_fn) gen_floatsidf2,
10825     &operand_data[309],
10826     2,
10827     0,
10828     1,
10829     1
10830   },
10831   {
10832     "floatdidf2",
10833     "cvt.d.l\t%0,%1",
10834     (insn_gen_fn) gen_floatdidf2,
10835     &operand_data[311],
10836     2,
10837     0,
10838     1,
10839     1
10840   },
10841   {
10842     "floatsisf2",
10843     "cvt.s.w\t%0,%1",
10844     (insn_gen_fn) gen_floatsisf2,
10845     &operand_data[313],
10846     2,
10847     0,
10848     1,
10849     1
10850   },
10851   {
10852     "floatdisf2",
10853     "cvt.s.l\t%0,%1",
10854     (insn_gen_fn) gen_floatdisf2,
10855     &operand_data[315],
10856     2,
10857     0,
10858     1,
10859     1
10860   },
10861   {
10862     "movsi_ulw",
10863     (const PTR) output_153,
10864     (insn_gen_fn) gen_movsi_ulw,
10865     &operand_data[317],
10866     2,
10867     0,
10868     2,
10869     3
10870   },
10871   {
10872     "movsi_usw",
10873     (const PTR) output_154,
10874     (insn_gen_fn) gen_movsi_usw,
10875     &operand_data[319],
10876     2,
10877     0,
10878     2,
10879     3
10880   },
10881   {
10882     "movdi_uld",
10883     (const PTR) output_155,
10884     (insn_gen_fn) gen_movdi_uld,
10885     &operand_data[321],
10886     2,
10887     0,
10888     2,
10889     3
10890   },
10891   {
10892     "movdi_usd",
10893     (const PTR) output_156,
10894     (insn_gen_fn) gen_movdi_usd,
10895     &operand_data[323],
10896     2,
10897     0,
10898     2,
10899     3
10900   },
10901   {
10902     "high",
10903     "lui\t%0,%%hi(%1) # high",
10904     (insn_gen_fn) gen_high,
10905     &operand_data[325],
10906     2,
10907     0,
10908     1,
10909     1
10910   },
10911   {
10912     "low",
10913     "addiu\t%0,%1,%%lo(%2) # low",
10914     (insn_gen_fn) gen_low,
10915     &operand_data[327],
10916     3,
10917     0,
10918     1,
10919     1
10920   },
10921   {
10922     "*mips.md:5249",
10923     (const PTR) output_159,
10924     0,
10925     &operand_data[330],
10926     1,
10927     0,
10928     2,
10929     3
10930   },
10931   {
10932     "movdi_internal",
10933     (const PTR) output_160,
10934     (insn_gen_fn) gen_movdi_internal,
10935     &operand_data[331],
10936     2,
10937     0,
10938     15,
10939     3
10940   },
10941   {
10942     "*mips.md:5275",
10943     (const PTR) output_161,
10944     0,
10945     &operand_data[333],
10946     2,
10947     0,
10948     10,
10949     3
10950   },
10951   {
10952     "movdi_internal2",
10953     (const PTR) output_162,
10954     (insn_gen_fn) gen_movdi_internal2,
10955     &operand_data[335],
10956     2,
10957     0,
10958     24,
10959     3
10960   },
10961   {
10962     "*movdi_internal2_extend",
10963     (const PTR) output_163,
10964     0,
10965     &operand_data[337],
10966     2,
10967     0,
10968     19,
10969     3
10970   },
10971   {
10972     "*movdi_internal2_mips16",
10973     (const PTR) output_164,
10974     0,
10975     &operand_data[339],
10976     2,
10977     0,
10978     11,
10979     3
10980   },
10981   {
10982     "*mips.md:5700",
10983     "sw\t$31,%0($sp)",
10984     0,
10985     &operand_data[341],
10986     1,
10987     0,
10988     1,
10989     1
10990   },
10991   {
10992     "movsi_internal",
10993     (const PTR) output_166,
10994     (insn_gen_fn) gen_movsi_internal,
10995     &operand_data[342],
10996     2,
10997     0,
10998     26,
10999     3
11000   },
11001   {
11002     "*mips.md:5739",
11003     (const PTR) output_167,
11004     0,
11005     &operand_data[344],
11006     2,
11007     0,
11008     12,
11009     3
11010   },
11011   {
11012     "hilo_delay",
11013     "",
11014     (insn_gen_fn) gen_hilo_delay,
11015     &operand_data[346],
11016     1,
11017     0,
11018     1,
11019     1
11020   },
11021   {
11022     "movcc",
11023     (const PTR) output_169,
11024     (insn_gen_fn) gen_movcc,
11025     &operand_data[347],
11026     2,
11027     0,
11028     13,
11029     3
11030   },
11031   {
11032     "*mips.md:6074",
11033     "lwxc1\t%0,%1(%2)",
11034     0,
11035     &operand_data[349],
11036     3,
11037     0,
11038     1,
11039     1
11040   },
11041   {
11042     "*mips.md:6083",
11043     "lwxc1\t%0,%1(%2)",
11044     0,
11045     &operand_data[352],
11046     3,
11047     0,
11048     1,
11049     1
11050   },
11051   {
11052     "*mips.md:6092",
11053     "ldxc1\t%0,%1(%2)",
11054     0,
11055     &operand_data[355],
11056     3,
11057     0,
11058     1,
11059     1
11060   },
11061   {
11062     "*mips.md:6101",
11063     "ldxc1\t%0,%1(%2)",
11064     0,
11065     &operand_data[358],
11066     3,
11067     0,
11068     1,
11069     1
11070   },
11071   {
11072     "*mips.md:6110",
11073     "swxc1\t%0,%1(%2)",
11074     0,
11075     &operand_data[361],
11076     3,
11077     0,
11078     1,
11079     1
11080   },
11081   {
11082     "*mips.md:6119",
11083     "swxc1\t%0,%1(%2)",
11084     0,
11085     &operand_data[364],
11086     3,
11087     0,
11088     1,
11089     1
11090   },
11091   {
11092     "*mips.md:6128",
11093     "sdxc1\t%0,%1(%2)",
11094     0,
11095     &operand_data[367],
11096     3,
11097     0,
11098     1,
11099     1
11100   },
11101   {
11102     "*mips.md:6137",
11103     "sdxc1\t%0,%1(%2)",
11104     0,
11105     &operand_data[370],
11106     3,
11107     0,
11108     1,
11109     1
11110   },
11111   {
11112     "movhi_internal",
11113     (const PTR) output_178,
11114     (insn_gen_fn) gen_movhi_internal,
11115     &operand_data[373],
11116     2,
11117     0,
11118     11,
11119     3
11120   },
11121   {
11122     "*mips.md:6187",
11123     (const PTR) output_179,
11124     0,
11125     &operand_data[375],
11126     2,
11127     0,
11128     10,
11129     3
11130   },
11131   {
11132     "movqi_internal",
11133     (const PTR) output_180,
11134     (insn_gen_fn) gen_movqi_internal,
11135     &operand_data[377],
11136     2,
11137     0,
11138     11,
11139     3
11140   },
11141   {
11142     "*mips.md:6297",
11143     (const PTR) output_181,
11144     0,
11145     &operand_data[379],
11146     2,
11147     0,
11148     10,
11149     3
11150   },
11151   {
11152     "movsf_internal1",
11153     (const PTR) output_182,
11154     (insn_gen_fn) gen_movsf_internal1,
11155     &operand_data[381],
11156     2,
11157     0,
11158     13,
11159     3
11160   },
11161   {
11162     "movsf_internal2",
11163     (const PTR) output_183,
11164     (insn_gen_fn) gen_movsf_internal2,
11165     &operand_data[383],
11166     2,
11167     0,
11168     5,
11169     3
11170   },
11171   {
11172     "*mips.md:6390",
11173     (const PTR) output_184,
11174     0,
11175     &operand_data[385],
11176     2,
11177     0,
11178     7,
11179     3
11180   },
11181   {
11182     "movdf_internal1",
11183     (const PTR) output_185,
11184     (insn_gen_fn) gen_movdf_internal1,
11185     &operand_data[387],
11186     2,
11187     0,
11188     13,
11189     3
11190   },
11191   {
11192     "movdf_internal1a",
11193     (const PTR) output_186,
11194     (insn_gen_fn) gen_movdf_internal1a,
11195     &operand_data[389],
11196     2,
11197     0,
11198     11,
11199     3
11200   },
11201   {
11202     "movdf_internal2",
11203     (const PTR) output_187,
11204     (insn_gen_fn) gen_movdf_internal2,
11205     &operand_data[391],
11206     2,
11207     0,
11208     8,
11209     3
11210   },
11211   {
11212     "*mips.md:6451",
11213     (const PTR) output_188,
11214     0,
11215     &operand_data[393],
11216     2,
11217     0,
11218     7,
11219     3
11220   },
11221   {
11222     "loadgp",
11223     "%[lui\t$1,%%hi(%%neg(%%gp_rel(%a0)))\n\taddiu\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\n\tdaddu\t$gp,$1,%1%]",
11224     (insn_gen_fn) gen_loadgp,
11225     &operand_data[395],
11226     2,
11227     0,
11228     0,
11229     1
11230   },
11231   {
11232     "movstrsi_internal",
11233     (const PTR) output_190,
11234     (insn_gen_fn) gen_movstrsi_internal,
11235     &operand_data[397],
11236     8,
11237     0,
11238     1,
11239     3
11240   },
11241   {
11242     "*mips.md:6532",
11243     (const PTR) output_191,
11244     0,
11245     &operand_data[397],
11246     8,
11247     0,
11248     1,
11249     3
11250   },
11251   {
11252     "movstrsi_internal2",
11253     (const PTR) output_192,
11254     (insn_gen_fn) gen_movstrsi_internal2,
11255     &operand_data[397],
11256     8,
11257     0,
11258     1,
11259     3
11260   },
11261   {
11262     "*mips.md:6613",
11263     (const PTR) output_193,
11264     0,
11265     &operand_data[397],
11266     8,
11267     0,
11268     1,
11269     3
11270   },
11271   {
11272     "movstrsi_internal3",
11273     (const PTR) output_194,
11274     (insn_gen_fn) gen_movstrsi_internal3,
11275     &operand_data[405],
11276     8,
11277     0,
11278     1,
11279     3
11280   },
11281   {
11282     "ashlsi3_internal1",
11283     (const PTR) output_195,
11284     (insn_gen_fn) gen_ashlsi3_internal1,
11285     &operand_data[413],
11286     3,
11287     0,
11288     1,
11289     3
11290   },
11291   {
11292     "ashlsi3_internal2",
11293     (const PTR) output_196,
11294     (insn_gen_fn) gen_ashlsi3_internal2,
11295     &operand_data[416],
11296     3,
11297     0,
11298     2,
11299     3
11300   },
11301   {
11302     "ashldi3_internal",