00001 /* Definitions for opcode table for the sparc. 00002 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, 00003 2003 Free Software Foundation, Inc. 00004 00005 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and 00006 the GNU Binutils. 00007 00008 GAS/GDB is free software; you can redistribute it and/or modify 00009 it under the terms of the GNU General Public License as published by 00010 the Free Software Foundation; either version 2, or (at your option) 00011 any later version. 00012 00013 GAS/GDB is distributed in the hope that it will be useful, 00014 but WITHOUT ANY WARRANTY; without even the implied warranty of 00015 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00016 GNU General Public License for more details. 00017 00018 You should have received a copy of the GNU General Public License 00019 along with GAS or GDB; see the file COPYING. If not, write to 00020 the Free Software Foundation, 59 Temple Place - Suite 330, 00021 Boston, MA 02111-1307, USA. */ 00022 00023 #include "ansidecl.h" 00024 00025 /* The SPARC opcode table (and other related data) is defined in 00026 the opcodes library in sparc-opc.c. If you change anything here, make 00027 sure you fix up that file, and vice versa. */ 00028 00029 /* FIXME-someday: perhaps the ,a's and such should be embedded in the 00030 instruction's name rather than the args. This would make gas faster, pinsn 00031 slower, but would mess up some macros a bit. xoxorich. */ 00032 00033 /* List of instruction sets variations. 00034 These values are such that each element is either a superset of a 00035 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P 00036 returns non-zero. 00037 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. 00038 Don't change this without updating sparc-opc.c. */ 00039 00040 enum sparc_opcode_arch_val { 00041 SPARC_OPCODE_ARCH_V6 = 0, 00042 SPARC_OPCODE_ARCH_V7, 00043 SPARC_OPCODE_ARCH_V8, 00044 SPARC_OPCODE_ARCH_SPARCLET, 00045 SPARC_OPCODE_ARCH_SPARCLITE, 00046 /* v9 variants must appear last */ 00047 SPARC_OPCODE_ARCH_V9, 00048 SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ 00049 SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */ 00050 SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ 00051 }; 00052 00053 /* The highest architecture in the table. */ 00054 #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) 00055 00056 /* Given an enum sparc_opcode_arch_val, return the bitmask to use in 00057 insn encoding/decoding. */ 00058 #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) 00059 00060 /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ 00061 #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) 00062 00063 /* Table of cpu variants. */ 00064 00065 struct sparc_opcode_arch { 00066 const char *name; 00067 /* Mask of sparc_opcode_arch_val's supported. 00068 EG: For v7 this would be 00069 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). 00070 These are short's because sparc_opcode.architecture is. */ 00071 short supported; 00072 }; 00073 00074 extern const struct sparc_opcode_arch sparc_opcode_archs[]; 00075 00076 /* Given architecture name, look up it's sparc_opcode_arch_val value. */ 00077 extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); 00078 00079 /* Return the bitmask of supported architectures for ARCH. */ 00080 #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) 00081 00082 /* Non-zero if ARCH1 conflicts with ARCH2. 00083 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ 00084 #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ 00085 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 00086 != SPARC_OPCODE_SUPPORTED (ARCH1)) \ 00087 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ 00088 != SPARC_OPCODE_SUPPORTED (ARCH2))) 00089 00090 /* Structure of an opcode table entry. */ 00091 00092 struct sparc_opcode { 00093 const char *name; 00094 unsigned long match; /* Bits that must be set. */ 00095 unsigned long lose; /* Bits that must not be set. */ 00096 const char *args; 00097 /* This was called "delayed" in versions before the flags. */ 00098 char flags; 00099 short architecture; /* Bitmask of sparc_opcode_arch_val's. */ 00100 }; 00101 00102 #define F_DELAYED 1 /* Delayed branch */ 00103 #define F_ALIAS 2 /* Alias for a "real" instruction */ 00104 #define F_UNBR 4 /* Unconditional branch */ 00105 #define F_CONDBR 8 /* Conditional branch */ 00106 #define F_JSR 16 /* Subroutine call */ 00107 #define F_FLOAT 32 /* Floating point instruction (not a branch) */ 00108 #define F_FBR 64 /* Floating point branch */ 00109 /* FIXME: Add F_ANACHRONISTIC flag for v9. */ 00110 00111 /* 00112 00113 All sparc opcodes are 32 bits, except for the `set' instruction (really a 00114 macro), which is 64 bits. It is handled as a special case. 00115 00116 The match component is a mask saying which bits must match a particular 00117 opcode in order for an instruction to be an instance of that opcode. 00118 00119 The args component is a string containing one character for each operand of the 00120 instruction. 00121 00122 Kinds of operands: 00123 # Number used by optimizer. It is ignored. 00124 1 rs1 register. 00125 2 rs2 register. 00126 d rd register. 00127 e frs1 floating point register. 00128 v frs1 floating point register (double/even). 00129 V frs1 floating point register (quad/multiple of 4). 00130 f frs2 floating point register. 00131 B frs2 floating point register (double/even). 00132 R frs2 floating point register (quad/multiple of 4). 00133 g frsd floating point register. 00134 H frsd floating point register (double/even). 00135 J frsd floating point register (quad/multiple of 4). 00136 b crs1 coprocessor register 00137 c crs2 coprocessor register 00138 D crsd coprocessor register 00139 m alternate space register (asr) in rd 00140 M alternate space register (asr) in rs1 00141 h 22 high bits. 00142 X 5 bit unsigned immediate 00143 Y 6 bit unsigned immediate 00144 3 SIAM mode (3 bits). (v9b) 00145 K MEMBAR mask (7 bits). (v9) 00146 j 10 bit Immediate. (v9) 00147 I 11 bit Immediate. (v9) 00148 i 13 bit Immediate. 00149 n 22 bit immediate. 00150 k 2+14 bit PC relative immediate. (v9) 00151 G 19 bit PC relative immediate. (v9) 00152 l 22 bit PC relative immediate. 00153 L 30 bit PC relative immediate. 00154 a Annul. The annul bit is set. 00155 A Alternate address space. Stored as 8 bits. 00156 C Coprocessor state register. 00157 F floating point state register. 00158 p Processor state register. 00159 N Branch predict clear ",pn" (v9) 00160 T Branch predict set ",pt" (v9) 00161 z %icc. (v9) 00162 Z %xcc. (v9) 00163 q Floating point queue. 00164 r Single register that is both rs1 and rd. 00165 O Single register that is both rs2 and rd. 00166 Q Coprocessor queue. 00167 S Special case. 00168 t Trap base register. 00169 w Window invalid mask register. 00170 y Y register. 00171 u sparclet coprocessor registers in rd position 00172 U sparclet coprocessor registers in rs1 position 00173 E %ccr. (v9) 00174 s %fprs. (v9) 00175 P %pc. (v9) 00176 W %tick. (v9) 00177 o %asi. (v9) 00178 6 %fcc0. (v9) 00179 7 %fcc1. (v9) 00180 8 %fcc2. (v9) 00181 9 %fcc3. (v9) 00182 ! Privileged Register in rd (v9) 00183 ? Privileged Register in rs1 (v9) 00184 * Prefetch function constant. (v9) 00185 x OPF field (v9 impdep). 00186 0 32/64 bit immediate for set or setx (v9) insns 00187 _ Ancillary state register in rd (v9a) 00188 / Ancillary state register in rs1 (v9a) 00189 00190 The following chars are unused: (note: ,[] are used as punctuation) 00191 [45] 00192 00193 */ 00194 00195 #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ 00196 #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ 00197 #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ 00198 #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ 00199 #define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ 00200 #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ 00201 #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ 00202 #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ 00203 #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ 00204 #define F1(x) (OP(x)) 00205 #define DISP30(x) ((x)&0x3fffffff) 00206 #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ 00207 #define RS2(x) ((x)&0x1f) /* rs2 field */ 00208 #define SIMM13(x) ((x)&0x1fff) /* simm13 field */ 00209 #define RD(x) (((x)&0x1f) << 25) /* destination register field */ 00210 #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ 00211 #define ASI_RS2(x) (SIMM13(x)) 00212 #define MEMBAR(x) ((x)&0x7f) 00213 #define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ 00214 00215 #define ANNUL (1<<29) 00216 #define BPRED (1<<19) /* v9 */ 00217 #define IMMED F3I(1) 00218 #define RD_G0 RD(~0) 00219 #define RS1_G0 RS1(~0) 00220 #define RS2_G0 RS2(~0) 00221 00222 extern const struct sparc_opcode sparc_opcodes[]; 00223 extern const int sparc_num_opcodes; 00224 00225 extern int sparc_encode_asi (const char *); 00226 extern const char *sparc_decode_asi (int); 00227 extern int sparc_encode_membar (const char *); 00228 extern const char *sparc_decode_membar (int); 00229 extern int sparc_encode_prefetch (const char *); 00230 extern const char *sparc_decode_prefetch (int); 00231 extern int sparc_encode_sparclet_cpreg (const char *); 00232 extern const char *sparc_decode_sparclet_cpreg (int); 00233 00234 /* 00235 * Local Variables: 00236 * fill-column: 131 00237 * comment-column: 0 00238 * End: 00239 */ 00240 00241 /* end of sparc.h */
1.5.6