Open64: osprey/kg++fe/gnu/longlong.h Source File

00001 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
00002    Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
00003    Free Software Foundation, Inc.
00004 
00005    This definition file is free software; you can redistribute it
00006    and/or modify it under the terms of the GNU General Public
00007    License as published by the Free Software Foundation; either
00008    version 2, or (at your option) any later version.
00009 
00010    This definition file is distributed in the hope that it will be
00011    useful, but WITHOUT ANY WARRANTY; without even the implied
00012    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
00013    See the GNU General Public License for more details.
00014 
00015    You should have received a copy of the GNU General Public License
00016    along with this program; if not, write to the Free Software
00017    Foundation, Inc., 59 Temple Place - Suite 330,
00018    Boston, MA 02111-1307, USA.  */
00019 
00020 /* You have to define the following before including this file:
00021 
00022    UWtype -- An unsigned type, default type for operations (typically a "word")
00023    UHWtype -- An unsigned type, at least half the size of UWtype.
00024    UDWtype -- An unsigned type, at least twice as large a UWtype
00025    W_TYPE_SIZE -- size in bits of UWtype
00026 
00027    UQItype -- Unsigned 8 bit type.
00028    SItype, USItype -- Signed and unsigned 32 bit types.
00029    DItype, UDItype -- Signed and unsigned 64 bit types.
00030 
00031    On a 32 bit machine UWtype should typically be USItype;
00032    on a 64 bit machine, UWtype should typically be UDItype.
00033 */
00034 
00035 #define __BITS4 (W_TYPE_SIZE / 4)
00036 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
00037 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
00038 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
00039 
00040 #ifndef W_TYPE_SIZE
00041 #define W_TYPE_SIZE 32
00042 #define UWtype    USItype
00043 #define UHWtype   USItype
00044 #define UDWtype   UDItype
00045 #endif
00046 
00047 /* Define auxiliary asm macros.
00048 
00049    1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
00050    UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
00051    word product in HIGH_PROD and LOW_PROD.
00052 
00053    2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
00054    UDWtype product.  This is just a variant of umul_ppmm.
00055 
00056    3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
00057    denominator) divides a UDWtype, composed by the UWtype integers
00058    HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
00059    in QUOTIENT and the remainder in REMAINDER.  HIGH_NUMERATOR must be less
00060    than DENOMINATOR for correct operation.  If, in addition, the most
00061    significant bit of DENOMINATOR must be 1, then the pre-processor symbol
00062    UDIV_NEEDS_NORMALIZATION is defined to 1.
00063 
00064    4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
00065    denominator).  Like udiv_qrnnd but the numbers are signed.  The quotient
00066    is rounded towards 0.
00067 
00068    5) count_leading_zeros(count, x) counts the number of zero-bits from the
00069    msb to the first nonzero bit in the UWtype X.  This is the number of
00070    steps X needs to be shifted left to set the msb.  Undefined for X == 0,
00071    unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
00072 
00073    6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
00074    from the least significant end.
00075 
00076    7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
00077    high_addend_2, low_addend_2) adds two UWtype integers, composed by
00078    HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
00079    respectively.  The result is placed in HIGH_SUM and LOW_SUM.  Overflow
00080    (i.e. carry out) is not stored anywhere, and is lost.
00081 
00082    8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
00083    high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
00084    composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
00085    LOW_SUBTRAHEND_2 respectively.  The result is placed in HIGH_DIFFERENCE
00086    and LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
00087    and is lost.
00088 
00089    If any of these macros are left undefined for a particular CPU,
00090    C macros are used.  */
00091 
00092 /* The CPUs come in alphabetical order below.
00093 
00094    Please add support for more CPUs here, or improve the current support
00095    for the CPUs below!
00096    (E.g. WE32100, IBM360.)  */
00097 
00098 #if defined (__GNUC__) && !defined (NO_ASM)
00099 
00100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
00101    understood by gcc1.  Use cpp to avoid major code duplication.  */
00102 #if __GNUC__ < 2
00103 #define __CLOBBER_CC
00104 #define __AND_CLOBBER_CC
00105 #else /* __GNUC__ >= 2 */
00106 #define __CLOBBER_CC : "cc"
00107 #define __AND_CLOBBER_CC , "cc"
00108 #endif /* __GNUC__ < 2 */
00109 
00110 #if defined (__alpha) && W_TYPE_SIZE == 64
00111 #define umul_ppmm(ph, pl, m0, m1) \
00112   do {                  \
00113     UDItype __m0 = (m0), __m1 = (m1);         \
00114     __asm__ ("umulh %r1,%2,%0"            \
00115        : "=r" ((UDItype) ph)          \
00116        : "%rJ" (__m0),            \
00117          "rI" (__m1));            \
00118     (pl) = __m0 * __m1;             \
00119   } while (0)
00120 #define UMUL_TIME 46
00121 #ifndef LONGLONG_STANDALONE
00122 #define udiv_qrnnd(q, r, n1, n0, d) \
00123   do { UDItype __r;             \
00124     (q) = __udiv_qrnnd (&__r, (n1), (n0), (d));       \
00125     (r) = __r;                \
00126   } while (0)
00127 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
00128 #define UDIV_TIME 220
00129 #endif /* LONGLONG_STANDALONE */
00130 #ifdef __alpha_cix__
00131 #define count_leading_zeros(COUNT,X) \
00132   __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
00133 #define count_trailing_zeros(COUNT,X) \
00134   __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
00135 #define COUNT_LEADING_ZEROS_0 64
00136 #else
00137 extern const UQItype __clz_tab[];
00138 #define count_leading_zeros(COUNT,X) \
00139   do {                  \
00140     UDItype __xr = (X), __t, __a;         \
00141     __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr));    \
00142     __a = __clz_tab[__t ^ 0xff] - 1;          \
00143     __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a));  \
00144     (COUNT) = 64 - (__clz_tab[__t] + __a*8);        \
00145   } while (0)
00146 #define count_trailing_zeros(COUNT,X) \
00147   do {                  \
00148     UDItype __xr = (X), __t, __a;         \
00149     __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr));    \
00150     __t = ~__t & -~__t;             \
00151     __a = ((__t & 0xCC) != 0) * 2;          \
00152     __a += ((__t & 0xF0) != 0) * 4;         \
00153     __a += ((__t & 0xAA) != 0);           \
00154     __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a));  \
00155     __a <<= 3;                \
00156     __t &= -__t;              \
00157     __a += ((__t & 0xCC) != 0) * 2;         \
00158     __a += ((__t & 0xF0) != 0) * 4;         \
00159     __a += ((__t & 0xAA) != 0);           \
00160     (COUNT) = __a;              \
00161   } while (0)
00162 #endif /* __alpha_cix__ */
00163 #endif /* __alpha */
00164 
00165 #if defined (__arc__) && W_TYPE_SIZE == 32
00166 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00167   __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3"   \
00168      : "=r" ((USItype) (sh)),         \
00169        "=&r" ((USItype) (sl))         \
00170      : "%r" ((USItype) (ah)),         \
00171        "rIJ" ((USItype) (bh)),          \
00172        "%r" ((USItype) (al)),         \
00173        "rIJ" ((USItype) (bl)))
00174 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00175   __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3"   \
00176      : "=r" ((USItype) (sh)),         \
00177        "=&r" ((USItype) (sl))         \
00178      : "r" ((USItype) (ah)),          \
00179        "rIJ" ((USItype) (bh)),          \
00180        "r" ((USItype) (al)),          \
00181        "rIJ" ((USItype) (bl)))
00182 /* Call libgcc routine.  */
00183 #define umul_ppmm(w1, w0, u, v) \
00184 do {                  \
00185   DWunion __w;                \
00186   __w.ll = __umulsidi3 (u, v);            \
00187   w1 = __w.s.high;              \
00188   w0 = __w.s.low;             \
00189 } while (0)
00190 #define __umulsidi3 __umulsidi3
00191 UDItype __umulsidi3 (USItype, USItype);
00192 #endif
00193 
00194 #if defined (__arm__) && W_TYPE_SIZE == 32
00195 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00196   __asm__ ("adds  %1, %4, %5\n\tadc %0, %2, %3"   \
00197      : "=r" ((USItype) (sh)),         \
00198        "=&r" ((USItype) (sl))         \
00199      : "%r" ((USItype) (ah)),         \
00200        "rI" ((USItype) (bh)),         \
00201        "%r" ((USItype) (al)),         \
00202        "rI" ((USItype) (bl)))
00203 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00204   __asm__ ("subs  %1, %4, %5\n\tsbc %0, %2, %3"   \
00205      : "=r" ((USItype) (sh)),         \
00206        "=&r" ((USItype) (sl))         \
00207      : "r" ((USItype) (ah)),          \
00208        "rI" ((USItype) (bh)),         \
00209        "r" ((USItype) (al)),          \
00210        "rI" ((USItype) (bl)))
00211 #define umul_ppmm(xh, xl, a, b) \
00212 {register USItype __t0, __t1, __t2;         \
00213   __asm__ ("%@ Inlined umul_ppmm\n"         \
00214      "  mov %2, %5, lsr #16\n"        \
00215      "  mov %0, %6, lsr #16\n"        \
00216      "  bic %3, %5, %2, lsl #16\n"        \
00217      "  bic %4, %6, %0, lsl #16\n"        \
00218      "  mul %1, %3, %4\n"         \
00219      "  mul %4, %2, %4\n"         \
00220      "  mul %3, %0, %3\n"         \
00221      "  mul %0, %2, %0\n"         \
00222      "  adds  %3, %4, %3\n"         \
00223      "  addcs %0, %0, #65536\n"       \
00224      "  adds  %1, %1, %3, lsl #16\n"        \
00225      "  adc %0, %0, %3, lsr #16"        \
00226      : "=&r" ((USItype) (xh)),          \
00227        "=r" ((USItype) (xl)),         \
00228        "=&r" (__t0), "=&r" (__t1), "=r" (__t2)      \
00229      : "r" ((USItype) (a)),         \
00230        "r" ((USItype) (b)));}
00231 #define UMUL_TIME 20
00232 #define UDIV_TIME 100
00233 #endif /* __arm__ */
00234 
00235 #if defined (__hppa) && W_TYPE_SIZE == 32
00236 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00237   __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"        \
00238      : "=r" ((USItype) (sh)),         \
00239        "=&r" ((USItype) (sl))         \
00240      : "%rM" ((USItype) (ah)),          \
00241        "rM" ((USItype) (bh)),         \
00242        "%rM" ((USItype) (al)),          \
00243        "rM" ((USItype) (bl)))
00244 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00245   __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"        \
00246      : "=r" ((USItype) (sh)),         \
00247        "=&r" ((USItype) (sl))         \
00248      : "rM" ((USItype) (ah)),         \
00249        "rM" ((USItype) (bh)),         \
00250        "rM" ((USItype) (al)),         \
00251        "rM" ((USItype) (bl)))
00252 #if defined (_PA_RISC1_1)
00253 #define umul_ppmm(w1, w0, u, v) \
00254   do {                  \
00255     union               \
00256       {                 \
00257   UDItype __f;              \
00258   struct {USItype __w1, __w0;} __w1w0;        \
00259       } __t;                \
00260     __asm__ ("xmpyu %1,%2,%0"           \
00261        : "=x" (__t.__f)           \
00262        : "x" ((USItype) (u)),         \
00263          "x" ((USItype) (v)));          \
00264     (w1) = __t.__w1w0.__w1;           \
00265     (w0) = __t.__w1w0.__w0;           \
00266      } while (0)
00267 #define UMUL_TIME 8
00268 #else
00269 #define UMUL_TIME 30
00270 #endif
00271 #define UDIV_TIME 40
00272 #define count_leading_zeros(count, x) \
00273   do {                  \
00274     USItype __tmp;              \
00275     __asm__ (               \
00276        "ldi   1,%0\n"           \
00277 " extru,=   %1,15,16,%%r0   ; Bits 31..16 zero?\n"  \
00278 " extru,tr  %1,15,16,%1   ; No.  Shift down, skip add.\n"\
00279 " ldo   16(%0),%0   ; Yes.  Perform add.\n" \
00280 " extru,=   %1,23,8,%%r0    ; Bits 15..8 zero?\n" \
00281 " extru,tr  %1,23,8,%1    ; No.  Shift down, skip add.\n"\
00282 " ldo   8(%0),%0    ; Yes.  Perform add.\n" \
00283 " extru,=   %1,27,4,%%r0    ; Bits 7..4 zero?\n"  \
00284 " extru,tr  %1,27,4,%1    ; No.  Shift down, skip add.\n"\
00285 " ldo   4(%0),%0    ; Yes.  Perform add.\n" \
00286 " extru,=   %1,29,2,%%r0    ; Bits 3..2 zero?\n"  \
00287 " extru,tr  %1,29,2,%1    ; No.  Shift down, skip add.\n"\
00288 " ldo   2(%0),%0    ; Yes.  Perform add.\n" \
00289 " extru   %1,30,1,%1    ; Extract bit 1.\n" \
00290 " sub   %0,%1,%0    ; Subtract it.\n" \
00291   : "=r" (count), "=r" (__tmp) : "1" (x));      \
00292   } while (0)
00293 #endif
00294 
00295 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
00296 #define smul_ppmm(xh, xl, m0, m1) \
00297   do {                  \
00298     union {DItype __ll;             \
00299      struct {USItype __h, __l;} __i;        \
00300     } __x;              \
00301     __asm__ ("lr %N0,%1\n\tmr %0,%2"          \
00302        : "=&r" (__x.__ll)           \
00303        : "r" (m0), "r" (m1));         \
00304     (xh) = __x.__i.__h; (xl) = __x.__i.__l;       \
00305   } while (0)
00306 #define sdiv_qrnnd(q, r, n1, n0, d) \
00307   do {                  \
00308     union {DItype __ll;             \
00309      struct {USItype __h, __l;} __i;        \
00310     } __x;              \
00311     __x.__i.__h = n1; __x.__i.__l = n0;         \
00312     __asm__ ("dr %0,%2"             \
00313        : "=r" (__x.__ll)            \
00314        : "0" (__x.__ll), "r" (d));        \
00315     (q) = __x.__i.__l; (r) = __x.__i.__h;       \
00316   } while (0)
00317 #endif
00318 
00319 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
00320 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00321   __asm__ ("addl %5,%1\n\tadcl %3,%0"         \
00322      : "=r" ((USItype) (sh)),         \
00323        "=&r" ((USItype) (sl))         \
00324      : "%0" ((USItype) (ah)),         \
00325        "g" ((USItype) (bh)),          \
00326        "%1" ((USItype) (al)),         \
00327        "g" ((USItype) (bl)))
00328 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00329   __asm__ ("subl %5,%1\n\tsbbl %3,%0"         \
00330      : "=r" ((USItype) (sh)),         \
00331        "=&r" ((USItype) (sl))         \
00332      : "0" ((USItype) (ah)),          \
00333        "g" ((USItype) (bh)),          \
00334        "1" ((USItype) (al)),          \
00335        "g" ((USItype) (bl)))
00336 #define umul_ppmm(w1, w0, u, v) \
00337   __asm__ ("mull %3"              \
00338      : "=a" ((USItype) (w0)),         \
00339        "=d" ((USItype) (w1))          \
00340      : "%0" ((USItype) (u)),          \
00341        "rm" ((USItype) (v)))
00342 #define udiv_qrnnd(q, r, n1, n0, dv) \
00343   __asm__ ("divl %4"              \
00344      : "=a" ((USItype) (q)),          \
00345        "=d" ((USItype) (r))         \
00346      : "0" ((USItype) (n0)),          \
00347        "1" ((USItype) (n1)),          \
00348        "rm" ((USItype) (dv)))
00349 #define count_leading_zeros(count, x) \
00350   do {                  \
00351     USItype __cbtmp;              \
00352     __asm__ ("bsrl %1,%0"           \
00353        : "=r" (__cbtmp) : "rm" ((USItype) (x)));      \
00354     (count) = __cbtmp ^ 31;           \
00355   } while (0)
00356 #define count_trailing_zeros(count, x) \
00357   __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
00358 #define UMUL_TIME 40
00359 #define UDIV_TIME 40
00360 #endif /* 80x86 */
00361 
00362 #if defined (__i960__) && W_TYPE_SIZE == 32
00363 #define umul_ppmm(w1, w0, u, v) \
00364   ({union {UDItype __ll;            \
00365      struct {USItype __l, __h;} __i;        \
00366     } __xx;             \
00367   __asm__ ("emul  %2,%1,%0"         \
00368      : "=d" (__xx.__ll)           \
00369      : "%dI" ((USItype) (u)),         \
00370        "dI" ((USItype) (v)));         \
00371   (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
00372 #define __umulsidi3(u, v) \
00373   ({UDItype __w;              \
00374     __asm__ ("emul  %2,%1,%0"         \
00375        : "=d" (__w)           \
00376        : "%dI" ((USItype) (u)),         \
00377          "dI" ((USItype) (v)));         \
00378     __w; })
00379 #endif /* __i960__ */
00380 
00381 #if defined (__M32R__) && W_TYPE_SIZE == 32
00382 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00383   /* The cmp clears the condition bit.  */ \
00384   __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0"      \
00385      : "=r" ((USItype) (sh)),         \
00386        "=&r" ((USItype) (sl))         \
00387      : "%0" ((USItype) (ah)),         \
00388        "r" ((USItype) (bh)),          \
00389        "%1" ((USItype) (al)),         \
00390        "r" ((USItype) (bl))         \
00391      : "cbit")
00392 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00393   /* The cmp clears the condition bit.  */ \
00394   __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0"      \
00395      : "=r" ((USItype) (sh)),         \
00396        "=&r" ((USItype) (sl))         \
00397      : "0" ((USItype) (ah)),          \
00398        "r" ((USItype) (bh)),          \
00399        "1" ((USItype) (al)),          \
00400        "r" ((USItype) (bl))         \
00401      : "cbit")
00402 #endif /* __M32R__ */
00403 
00404 #if defined (__mc68000__) && W_TYPE_SIZE == 32
00405 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00406   __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"        \
00407      : "=d" ((USItype) (sh)),         \
00408        "=&d" ((USItype) (sl))         \
00409      : "%0" ((USItype) (ah)),         \
00410        "d" ((USItype) (bh)),          \
00411        "%1" ((USItype) (al)),         \
00412        "g" ((USItype) (bl)))
00413 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00414   __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"        \
00415      : "=d" ((USItype) (sh)),         \
00416        "=&d" ((USItype) (sl))         \
00417      : "0" ((USItype) (ah)),          \
00418        "d" ((USItype) (bh)),          \
00419        "1" ((USItype) (al)),          \
00420        "g" ((USItype) (bl)))
00421 
00422 /* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r.  */
00423 #if defined (__mc68020__) || defined(mc68020) \
00424   || defined(__mc68030__) || defined(mc68030) \
00425   || defined(__mc68040__) || defined(mc68040) \
00426   || defined(__mcpu32__) || defined(mcpu32)
00427 #define umul_ppmm(w1, w0, u, v) \
00428   __asm__ ("mulu%.l %3,%1:%0"           \
00429      : "=d" ((USItype) (w0)),         \
00430        "=d" ((USItype) (w1))          \
00431      : "%0" ((USItype) (u)),          \
00432        "dmi" ((USItype) (v)))
00433 #define UMUL_TIME 45
00434 #define udiv_qrnnd(q, r, n1, n0, d) \
00435   __asm__ ("divu%.l %4,%1:%0"           \
00436      : "=d" ((USItype) (q)),          \
00437        "=d" ((USItype) (r))         \
00438      : "0" ((USItype) (n0)),          \
00439        "1" ((USItype) (n1)),          \
00440        "dmi" ((USItype) (d)))
00441 #define UDIV_TIME 90
00442 #define sdiv_qrnnd(q, r, n1, n0, d) \
00443   __asm__ ("divs%.l %4,%1:%0"           \
00444      : "=d" ((USItype) (q)),          \
00445        "=d" ((USItype) (r))         \
00446      : "0" ((USItype) (n0)),          \
00447        "1" ((USItype) (n1)),          \
00448        "dmi" ((USItype) (d)))
00449 
00450 #else /* not mc68020 */
00451 #if !defined(__mcf5200__)
00452 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX.  */
00453 #define umul_ppmm(xh, xl, a, b) \
00454   __asm__ ("| Inlined umul_ppmm\n"          \
00455      "  move%.l %2,%/d0\n"          \
00456      "  move%.l %3,%/d1\n"          \
00457      "  move%.l %/d0,%/d2\n"          \
00458      "  swap  %/d0\n"           \
00459      "  move%.l %/d1,%/d3\n"          \
00460      "  swap  %/d1\n"           \
00461      "  move%.w %/d2,%/d4\n"          \
00462      "  mulu  %/d3,%/d4\n"          \
00463      "  mulu  %/d1,%/d2\n"          \
00464      "  mulu  %/d0,%/d3\n"          \
00465      "  mulu  %/d0,%/d1\n"          \
00466      "  move%.l %/d4,%/d0\n"          \
00467      "  eor%.w  %/d0,%/d0\n"          \
00468      "  swap  %/d0\n"           \
00469      "  add%.l  %/d0,%/d2\n"          \
00470      "  add%.l  %/d3,%/d2\n"          \
00471      "  jcc 1f\n"           \
00472      "  add%.l  %#65536,%/d1\n"         \
00473      "1:  swap  %/d2\n"           \
00474      "  moveq %#0,%/d0\n"         \
00475      "  move%.w %/d2,%/d0\n"          \
00476      "  move%.w %/d4,%/d2\n"          \
00477      "  move%.l %/d2,%1\n"          \
00478      "  add%.l  %/d1,%/d0\n"          \
00479      "  move%.l %/d0,%0"          \
00480      : "=g" ((USItype) (xh)),         \
00481        "=g" ((USItype) (xl))          \
00482      : "g" ((USItype) (a)),         \
00483        "g" ((USItype) (b))          \
00484      : "d0", "d1", "d2", "d3", "d4")
00485 #define UMUL_TIME 100
00486 #define UDIV_TIME 400
00487 #endif /* not mcf5200 */
00488 #endif /* not mc68020 */
00489 
00490 /* The '020, '030, '040 and '060 have bitfield insns.  */
00491 #if defined (__mc68020__) || defined(mc68020) \
00492   || defined(__mc68030__) || defined(mc68030) \
00493   || defined(__mc68040__) || defined(mc68040) \
00494   || defined(__mc68060__) || defined(mc68060)
00495 #define count_leading_zeros(count, x) \
00496   __asm__ ("bfffo %1{%b2:%b2},%0"         \
00497      : "=d" ((USItype) (count))         \
00498      : "od" ((USItype) (x)), "n" (0))
00499 #endif
00500 #endif /* mc68000 */
00501 
00502 #if defined (__m88000__) && W_TYPE_SIZE == 32
00503 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00504   __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"     \
00505      : "=r" ((USItype) (sh)),         \
00506        "=&r" ((USItype) (sl))         \
00507      : "%rJ" ((USItype) (ah)),          \
00508        "rJ" ((USItype) (bh)),         \
00509        "%rJ" ((USItype) (al)),          \
00510        "rJ" ((USItype) (bl)))
00511 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00512   __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"     \
00513      : "=r" ((USItype) (sh)),         \
00514        "=&r" ((USItype) (sl))         \
00515      : "rJ" ((USItype) (ah)),         \
00516        "rJ" ((USItype) (bh)),         \
00517        "rJ" ((USItype) (al)),         \
00518        "rJ" ((USItype) (bl)))
00519 #define count_leading_zeros(count, x) \
00520   do {                  \
00521     USItype __cbtmp;              \
00522     __asm__ ("ff1 %0,%1"            \
00523        : "=r" (__cbtmp)           \
00524        : "r" ((USItype) (x)));          \
00525     (count) = __cbtmp ^ 31;           \
00526   } while (0)
00527 #define COUNT_LEADING_ZEROS_0 63 /* sic */
00528 #if defined (__mc88110__)
00529 #define umul_ppmm(wh, wl, u, v) \
00530   do {                  \
00531     union {UDItype __ll;            \
00532      struct {USItype __h, __l;} __i;        \
00533     } __xx;             \
00534     __asm__ ("mulu.d  %0,%1,%2"         \
00535        : "=r" (__xx.__ll)           \
00536        : "r" ((USItype) (u)),         \
00537          "r" ((USItype) (v)));          \
00538     (wh) = __xx.__i.__h;            \
00539     (wl) = __xx.__i.__l;            \
00540   } while (0)
00541 #define udiv_qrnnd(q, r, n1, n0, d) \
00542   ({union {UDItype __ll;            \
00543      struct {USItype __h, __l;} __i;        \
00544     } __xx;             \
00545   USItype __q;                \
00546   __xx.__i.__h = (n1); __xx.__i.__l = (n0);       \
00547   __asm__ ("divu.d %0,%1,%2"            \
00548      : "=r" (__q)             \
00549      : "r" (__xx.__ll),           \
00550        "r" ((USItype) (d)));          \
00551   (r) = (n0) - __q * (d); (q) = __q; })
00552 #define UMUL_TIME 5
00553 #define UDIV_TIME 25
00554 #else
00555 #define UMUL_TIME 17
00556 #define UDIV_TIME 150
00557 #endif /* __mc88110__ */
00558 #endif /* __m88000__ */
00559 
00560 #if defined (__mips__) && W_TYPE_SIZE == 32
00561 #define umul_ppmm(w1, w0, u, v) \
00562   __asm__ ("multu %2,%3"            \
00563      : "=l" ((USItype) (w0)),         \
00564        "=h" ((USItype) (w1))          \
00565      : "d" ((USItype) (u)),         \
00566        "d" ((USItype) (v)))
00567 #define UMUL_TIME 10
00568 #define UDIV_TIME 100
00569 #endif /* __mips__ */
00570 
00571 #if defined (__ns32000__) && W_TYPE_SIZE == 32
00572 #define umul_ppmm(w1, w0, u, v) \
00573   ({union {UDItype __ll;            \
00574      struct {USItype __l, __h;} __i;        \
00575     } __xx;             \
00576   __asm__ ("meid %2,%0"             \
00577      : "=g" (__xx.__ll)           \
00578      : "%0" ((USItype) (u)),          \
00579        "g" ((USItype) (v)));          \
00580   (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
00581 #define __umulsidi3(u, v) \
00582   ({UDItype __w;              \
00583     __asm__ ("meid %2,%0"           \
00584        : "=g" (__w)           \
00585        : "%0" ((USItype) (u)),          \
00586          "g" ((USItype) (v)));          \
00587     __w; })
00588 #define udiv_qrnnd(q, r, n1, n0, d) \
00589   ({union {UDItype __ll;            \
00590      struct {USItype __l, __h;} __i;        \
00591     } __xx;             \
00592   __xx.__i.__h = (n1); __xx.__i.__l = (n0);       \
00593   __asm__ ("deid %2,%0"             \
00594      : "=g" (__xx.__ll)           \
00595      : "0" (__xx.__ll),           \
00596        "g" ((USItype) (d)));          \
00597   (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
00598 #define count_trailing_zeros(count,x) \
00599   do {                  \
00600     __asm__ ("ffsd     %2,%0"           \
00601             : "=r" ((USItype) (count))          \
00602             : "0" ((USItype) 0),          \
00603               "r" ((USItype) (x)));         \
00604   } while (0)
00605 #endif /* __ns32000__ */
00606 
00607 /* FIXME: We should test _IBMR2 here when we add assembly support for the
00608    system vendor compilers.
00609    FIXME: What's needed for gcc PowerPC VxWorks?  __vxworks__ is not good
00610    enough, since that hits ARM and m68k too.  */
00611 #if (defined (_ARCH_PPC)  /* AIX */       \
00612      || defined (_ARCH_PWR) /* AIX */       \
00613      || defined (_ARCH_COM) /* AIX */       \
00614      || defined (__powerpc__) /* gcc */       \
00615      || defined (__POWERPC__) /* BEOS */        \
00616      || defined (__ppc__) /* Darwin */        \
00617      || defined (PPC)   /* GNU/Linux, SysV */     \
00618      ) && W_TYPE_SIZE == 32
00619 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00620   do {                  \
00621     if (__builtin_constant_p (bh) && (bh) == 0)       \
00622       __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"   \
00623        : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
00624     else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)   \
00625       __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"   \
00626        : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
00627     else                \
00628       __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"    \
00629        : "=r" (sh), "=&r" (sl)          \
00630        : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));    \
00631   } while (0)
00632 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00633   do {                  \
00634     if (__builtin_constant_p (ah) && (ah) == 0)       \
00635       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
00636          : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
00637     else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0)   \
00638       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
00639          : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
00640     else if (__builtin_constant_p (bh) && (bh) == 0)      \
00641       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"   \
00642          : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
00643     else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)   \
00644       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"   \
00645          : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
00646     else                \
00647       __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"  \
00648          : "=r" (sh), "=&r" (sl)          \
00649          : "r" (ah), "r" (bh), "rI" (al), "r" (bl));    \
00650   } while (0)
00651 #define count_leading_zeros(count, x) \
00652   __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
00653 #define COUNT_LEADING_ZEROS_0 32
00654 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
00655   || defined (__ppc__) || defined (PPC) || defined (__vxworks__)
00656 #define umul_ppmm(ph, pl, m0, m1) \
00657   do {                  \
00658     USItype __m0 = (m0), __m1 = (m1);         \
00659     __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));  \
00660     (pl) = __m0 * __m1;             \
00661   } while (0)
00662 #define UMUL_TIME 15
00663 #define smul_ppmm(ph, pl, m0, m1) \
00664   do {                  \
00665     SItype __m0 = (m0), __m1 = (m1);          \
00666     __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
00667     (pl) = __m0 * __m1;             \
00668   } while (0)
00669 #define SMUL_TIME 14
00670 #define UDIV_TIME 120
00671 #elif defined (_ARCH_PWR)
00672 #define UMUL_TIME 8
00673 #define smul_ppmm(xh, xl, m0, m1) \
00674   __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
00675 #define SMUL_TIME 4
00676 #define sdiv_qrnnd(q, r, nh, nl, d) \
00677   __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
00678 #define UDIV_TIME 100
00679 #endif
00680 #endif /* 32-bit POWER architecture variants.  */
00681 
00682 /* We should test _IBMR2 here when we add assembly support for the system
00683    vendor compilers.  */
00684 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
00685 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00686   do {                  \
00687     if (__builtin_constant_p (bh) && (bh) == 0)       \
00688       __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"   \
00689        : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
00690     else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)   \
00691       __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"   \
00692        : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
00693     else                \
00694       __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"    \
00695        : "=r" (sh), "=&r" (sl)          \
00696        : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));    \
00697   } while (0)
00698 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00699   do {                  \
00700     if (__builtin_constant_p (ah) && (ah) == 0)       \
00701       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
00702          : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
00703     else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0)   \
00704       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
00705          : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
00706     else if (__builtin_constant_p (bh) && (bh) == 0)      \
00707       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"   \
00708          : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
00709     else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)   \
00710       __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"   \
00711          : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
00712     else                \
00713       __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"  \
00714          : "=r" (sh), "=&r" (sl)          \
00715          : "r" (ah), "r" (bh), "rI" (al), "r" (bl));    \
00716   } while (0)
00717 #define count_leading_zeros(count, x) \
00718   __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
00719 #define COUNT_LEADING_ZEROS_0 64
00720 #define umul_ppmm(ph, pl, m0, m1) \
00721   do {                  \
00722     UDItype __m0 = (m0), __m1 = (m1);         \
00723     __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));  \
00724     (pl) = __m0 * __m1;             \
00725   } while (0)
00726 #define UMUL_TIME 15
00727 #define smul_ppmm(ph, pl, m0, m1) \
00728   do {                  \
00729     DItype __m0 = (m0), __m1 = (m1);          \
00730     __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
00731     (pl) = __m0 * __m1;             \
00732   } while (0)
00733 #define SMUL_TIME 14  /* ??? */
00734 #define UDIV_TIME 120 /* ??? */
00735 #endif /* 64-bit PowerPC.  */
00736 
00737 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
00738 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00739   __asm__ ("a %1,%5\n\tae %0,%3"          \
00740      : "=r" ((USItype) (sh)),         \
00741        "=&r" ((USItype) (sl))         \
00742      : "%0" ((USItype) (ah)),         \
00743        "r" ((USItype) (bh)),          \
00744        "%1" ((USItype) (al)),         \
00745        "r" ((USItype) (bl)))
00746 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00747   __asm__ ("s %1,%5\n\tse %0,%3"          \
00748      : "=r" ((USItype) (sh)),         \
00749        "=&r" ((USItype) (sl))         \
00750      : "0" ((USItype) (ah)),          \
00751        "r" ((USItype) (bh)),          \
00752        "1" ((USItype) (al)),          \
00753        "r" ((USItype) (bl)))
00754 #define umul_ppmm(ph, pl, m0, m1) \
00755   do {                  \
00756     USItype __m0 = (m0), __m1 = (m1);         \
00757     __asm__ (               \
00758        "s r2,r2\n"            \
00759 " mts r10,%2\n"           \
00760 " m r2,%3\n"            \
00761 " m r2,%3\n"            \
00762 " m r2,%3\n"            \
00763 " m r2,%3\n"            \
00764 " m r2,%3\n"            \
00765 " m r2,%3\n"            \
00766 " m r2,%3\n"            \
00767 " m r2,%3\n"            \
00768 " m r2,%3\n"            \
00769 " m r2,%3\n"            \
00770 " m r2,%3\n"            \
00771 " m r2,%3\n"            \
00772 " m r2,%3\n"            \
00773 " m r2,%3\n"            \
00774 " m r2,%3\n"            \
00775 " m r2,%3\n"            \
00776 " cas %0,r2,r0\n"           \
00777 " mfs r10,%1"             \
00778        : "=r" ((USItype) (ph)),         \
00779          "=r" ((USItype) (pl))          \
00780        : "%r" (__m0),           \
00781     "r" (__m1)            \
00782        : "r2");             \
00783     (ph) += ((((SItype) __m0 >> 31) & __m1)       \
00784        + (((SItype) __m1 >> 31) & __m0));       \
00785   } while (0)
00786 #define UMUL_TIME 20
00787 #define UDIV_TIME 200
00788 #define count_leading_zeros(count, x) \
00789   do {                  \
00790     if ((x) >= 0x10000)             \
00791       __asm__ ("clz %0,%1"            \
00792          : "=r" ((USItype) (count))       \
00793          : "r" ((USItype) (x) >> 16));        \
00794     else                \
00795       {                 \
00796   __asm__ ("clz %0,%1"            \
00797      : "=r" ((USItype) (count))       \
00798      : "r" ((USItype) (x)));          \
00799   (count) += 16;              \
00800       }                 \
00801   } while (0)
00802 #endif
00803 
00804 #if defined (__sh2__) && W_TYPE_SIZE == 32
00805 #define umul_ppmm(w1, w0, u, v) \
00806   __asm__ (               \
00807        "dmulu.l %2,%3\n\tsts  macl,%1\n\tsts  mach,%0"    \
00808      : "=r" ((USItype)(w1)),          \
00809        "=r" ((USItype)(w0))         \
00810      : "r" ((USItype)(u)),          \
00811        "r" ((USItype)(v))           \
00812      : "macl", "mach")
00813 #define UMUL_TIME 5
00814 #endif
00815 
00816 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
00817 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
00818 #define count_leading_zeros(count, x) \
00819   do                  \
00820     {                 \
00821       UDItype x_ = (USItype)(x);          \
00822       SItype c_;              \
00823                   \
00824       __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_));      \
00825       (count) = c_ - 31;            \
00826     }                 \
00827   while (0)
00828 #define COUNT_LEADING_ZEROS_0 32
00829 #endif
00830 
00831 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
00832     && W_TYPE_SIZE == 32
00833 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
00834   __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"        \
00835      : "=r" ((USItype) (sh)),         \
00836        "=&r" ((USItype) (sl))         \
00837      : "%rJ" ((USItype) (ah)),          \
00838        "rI" ((USItype) (bh)),         \
00839        "%rJ" ((USItype) (al)),          \
00840        "rI" ((USItype) (bl))          \
00841      __CLOBBER_CC)
00842 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
00843   __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"        \
00844      : "=r" ((USItype) (sh)),         \
00845        "=&r" ((USItype) (sl))         \
00846      : "rJ" ((USItype) (ah)),         \
00847        "rI" ((USItype) (bh)),         \
00848        "rJ" ((USItype) (al)),         \
00849        "rI" ((USItype) (bl))          \
00850      __CLOBBER_CC)
00851 #if defined (__sparc_v8__)
00852 #define umul_ppmm(w1, w0, u, v) \
00853   __asm__ ("umul %2,%3,%1;rd %%y,%0"          \
00854      : "=r" ((USItype) (w1)),         \
00855        "=r" ((USItype) (w0))          \
00856      : "r" ((USItype) (u)),         \
00857        "r" ((USItype) (v)))
00858 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
00859   __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
00860      : "=&r" ((USItype) (__q)),         \
00861        "=&r" ((USItype) (__r))          \
00862      : "r" ((USItype) (__n1)),          \
00863        "r" ((USItype) (__n0)),          \
00864        "r" ((USItype) (__d)))
00865 #else
00866 #if defined (__sparclite__)
00867 /* This has hardware multiply but not divide.  It also has two additional
00868    instructions scan (ffs from high bit) and divscc.  */
00869 #define umul_ppmm(w1, w0, u, v) \
00870   __asm__ ("umul %2,%3,%1;rd %%y,%0"          \
00871      : "=r" ((USItype) (w1)),         \
00872        "=r" ((USItype) (w0))          \
00873      : "r" ((USItype) (u)),         \
00874        "r" ((USItype) (v)))
00875 #define udiv_qrnnd(q, r, n1, n0, d) \
00876   __asm__ ("! Inlined udiv_qrnnd\n"         \
00877 " wr  %%g0,%2,%%y ! Not a delayed write for sparclite\n"  \
00878 " tst %%g0\n"             \
00879 " divscc  %3,%4,%%g1\n"           \
00880 " divscc  %%g1,%4,%%g1\n"           \
00881 " divscc  %%g1,%4,%%g1\n"           \
00882 " divscc  %%g1,%4,%%g1\n"           \
00883 " divscc  %%g1,%4,%%g1\n"           \
00884 " divscc  %%g1,%4,%%g1\n"           \
00885 " divscc  %%g1,%4,%%g1\n"           \
00886 " divscc  %%g1,%4,%%g1\n"           \
00887 " divscc  %%g1,%4,%%g1\n"           \
00888 " divscc  %%g1,%4,%%g1\n"           \
00889 " divscc  %%g1,%4,%%g1\n"           \
00890 " divscc  %%g1,%4,%%g1\n"           \
00891 " divscc  %%g1,%4,%%g1\n"           \
00892 " divscc  %%g1,%4,%%g1\n"           \
00893 " divscc  %%g1,%4,%%g1\n"           \
00894 " divscc  %%g1,%4,%%g1\n"           \
00895 " divscc  %%g1,%4,%%g1\n"           \
00896 " divscc  %%g1,%4,%%g1\n"           \
00897 " divscc  %%g1,%4,%%g1\n"           \
00898 " divscc  %%g1,%4,%%g1\n"           \
00899 " divscc  %%g1,%4,%%g1\n"           \
00900 " divscc  %%g1,%4,%%g1\n"           \
00901 " divscc  %%g1,%4,%%g1\n"           \
00902 " divscc  %%g1,%4,%%g1\n"           \
00903 " divscc  %%g1,%4,%%g1\n"           \
00904 " divscc  %%g1,%4,%%g1\n"           \
00905 " divscc  %%g1,%4,%%g1\n"           \
00906 " divscc  %%g1,%4,%%g1\n"           \
00907 " divscc  %%g1,%4,%%g1\n"           \
00908 " divscc  %%g1,%4,%%g1\n"           \
00909 " divscc  %%g1,%4,%%g1\n"           \
00910 " divscc  %%g1,%4,%0\n"           \
00911 " rd  %%y,%1\n"           \
00912 " bl,a 1f\n"              \
00913 " add %1,%4,%1\n"           \
00914 "1: ! End of inline udiv_qrnnd"         \
00915      : "=r" ((USItype) (q)),          \
00916        "=r" ((USItype) (r))         \
00917      : "r" ((USItype) (n1)),          \
00918        "r" ((USItype) (n0)),          \
00919        "rI" ((USItype) (d))         \
00920      : "g1" __AND_CLOBBER_CC)
00921 #define UDIV_TIME 37
00922 #define count_leading_zeros(count, x) \
00923   do {                                                                  \
00924   __asm__ ("scan %1,1,%0"                                               \
00925            : "=r" ((USItype) (count))                                   \
00926            : "r" ((USItype) (x)));          \
00927   } while (0)
00928 /* Early sparclites return 63 for an argument of 0, but they warn that future
00929    implementations might change this.  Therefore, leave COUNT_LEADING_ZEROS_0
00930    undefined.  */
00931 #else
00932 /* SPARC without integer multiplication and divide instructions.
00933    (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
00934 #define umul_ppmm(w1, w0, u, v) \
00935   __asm__ ("! Inlined umul_ppmm\n"          \
00936 " wr  %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
00937 " sra %3,31,%%o5  ! Don't move this insn\n"   \
00938 " and %2,%%o5,%%o5  ! Don't move this insn\n"   \
00939 " andcc %%g0,0,%%g1 ! Don't move this insn\n"   \
00940 " mulscc  %%g1,%3,%%g1\n"           \
00941 " mulscc  %%g1,%3,%%g1\n"           \
00942 " mulscc  %%g1,%3,%%g1\n"           \
00943 " mulscc  %%g1,%3,%%g1\n"           \
00944 " mulscc  %%g1,%3,%%g1\n"           \
00945 " mulscc  %%g1,%3,%%g1\n"           \
00946 " mulscc  %%g1,%3,%%g1\n"           \
00947 " mulscc  %%g1,%3,%%g1\n"           \
00948 " mulscc  %%g1,%3,%%g1\n"           \
00949 " mulscc  %%g1,%3,%%g1\n"           \
00950 " mulscc  %%g1,%3,%%g1\n"           \
00951 " mulscc  %%g1,%3,%%g1\n"           \
00952 " mulscc  %%g1,%3,%%g1\n"           \
00953 " mulscc  %%g1,%3,%%g1\n"           \
00954 " mulscc  %%g1,%3,%%g1\n"           \
00955 " mulscc  %%g1,%3,%%g1\n"           \
00956 " mulscc  %%g1,%3,%%g1\n"           \
00957 " mulscc  %%g1,%3,%%g1\n"           \
00958 " mulscc  %%g1,%3,%%g1\n"           \
00959 " mulscc  %%g1,%3,%%g1\n"           \
00960 " mulscc  %%g1,%3,%%g1\n"           \
00961 " mulscc  %%g1,%3,%%g1\n"           \
00962 " mulscc  %%g1,%3,%%g1\n"           \
00963 " mulscc  %%g1,%3,%%g1\n"           \
00964 " mulscc  %%g1,%3,%%g1\n"           \
00965 " mulscc  %%g1,%3,%%g1\n"           \
00966 " mulscc  %%g1,%3,%%g1\n"           \
00967 " mulscc  %%g1,%3,%%g1\n"           \
00968 " mulscc  %%g1,%3,%%g1\n"           \
00969 " mulscc  %%g1,%3,%%g1\n"           \
00970 " mulscc  %%g1,%3,%%g1\n"           \
00971 " mulscc  %%g1,%3,%%g1\n"           \
00972 " mulscc  %%g1,0,%%g1\n"            \
00973 " add %%g1,%%o5,%0\n"           \
00974 " rd  %%y,%1"             \
00975      : "=r" ((USItype) (w1)),         \
00976        "=r" ((USItype) (w0))          \
00977      : "%rI" ((USItype) (u)),         \
00978        "r" ((USItype) (v))            \
00979      : "g1", "o5" __AND_CLOBBER_CC)
00980 #define UMUL_TIME 39    /* 39 instructions */
00981 /* It's quite necessary to add this much assembler for the sparc.
00982    The default udiv_qrnnd (in C) is more than 10 times slower!  */
00983 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
00984   __asm__ ("! Inlined udiv_qrnnd\n"         \
00985 " mov 32,%%g1\n"            \
00986 " subcc %1,%2,%%g0\n"           \
00987 "1: bcs 5f\n"             \
00988 "  addxcc %0,%0,%0  ! shift n1n0 and a q-bit in lsb\n"  \
00989 " sub %1,%2,%1  ! this kills msb of n\n"    \
00990 " addx  %1,%1,%1  ! so this can't give carry\n"   \
00991 " subcc %%g1,1,%%g1\n"            \
00992 "2: bne 1b\n"             \
00993 "  subcc  %1,%2,%%g0\n"           \
00994 " bcs 3f\n"             \
00995 "  addxcc %0,%0,%0  ! shift n1n0 and a q-bit in lsb\n"  \
00996 " b 3f\n"             \
00997 "  sub  %1,%2,%1  ! this kills msb of n\n"    \
00998 "4: sub %1,%2,%1\n"           \
00999 "5: addxcc  %1,%1,%1\n"           \
01000 " bcc 2b\n"             \
01001 "  subcc  %%g1,1,%%g1\n"            \
01002 "! Got carry from n.  Subtract next step to cancel this carry.\n" \
01003 " bne 4b\n"             \
01004 "  addcc  %0,%0,%0  ! shift n1n0 and a 0-bit in lsb\n"  \
01005 " sub %1,%2,%1\n"           \
01006 "3: xnor  %0,0,%0\n"            \
01007 " ! End of inline udiv_qrnnd"         \
01008      : "=&r" ((USItype) (__q)),         \
01009        "=&r" ((USItype) (__r))          \
01010      : "r" ((USItype) (__d)),         \
01011        "1" ((USItype) (__n1)),          \
01012        "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
01013 #define UDIV_TIME (3+7*32)  /* 7 instructions/iteration. 32 iterations.  */
01014 #endif /* __sparclite__ */
01015 #endif /* __sparc_v8__ */
01016 #endif /* sparc32 */
01017 
01018 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
01019     && W_TYPE_SIZE == 64
01020 #define add_ssaaaa(sh, sl, ah, al, bh, bl)        \
01021   __asm__ ("addcc %r4,%5,%1\n\t"          \
01022        "add %r2,%3,%0\n\t"            \
01023        "bcs,a,pn %%xcc, 1f\n\t"         \
01024        "add %0, 1, %0\n"            \
01025      "1:"               \
01026      : "=r" ((UDItype)(sh)),                \
01027        "=&r" ((UDItype)(sl))                \
01028      : "%rJ" ((UDItype)(ah)),             \
01029        "rI" ((UDItype)(bh)),                \
01030        "%rJ" ((UDItype)(al)),             \
01031        "rI" ((UDItype)(bl))               \
01032      __CLOBBER_CC)
01033 
01034 #define sub_ddmmss(sh, sl, ah, al, bh, bl)        \
01035   __asm__ ("subcc %r4,%5,%1\n\t"          \
01036        "sub %r2,%3,%0\n\t"            \
01037        "bcs,a,pn %%xcc, 1f\n\t"         \
01038        "sub %0, 1, %0\n\t"            \
01039      "1:"               \
01040      : "=r" ((UDItype)(sh)),                \
01041        "=&r" ((UDItype)(sl))                \
01042      : "rJ" ((UDItype)(ah)),              \
01043        "rI" ((UDItype)(bh)),                \
01044        "rJ" ((UDItype)(al)),              \
01045        "rI" ((UDItype)(bl))               \
01046      __CLOBBER_CC)
01047 
01048 #define umul_ppmm(wh, wl, u, v)           \
01049   do {                  \
01050     UDItype tmp1, tmp2, tmp3, tmp4;       \
01051     __asm__ __volatile__ (          \
01052        "srl %7,0,%3\n\t"          \
01053        "mulx %3,%6,%1\n\t"          \
01054        "srlx %6,32,%2\n\t"          \
01055        "mulx %2,%3,%4\n\t"          \
01056        "sllx %4,32,%5\n\t"          \
01057        "srl %6,0,%3\n\t"          \
01058        "sub %1,%5,%5\n\t"         \
01059        "srlx %5,32,%5\n\t"          \
01060        "addcc %4,%5,%4\n\t"         \
01061        "srlx %7,32,%5\n\t"          \
01062        "mulx %3,%5,%3\n\t"          \
01063        "mulx %2,%5,%5\n\t"          \
01064        "sethi %%hi(0x80000000),%2\n\t"      \
01065        "addcc %4,%3,%4\n\t"         \
01066        "srlx %4,32,%4\n\t"          \
01067        "add %2,%2,%2\n\t"         \
01068        "movcc %%xcc,%%g0,%2\n\t"        \
01069        "addcc %5,%4,%5\n\t"         \
01070        "sllx %3,32,%3\n\t"          \
01071        "add %1,%3,%1\n\t"         \
01072        "add %5,%2,%0"         \
01073      : "=r" ((UDItype)(wh)),          \
01074        "=&r" ((UDItype)(wl)),         \
01075        "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
01076      : "r" ((UDItype)(u)),          \
01077        "r" ((UDItype)(v))           \
01078      __CLOBBER_CC);           \
01079   } while (0)
01080 #define UMUL_TIME 96
01081 #define UDIV_TIME 230
01082 #endif /* sparc64 */
01083 
01084 #if defined (__vax__) && W_TYPE_SIZE == 32
01085 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
01086   __asm__ ("addl2 %5,%1\n\tadwc %3,%0"          \
01087      : "=g" ((USItype) (sh)),         \
01088        "=&g" ((USItype) (sl))         \
01089      : "%0" ((USItype) (ah)),         \
01090        "g" ((USItype) (bh)),          \
01091        "%1" ((USItype) (al)),         \
01092        "g" ((USItype) (bl)))
01093 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
01094   __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"          \
01095      : "=g" ((USItype) (sh)),         \
01096        "=&g" ((USItype) (sl))         \
01097      : "0" ((USItype) (ah)),          \
01098        "g" ((USItype) (bh)),          \
01099        "1" ((USItype) (al)),          \
01100        "g" ((USItype) (bl)))
01101 #define umul_ppmm(xh, xl, m0, m1) \
01102   do {                  \
01103     union {               \
01104   UDItype __ll;             \
01105   struct {USItype __l, __h;} __i;         \
01106       } __xx;               \
01107     USItype __m0 = (m0), __m1 = (m1);         \
01108     __asm__ ("emul %1,%2,$0,%0"           \
01109        : "=r" (__xx.__ll)           \
01110        : "g" (__m0),            \
01111          "g" (__m1));           \
01112     (xh) = __xx.__i.__h;            \
01113     (xl) = __xx.__i.__l;            \
01114     (xh) += ((((SItype) __m0 >> 31) & __m1)       \
01115        + (((SItype) __m1 >> 31) & __m0));       \
01116   } while (0)
01117 #define sdiv_qrnnd(q, r, n1, n0, d) \
01118   do {                  \
01119     union {DItype __ll;             \
01120      struct {SItype __l, __h;} __i;       \
01121     } __xx;             \
01122     __xx.__i.__h = n1; __xx.__i.__l = n0;       \
01123     __asm__ ("ediv %3,%2,%0,%1"           \
01124        : "=g" (q), "=g" (r)         \
01125        : "g" (__xx.__ll), "g" (d));       \
01126   } while (0)
01127 #endif /* __vax__ */
01128 
01129 #if defined (__z8000__) && W_TYPE_SIZE == 16
01130 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
01131   __asm__ ("add %H1,%H5\n\tadc  %H0,%H3"        \
01132      : "=r" ((unsigned int)(sh)),         \
01133        "=&r" ((unsigned int)(sl))         \
01134      : "%0" ((unsigned int)(ah)),         \
01135        "r" ((unsigned int)(bh)),          \
01136        "%1" ((unsigned int)(al)),         \
01137        "rQR" ((unsigned int)(bl)))
01138 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
01139   __asm__ ("sub %H1,%H5\n\tsbc  %H0,%H3"        \
01140      : "=r" ((unsigned int)(sh)),         \
01141        "=&r" ((unsigned int)(sl))         \
01142      : "0" ((unsigned int)(ah)),          \
01143        "r" ((unsigned int)(bh)),          \
01144        "1" ((unsigned int)(al)),          \
01145        "rQR" ((unsigned int)(bl)))
01146 #define umul_ppmm(xh, xl, m0, m1) \
01147   do {                  \
01148     union {long int __ll;           \
01149      struct {unsigned int __h, __l;} __i;       \
01150     } __xx;             \
01151     unsigned int __m0 = (m0), __m1 = (m1);        \
01152     __asm__ ("mult  %S0,%H3"          \
01153        : "=r" (__xx.__i.__h),         \
01154          "=r" (__xx.__i.__l)          \
01155        : "%1" (__m0),           \
01156          "rQR" (__m1));           \
01157     (xh) = __xx.__i.__h; (xl) = __xx.__i.__l;       \
01158     (xh) += ((((signed int) __m0 >> 15) & __m1)       \
01159        + (((signed int) __m1 >> 15) & __m0));     \
01160   } while (0)
01161 #endif /* __z8000__ */
01162 
01163 #endif /* __GNUC__ */
01164 
01165 /* If this machine has no inline assembler, use C macros.  */
01166 
01167 #if !defined (add_ssaaaa)
01168 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
01169   do {                  \
01170     UWtype __x;               \
01171     __x = (al) + (bl);              \
01172     (sh) = (ah) + (bh) + (__x < (al));          \
01173     (sl) = __x;               \
01174   } while (0)
01175 #endif
01176 
01177 #if !defined (sub_ddmmss)
01178 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
01179   do {                  \
01180     UWtype __x;               \
01181     __x = (al) - (bl);              \
01182     (sh) = (ah) - (bh) - (__x > (al));          \
01183     (sl) = __x;               \
01184   } while (0)
01185 #endif
01186 
01187 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
01188    smul_ppmm.  */
01189 #if !defined (umul_ppmm) && defined (smul_ppmm)
01190 #define umul_ppmm(w1, w0, u, v)           \
01191   do {                  \
01192     UWtype __w1;              \
01193     UWtype __xm0 = (u), __xm1 = (v);          \
01194     smul_ppmm (__w1, w0, __xm0, __xm1);         \
01195     (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1)   \
01196     + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0);    \
01197   } while (0)
01198 #endif
01199 
01200 /* If we still don't have umul_ppmm, define it using plain C.  */
01201 #if !defined (umul_ppmm)
01202 #define umul_ppmm(w1, w0, u, v)           \
01203   do {                  \
01204     UWtype __x0, __x1, __x2, __x3;          \
01205     UHWtype __ul, __vl, __uh, __vh;         \
01206                   \
01207     __ul = __ll_lowpart (u);            \
01208     __uh = __ll_highpart (u);           \
01209     __vl = __ll_lowpart (v);            \
01210     __vh = __ll_highpart (v);           \
01211                   \
01212     __x0 = (UWtype) __ul * __vl;          \
01213     __x1 = (UWtype) __ul * __vh;          \
01214     __x2 = (UWtype) __uh * __vl;          \
01215     __x3 = (UWtype) __uh * __vh;          \
01216                   \
01217     __x1 += __ll_highpart (__x0);/* this can't give carry */    \
01218     __x1 += __x2;   /* but this indeed can */   \
01219     if (__x1 < __x2)    /* did we get it? */      \
01220       __x3 += __ll_B;   /* yes, add it in the proper pos.  */ \
01221                   \
01222     (w1) = __x3 + __ll_highpart (__x1);         \
01223     (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);    \
01224   } while (0)
01225 #endif
01226 
01227 #if !defined (__umulsidi3)
01228 #define __umulsidi3(u, v) \
01229   ({DWunion __w;              \
01230     umul_ppmm (__w.s.high, __w.s.low, u, v);        \
01231     __w.ll; })
01232 #endif
01233 
01234 /* Define this unconditionally, so it can be used for debugging.  */
01235 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
01236   do {                  \
01237     UWtype __d1, __d0, __q1, __q0;          \
01238     UWtype __r1, __r0, __m;           \
01239     __d1 = __ll_highpart (d);           \
01240     __d0 = __ll_lowpart (d);            \
01241                   \
01242     __r1 = (n1) % __d1;             \
01243     __q1 = (n1) / __d1;             \
01244     __m = (UWtype) __q1 * __d0;           \
01245     __r1 = __r1 * __ll_B | __ll_highpart (n0);        \
01246     if (__r1 < __m)             \
01247       {                 \
01248   __q1--, __r1 += (d);            \
01249   if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
01250     if (__r1 < __m)           \
01251       __q1--, __r1 += (d);          \
01252       }                 \
01253     __r1 -= __m;              \
01254                   \
01255     __r0 = __r1 % __d1;             \
01256     __q0 = __r1 / __d1;             \
01257     __m = (UWtype) __q0 * __d0;           \
01258     __r0 = __r0 * __ll_B | __ll_lowpart (n0);       \
01259     if (__r0 < __m)             \
01260       {                 \
01261   __q0--, __r0 += (d);            \
01262   if (__r0 >= (d))            \
01263     if (__r0 < __m)           \
01264       __q0--, __r0 += (d);          \
01265       }                 \
01266     __r0 -= __m;              \
01267                   \
01268     (q) = (UWtype) __q1 * __ll_B | __q0;        \
01269     (r) = __r0;               \
01270   } while (0)
01271 
01272 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
01273    __udiv_w_sdiv (defined in libgcc or elsewhere).  */
01274 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
01275 #define udiv_qrnnd(q, r, nh, nl, d) \
01276   do {                  \
01277     USItype __r;              \
01278     (q) = __udiv_w_sdiv (&__r, nh, nl, d);        \
01279     (r) = __r;                \
01280   } while (0)
01281 #endif
01282 
01283 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c.  */
01284 #if !defined (udiv_qrnnd)
01285 #define UDIV_NEEDS_NORMALIZATION 1
01286 #define udiv_qrnnd __udiv_qrnnd_c
01287 #endif
01288 
01289 #if !defined (count_leading_zeros)
01290 extern const UQItype __clz_tab[];
01291 #define count_leading_zeros(count, x) \
01292   do {                  \
01293     UWtype __xr = (x);              \
01294     UWtype __a;               \
01295                   \
01296     if (W_TYPE_SIZE <= 32)            \
01297       {                 \
01298   __a = __xr < ((UWtype)1<<2*__BITS4)       \
01299     ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4)     \
01300     : (__xr < ((UWtype)1<<3*__BITS4) ?  2*__BITS4 : 3*__BITS4); \
01301       }                 \
01302     else                \
01303       {                 \
01304   for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8)      \
01305     if (((__xr >> __a) & 0xff) != 0)        \
01306       break;              \
01307       }                 \
01308                   \
01309     (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a);   \
01310   } while (0)
01311 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
01312 #endif
01313 
01314 #if !defined (count_trailing_zeros)
01315 /* Define count_trailing_zeros using count_leading_zeros.  The latter might be
01316    defined in asm, but if it is not, the C version above is good enough.  */
01317 #define count_trailing_zeros(count, x) \
01318   do {                  \
01319     UWtype __ctz_x = (x);           \
01320     UWtype __ctz_c;             \
01321     count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x);      \
01322     (count) = W_TYPE_SIZE - 1 - __ctz_c;        \
01323   } while (0)
01324 #endif
01325 
01326 #ifndef UDIV_NEEDS_NORMALIZATION
01327 #define UDIV_NEEDS_NORMALIZATION 0
01328 #endif