Open64: osprey/cygnus/opcodes/s390-opc.c Source File

00001 /*
00002  * Copyright 2003, 2004, 2005, 2006 PathScale, Inc.  All Rights Reserved.
00003  */
00004 
00005 /* s390-opc.c -- S390 opcode list
00006    Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
00007    Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
00008 
00009    This file is part of GDB, GAS, and the GNU binutils.
00010 
00011    This program is free software; you can redistribute it and/or modify
00012    it under the terms of the GNU General Public License as published by
00013    the Free Software Foundation; either version 2 of the License, or
00014    (at your option) any later version.
00015 
00016    This program is distributed in the hope that it will be useful,
00017    but WITHOUT ANY WARRANTY; without even the implied warranty of
00018    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00019    GNU General Public License for more details.
00020 
00021    You should have received a copy of the GNU General Public License
00022    along with this program; if not, write to the Free Software
00023    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
00024    02111-1307, USA.  */
00025 
00026 #include <stdio.h>
00027 #include "ansidecl.h"
00028 #include "opcode/s390.h"
00029 
00030 /* This file holds the S390 opcode table.  The opcode table
00031    includes almost all of the extended instruction mnemonics.  This
00032    permits the disassembler to use them, and simplifies the assembler
00033    logic, at the cost of increasing the table size.  The table is
00034    strictly constant data, so the compiler should be able to put it in
00035    the .text section.
00036 
00037    This file also holds the operand table.  All knowledge about
00038    inserting operands into instructions and vice-versa is kept in this
00039    file.  */
00040 
00041 /* The operands table.
00042    The fields are bits, shift, insert, extract, flags.  */
00043 
00044 const struct s390_operand s390_operands[] =
00045 {
00046 #define UNUSED 0
00047   { 0, 0, 0 },                    /* Indicates the end of the operand list */
00048 
00049 #define R_8    1                  /* GPR starting at position 8 */
00050   { 4, 8, S390_OPERAND_GPR },
00051 #define R_12   2                  /* GPR starting at position 12 */
00052   { 4, 12, S390_OPERAND_GPR },
00053 #define R_16   3                  /* GPR starting at position 16 */
00054   { 4, 16, S390_OPERAND_GPR },
00055 #define R_20   4                  /* GPR starting at position 20 */
00056   { 4, 20, S390_OPERAND_GPR },
00057 #define R_24   5                  /* GPR starting at position 24 */
00058   { 4, 24, S390_OPERAND_GPR },
00059 #define R_28   6                  /* GPR starting at position 28 */
00060   { 4, 28, S390_OPERAND_GPR },
00061 #define R_32   7                  /* GPR starting at position 32 */
00062   { 4, 32, S390_OPERAND_GPR },
00063 
00064 #define F_8    8                  /* FPR starting at position 8 */
00065   { 4, 8, S390_OPERAND_FPR },
00066 #define F_12   9                  /* FPR starting at position 12 */
00067   { 4, 12, S390_OPERAND_FPR },
00068 #define F_16   10                 /* FPR starting at position 16 */
00069   { 4, 16, S390_OPERAND_FPR },
00070 #define F_20   11                 /* FPR starting at position 16 */
00071   { 4, 16, S390_OPERAND_FPR },
00072 #define F_24   12                 /* FPR starting at position 24 */
00073   { 4, 24, S390_OPERAND_FPR },
00074 #define F_28   13                 /* FPR starting at position 28 */
00075   { 4, 28, S390_OPERAND_FPR },
00076 #define F_32   14                 /* FPR starting at position 32 */
00077   { 4, 32, S390_OPERAND_FPR },
00078 
00079 #define A_8    15                 /* Access reg. starting at position 8 */
00080   { 4, 8, S390_OPERAND_AR },
00081 #define A_12   16                 /* Access reg. starting at position 12 */
00082   { 4, 12, S390_OPERAND_AR },
00083 #define A_24   17                 /* Access reg. starting at position 24 */
00084   { 4, 24, S390_OPERAND_AR },
00085 #define A_28   18                 /* Access reg. starting at position 28 */
00086   { 4, 28, S390_OPERAND_AR },
00087 
00088 #define C_8    19                 /* Control reg. starting at position 8 */
00089   { 4, 8, S390_OPERAND_CR },
00090 #define C_12   20                 /* Control reg. starting at position 12 */
00091   { 4, 12, S390_OPERAND_CR },
00092 
00093 #define B_16   21                 /* Base register starting at position 16 */
00094   { 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
00095 #define B_32   22                 /* Base register starting at position 32 */
00096   { 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
00097 
00098 #define X_12   23                 /* Index register starting at position 12 */
00099   { 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
00100 
00101 #define D_20   24                 /* Displacement starting at position 20 */
00102   { 12, 20, S390_OPERAND_DISP },
00103 #define D_36   25                 /* Displacement starting at position 36 */
00104   { 12, 36, S390_OPERAND_DISP },
00105 #define D20_20 26     /* 20 bit displacement starting at 20 */
00106   { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
00107 
00108 #define L4_8   27                 /* 4 bit length starting at position 8 */
00109   { 4, 8, S390_OPERAND_LENGTH },
00110 #define L4_12  28                 /* 4 bit length starting at position 12 */
00111   { 4, 12, S390_OPERAND_LENGTH },
00112 #define L8_8   29                 /* 8 bit length starting at position 8 */
00113   { 8, 8, S390_OPERAND_LENGTH },
00114 
00115 #define U4_8   30                 /* 4 bit unsigned value starting at 8 */
00116   { 4, 8, 0 },
00117 #define U4_12  31                 /* 4 bit unsigned value starting at 12 */
00118   { 4, 12, 0 },
00119 #define U4_16  32                 /* 4 bit unsigned value starting at 16 */
00120   { 4, 16, 0 },
00121 #define U4_20  33                 /* 4 bit unsigned value starting at 20 */
00122   { 4, 20, 0 },
00123 #define U8_8   34                 /* 8 bit unsigned value starting at 8 */
00124   { 8, 8, 0 },
00125 #define U8_16  35                 /* 8 bit unsigned value starting at 16 */
00126   { 8, 16, 0 },
00127 #define I16_16 36                 /* 16 bit signed value starting at 16 */
00128   { 16, 16, S390_OPERAND_SIGNED },
00129 #define U16_16 37                 /* 16 bit unsigned value starting at 16 */
00130   { 16, 16, 0 },
00131 #define J16_16 38                 /* PC relative jump offset at 16 */
00132   { 16, 16, S390_OPERAND_PCREL },
00133 #define J32_16 39                 /* PC relative long offset at 16 */
00134   { 32, 16, S390_OPERAND_PCREL }
00135 };
00136 
00137 
00138 /* Macros used to form opcodes.  */
00139 
00140 /* 8/16/48 bit opcodes.  */
00141 #define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 }
00142 #define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 }
00143 #define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \
00144                   (x >> 16) & 255, (x >> 8) & 255, x & 255}
00145 
00146 /* The new format of the INSTR_x_y and MASK_x_y defines is based
00147    on the following rules:
00148    1) the middle part of the definition (x in INSTR_x_y) is the official
00149       names of the instruction format that you can find in the principals
00150       of operation.
00151    2) the last part of the definition (y in INSTR_x_y) gives you an idea
00152       which operands the binary represenation of the instruction has.
00153       The meanings of the letters in y are:
00154       a - access register
00155       c - control register
00156       d - displacement, 12 bit
00157       f - floating pointer register
00158       i - signed integer, 4 or 8 bit
00159       l - length, 4 or 8 bit
00160       p - pc relative
00161       r - general purpose register
00162       u - unsigned integer, 4 or 8 bit
00163       0 - operand skipped.
00164       The order of the letters reflects the layout of the format in
00165       storage and not the order of the paramaters of the instructions.
00166       The use of the letters is not a 100% match with the PoP but it is
00167       quite close.
00168 
00169       For example the instruction "mvo" is defined in the PoP as follows:
00170       
00171       MVO  D1(L1,B1),D2(L2,B2)   [SS]
00172 
00173       --------------------------------------
00174       | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
00175       --------------------------------------
00176        0      8    12   16   20   32   36
00177 
00178       The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD.  */
00179 
00180 #define INSTR_E          2, { 0,0,0,0,0,0 }                    /* e.g. pr    */
00181 #define INSTR_RIE_RRP    6, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxhg */
00182 #define INSTR_RIL_0P     6, { J32_16,0,0,0,0 }                 /* e.g. jg    */
00183 #define INSTR_RIL_RP     6, { R_8,J32_16,0,0,0,0 }             /* e.g. brasl */
00184 #define INSTR_RIL_UP     6, { U4_8,J32_16,0,0,0,0 }            /* e.g. brcl  */
00185 #define INSTR_RI_0P      4, { J16_16,0,0,0,0,0 }               /* e.g. j     */
00186 #define INSTR_RI_RI      4, { R_8,I16_16,0,0,0,0 }             /* e.g. ahi   */
00187 #define INSTR_RI_RP      4, { R_8,J16_16,0,0,0,0 }             /* e.g. brct  */
00188 #define INSTR_RI_RU      4, { R_8,U16_16,0,0,0,0 }             /* e.g. tml   */
00189 #define INSTR_RI_UP      4, { U4_8,J16_16,0,0,0,0 }            /* e.g. brc   */
00190 #define INSTR_RRE_00     4, { 0,0,0,0,0,0 }                    /* e.g. palb  */
00191 #define INSTR_RRE_0R     4, { R_28,0,0,0,0,0 }                 /* e.g. tb    */
00192 #define INSTR_RRE_AA     4, { A_24,A_28,0,0,0,0 }              /* e.g. cpya  */
00193 #define INSTR_RRE_AR     4, { A_24,R_28,0,0,0,0 }              /* e.g. sar   */
00194 #define INSTR_RRE_F0     4, { F_24,0,0,0,0,0 }                 /* e.g. sqer  */
00195 #define INSTR_RRE_FF     4, { F_24,F_28,0,0,0,0 }              /* e.g. debr  */
00196 #define INSTR_RRE_R0     4, { R_24,0,0,0,0,0 }                 /* e.g. ipm   */
00197 #define INSTR_RRE_RA     4, { R_24,A_28,0,0,0,0 }              /* e.g. ear   */
00198 #define INSTR_RRE_RF     4, { R_24,F_28,0,0,0,0 }              /* e.g. cefbr */
00199 #define INSTR_RRE_RR     4, { R_24,R_28,0,0,0,0 }              /* e.g. lura  */
00200 #define INSTR_RRF_F0FF   4, { F_16,F_24,F_28,0,0,0 }           /* e.g. madbr */
00201 #define INSTR_RRF_FUFF   4, { F_24,F_16,F_28,U4_20,0,0 }       /* e.g. didbr */
00202 #define INSTR_RRF_RURR   4, { R_24,R_28,R_16,U4_20,0,0 }       /* e.g. .insn */
00203 #define INSTR_RRF_R0RR   4, { R_24,R_28,R_16,0,0,0 }           /* e.g. idte  */
00204 #define INSTR_RRF_U0FF   4, { F_24,U4_16,F_28,0,0,0 }          /* e.g. cfxbr */
00205 #define INSTR_RRF_U0FR   4, { F_24,U4_16,R_28,0,0,0 }          /* e.g. cfebr */
00206 #define INSTR_RRF_U0FR   4, { F_24,U4_16,R_28,0,0,0 }          /* e.g. cfxbr */
00207 #define INSTR_RR_0R      2, { R_12, 0,0,0,0,0 }                /* e.g. br    */
00208 #define INSTR_RR_FF      2, { F_8,F_12,0,0,0,0 }               /* e.g. adr   */
00209 #define INSTR_RR_R0      2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
00210 #define INSTR_RR_RR      2, { R_8,R_12,0,0,0,0 }               /* e.g. lr    */
00211 #define INSTR_RR_U0      2, { U8_8, 0,0,0,0,0 }                /* e.g. svc   */
00212 #define INSTR_RR_UR      2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
00213 #define INSTR_RSE_RRRD   6, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. lmh   */
00214 #define INSTR_RSE_RURD   6, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icmh  */
00215 #define INSTR_RSL_R0RD   6, { R_8,D_20,B_16,0,0,0 }            /* e.g. tp    */
00216 #define INSTR_RSI_RRP    4, { R_8,R_12,J16_16,0,0,0 }          /* e.g. brxh  */
00217 #define INSTR_RSY_RRRD   6, { R_8,R_12,D20_20,B_16,0,0 }       /* e.g. stmy  */
00218 #define INSTR_RSY_RURD   6, { R_8,U4_12,D20_20,B_16,0,0 }      /* e.g. icmh  */
00219 #define INSTR_RSY_AARD   6, { A_8,A_12,D20_20,B_16,0,0 }       /* e.g. lamy  */
00220 #define INSTR_RS_AARD    4, { A_8,A_12,D_20,B_16,0,0 }         /* e.g. lam   */
00221 #define INSTR_RS_CCRD    4, { C_8,C_12,D_20,B_16,0,0 }         /* e.g. lctl  */
00222 #define INSTR_RS_R0RD    4, { R_8,D_20,B_16,0,0,0 }            /* e.g. sll   */
00223 #define INSTR_RS_RRRD    4, { R_8,R_12,D_20,B_16,0,0 }         /* e.g. cs    */
00224 #define INSTR_RS_RURD    4, { R_8,U4_12,D_20,B_16,0,0 }        /* e.g. icm   */
00225 #define INSTR_RXE_FRRD   6, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. axbr  */
00226 #define INSTR_RXE_RRRD   6, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. lg    */
00227 #define INSTR_RXF_FRRDF  6, { F_32,F_8,D_20,X_12,B_16,0 }      /* e.g. madb  */
00228 #define INSTR_RXF_RRRDR  6, { R_32,R_8,D_20,X_12,B_16,0 }      /* e.g. .insn */
00229 #define INSTR_RXY_RRRD   6, { R_8,D20_20,X_12,B_16,0,0 }       /* e.g. ly    */
00230 #define INSTR_RXY_FRRD   6, { F_8,D20_20,X_12,B_16,0,0 }       /* e.g. ley   */
00231 #define INSTR_RX_0RRD    4, { D_20,X_12,B_16,0,0,0 }           /* e.g. be    */
00232 #define INSTR_RX_FRRD    4, { F_8,D_20,X_12,B_16,0,0 }         /* e.g. ae    */
00233 #define INSTR_RX_RRRD    4, { R_8,D_20,X_12,B_16,0,0 }         /* e.g. l     */
00234 #define INSTR_RX_URRD    4, { U4_8,D_20,X_12,B_16,0,0 }        /* e.g. bc    */
00235 #define INSTR_SI_URD     4, { D_20,B_16,U8_8,0,0,0 }           /* e.g. cli   */
00236 #define INSTR_SIY_URD    6, { D20_20,B_16,U8_8,0,0,0 }         /* e.g. tmy   */
00237 #define INSTR_SSE_RDRD   6, { D_20,B_16,D_36,B_32,0,0 }        /* e.g. mvsdk */
00238 #define INSTR_SS_L0RDRD  6, { D_20,L8_8,B_16,D_36,B_32,0     } /* e.g. mvc   */
00239 #define INSTR_SS_LIRDRD  6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp   */
00240 #define INSTR_SS_LLRDRD  6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack  */
00241 #define INSTR_SS_RRRDRD  6, { D_20,R_8,B_16,D_36,B_32,R_12 }   /* e.g. mvck  */
00242 #define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 }   /* e.g. plo   */
00243 #define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 }   /* e.g. lmd   */
00244 #define INSTR_S_00       4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
00245 #define INSTR_S_RD       4, { D_20,B_16,0,0,0,0 }              /* e.g. lpsw  */
00246 
00247 #define MASK_E           { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
00248 #define MASK_RIE_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00249 #define MASK_RIL_0P      { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
00250 #define MASK_RIL_RP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
00251 #define MASK_RIL_UP      { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
00252 #define MASK_RI_0P       { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
00253 #define MASK_RI_RI       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
00254 #define MASK_RI_RP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
00255 #define MASK_RI_RU       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
00256 #define MASK_RI_UP       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
00257 #define MASK_RRE_00      { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
00258 #define MASK_RRE_0R      { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 }
00259 #define MASK_RRE_AA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
00260 #define MASK_RRE_AR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
00261 #define MASK_RRE_F0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
00262 #define MASK_RRE_FF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
00263 #define MASK_RRE_R0      { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 }
00264 #define MASK_RRE_RA      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
00265 #define MASK_RRE_RF      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
00266 #define MASK_RRE_RR      { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
00267 #define MASK_RRF_F0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
00268 #define MASK_RRF_FUFF    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
00269 #define MASK_RRF_RURR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
00270 #define MASK_RRF_R0RR    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
00271 #define MASK_RRF_U0FF    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
00272 #define MASK_RRF_U0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
00273 #define MASK_RRF_U0FR    { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
00274 #define MASK_RR_0R       { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
00275 #define MASK_RR_FF       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00276 #define MASK_RR_R0       { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
00277 #define MASK_RR_RR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00278 #define MASK_RR_U0       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00279 #define MASK_RR_UR       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00280 #define MASK_RSE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00281 #define MASK_RSE_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00282 #define MASK_RSL_R0RD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00283 #define MASK_RSI_RRP     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00284 #define MASK_RS_AARD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00285 #define MASK_RS_CCRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00286 #define MASK_RS_R0RD     { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
00287 #define MASK_RS_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00288 #define MASK_RS_RURD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00289 #define MASK_RSY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00290 #define MASK_RSY_RURD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00291 #define MASK_RSY_AARD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00292 #define MASK_RXE_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00293 #define MASK_RXE_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00294 #define MASK_RXF_FRRDF   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00295 #define MASK_RXF_RRRDR   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00296 #define MASK_RXY_RRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00297 #define MASK_RXY_FRRD    { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00298 #define MASK_RX_0RRD     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
00299 #define MASK_RX_FRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00300 #define MASK_RX_RRRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00301 #define MASK_RX_URRD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00302 #define MASK_SI_URD      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00303 #define MASK_SIY_URD     { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
00304 #define MASK_SSE_RDRD    { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
00305 #define MASK_SS_L0RDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00306 #define MASK_SS_LIRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00307 #define MASK_SS_LLRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00308 #define MASK_SS_RRRDRD   { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00309 #define MASK_SS_RRRDRD2  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00310 #define MASK_SS_RRRDRD3  { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
00311 #define MASK_S_00        { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
00312 #define MASK_S_RD        { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
00313 
00314 /* The opcode formats table (blueprints for .insn pseudo mnemonic).  */
00315 
00316 const struct s390_opcode s390_opformats[] =
00317   {
00318   { "e",  OP8(0x00LL),  MASK_E,   INSTR_E,  3, 0 },
00319   { "ri", OP8(0x00LL),  MASK_RI_RI, INSTR_RI_RI,  3, 0 },
00320   { "rie",  OP8(0x00LL),  MASK_RIE_RRP, INSTR_RIE_RRP,  3, 0 },
00321   { "ril",  OP8(0x00LL),  MASK_RIL_RP,  INSTR_RIL_RP, 3, 0 },
00322   { "rr", OP8(0x00LL),  MASK_RR_RR, INSTR_RR_RR,  3, 0 },
00323   { "rre",  OP8(0x00LL),  MASK_RRE_RR,  INSTR_RRE_RR, 3, 0 },
00324   { "rrf",  OP8(0x00LL),  MASK_RRF_RURR,  INSTR_RRF_RURR, 3, 0 },
00325   { "rs", OP8(0x00LL),  MASK_RS_RRRD, INSTR_RS_RRRD,  3, 0 },
00326   { "rse",  OP8(0x00LL),  MASK_RSE_RRRD,  INSTR_RSE_RRRD, 3, 0 },
00327   { "rsi",  OP8(0x00LL),  MASK_RSI_RRP, INSTR_RSI_RRP,  3, 0 },
00328   { "rsy",  OP8(0x00LL),  MASK_RSY_RRRD,  INSTR_RSY_RRRD, 3, 3 },
00329   { "rx", OP8(0x00LL),  MASK_RX_RRRD, INSTR_RX_RRRD,  3, 0 },
00330   { "rxe",  OP8(0x00LL),  MASK_RXE_RRRD,  INSTR_RXE_RRRD, 3, 0 },
00331   { "rxf",  OP8(0x00LL),  MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
00332   { "rxy",  OP8(0x00LL),  MASK_RXY_RRRD,  INSTR_RXY_RRRD, 3, 3 },
00333   { "s",  OP8(0x00LL),  MASK_S_RD,  INSTR_S_RD, 3, 0 },
00334   { "si", OP8(0x00LL),  MASK_SI_URD,  INSTR_SI_URD, 3, 0 },
00335   { "siy",  OP8(0x00LL),  MASK_SIY_URD, INSTR_SIY_URD,  3, 3 },
00336   { "ss", OP8(0x00LL),  MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
00337   { "sse",  OP8(0x00LL),  MASK_SSE_RDRD,  INSTR_SSE_RDRD, 3, 0 },
00338 };
00339 
00340 const int s390_num_opformats =
00341   sizeof (s390_opformats) / sizeof (s390_opformats[0]);
00342 
00343 #include "s390-opc.tab"