|
Data Types |
| type | mips_opcode |
Defines |
| #define | OP_MASK_OP 0x3f |
| #define | OP_SH_OP 26 |
| #define | OP_MASK_RS 0x1f |
| #define | OP_SH_RS 21 |
| #define | OP_MASK_FR 0x1f |
| #define | OP_SH_FR 21 |
| #define | OP_MASK_FMT 0x1f |
| #define | OP_SH_FMT 21 |
| #define | OP_MASK_BCC 0x7 |
| #define | OP_SH_BCC 18 |
| #define | OP_MASK_CODE 0x3ff |
| #define | OP_SH_CODE 16 |
| #define | OP_MASK_CODE2 0x3ff |
| #define | OP_SH_CODE2 6 |
| #define | OP_MASK_RT 0x1f |
| #define | OP_SH_RT 16 |
| #define | OP_MASK_FT 0x1f |
| #define | OP_SH_FT 16 |
| #define | OP_MASK_CACHE 0x1f |
| #define | OP_SH_CACHE 16 |
| #define | OP_MASK_RD 0x1f |
| #define | OP_SH_RD 11 |
| #define | OP_MASK_FS 0x1f |
| #define | OP_SH_FS 11 |
| #define | OP_MASK_PREFX 0x1f |
| #define | OP_SH_PREFX 11 |
| #define | OP_MASK_CCC 0x7 |
| #define | OP_SH_CCC 8 |
| #define | OP_MASK_CODE20 0xfffff |
| #define | OP_SH_CODE20 6 |
| #define | OP_MASK_SHAMT 0x1f |
| #define | OP_SH_SHAMT 6 |
| #define | OP_MASK_FD 0x1f |
| #define | OP_SH_FD 6 |
| #define | OP_MASK_TARGET 0x3ffffff |
| #define | OP_SH_TARGET 0 |
| #define | OP_MASK_COPZ 0x1ffffff |
| #define | OP_SH_COPZ 0 |
| #define | OP_MASK_IMMEDIATE 0xffff |
| #define | OP_SH_IMMEDIATE 0 |
| #define | OP_MASK_DELTA 0xffff |
| #define | OP_SH_DELTA 0 |
| #define | OP_MASK_FUNCT 0x3f |
| #define | OP_SH_FUNCT 0 |
| #define | OP_MASK_SPEC 0x3f |
| #define | OP_SH_SPEC 0 |
| #define | OP_SH_LOCC 8 |
| #define | OP_SH_HICC 18 |
| #define | OP_MASK_CC 0x7 |
| #define | OP_SH_COP1NORM 25 |
| #define | OP_MASK_COP1NORM 0x1 |
| #define | OP_SH_COP1SPEC 21 |
| #define | OP_MASK_COP1SPEC 0xf |
| #define | OP_MASK_COP1SCLR 0x4 |
| #define | OP_MASK_COP1CMP 0x3 |
| #define | OP_SH_COP1CMP 4 |
| #define | OP_SH_FORMAT 21 |
| #define | OP_MASK_FORMAT 0x7 |
| #define | OP_SH_TRUE 16 |
| #define | OP_MASK_TRUE 0x1 |
| #define | OP_SH_GE 17 |
| #define | OP_MASK_GE 0x01 |
| #define | OP_SH_UNSIGNED 16 |
| #define | OP_MASK_UNSIGNED 0x1 |
| #define | OP_SH_HINT 16 |
| #define | OP_MASK_HINT 0x1f |
| #define | OP_SH_MMI 0 |
| #define | OP_MASK_MMI 0x3f |
| #define | OP_SH_MMISUB 6 |
| #define | OP_MASK_MMISUB 0x1f |
| #define | OP_MASK_PERFREG 0x1f |
| #define | OP_SH_PERFREG 1 |
| #define | OP_SH_SEL 0 |
| #define | OP_MASK_SEL 0x7 |
| #define | OP_SH_CODE19 6 |
| #define | OP_MASK_CODE19 0x7ffff |
| #define | OP_SH_ALN 21 |
| #define | OP_MASK_ALN 0x7 |
| #define | OP_SH_VSEL 21 |
| #define | OP_MASK_VSEL 0x1f |
| #define | OP_MASK_VECBYTE 0x7 |
| #define | OP_SH_VECBYTE 22 |
| #define | OP_MASK_VECALIGN 0x7 |
| #define | OP_SH_VECALIGN 21 |
| #define | OP_MASK_INSMSB 0x1f |
| #define | OP_SH_INSMSB 11 |
| #define | OP_MASK_EXTMSBD 0x1f |
| #define | OP_SH_EXTMSBD 11 |
| #define | OP_OP_COP0 0x10 |
| #define | OP_OP_COP1 0x11 |
| #define | OP_OP_COP2 0x12 |
| #define | OP_OP_COP3 0x13 |
| #define | OP_OP_LWC1 0x31 |
| #define | OP_OP_LWC2 0x32 |
| #define | OP_OP_LWC3 0x33 |
| #define | OP_OP_LDC1 0x35 |
| #define | OP_OP_LDC2 0x36 |
| #define | OP_OP_LDC3 0x37 |
| #define | OP_OP_SWC1 0x39 |
| #define | OP_OP_SWC2 0x3a |
| #define | OP_OP_SWC3 0x3b |
| #define | OP_OP_SDC1 0x3d |
| #define | OP_OP_SDC2 0x3e |
| #define | OP_OP_SDC3 0x3f |
| #define | MDMX_FMTSEL_IMM_QH 0x1d |
| #define | MDMX_FMTSEL_IMM_OB 0x1e |
| #define | MDMX_FMTSEL_VEC_QH 0x15 |
| #define | MDMX_FMTSEL_VEC_OB 0x16 |
| #define | INSN_WRITE_GPR_D 0x00000001 |
| #define | INSN_WRITE_GPR_T 0x00000002 |
| #define | INSN_WRITE_GPR_31 0x00000004 |
| #define | INSN_WRITE_FPR_D 0x00000008 |
| #define | INSN_WRITE_FPR_S 0x00000010 |
| #define | INSN_WRITE_FPR_T 0x00000020 |
| #define | INSN_READ_GPR_S 0x00000040 |
| #define | INSN_READ_GPR_T 0x00000080 |
| #define | INSN_READ_FPR_S 0x00000100 |
| #define | INSN_READ_FPR_T 0x00000200 |
| #define | INSN_READ_FPR_R 0x00000400 |
| #define | INSN_WRITE_COND_CODE 0x00000800 |
| #define | INSN_READ_COND_CODE 0x00001000 |
| #define | INSN_TLB 0x00002000 |
| #define | INSN_COP 0x00004000 |
| #define | INSN_LOAD_MEMORY_DELAY 0x00008000 |
| #define | INSN_LOAD_COPROC_DELAY 0x00010000 |
| #define | INSN_UNCOND_BRANCH_DELAY 0x00020000 |
| #define | INSN_COND_BRANCH_DELAY 0x00040000 |
| #define | INSN_COND_BRANCH_LIKELY 0x00080000 |
| #define | INSN_COPROC_MOVE_DELAY 0x00100000 |
| #define | INSN_COPROC_MEMORY_DELAY 0x00200000 |
| #define | INSN_READ_HI 0x00400000 |
| #define | INSN_READ_LO 0x00800000 |
| #define | INSN_WRITE_HI 0x01000000 |
| #define | INSN_WRITE_LO 0x02000000 |
| #define | INSN_TRAP 0x04000000 |
| #define | INSN_STORE_MEMORY 0x08000000 |
| #define | FP_S 0x10000000 |
| #define | FP_D 0x20000000 |
| #define | INSN_MULT 0x40000000 |
| #define | INSN_SYNC 0x80000000 |
| #define | INSN2_ALIAS 0x00000001 |
| #define | INSN2_READ_MDMX_ACC 0x00000002 |
| #define | INSN2_WRITE_MDMX_ACC 0x00000004 |
| #define | INSN_MACRO 0xffffffff |
| #define | INSN_ISA_MASK 0x00000fff |
| #define | INSN_ISA1 0x00000001 |
| #define | INSN_ISA2 0x00000002 |
| #define | INSN_ISA3 0x00000004 |
| #define | INSN_ISA4 0x00000008 |
| #define | INSN_ISA5 0x00000010 |
| #define | INSN_ISA32 0x00000020 |
| #define | INSN_ISA64 0x00000040 |
| #define | INSN_ISA32R2 0x00000080 |
| #define | INSN_ISA64R2 0x00000100 |
| #define | INSN_ASE_MASK 0x0000f000 |
| #define | INSN_MIPS16 0x00002000 |
| #define | INSN_MIPS3D 0x00004000 |
| #define | INSN_MDMX 0x00008000 |
| #define | INSN_4650 0x00010000 |
| #define | INSN_4010 0x00020000 |
| #define | INSN_4100 0x00040000 |
| #define | INSN_3900 0x00080000 |
| #define | INSN_10000 0x00100000 |
| #define | INSN_SB1 0x00200000 |
| #define | INSN_4111 0x00400000 |
| #define | INSN_4120 0x00800000 |
| #define | INSN_5400 0x01000000 |
| #define | INSN_5500 0x02000000 |
| #define | ISA_UNKNOWN 0 |
| #define | ISA_MIPS1 (INSN_ISA1) |
| #define | ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) |
| #define | ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) |
| #define | ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) |
| #define | ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) |
| #define | ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) |
| #define | ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) |
| #define | ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) |
| #define | ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) |
| #define | CPU_UNKNOWN 0 |
| #define | CPU_R3000 3000 |
| #define | CPU_R3900 3900 |
| #define | CPU_R4000 4000 |
| #define | CPU_R4010 4010 |
| #define | CPU_VR4100 4100 |
| #define | CPU_R4111 4111 |
| #define | CPU_VR4120 4120 |
| #define | CPU_R4300 4300 |
| #define | CPU_R4400 4400 |
| #define | CPU_R4600 4600 |
| #define | CPU_R4650 4650 |
| #define | CPU_R5000 5000 |
| #define | CPU_VR5400 5400 |
| #define | CPU_VR5500 5500 |
| #define | CPU_R6000 6000 |
| #define | CPU_RM7000 7000 |
| #define | CPU_R8000 8000 |
| #define | CPU_RM9000 9000 |
| #define | CPU_R10000 10000 |
| #define | CPU_R12000 12000 |
| #define | CPU_MIPS16 16 |
| #define | CPU_MIPS32 32 |
| #define | CPU_MIPS32R2 33 |
| #define | CPU_MIPS5 5 |
| #define | CPU_MIPS64 64 |
| #define | CPU_MIPS64R2 65 |
| #define | CPU_SB1 12310201 |
| #define | OPCODE_IS_MEMBER(insn, isa, cpu) |
| #define | NUMOPCODES bfd_mips_num_opcodes |
| #define | MIPS16OP_MASK_OP 0x1f |
| #define | MIPS16OP_SH_OP 11 |
| #define | MIPS16OP_MASK_IMM11 0x7ff |
| #define | MIPS16OP_SH_IMM11 0 |
| #define | MIPS16OP_MASK_RX 0x7 |
| #define | MIPS16OP_SH_RX 8 |
| #define | MIPS16OP_MASK_IMM8 0xff |
| #define | MIPS16OP_SH_IMM8 0 |
| #define | MIPS16OP_MASK_RY 0x7 |
| #define | MIPS16OP_SH_RY 5 |
| #define | MIPS16OP_MASK_IMM5 0x1f |
| #define | MIPS16OP_SH_IMM5 0 |
| #define | MIPS16OP_MASK_RZ 0x7 |
| #define | MIPS16OP_SH_RZ 2 |
| #define | MIPS16OP_MASK_IMM4 0xf |
| #define | MIPS16OP_SH_IMM4 0 |
| #define | MIPS16OP_MASK_REGR32 0x1f |
| #define | MIPS16OP_SH_REGR32 0 |
| #define | MIPS16OP_MASK_REG32R 0x1f |
| #define | MIPS16OP_SH_REG32R 3 |
| #define | MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) |
| #define | MIPS16OP_MASK_MOVE32Z 0x7 |
| #define | MIPS16OP_SH_MOVE32Z 0 |
| #define | MIPS16OP_MASK_IMM6 0x3f |
| #define | MIPS16OP_SH_IMM6 5 |
| #define | MIPS16_INSN_WRITE_X 0x00000001 |
| #define | MIPS16_INSN_WRITE_Y 0x00000002 |
| #define | MIPS16_INSN_WRITE_Z 0x00000004 |
| #define | MIPS16_INSN_WRITE_T 0x00000008 |
| #define | MIPS16_INSN_WRITE_SP 0x00000010 |
| #define | MIPS16_INSN_WRITE_31 0x00000020 |
| #define | MIPS16_INSN_WRITE_GPR_Y 0x00000040 |
| #define | MIPS16_INSN_READ_X 0x00000080 |
| #define | MIPS16_INSN_READ_Y 0x00000100 |
| #define | MIPS16_INSN_READ_Z 0x00000200 |
| #define | MIPS16_INSN_READ_T 0x00000400 |
| #define | MIPS16_INSN_READ_SP 0x00000800 |
| #define | MIPS16_INSN_READ_31 0x00001000 |
| #define | MIPS16_INSN_READ_PC 0x00002000 |
| #define | MIPS16_INSN_READ_GPR_X 0x00004000 |
| #define | MIPS16_INSN_BRANCH 0x00010000 |
Enumerations |
| enum | {
M_ABS,
M_ADD_I,
M_ADDU_I,
M_AND_I,
M_BEQ,
M_BEQ_I,
M_BEQL_I,
M_BGE,
M_BGEL,
M_BGE_I,
M_BGEL_I,
M_BGEU,
M_BGEUL,
M_BGEU_I,
M_BGEUL_I,
M_BGT,
M_BGTL,
M_BGT_I,
M_BGTL_I,
M_BGTU,
M_BGTUL,
M_BGTU_I,
M_BGTUL_I,
M_BLE,
M_BLEL,
M_BLE_I,
M_BLEL_I,
M_BLEU,
M_BLEUL,
M_BLEU_I,
M_BLEUL_I,
M_BLT,
M_BLTL,
M_BLT_I,
M_BLTL_I,
M_BLTU,
M_BLTUL,
M_BLTU_I,
M_BLTUL_I,
M_BNE,
M_BNE_I,
M_BNEL_I,
M_DABS,
M_DADD_I,
M_DADDU_I,
M_DDIV_3,
M_DDIV_3I,
M_DDIVU_3,
M_DDIVU_3I,
M_DEXT,
M_DINS,
M_DIV_3,
M_DIV_3I,
M_DIVU_3,
M_DIVU_3I,
M_DLA_AB,
M_DLCA_AB,
M_DLI,
M_DMUL,
M_DMUL_I,
M_DMULO,
M_DMULO_I,
M_DMULOU,
M_DMULOU_I,
M_DREM_3,
M_DREM_3I,
M_DREMU_3,
M_DREMU_3I,
M_DSUB_I,
M_DSUBU_I,
M_DSUBU_I_2,
M_J_A,
M_JAL_1,
M_JAL_2,
M_JAL_A,
M_L_DOB,
M_L_DAB,
M_LA_AB,
M_LB_A,
M_LB_AB,
M_LBU_A,
M_LBU_AB,
M_LCA_AB,
M_LD_A,
M_LD_OB,
M_LD_AB,
M_LDC1_AB,
M_LDC2_AB,
M_LDC3_AB,
M_LDL_AB,
M_LDR_AB,
M_LH_A,
M_LH_AB,
M_LHU_A,
M_LHU_AB,
M_LI,
M_LI_D,
M_LI_DD,
M_LI_S,
M_LI_SS,
M_LL_AB,
M_LLD_AB,
M_LS_A,
M_LW_A,
M_LW_AB,
M_LWC0_A,
M_LWC0_AB,
M_LWC1_A,
M_LWC1_AB,
M_LWC2_A,
M_LWC2_AB,
M_LWC3_A,
M_LWC3_AB,
M_LWL_A,
M_LWL_AB,
M_LWR_A,
M_LWR_AB,
M_LWU_AB,
M_MOVE,
M_MUL,
M_MUL_I,
M_MULO,
M_MULO_I,
M_MULOU,
M_MULOU_I,
M_NOR_I,
M_OR_I,
M_REM_3,
M_REM_3I,
M_REMU_3,
M_REMU_3I,
M_DROL,
M_ROL,
M_DROL_I,
M_ROL_I,
M_DROR,
M_ROR,
M_DROR_I,
M_ROR_I,
M_S_DA,
M_S_DOB,
M_S_DAB,
M_S_S,
M_SC_AB,
M_SCD_AB,
M_SD_A,
M_SD_OB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
M_SDC3_AB,
M_SDL_AB,
M_SDR_AB,
M_SEQ,
M_SEQ_I,
M_SGE,
M_SGE_I,
M_SGEU,
M_SGEU_I,
M_SGT,
M_SGT_I,
M_SGTU,
M_SGTU_I,
M_SLE,
M_SLE_I,
M_SLEU,
M_SLEU_I,
M_SLT_I,
M_SLTU_I,
M_SNE,
M_SNE_I,
M_SB_A,
M_SB_AB,
M_SH_A,
M_SH_AB,
M_SW_A,
M_SW_AB,
M_SWC0_A,
M_SWC0_AB,
M_SWC1_A,
M_SWC1_AB,
M_SWC2_A,
M_SWC2_AB,
M_SWC3_A,
M_SWC3_AB,
M_SWL_A,
M_SWL_AB,
M_SWR_A,
M_SWR_AB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
M_TEQ_I,
M_TGE_I,
M_TGEU_I,
M_TLT_I,
M_TLTU_I,
M_TNE_I,
M_TRUNCWD,
M_TRUNCWS,
M_ULD,
M_ULD_A,
M_ULH,
M_ULH_A,
M_ULHU,
M_ULHU_A,
M_ULW,
M_ULW_A,
M_USH,
M_USH_A,
M_USW,
M_USW_A,
M_USD,
M_USD_A,
M_XOR_I,
M_COP0,
M_COP1,
M_COP2,
M_COP3,
M_NUM_MACROS
} |
Variables |
| struct mips_opcode | mips_builtin_opcodes [] |
| const int | bfd_mips_num_builtin_opcodes |
| struct mips_opcode * | mips_opcodes |
| int | bfd_mips_num_opcodes |
| struct mips_opcode | mips16_opcodes [] |
| const int | bfd_mips16_num_opcodes |
